[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tx.c

/*
 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/tcp.h>
#include <linux/if_vlan.h>
#include "en.h"

#define MLX5E_SQ_NOPS_ROOM  MLX5_SEND_WQE_MAX_WQEBBS
#define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
			    MLX5E_SQ_NOPS_ROOM)

void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
{
	struct mlx5_wq_cyc                *wq  = &sq->wq;

	u16 pi = sq->pc & wq->sz_m1;
	struct mlx5e_tx_wqe              *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);

	struct mlx5_wqe_ctrl_seg         *cseg = &wqe->ctrl;

	memset(cseg, 0, sizeof(*cseg));

	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
	cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | 0x01);

	sq->skb[pi] = NULL;
	sq->pc++;

	if (notify_hw) {
		cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
		mlx5e_tx_notify_hw(sq, wqe, 0);
	}
}

static inline void mlx5e_tx_dma_unmap(struct device *pdev,
				      struct mlx5e_sq_dma *dma)
{
	switch (dma->type) {
	case MLX5E_DMA_MAP_SINGLE:
		dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
		break;
	case MLX5E_DMA_MAP_PAGE:
		dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
		break;
	default:
		WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
	}
}

static inline void mlx5e_dma_push(struct mlx5e_sq *sq,
				  dma_addr_t addr,
				  u32 size,
				  enum mlx5e_dma_map_type map_type)
{
	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].type = map_type;
	sq->dma_fifo_pc++;
}

static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_sq *sq, u32 i)
{
	return &sq->dma_fifo[i & sq->dma_fifo_mask];
}

static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, u8 num_dma)
{
	int i;

	for (i = 0; i < num_dma; i++) {
		struct mlx5e_sq_dma *last_pushed_dma =
			mlx5e_dma_get(sq, --sq->dma_fifo_pc);

		mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
	}
}

u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
		       void *accel_priv, select_queue_fallback_t fallback)
{
	struct mlx5e_priv *priv = netdev_priv(dev);
	int channel_ix = fallback(dev, skb);
	int up = skb_vlan_tag_present(skb)        ?
		 skb->vlan_tci >> VLAN_PRIO_SHIFT :
		 priv->default_vlan_prio;
	int tc = netdev_get_prio_tc_map(dev, up);

	return priv->channeltc_to_txq_map[channel_ix][tc];
}

static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
					    struct sk_buff *skb, bool bf)
{
	/* Some NIC TX decisions, e.g loopback, are based on the packet
	 * headers and occur before the data gather.
	 * Therefore these headers must be copied into the WQE
	 */
#define MLX5E_MIN_INLINE ETH_HLEN

	if (bf) {
		u16 ihs = skb_headlen(skb);

		if (skb_vlan_tag_present(skb))
			ihs += VLAN_HLEN;

		if (ihs <= sq->max_inline)
			return skb_headlen(skb);
	}

	return MLX5E_MIN_INLINE;
}

static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
					    unsigned int *skb_len,
					    unsigned int len)
{
	*skb_len -= len;
	*skb_data += len;
}

static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs,
				     unsigned char **skb_data,
				     unsigned int *skb_len)
{
	struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
	int cpy1_sz = 2 * ETH_ALEN;
	int cpy2_sz = ihs - cpy1_sz;

	memcpy(vhdr, *skb_data, cpy1_sz);
	mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
	vhdr->h_vlan_proto = skb->vlan_proto;
	vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
	memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
	mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
}

static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq *sq, struct sk_buff *skb)
{
	struct mlx5_wq_cyc       *wq   = &sq->wq;

	u16 pi = sq->pc & wq->sz_m1;
	struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
	struct mlx5e_tx_wqe_info *wi   = &sq->wqe_info[pi];

	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
	struct mlx5_wqe_data_seg *dseg;

	unsigned char *skb_data = skb->data;
	unsigned int skb_len = skb->len;
	u8  opcode = MLX5_OPCODE_SEND;
	dma_addr_t dma_addr = 0;
	unsigned int num_bytes;
	bool bf = false;
	u16 headlen;
	u16 ds_cnt;
	u16 ihs;
	int i;

	memset(wqe, 0, sizeof(*wqe));

	if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
		eseg->cs_flags	= MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
	else
		sq->stats.csum_offload_none++;

	if (sq->cc != sq->prev_cc) {
		sq->prev_cc = sq->cc;
		sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
	}

	if (skb_is_gso(skb)) {
		u32 payload_len;

		eseg->mss    = cpu_to_be16(skb_shinfo(skb)->gso_size);
		opcode       = MLX5_OPCODE_LSO;
		ihs          = skb_transport_offset(skb) + tcp_hdrlen(skb);
		payload_len  = skb->len - ihs;
		num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
		sq->stats.tso_packets++;
		sq->stats.tso_bytes += payload_len;
	} else {
		bf = sq->bf_budget &&
		     !skb->xmit_more &&
		     !skb_shinfo(skb)->nr_frags;
		ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
		num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
	}

	wi->num_bytes = num_bytes;

	if (skb_vlan_tag_present(skb)) {
		mlx5e_insert_vlan(eseg->inline_hdr_start, skb, ihs, &skb_data,
				  &skb_len);
		ihs += VLAN_HLEN;
	} else {
		memcpy(eseg->inline_hdr_start, skb_data, ihs);
		mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
	}

	eseg->inline_hdr_sz = cpu_to_be16(ihs);

	ds_cnt  = sizeof(*wqe) / MLX5_SEND_WQE_DS;
	ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
			       MLX5_SEND_WQE_DS);
	dseg    = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;

	wi->num_dma = 0;

	headlen = skb_len - skb->data_len;
	if (headlen) {
		dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
					  DMA_TO_DEVICE);
		if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
			goto dma_unmap_wqe_err;

		dseg->addr       = cpu_to_be64(dma_addr);
		dseg->lkey       = sq->mkey_be;
		dseg->byte_count = cpu_to_be32(headlen);

		mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
		wi->num_dma++;

		dseg++;
	}

	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
		struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
		int fsz = skb_frag_size(frag);

		dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
					    DMA_TO_DEVICE);
		if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
			goto dma_unmap_wqe_err;

		dseg->addr       = cpu_to_be64(dma_addr);
		dseg->lkey       = sq->mkey_be;
		dseg->byte_count = cpu_to_be32(fsz);

		mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
		wi->num_dma++;

		dseg++;
	}

	ds_cnt += wi->num_dma;

	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
	cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | ds_cnt);

	sq->skb[pi] = skb;

	wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
	sq->pc += wi->num_wqebbs;

	netdev_tx_sent_queue(sq->txq, wi->num_bytes);

	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;

	if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
		netif_tx_stop_queue(sq->txq);
		sq->stats.stopped++;
	}

	if (!skb->xmit_more || netif_xmit_stopped(sq->txq)) {
		int bf_sz = 0;

		if (bf && sq->uar_bf_map)
			bf_sz = wi->num_wqebbs << 3;

		cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
		mlx5e_tx_notify_hw(sq, wqe, bf_sz);
	}

	/* fill sq edge with nops to avoid wqe wrap around */
	while ((sq->pc & wq->sz_m1) > sq->edge)
		mlx5e_send_nop(sq, false);

	sq->bf_budget = bf ? sq->bf_budget - 1 : 0;

	sq->stats.packets++;
	sq->stats.bytes += num_bytes;
	return NETDEV_TX_OK;

dma_unmap_wqe_err:
	sq->stats.dropped++;
	mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);

	dev_kfree_skb_any(skb);

	return NETDEV_TX_OK;
}

netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct mlx5e_priv *priv = netdev_priv(dev);
	struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];

	return mlx5e_sq_xmit(sq, skb);
}

bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq)
{
	struct mlx5e_sq *sq;
	u32 dma_fifo_cc;
	u32 nbytes;
	u16 npkts;
	u16 sqcc;
	int i;

	sq = container_of(cq, struct mlx5e_sq, cq);

	npkts = 0;
	nbytes = 0;

	/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
	 * otherwise a cq overrun may occur
	 */
	sqcc = sq->cc;

	/* avoid dirtying sq cache line every cqe */
	dma_fifo_cc = sq->dma_fifo_cc;

	for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
		struct mlx5_cqe64 *cqe;
		u16 wqe_counter;
		bool last_wqe;

		cqe = mlx5e_get_cqe(cq);
		if (!cqe)
			break;

		mlx5_cqwq_pop(&cq->wq);

		wqe_counter = be16_to_cpu(cqe->wqe_counter);

		do {
			struct mlx5e_tx_wqe_info *wi;
			struct sk_buff *skb;
			u16 ci;
			int j;

			last_wqe = (sqcc == wqe_counter);

			ci = sqcc & sq->wq.sz_m1;
			skb = sq->skb[ci];
			wi = &sq->wqe_info[ci];

			if (unlikely(!skb)) { /* nop */
				sq->stats.nop++;
				sqcc++;
				continue;
			}

			if (unlikely(skb_shinfo(skb)->tx_flags &
				     SKBTX_HW_TSTAMP)) {
				struct skb_shared_hwtstamps hwts = {};

				mlx5e_fill_hwstamp(sq->tstamp,
						   get_cqe_ts(cqe), &hwts);
				skb_tstamp_tx(skb, &hwts);
			}

			for (j = 0; j < wi->num_dma; j++) {
				struct mlx5e_sq_dma *dma =
					mlx5e_dma_get(sq, dma_fifo_cc++);

				mlx5e_tx_dma_unmap(sq->pdev, dma);
			}

			npkts++;
			nbytes += wi->num_bytes;
			sqcc += wi->num_wqebbs;
			dev_kfree_skb(skb);
		} while (!last_wqe);
	}

	mlx5_cqwq_update_db_record(&cq->wq);

	/* ensure cq space is freed before enabling more cqes */
	wmb();

	sq->dma_fifo_cc = dma_fifo_cc;
	sq->cc = sqcc;

	netdev_tx_completed_queue(sq->txq, npkts, nbytes);

	if (netif_tx_queue_stopped(sq->txq) &&
	    mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
	    likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
				netif_tx_wake_queue(sq->txq);
				sq->stats.wake++;
	}

	return (i == MLX5E_TX_CQ_POLL_BUDGET);
}
Commit	Line	Data
e586b3b0 AV	1	/*
	2	* Copyright (c) 2015, Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/tcp.h>
	34	#include <linux/if_vlan.h>
	35	#include "en.h"
	36
12be4b21 SM	37	#define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
	38	#define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
	39	MLX5E_SQ_NOPS_ROOM)
	40
	41	void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
	42	{
	43	struct mlx5_wq_cyc *wq = &sq->wq;
	44
	45	u16 pi = sq->pc & wq->sz_m1;
	46	struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
	47
	48	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	49
	50	memset(cseg, 0, sizeof(*cseg));
	51
	52	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) \| MLX5_OPCODE_NOP);
	53	cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) \| 0x01);
	54
	55	sq->skb[pi] = NULL;
	56	sq->pc++;
	57
	58	if (notify_hw) {
	59	cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
88a85f99	60	mlx5e_tx_notify_hw(sq, wqe, 0);
12be4b21 SM	61	}
	62	}
	63
d4e28cbd AS	64	static inline void mlx5e_tx_dma_unmap(struct device *pdev,
d4e28cbd AS	65	struct mlx5e_sq_dma *dma)
e586b3b0	66	{
d4e28cbd AS	67	switch (dma->type) {
	68	case MLX5E_DMA_MAP_SINGLE:
	69	dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
	70	break;
	71	case MLX5E_DMA_MAP_PAGE:
	72	dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
	73	break;
	74	default:
	75	WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
e586b3b0 AV	76	}
	77	}
	78
d4e28cbd AS	79	static inline void mlx5e_dma_push(struct mlx5e_sq *sq,
	80	dma_addr_t addr,
	81	u32 size,
	82	enum mlx5e_dma_map_type map_type)
e586b3b0 AV	83	{
	84	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
	85	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
d4e28cbd	86	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].type = map_type;
e586b3b0 AV	87	sq->dma_fifo_pc++;
	88	}
	89
d4e28cbd AS	90	static inline struct mlx5e_sq_dma mlx5e_dma_get(struct mlx5e_sq sq, u32 i)
	91	{
	92	return &sq->dma_fifo[i & sq->dma_fifo_mask];
	93	}
	94
34802a42	95	static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, u8 num_dma)
e586b3b0	96	{
d4e28cbd AS	97	int i;
d4e28cbd AS	98
34802a42	99	for (i = 0; i < num_dma; i++) {
d4e28cbd AS	100	struct mlx5e_sq_dma *last_pushed_dma =
	101	mlx5e_dma_get(sq, --sq->dma_fifo_pc);
	102
	103	mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
	104	}
e586b3b0 AV	105	}
	106
	107	u16 mlx5e_select_queue(struct net_device dev, struct sk_buff skb,
	108	void *accel_priv, select_queue_fallback_t fallback)
	109	{
	110	struct mlx5e_priv *priv = netdev_priv(dev);
	111	int channel_ix = fallback(dev, skb);
	112	int up = skb_vlan_tag_present(skb) ?
	113	skb->vlan_tci >> VLAN_PRIO_SHIFT :
	114	priv->default_vlan_prio;
	115	int tc = netdev_get_prio_tc_map(dev, up);
	116
5283af89	117	return priv->channeltc_to_txq_map[channel_ix][tc];
e586b3b0 AV	118	}
	119
	120	static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
88a85f99	121	struct sk_buff *skb, bool bf)
e586b3b0	122	{
58d52291 AS	123	/* Some NIC TX decisions, e.g loopback, are based on the packet
	124	* headers and occur before the data gather.
	125	* Therefore these headers must be copied into the WQE
	126	*/
3ea4891d	127	#define MLX5E_MIN_INLINE ETH_HLEN
58d52291	128
ba6c4c09 SM	129	if (bf) {
	130	u16 ihs = skb_headlen(skb);
	131
	132	if (skb_vlan_tag_present(skb))
	133	ihs += VLAN_HLEN;
	134
	135	if (ihs <= sq->max_inline)
	136	return skb_headlen(skb);
	137	}
58d52291	138
e586b3b0 AV	139	return MLX5E_MIN_INLINE;
	140	}
	141
34802a42 AS	142	static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
	143	unsigned int *skb_len,
	144	unsigned int len)
	145	{
	146	*skb_len -= len;
	147	*skb_data += len;
	148	}
	149
	150	static inline void mlx5e_insert_vlan(void start, struct sk_buff skb, u16 ihs,
	151	unsigned char **skb_data,
	152	unsigned int *skb_len)
e4cf27bd AS	153	{
	154	struct vlan_ethhdr vhdr = (struct vlan_ethhdr )start;
	155	int cpy1_sz = 2 * ETH_ALEN;
3ea4891d	156	int cpy2_sz = ihs - cpy1_sz;
e4cf27bd	157
34802a42 AS	158	memcpy(vhdr, *skb_data, cpy1_sz);
34802a42 AS	159	mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
e4cf27bd AS	160	vhdr->h_vlan_proto = skb->vlan_proto;
e4cf27bd AS	161	vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
34802a42 AS	162	memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
34802a42 AS	163	mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
e4cf27bd AS	164	}
e4cf27bd AS	165
e586b3b0 AV	166	static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq sq, struct sk_buff skb)
	167	{
	168	struct mlx5_wq_cyc *wq = &sq->wq;
	169
	170	u16 pi = sq->pc & wq->sz_m1;
	171	struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
34802a42	172	struct mlx5e_tx_wqe_info *wi = &sq->wqe_info[pi];
e586b3b0 AV	173
	174	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	175	struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
	176	struct mlx5_wqe_data_seg *dseg;
	177
34802a42 AS	178	unsigned char *skb_data = skb->data;
34802a42 AS	179	unsigned int skb_len = skb->len;
e586b3b0 AV	180	u8 opcode = MLX5_OPCODE_SEND;
e586b3b0 AV	181	dma_addr_t dma_addr = 0;
b081da5e	182	unsigned int num_bytes;
88a85f99	183	bool bf = false;
e586b3b0 AV	184	u16 headlen;
	185	u16 ds_cnt;
	186	u16 ihs;
	187	int i;
	188
	189	memset(wqe, 0, sizeof(*wqe));
	190
	191	if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
	192	eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM \| MLX5_ETH_WQE_L4_CSUM;
	193	else
	194	sq->stats.csum_offload_none++;
	195
88a85f99 AS	196	if (sq->cc != sq->prev_cc) {
	197	sq->prev_cc = sq->cc;
	198	sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
	199	}
	200
e586b3b0 AV	201	if (skb_is_gso(skb)) {
e586b3b0 AV	202	u32 payload_len;
e586b3b0 AV	203
	204	eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
	205	opcode = MLX5_OPCODE_LSO;
	206	ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
	207	payload_len = skb->len - ihs;
b081da5e	208	num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
e586b3b0 AV	209	sq->stats.tso_packets++;
	210	sq->stats.tso_bytes += payload_len;
	211	} else {
88a85f99 AS	212	bf = sq->bf_budget &&
	213	!skb->xmit_more &&
	214	!skb_shinfo(skb)->nr_frags;
	215	ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
b081da5e	216	num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
e586b3b0 AV	217	}
e586b3b0 AV	218
b081da5e GP	219	wi->num_bytes = num_bytes;
b081da5e GP	220
e4cf27bd	221	if (skb_vlan_tag_present(skb)) {
34802a42 AS	222	mlx5e_insert_vlan(eseg->inline_hdr_start, skb, ihs, &skb_data,
34802a42 AS	223	&skb_len);
3ea4891d	224	ihs += VLAN_HLEN;
e4cf27bd	225	} else {
34802a42 AS	226	memcpy(eseg->inline_hdr_start, skb_data, ihs);
34802a42 AS	227	mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
e4cf27bd	228	}
e586b3b0	229
8ca56ce3	230	eseg->inline_hdr_sz = cpu_to_be16(ihs);
e586b3b0 AV	231
	232	ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
	233	ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
	234	MLX5_SEND_WQE_DS);
	235	dseg = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;
	236
34802a42	237	wi->num_dma = 0;
e586b3b0	238
34802a42	239	headlen = skb_len - skb->data_len;
e586b3b0	240	if (headlen) {
34802a42	241	dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
e586b3b0 AV	242	DMA_TO_DEVICE);
	243	if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
	244	goto dma_unmap_wqe_err;
	245
	246	dseg->addr = cpu_to_be64(dma_addr);
	247	dseg->lkey = sq->mkey_be;
	248	dseg->byte_count = cpu_to_be32(headlen);
	249
d4e28cbd	250	mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
34802a42	251	wi->num_dma++;
e586b3b0 AV	252
	253	dseg++;
	254	}
	255
	256	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
	257	struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
	258	int fsz = skb_frag_size(frag);
	259
	260	dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
	261	DMA_TO_DEVICE);
	262	if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
	263	goto dma_unmap_wqe_err;
	264
	265	dseg->addr = cpu_to_be64(dma_addr);
	266	dseg->lkey = sq->mkey_be;
	267	dseg->byte_count = cpu_to_be32(fsz);
	268
d4e28cbd	269	mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
34802a42	270	wi->num_dma++;
e586b3b0 AV	271
	272	dseg++;
	273	}
	274
34802a42	275	ds_cnt += wi->num_dma;
e586b3b0	276
8ca56ce3 AS	277	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) \| opcode);
8ca56ce3 AS	278	cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) \| ds_cnt);
e586b3b0 AV	279
	280	sq->skb[pi] = skb;
	281
34802a42 AS	282	wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
34802a42 AS	283	sq->pc += wi->num_wqebbs;
e586b3b0	284
34802a42	285	netdev_tx_sent_queue(sq->txq, wi->num_bytes);
e586b3b0	286
ef9814de EBE	287	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
	288	skb_shinfo(skb)->tx_flags \|= SKBTX_IN_PROGRESS;
	289
12be4b21	290	if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
e586b3b0 AV	291	netif_tx_stop_queue(sq->txq);
	292	sq->stats.stopped++;
	293	}
	294
059ba072	295	if (!skb->xmit_more \|\| netif_xmit_stopped(sq->txq)) {
88a85f99 AS	296	int bf_sz = 0;
	297
	298	if (bf && sq->uar_bf_map)
34802a42	299	bf_sz = wi->num_wqebbs << 3;
88a85f99	300
059ba072	301	cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
88a85f99	302	mlx5e_tx_notify_hw(sq, wqe, bf_sz);
059ba072	303	}
e586b3b0	304
12be4b21 SM	305	/* fill sq edge with nops to avoid wqe wrap around */
	306	while ((sq->pc & wq->sz_m1) > sq->edge)
	307	mlx5e_send_nop(sq, false);
	308
88a85f99 AS	309	sq->bf_budget = bf ? sq->bf_budget - 1 : 0;
88a85f99 AS	310
e586b3b0	311	sq->stats.packets++;
b081da5e	312	sq->stats.bytes += num_bytes;
e586b3b0 AV	313	return NETDEV_TX_OK;
	314
	315	dma_unmap_wqe_err:
	316	sq->stats.dropped++;
34802a42	317	mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);
e586b3b0 AV	318
	319	dev_kfree_skb_any(skb);
	320
	321	return NETDEV_TX_OK;
	322	}
	323
	324	netdev_tx_t mlx5e_xmit(struct sk_buff skb, struct net_device dev)
	325	{
	326	struct mlx5e_priv *priv = netdev_priv(dev);
03289b88	327	struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];
e586b3b0 AV	328
	329	return mlx5e_sq_xmit(sq, skb);
	330	}
	331
	332	bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq)
	333	{
	334	struct mlx5e_sq *sq;
	335	u32 dma_fifo_cc;
	336	u32 nbytes;
	337	u16 npkts;
	338	u16 sqcc;
	339	int i;
	340
e3391054	341	sq = container_of(cq, struct mlx5e_sq, cq);
e586b3b0 AV	342
	343	npkts = 0;
	344	nbytes = 0;
	345
	346	/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
	347	* otherwise a cq overrun may occur
	348	*/
	349	sqcc = sq->cc;
	350
	351	/* avoid dirtying sq cache line every cqe */
	352	dma_fifo_cc = sq->dma_fifo_cc;
	353
	354	for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
	355	struct mlx5_cqe64 *cqe;
059ba072 AS	356	u16 wqe_counter;
059ba072 AS	357	bool last_wqe;
e586b3b0 AV	358
	359	cqe = mlx5e_get_cqe(cq);
	360	if (!cqe)
	361	break;
	362
a1f5a1a8 AS	363	mlx5_cqwq_pop(&cq->wq);
a1f5a1a8 AS	364
059ba072 AS	365	wqe_counter = be16_to_cpu(cqe->wqe_counter);
	366
	367	do {
34802a42	368	struct mlx5e_tx_wqe_info *wi;
059ba072 AS	369	struct sk_buff *skb;
	370	u16 ci;
	371	int j;
	372
	373	last_wqe = (sqcc == wqe_counter);
	374
	375	ci = sqcc & sq->wq.sz_m1;
	376	skb = sq->skb[ci];
34802a42	377	wi = &sq->wqe_info[ci];
e586b3b0	378
059ba072 AS	379	if (unlikely(!skb)) { /* nop */
	380	sq->stats.nop++;
	381	sqcc++;
	382	continue;
	383	}
e586b3b0	384
ef9814de EBE	385	if (unlikely(skb_shinfo(skb)->tx_flags &
	386	SKBTX_HW_TSTAMP)) {
	387	struct skb_shared_hwtstamps hwts = {};
	388
	389	mlx5e_fill_hwstamp(sq->tstamp,
	390	get_cqe_ts(cqe), &hwts);
	391	skb_tstamp_tx(skb, &hwts);
	392	}
	393
34802a42	394	for (j = 0; j < wi->num_dma; j++) {
d4e28cbd AS	395	struct mlx5e_sq_dma *dma =
d4e28cbd AS	396	mlx5e_dma_get(sq, dma_fifo_cc++);
e586b3b0	397
d4e28cbd	398	mlx5e_tx_dma_unmap(sq->pdev, dma);
059ba072	399	}
e586b3b0	400
059ba072	401	npkts++;
34802a42 AS	402	nbytes += wi->num_bytes;
34802a42 AS	403	sqcc += wi->num_wqebbs;
059ba072 AS	404	dev_kfree_skb(skb);
059ba072 AS	405	} while (!last_wqe);
e586b3b0 AV	406	}
	407
	408	mlx5_cqwq_update_db_record(&cq->wq);
	409
	410	/* ensure cq space is freed before enabling more cqes */
	411	wmb();
	412
	413	sq->dma_fifo_cc = dma_fifo_cc;
	414	sq->cc = sqcc;
	415
	416	netdev_tx_completed_queue(sq->txq, npkts, nbytes);
	417
	418	if (netif_tx_queue_stopped(sq->txq) &&
12be4b21	419	mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
e586b3b0 AV	420	likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
	421	netif_tx_wake_queue(sq->txq);
	422	sq->stats.wake++;
	423	}
e586b3b0	424
59a7c2fd	425	return (i == MLX5E_TX_CQ_POLL_BUDGET);
e586b3b0	426	}