[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c

/*
 * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <asm-generic/kmap_types.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/io-mapping.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/cq.h>
#include <linux/mlx5/qp.h>
#include <linux/mlx5/srq.h>
#include <linux/debugfs.h>
#include "mlx5_core.h"

#define DRIVER_NAME "mlx5_core"
#define DRIVER_VERSION "2.2-1"
#define DRIVER_RELDATE	"Feb 2014"

MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_VERSION(DRIVER_VERSION);

int mlx5_core_debug_mask;
module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");

struct workqueue_struct *mlx5_core_wq;

static int set_dma_caps(struct pci_dev *pdev)
{
	int err;

	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
	if (err) {
		dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (err) {
			dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
			return err;
		}
	}

	err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
	if (err) {
		dev_warn(&pdev->dev,
			 "Warning: couldn't set 64-bit consistent PCI DMA mask.\n");
		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
		if (err) {
			dev_err(&pdev->dev,
				"Can't set consistent PCI DMA mask, aborting.\n");
			return err;
		}
	}

	dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
	return err;
}

static int request_bar(struct pci_dev *pdev)
{
	int err = 0;

	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
		dev_err(&pdev->dev, "Missing registers BAR, aborting.\n");
		return -ENODEV;
	}

	err = pci_request_regions(pdev, DRIVER_NAME);
	if (err)
		dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");

	return err;
}

static void release_bar(struct pci_dev *pdev)
{
	pci_release_regions(pdev);
}

static int mlx5_enable_msix(struct mlx5_core_dev *dev)
{
	struct mlx5_eq_table *table = &dev->priv.eq_table;
	int num_eqs = 1 << dev->caps.log_max_eq;
	int nvec;
	int i;

	nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
	nvec = min_t(int, nvec, num_eqs);
	if (nvec <= MLX5_EQ_VEC_COMP_BASE)
		return -ENOMEM;

	table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
	if (!table->msix_arr)
		return -ENOMEM;

	for (i = 0; i < nvec; i++)
		table->msix_arr[i].entry = i;

	nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
				     MLX5_EQ_VEC_COMP_BASE, nvec);
	if (nvec < 0)
		return nvec;

	table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;

	return 0;
}

static void mlx5_disable_msix(struct mlx5_core_dev *dev)
{
	struct mlx5_eq_table *table = &dev->priv.eq_table;

	pci_disable_msix(dev->pdev);
	kfree(table->msix_arr);
}

struct mlx5_reg_host_endianess {
	u8	he;
	u8      rsvd[15];
};


#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))

enum {
	MLX5_CAP_BITS_RW_MASK	= CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
				  CAP_MASK(MLX5_CAP_OFF_DCT, 1),
};

/* selectively copy writable fields clearing any reserved area
 */
static void copy_rw_fields(struct mlx5_hca_cap *to, struct mlx5_hca_cap *from)
{
	u64 v64;

	to->log_max_qp = from->log_max_qp & 0x1f;
	to->log_max_ra_req_dc = from->log_max_ra_req_dc & 0x3f;
	to->log_max_ra_res_dc = from->log_max_ra_res_dc & 0x3f;
	to->log_max_ra_req_qp = from->log_max_ra_req_qp & 0x3f;
	to->log_max_ra_res_qp = from->log_max_ra_res_qp & 0x3f;
	to->log_max_atomic_size_qp = from->log_max_atomic_size_qp;
	to->log_max_atomic_size_dc = from->log_max_atomic_size_dc;
	v64 = be64_to_cpu(from->flags) & MLX5_CAP_BITS_RW_MASK;
	to->flags = cpu_to_be64(v64);
}

enum {
	HCA_CAP_OPMOD_GET_MAX	= 0,
	HCA_CAP_OPMOD_GET_CUR	= 1,
};

static int handle_hca_cap(struct mlx5_core_dev *dev)
{
	struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
	struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL;
	struct mlx5_cmd_query_hca_cap_mbox_in query_ctx;
	struct mlx5_cmd_set_hca_cap_mbox_out set_out;
	u64 flags;
	int err;

	memset(&query_ctx, 0, sizeof(query_ctx));
	query_out = kzalloc(sizeof(*query_out), GFP_KERNEL);
	if (!query_out)
		return -ENOMEM;

	set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL);
	if (!set_ctx) {
		err = -ENOMEM;
		goto query_ex;
	}

	query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
	query_ctx.hdr.opmod  = cpu_to_be16(HCA_CAP_OPMOD_GET_CUR);
	err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
				 query_out, sizeof(*query_out));
	if (err)
		goto query_ex;

	err = mlx5_cmd_status_to_err(&query_out->hdr);
	if (err) {
		mlx5_core_warn(dev, "query hca cap failed, %d\n", err);
		goto query_ex;
	}

	copy_rw_fields(&set_ctx->hca_cap, &query_out->hca_cap);

	if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
		set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;

	flags = be64_to_cpu(query_out->hca_cap.flags);
	/* disable checksum */
	flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;

	set_ctx->hca_cap.flags = cpu_to_be64(flags);
	memset(&set_out, 0, sizeof(set_out));
	set_ctx->hca_cap.log_uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12);
	set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP);
	err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx),
				 &set_out, sizeof(set_out));
	if (err) {
		mlx5_core_warn(dev, "set hca cap failed, %d\n", err);
		goto query_ex;
	}

	err = mlx5_cmd_status_to_err(&set_out.hdr);
	if (err)
		goto query_ex;

query_ex:
	kfree(query_out);
	kfree(set_ctx);

	return err;
}

static int set_hca_ctrl(struct mlx5_core_dev *dev)
{
	struct mlx5_reg_host_endianess he_in;
	struct mlx5_reg_host_endianess he_out;
	int err;

	memset(&he_in, 0, sizeof(he_in));
	he_in.he = MLX5_SET_HOST_ENDIANNESS;
	err = mlx5_core_access_reg(dev, &he_in,  sizeof(he_in),
					&he_out, sizeof(he_out),
					MLX5_REG_HOST_ENDIANNESS, 0, 1);
	return err;
}

static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
{
	int err;
	struct mlx5_enable_hca_mbox_in in;
	struct mlx5_enable_hca_mbox_out out;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		return mlx5_cmd_status_to_err(&out.hdr);

	return 0;
}

static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
{
	int err;
	struct mlx5_disable_hca_mbox_in in;
	struct mlx5_disable_hca_mbox_out out;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		return mlx5_cmd_status_to_err(&out.hdr);

	return 0;
}

int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
{
	struct mlx5_priv *priv = &dev->priv;
	int err;

	dev->pdev = pdev;
	pci_set_drvdata(dev->pdev, dev);
	strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
	priv->name[MLX5_MAX_NAME_LEN - 1] = 0;

	mutex_init(&priv->pgdir_mutex);
	INIT_LIST_HEAD(&priv->pgdir_list);
	spin_lock_init(&priv->mkey_lock);

	priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
	if (!priv->dbg_root)
		return -ENOMEM;

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
		goto err_dbg;
	}

	err = request_bar(pdev);
	if (err) {
		dev_err(&pdev->dev, "error requesting BARs, aborting.\n");
		goto err_disable;
	}

	pci_set_master(pdev);

	err = set_dma_caps(pdev);
	if (err) {
		dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
		goto err_clr_master;
	}

	dev->iseg_base = pci_resource_start(dev->pdev, 0);
	dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
	if (!dev->iseg) {
		err = -ENOMEM;
		dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
		goto err_clr_master;
	}
	dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
		 fw_rev_min(dev), fw_rev_sub(dev));

	err = mlx5_cmd_init(dev);
	if (err) {
		dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
		goto err_unmap;
	}

	mlx5_pagealloc_init(dev);

	err = mlx5_core_enable_hca(dev);
	if (err) {
		dev_err(&pdev->dev, "enable hca failed\n");
		goto err_pagealloc_cleanup;
	}

	err = mlx5_satisfy_startup_pages(dev, 1);
	if (err) {
		dev_err(&pdev->dev, "failed to allocate boot pages\n");
		goto err_disable_hca;
	}

	err = set_hca_ctrl(dev);
	if (err) {
		dev_err(&pdev->dev, "set_hca_ctrl failed\n");
		goto reclaim_boot_pages;
	}

	err = handle_hca_cap(dev);
	if (err) {
		dev_err(&pdev->dev, "handle_hca_cap failed\n");
		goto reclaim_boot_pages;
	}

	err = mlx5_satisfy_startup_pages(dev, 0);
	if (err) {
		dev_err(&pdev->dev, "failed to allocate init pages\n");
		goto reclaim_boot_pages;
	}

	err = mlx5_pagealloc_start(dev);
	if (err) {
		dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
		goto reclaim_boot_pages;
	}

	err = mlx5_cmd_init_hca(dev);
	if (err) {
		dev_err(&pdev->dev, "init hca failed\n");
		goto err_pagealloc_stop;
	}

	mlx5_start_health_poll(dev);

	err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
	if (err) {
		dev_err(&pdev->dev, "query hca failed\n");
		goto err_stop_poll;
	}

	err = mlx5_cmd_query_adapter(dev);
	if (err) {
		dev_err(&pdev->dev, "query adapter failed\n");
		goto err_stop_poll;
	}

	err = mlx5_enable_msix(dev);
	if (err) {
		dev_err(&pdev->dev, "enable msix failed\n");
		goto err_stop_poll;
	}

	err = mlx5_eq_init(dev);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize eq\n");
		goto disable_msix;
	}

	err = mlx5_alloc_uuars(dev, &priv->uuari);
	if (err) {
		dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
		goto err_eq_cleanup;
	}

	err = mlx5_start_eqs(dev);
	if (err) {
		dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
		goto err_free_uar;
	}

	MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);

	mlx5_init_cq_table(dev);
	mlx5_init_qp_table(dev);
	mlx5_init_srq_table(dev);
	mlx5_init_mr_table(dev);

	return 0;

err_free_uar:
	mlx5_free_uuars(dev, &priv->uuari);

err_eq_cleanup:
	mlx5_eq_cleanup(dev);

disable_msix:
	mlx5_disable_msix(dev);

err_stop_poll:
	mlx5_stop_health_poll(dev);
	if (mlx5_cmd_teardown_hca(dev)) {
		dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
		return err;
	}

err_pagealloc_stop:
	mlx5_pagealloc_stop(dev);

reclaim_boot_pages:
	mlx5_reclaim_startup_pages(dev);

err_disable_hca:
	mlx5_core_disable_hca(dev);

err_pagealloc_cleanup:
	mlx5_pagealloc_cleanup(dev);
	mlx5_cmd_cleanup(dev);

err_unmap:
	iounmap(dev->iseg);

err_clr_master:
	pci_clear_master(dev->pdev);
	release_bar(dev->pdev);

err_disable:
	pci_disable_device(dev->pdev);

err_dbg:
	debugfs_remove(priv->dbg_root);
	return err;
}
EXPORT_SYMBOL(mlx5_dev_init);

void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
{
	struct mlx5_priv *priv = &dev->priv;

	mlx5_cleanup_srq_table(dev);
	mlx5_cleanup_qp_table(dev);
	mlx5_cleanup_cq_table(dev);
	mlx5_stop_eqs(dev);
	mlx5_free_uuars(dev, &priv->uuari);
	mlx5_eq_cleanup(dev);
	mlx5_disable_msix(dev);
	mlx5_stop_health_poll(dev);
	if (mlx5_cmd_teardown_hca(dev)) {
		dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
		return;
	}
	mlx5_pagealloc_stop(dev);
	mlx5_reclaim_startup_pages(dev);
	mlx5_core_disable_hca(dev);
	mlx5_pagealloc_cleanup(dev);
	mlx5_cmd_cleanup(dev);
	iounmap(dev->iseg);
	pci_clear_master(dev->pdev);
	release_bar(dev->pdev);
	pci_disable_device(dev->pdev);
	debugfs_remove(priv->dbg_root);
}
EXPORT_SYMBOL(mlx5_dev_cleanup);

static int __init init(void)
{
	int err;

	mlx5_register_debugfs();
	mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
	if (!mlx5_core_wq) {
		err = -ENOMEM;
		goto err_debug;
	}
	mlx5_health_init();

	return 0;

err_debug:
	mlx5_unregister_debugfs();
	return err;
}

static void __exit cleanup(void)
{
	mlx5_health_cleanup();
	destroy_workqueue(mlx5_core_wq);
	mlx5_unregister_debugfs();
}

module_init(init);
module_exit(cleanup);
Commit	Line	Data
e126ba97 EC	1	/*
	2	* Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <asm-generic/kmap_types.h>
	34	#include <linux/module.h>
	35	#include <linux/init.h>
	36	#include <linux/errno.h>
	37	#include <linux/pci.h>
	38	#include <linux/dma-mapping.h>
	39	#include <linux/slab.h>
	40	#include <linux/io-mapping.h>
	41	#include <linux/mlx5/driver.h>
	42	#include <linux/mlx5/cq.h>
	43	#include <linux/mlx5/qp.h>
	44	#include <linux/mlx5/srq.h>
	45	#include <linux/debugfs.h>
	46	#include "mlx5_core.h"
	47
	48	#define DRIVER_NAME "mlx5_core"
169a1d85 AV	49	#define DRIVER_VERSION "2.2-1"
169a1d85 AV	50	#define DRIVER_RELDATE "Feb 2014"
e126ba97 EC	51
	52	MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
	53	MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
	54	MODULE_LICENSE("Dual BSD/GPL");
	55	MODULE_VERSION(DRIVER_VERSION);
	56
	57	int mlx5_core_debug_mask;
	58	module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
	59	MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
	60
	61	struct workqueue_struct *mlx5_core_wq;
	62
	63	static int set_dma_caps(struct pci_dev *pdev)
	64	{
	65	int err;
	66
	67	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
	68	if (err) {
	69	dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
	70	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	71	if (err) {
	72	dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
	73	return err;
	74	}
	75	}
	76
	77	err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
	78	if (err) {
	79	dev_warn(&pdev->dev,
	80	"Warning: couldn't set 64-bit consistent PCI DMA mask.\n");
	81	err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	82	if (err) {
	83	dev_err(&pdev->dev,
	84	"Can't set consistent PCI DMA mask, aborting.\n");
	85	return err;
	86	}
	87	}
	88
	89	dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
	90	return err;
	91	}
	92
	93	static int request_bar(struct pci_dev *pdev)
	94	{
	95	int err = 0;
	96
	97	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
	98	dev_err(&pdev->dev, "Missing registers BAR, aborting.\n");
	99	return -ENODEV;
	100	}
	101
	102	err = pci_request_regions(pdev, DRIVER_NAME);
	103	if (err)
	104	dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
	105
	106	return err;
	107	}
	108
	109	static void release_bar(struct pci_dev *pdev)
	110	{
	111	pci_release_regions(pdev);
	112	}
	113
	114	static int mlx5_enable_msix(struct mlx5_core_dev *dev)
115	{
116	struct mlx5_eq_table *table = &dev->priv.eq_table;
117	int num_eqs = 1 << dev->caps.log_max_eq;
118	int nvec;
e126ba97 EC	119	int i;
	120
	121	nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
	122	nvec = min_t(int, nvec, num_eqs);
	123	if (nvec <= MLX5_EQ_VEC_COMP_BASE)
	124	return -ENOMEM;
	125
	126	table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
	127	if (!table->msix_arr)
	128	return -ENOMEM;
	129
	130	for (i = 0; i < nvec; i++)
	131	table->msix_arr[i].entry = i;
	132
f3c9407b AG	133	nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
	134	MLX5_EQ_VEC_COMP_BASE, nvec);
	135	if (nvec < 0)
	136	return nvec;
e126ba97	137
f3c9407b	138	table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97 EC	139
	140	return 0;
	141	}
	142
	143	static void mlx5_disable_msix(struct mlx5_core_dev *dev)
	144	{
	145	struct mlx5_eq_table *table = &dev->priv.eq_table;
	146
	147	pci_disable_msix(dev->pdev);
	148	kfree(table->msix_arr);
	149	}
	150
	151	struct mlx5_reg_host_endianess {
	152	u8 he;
	153	u8 rsvd[15];
	154	};
	155
87b8de49 EC	156
	157	#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
	158
	159	enum {
	160	MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) \|
	161	CAP_MASK(MLX5_CAP_OFF_DCT, 1),
	162	};
	163
	164	/* selectively copy writable fields clearing any reserved area
	165	*/
	166	static void copy_rw_fields(struct mlx5_hca_cap to, struct mlx5_hca_cap from)
	167	{
	168	u64 v64;
	169
	170	to->log_max_qp = from->log_max_qp & 0x1f;
	171	to->log_max_ra_req_dc = from->log_max_ra_req_dc & 0x3f;
	172	to->log_max_ra_res_dc = from->log_max_ra_res_dc & 0x3f;
	173	to->log_max_ra_req_qp = from->log_max_ra_req_qp & 0x3f;
	174	to->log_max_ra_res_qp = from->log_max_ra_res_qp & 0x3f;
	175	to->log_max_atomic_size_qp = from->log_max_atomic_size_qp;
	176	to->log_max_atomic_size_dc = from->log_max_atomic_size_dc;
	177	v64 = be64_to_cpu(from->flags) & MLX5_CAP_BITS_RW_MASK;
	178	to->flags = cpu_to_be64(v64);
	179	}
	180
	181	enum {
	182	HCA_CAP_OPMOD_GET_MAX = 0,
	183	HCA_CAP_OPMOD_GET_CUR = 1,
	184	};
	185
e126ba97 EC	186	static int handle_hca_cap(struct mlx5_core_dev *dev)
	187	{
	188	struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
	189	struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL;
	190	struct mlx5_cmd_query_hca_cap_mbox_in query_ctx;
	191	struct mlx5_cmd_set_hca_cap_mbox_out set_out;
e126ba97	192	u64 flags;
e126ba97 EC	193	int err;
	194
	195	memset(&query_ctx, 0, sizeof(query_ctx));
	196	query_out = kzalloc(sizeof(*query_out), GFP_KERNEL);
	197	if (!query_out)
	198	return -ENOMEM;
	199
	200	set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL);
	201	if (!set_ctx) {
	202	err = -ENOMEM;
	203	goto query_ex;
	204	}
	205
	206	query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
87b8de49	207	query_ctx.hdr.opmod = cpu_to_be16(HCA_CAP_OPMOD_GET_CUR);
e126ba97 EC	208	err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
	209	query_out, sizeof(*query_out));
	210	if (err)
	211	goto query_ex;
	212
	213	err = mlx5_cmd_status_to_err(&query_out->hdr);
	214	if (err) {
	215	mlx5_core_warn(dev, "query hca cap failed, %d\n", err);
	216	goto query_ex;
	217	}
	218
87b8de49	219	copy_rw_fields(&set_ctx->hca_cap, &query_out->hca_cap);
e126ba97	220
e126ba97 EC	221	if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
	222	set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;
	223
c1868b82 EC	224	flags = be64_to_cpu(query_out->hca_cap.flags);
	225	/* disable checksum */
	226	flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
	227
	228	set_ctx->hca_cap.flags = cpu_to_be64(flags);
e126ba97	229	memset(&set_out, 0, sizeof(set_out));
288dde9f	230	set_ctx->hca_cap.log_uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12);
e126ba97 EC	231	set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP);
	232	err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx),
	233	&set_out, sizeof(set_out));
	234	if (err) {
	235	mlx5_core_warn(dev, "set hca cap failed, %d\n", err);
	236	goto query_ex;
	237	}
	238
	239	err = mlx5_cmd_status_to_err(&set_out.hdr);
	240	if (err)
	241	goto query_ex;
	242
e126ba97 EC	243	query_ex:
	244	kfree(query_out);
	245	kfree(set_ctx);
	246
	247	return err;
	248	}
	249
	250	static int set_hca_ctrl(struct mlx5_core_dev *dev)
	251	{
	252	struct mlx5_reg_host_endianess he_in;
	253	struct mlx5_reg_host_endianess he_out;
	254	int err;
	255
	256	memset(&he_in, 0, sizeof(he_in));
	257	he_in.he = MLX5_SET_HOST_ENDIANNESS;
	258	err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
	259	&he_out, sizeof(he_out),
	260	MLX5_REG_HOST_ENDIANNESS, 0, 1);
	261	return err;
	262	}
	263
cd23b14b EC	264	static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
	265	{
	266	int err;
	267	struct mlx5_enable_hca_mbox_in in;
	268	struct mlx5_enable_hca_mbox_out out;
	269
	270	memset(&in, 0, sizeof(in));
	271	memset(&out, 0, sizeof(out));
	272	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
	273	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	274	if (err)
	275	return err;
	276
	277	if (out.hdr.status)
	278	return mlx5_cmd_status_to_err(&out.hdr);
	279
	280	return 0;
	281	}
	282
	283	static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
	284	{
	285	int err;
	286	struct mlx5_disable_hca_mbox_in in;
	287	struct mlx5_disable_hca_mbox_out out;
	288
	289	memset(&in, 0, sizeof(in));
	290	memset(&out, 0, sizeof(out));
	291	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
	292	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	293	if (err)
	294	return err;
	295
	296	if (out.hdr.status)
	297	return mlx5_cmd_status_to_err(&out.hdr);
	298
	299	return 0;
	300	}
	301
e126ba97 EC	302	int mlx5_dev_init(struct mlx5_core_dev dev, struct pci_dev pdev)
	303	{
	304	struct mlx5_priv *priv = &dev->priv;
	305	int err;
	306
	307	dev->pdev = pdev;
	308	pci_set_drvdata(dev->pdev, dev);
	309	strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
	310	priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
	311
	312	mutex_init(&priv->pgdir_mutex);
	313	INIT_LIST_HEAD(&priv->pgdir_list);
	314	spin_lock_init(&priv->mkey_lock);
	315
	316	priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
	317	if (!priv->dbg_root)
	318	return -ENOMEM;
	319
	320	err = pci_enable_device(pdev);
	321	if (err) {
	322	dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
	323	goto err_dbg;
	324	}
	325
	326	err = request_bar(pdev);
	327	if (err) {
	328	dev_err(&pdev->dev, "error requesting BARs, aborting.\n");
	329	goto err_disable;
	330	}
	331
	332	pci_set_master(pdev);
	333
	334	err = set_dma_caps(pdev);
	335	if (err) {
	336	dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
	337	goto err_clr_master;
	338	}
	339
	340	dev->iseg_base = pci_resource_start(dev->pdev, 0);
	341	dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
	342	if (!dev->iseg) {
	343	err = -ENOMEM;
	344	dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
	345	goto err_clr_master;
	346	}
	347	dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
	348	fw_rev_min(dev), fw_rev_sub(dev));
	349
	350	err = mlx5_cmd_init(dev);
	351	if (err) {
	352	dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
	353	goto err_unmap;
	354	}
	355
	356	mlx5_pagealloc_init(dev);
cd23b14b EC	357
	358	err = mlx5_core_enable_hca(dev);
	359	if (err) {
	360	dev_err(&pdev->dev, "enable hca failed\n");
	361	goto err_pagealloc_cleanup;
	362	}
	363
	364	err = mlx5_satisfy_startup_pages(dev, 1);
	365	if (err) {
	366	dev_err(&pdev->dev, "failed to allocate boot pages\n");
	367	goto err_disable_hca;
	368	}
	369
e126ba97 EC	370	err = set_hca_ctrl(dev);
	371	if (err) {
	372	dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b	373	goto reclaim_boot_pages;
e126ba97 EC	374	}
	375
	376	err = handle_hca_cap(dev);
	377	if (err) {
	378	dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b	379	goto reclaim_boot_pages;
e126ba97 EC	380	}
e126ba97 EC	381
cd23b14b	382	err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97	383	if (err) {
cd23b14b EC	384	dev_err(&pdev->dev, "failed to allocate init pages\n");
cd23b14b EC	385	goto reclaim_boot_pages;
e126ba97 EC	386	}
	387
	388	err = mlx5_pagealloc_start(dev);
	389	if (err) {
	390	dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b	391	goto reclaim_boot_pages;
e126ba97 EC	392	}
	393
	394	err = mlx5_cmd_init_hca(dev);
	395	if (err) {
	396	dev_err(&pdev->dev, "init hca failed\n");
	397	goto err_pagealloc_stop;
	398	}
	399
	400	mlx5_start_health_poll(dev);
	401
	402	err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
	403	if (err) {
	404	dev_err(&pdev->dev, "query hca failed\n");
	405	goto err_stop_poll;
	406	}
	407
	408	err = mlx5_cmd_query_adapter(dev);
	409	if (err) {
	410	dev_err(&pdev->dev, "query adapter failed\n");
	411	goto err_stop_poll;
	412	}
	413
	414	err = mlx5_enable_msix(dev);
	415	if (err) {
	416	dev_err(&pdev->dev, "enable msix failed\n");
	417	goto err_stop_poll;
	418	}
	419
	420	err = mlx5_eq_init(dev);
	421	if (err) {
	422	dev_err(&pdev->dev, "failed to initialize eq\n");
	423	goto disable_msix;
	424	}
	425
	426	err = mlx5_alloc_uuars(dev, &priv->uuari);
	427	if (err) {
	428	dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
	429	goto err_eq_cleanup;
	430	}
	431
	432	err = mlx5_start_eqs(dev);
	433	if (err) {
	434	dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
	435	goto err_free_uar;
	436	}
	437
	438	MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
	439
	440	mlx5_init_cq_table(dev);
	441	mlx5_init_qp_table(dev);
	442	mlx5_init_srq_table(dev);
3bcdb17a	443	mlx5_init_mr_table(dev);
e126ba97 EC	444
	445	return 0;
	446
	447	err_free_uar:
	448	mlx5_free_uuars(dev, &priv->uuari);
	449
	450	err_eq_cleanup:
	451	mlx5_eq_cleanup(dev);
	452
	453	disable_msix:
	454	mlx5_disable_msix(dev);
	455
	456	err_stop_poll:
	457	mlx5_stop_health_poll(dev);
1bde6e30 EC	458	if (mlx5_cmd_teardown_hca(dev)) {
	459	dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
	460	return err;
	461	}
e126ba97 EC	462
	463	err_pagealloc_stop:
	464	mlx5_pagealloc_stop(dev);
	465
cd23b14b	466	reclaim_boot_pages:
e126ba97 EC	467	mlx5_reclaim_startup_pages(dev);
e126ba97 EC	468
cd23b14b EC	469	err_disable_hca:
	470	mlx5_core_disable_hca(dev);
	471
e126ba97 EC	472	err_pagealloc_cleanup:
	473	mlx5_pagealloc_cleanup(dev);
	474	mlx5_cmd_cleanup(dev);
	475
	476	err_unmap:
	477	iounmap(dev->iseg);
	478
	479	err_clr_master:
	480	pci_clear_master(dev->pdev);
	481	release_bar(dev->pdev);
	482
	483	err_disable:
	484	pci_disable_device(dev->pdev);
	485
	486	err_dbg:
	487	debugfs_remove(priv->dbg_root);
	488	return err;
	489	}
	490	EXPORT_SYMBOL(mlx5_dev_init);
	491
	492	void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
	493	{
	494	struct mlx5_priv *priv = &dev->priv;
	495
	496	mlx5_cleanup_srq_table(dev);
	497	mlx5_cleanup_qp_table(dev);
	498	mlx5_cleanup_cq_table(dev);
	499	mlx5_stop_eqs(dev);
	500	mlx5_free_uuars(dev, &priv->uuari);
	501	mlx5_eq_cleanup(dev);
	502	mlx5_disable_msix(dev);
	503	mlx5_stop_health_poll(dev);
1bde6e30 EC	504	if (mlx5_cmd_teardown_hca(dev)) {
	505	dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
	506	return;
	507	}
e126ba97 EC	508	mlx5_pagealloc_stop(dev);
e126ba97 EC	509	mlx5_reclaim_startup_pages(dev);
cd23b14b	510	mlx5_core_disable_hca(dev);
e126ba97 EC	511	mlx5_pagealloc_cleanup(dev);
	512	mlx5_cmd_cleanup(dev);
	513	iounmap(dev->iseg);
	514	pci_clear_master(dev->pdev);
	515	release_bar(dev->pdev);
	516	pci_disable_device(dev->pdev);
	517	debugfs_remove(priv->dbg_root);
	518	}
	519	EXPORT_SYMBOL(mlx5_dev_cleanup);
	520
	521	static int __init init(void)
	522	{
	523	int err;
	524
	525	mlx5_register_debugfs();
	526	mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
	527	if (!mlx5_core_wq) {
	528	err = -ENOMEM;
	529	goto err_debug;
	530	}
	531	mlx5_health_init();
	532
	533	return 0;
	534
e126ba97 EC	535	err_debug:
	536	mlx5_unregister_debugfs();
	537	return err;
	538	}
	539
	540	static void __exit cleanup(void)
	541	{
	542	mlx5_health_cleanup();
	543	destroy_workqueue(mlx5_core_wq);
	544	mlx5_unregister_debugfs();
	545	}
	546
	547	module_init(init);
	548	module_exit(cleanup);