projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5_core: Fix a bug in alloc_token
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/mlx5/driver.h>
42#include <linux/mlx5/cq.h>
43#include <linux/mlx5/qp.h>
44#include <linux/mlx5/srq.h>
45#include <linux/debugfs.h>
f66f049f 46#include <linux/kmod.h>
b775516b 47#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 48#include "mlx5_core.h"
49
50#define DRIVER_NAME "mlx5_core"
169a1d85
AV		 51#define DRIVER_VERSION "2.2-1"
52#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 53
54MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
56MODULE_LICENSE("Dual BSD/GPL");
57MODULE_VERSION(DRIVER_VERSION);
58
59int mlx5_core_debug_mask;
60module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
61MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
62
9603b61d
JM		 63#define MLX5_DEFAULT_PROF 2
64static int prof_sel = MLX5_DEFAULT_PROF;
65module_param_named(prof_sel, prof_sel, int, 0444);
66MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
67
e126ba97 68struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 69static LIST_HEAD(intf_list);
70static LIST_HEAD(dev_list);
71static DEFINE_MUTEX(intf_mutex);
72
73struct mlx5_device_context {
74 struct list_head list;
75 struct mlx5_interface *intf;
76 void *context;
77};
78
79static struct mlx5_profile profile[] = {
80 [0] = {
81 .mask = 0,
82 },
83 [1] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .log_max_qp = 12,
86 },
87 [2] = {
88 .mask = MLX5_PROF_MASK_QP_SIZE |
89 MLX5_PROF_MASK_MR_CACHE,
90 .log_max_qp = 17,
91 .mr_cache[0] = {
92 .size = 500,
93 .limit = 250
94 },
95 .mr_cache[1] = {
96 .size = 500,
97 .limit = 250
98 },
99 .mr_cache[2] = {
100 .size = 500,
101 .limit = 250
102 },
103 .mr_cache[3] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[4] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[5] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[6] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[7] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[8] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[9] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[10] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[11] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[12] = {
140 .size = 64,
141 .limit = 32
142 },
143 .mr_cache[13] = {
144 .size = 32,
145 .limit = 16
146 },
147 .mr_cache[14] = {
148 .size = 16,
149 .limit = 8
150 },
151 .mr_cache[15] = {
152 .size = 8,
153 .limit = 4
154 },
155 },
156};
e126ba97
EC		 157
158static int set_dma_caps(struct pci_dev *pdev)
159{
160 int err;
161
162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
163 if (err) {
1a91de28 164 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 165 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
166 if (err) {
1a91de28 167 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 168 return err;
169 }
170 }
171
172 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
173 if (err) {
174 dev_warn(&pdev->dev,
1a91de28 175 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 176 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
177 if (err) {
178 dev_err(&pdev->dev,
1a91de28 179 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 180 return err;
181 }
182 }
183
184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
185 return err;
186}
187
188static int request_bar(struct pci_dev *pdev)
189{
190 int err = 0;
191
192 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 193 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 194 return -ENODEV;
195 }
196
197 err = pci_request_regions(pdev, DRIVER_NAME);
198 if (err)
199 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
200
201 return err;
202}
203
204static void release_bar(struct pci_dev *pdev)
205{
206 pci_release_regions(pdev);
207}
208
209static int mlx5_enable_msix(struct mlx5_core_dev *dev)
210{
211 struct mlx5_eq_table *table = &dev->priv.eq_table;
c7a08ac7 212 int num_eqs = 1 << dev->caps.gen.log_max_eq;
e126ba97 213 int nvec;
e126ba97
EC		 214 int i;
215
c7a08ac7 216 nvec = dev->caps.gen.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 217 nvec = min_t(int, nvec, num_eqs);
218 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
219 return -ENOMEM;
220
221 table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
222 if (!table->msix_arr)
223 return -ENOMEM;
224
225 for (i = 0; i < nvec; i++)
226 table->msix_arr[i].entry = i;
227
f3c9407b 228 nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
3a9e161a 229 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 230 if (nvec < 0)
231 return nvec;
e126ba97 232
f3c9407b 233 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 234
235 return 0;
236}
237
238static void mlx5_disable_msix(struct mlx5_core_dev *dev)
239{
240 struct mlx5_eq_table *table = &dev->priv.eq_table;
241
242 pci_disable_msix(dev->pdev);
243 kfree(table->msix_arr);
244}
245
246struct mlx5_reg_host_endianess {
247 u8 he;
248 u8 rsvd[15];
249};
250
87b8de49
EC		 251
252#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
253
254enum {
c7a08ac7
EC		 255 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
256 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 257};
258
c7a08ac7
EC		 259static u16 to_fw_pkey_sz(u32 size)
260{
261 switch (size) {
262 case 128:
263 return 0;
264 case 256:
265 return 1;
266 case 512:
267 return 2;
268 case 1024:
269 return 3;
270 case 2048:
271 return 4;
272 case 4096:
273 return 5;
274 default:
275 pr_warn("invalid pkey table size %d\n", size);
276 return 0;
277 }
278}
279
87b8de49
EC		 280/* selectively copy writable fields clearing any reserved area
281 */
b775516b 282static void copy_rw_fields(void *to, struct mlx5_caps *from)
87b8de49 283{
b775516b 284 __be64 *flags_off = (__be64 *)MLX5_ADDR_OF(cmd_hca_cap, to, reserved_22);
87b8de49
EC		 285 u64 v64;
286
b775516b
EC		 287 MLX5_SET(cmd_hca_cap, to, log_max_qp, from->gen.log_max_qp);
288 MLX5_SET(cmd_hca_cap, to, log_max_ra_req_qp, from->gen.log_max_ra_req_qp);
289 MLX5_SET(cmd_hca_cap, to, log_max_ra_res_qp, from->gen.log_max_ra_res_qp);
290 MLX5_SET(cmd_hca_cap, to, pkey_table_size, from->gen.pkey_table_size);
b775516b 291 MLX5_SET(cmd_hca_cap, to, pkey_table_size, to_fw_pkey_sz(from->gen.pkey_table_size));
de61390c 292 MLX5_SET(cmd_hca_cap, to, log_uar_page_sz, PAGE_SHIFT - 12);
b775516b
EC		 293 v64 = from->gen.flags & MLX5_CAP_BITS_RW_MASK;
294 *flags_off = cpu_to_be64(v64);
87b8de49
EC		 295}
296
c7a08ac7
EC		 297static u16 get_pkey_table_size(int pkey)
298{
299 if (pkey > MLX5_MAX_LOG_PKEY_TABLE)
300 return 0;
87b8de49 301
c7a08ac7
EC		 302 return MLX5_MIN_PKEY_TABLE_SIZE << pkey;
303}
304
b775516b 305static void fw2drv_caps(struct mlx5_caps *caps, void *out)
e126ba97 306{
c7a08ac7 307 struct mlx5_general_caps *gen = &caps->gen;
b775516b
EC		 308
309 gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
310 gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
311 gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
312 gen->log_max_strq = MLX5_GET_PR(cmd_hca_cap, out, log_max_strq_sz);
313 gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srqs);
314 gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
315 gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
316 gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
317 gen->log_max_mkey = MLX5_GET_PR(cmd_hca_cap, out, log_max_mkey);
318 gen->log_max_eq = MLX5_GET_PR(cmd_hca_cap, out, log_max_eq);
319 gen->max_indirection = MLX5_GET_PR(cmd_hca_cap, out, max_indirection);
320 gen->log_max_mrw_sz = MLX5_GET_PR(cmd_hca_cap, out, log_max_mrw_sz);
321 gen->log_max_bsf_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_bsf_list_size);
322 gen->log_max_klm_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_klm_list_size);
323 gen->log_max_ra_req_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_dc);
324 gen->log_max_ra_res_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_dc);
325 gen->log_max_ra_req_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_qp);
326 gen->log_max_ra_res_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_qp);
327 gen->max_qp_counters = MLX5_GET_PR(cmd_hca_cap, out, max_qp_cnt);
328 gen->pkey_table_size = get_pkey_table_size(MLX5_GET_PR(cmd_hca_cap, out, pkey_table_size));
329 gen->local_ca_ack_delay = MLX5_GET_PR(cmd_hca_cap, out, local_ca_ack_delay);
330 gen->num_ports = MLX5_GET_PR(cmd_hca_cap, out, num_ports);
331 gen->log_max_msg = MLX5_GET_PR(cmd_hca_cap, out, log_max_msg);
332 gen->stat_rate_support = MLX5_GET_PR(cmd_hca_cap, out, stat_rate_support);
333 gen->flags = be64_to_cpu(*(__be64 *)MLX5_ADDR_OF(cmd_hca_cap, out, reserved_22));
c7a08ac7 334 pr_debug("flags = 0x%llx\n", gen->flags);
b775516b
EC		 335 gen->uar_sz = MLX5_GET_PR(cmd_hca_cap, out, uar_sz);
336 gen->min_log_pg_sz = MLX5_GET_PR(cmd_hca_cap, out, log_pg_sz);
337 gen->bf_reg_size = MLX5_GET_PR(cmd_hca_cap, out, bf);
338 gen->bf_reg_size = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_bf_reg_size);
339 gen->max_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq);
340 gen->max_rq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_rq);
341 gen->max_dc_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq_dc);
342 gen->max_qp_mcg = MLX5_GET_PR(cmd_hca_cap, out, max_qp_mcg);
343 gen->log_max_pd = MLX5_GET_PR(cmd_hca_cap, out, log_max_pd);
344 gen->log_max_xrcd = MLX5_GET_PR(cmd_hca_cap, out, log_max_xrcd);
345 gen->log_uar_page_sz = MLX5_GET_PR(cmd_hca_cap, out, log_uar_page_sz);
c7a08ac7
EC		 346}
347
348static const char *caps_opmod_str(u16 opmod)
349{
350 switch (opmod) {
351 case HCA_CAP_OPMOD_GET_MAX:
352 return "GET_MAX";
353 case HCA_CAP_OPMOD_GET_CUR:
354 return "GET_CUR";
355 default:
356 return "Invalid";
357 }
358}
359
360int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
361 u16 opmod)
362{
b775516b
EC		 363 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
364 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
365 void *out;
e126ba97
EC		 366 int err;
367
b775516b
EC		 368 memset(in, 0, sizeof(in));
369 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 370 if (!out)
e126ba97 371 return -ENOMEM;
b775516b
EC		 372 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
373 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
374 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
375 if (err)
376 goto query_ex;
e126ba97 377
b775516b 378 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 379 if (err) {
380 mlx5_core_warn(dev, "query max hca cap failed, %d\n", err);
e126ba97
EC		 381 goto query_ex;
382 }
c7a08ac7 383 mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
b775516b 384 fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability_struct));
c7a08ac7
EC		 385
386query_ex:
387 kfree(out);
388 return err;
389}
390
b775516b 391static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 392{
b775516b 393 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 394 int err;
395
b775516b 396 memset(out, 0, sizeof(out));
e126ba97 397
b775516b
EC		 398 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
399 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 400 if (err)
c7a08ac7 401 return err;
e126ba97 402
b775516b 403 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 404
405 return err;
406}
407
408static int handle_hca_cap(struct mlx5_core_dev *dev)
409{
b775516b 410 void *set_ctx = NULL;
c7a08ac7
EC		 411 struct mlx5_profile *prof = dev->profile;
412 struct mlx5_caps *cur_caps = NULL;
413 struct mlx5_caps *max_caps = NULL;
414 int err = -ENOMEM;
b775516b 415 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
c7a08ac7 416
b775516b 417 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 418 if (!set_ctx)
e126ba97 419 goto query_ex;
e126ba97 420
c7a08ac7
EC		 421 max_caps = kzalloc(sizeof(*max_caps), GFP_KERNEL);
422 if (!max_caps)
423 goto query_ex;
e126ba97 424
c7a08ac7
EC		 425 cur_caps = kzalloc(sizeof(*cur_caps), GFP_KERNEL);
426 if (!cur_caps)
427 goto query_ex;
e126ba97 428
c7a08ac7
EC		 429 err = mlx5_core_get_caps(dev, max_caps, HCA_CAP_OPMOD_GET_MAX);
430 if (err)
e126ba97 431 goto query_ex;
e126ba97 432
c7a08ac7 433 err = mlx5_core_get_caps(dev, cur_caps, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 434 if (err)
435 goto query_ex;
436
c7a08ac7
EC		 437 /* we limit the size of the pkey table to 128 entries for now */
438 cur_caps->gen.pkey_table_size = 128;
439
440 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
441 cur_caps->gen.log_max_qp = prof->log_max_qp;
442
443 /* disable checksum */
444 cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
445
b775516b
EC		 446 copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, hca_capability_struct),
447 cur_caps);
448 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 449
e126ba97 450query_ex:
c7a08ac7
EC		 451 kfree(cur_caps);
452 kfree(max_caps);
e126ba97
EC		 453 kfree(set_ctx);
454
455 return err;
456}
457
458static int set_hca_ctrl(struct mlx5_core_dev *dev)
459{
460 struct mlx5_reg_host_endianess he_in;
461 struct mlx5_reg_host_endianess he_out;
462 int err;
463
464 memset(&he_in, 0, sizeof(he_in));
465 he_in.he = MLX5_SET_HOST_ENDIANNESS;
466 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
467 &he_out, sizeof(he_out),
468 MLX5_REG_HOST_ENDIANNESS, 0, 1);
469 return err;
470}
471
cd23b14b
EC		 472static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
473{
474 int err;
475 struct mlx5_enable_hca_mbox_in in;
476 struct mlx5_enable_hca_mbox_out out;
477
478 memset(&in, 0, sizeof(in));
479 memset(&out, 0, sizeof(out));
480 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
481 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
482 if (err)
483 return err;
484
485 if (out.hdr.status)
486 return mlx5_cmd_status_to_err(&out.hdr);
487
488 return 0;
489}
490
491static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
492{
493 int err;
494 struct mlx5_disable_hca_mbox_in in;
495 struct mlx5_disable_hca_mbox_out out;
496
497 memset(&in, 0, sizeof(in));
498 memset(&out, 0, sizeof(out));
499 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
500 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
501 if (err)
502 return err;
503
504 if (out.hdr.status)
505 return mlx5_cmd_status_to_err(&out.hdr);
506
507 return 0;
508}
509
9603b61d 510static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 511{
512 struct mlx5_priv *priv = &dev->priv;
513 int err;
514
515 dev->pdev = pdev;
516 pci_set_drvdata(dev->pdev, dev);
517 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
518 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
519
520 mutex_init(&priv->pgdir_mutex);
521 INIT_LIST_HEAD(&priv->pgdir_list);
522 spin_lock_init(&priv->mkey_lock);
523
524 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
525 if (!priv->dbg_root)
526 return -ENOMEM;
527
528 err = pci_enable_device(pdev);
529 if (err) {
1a91de28 530 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 531 goto err_dbg;
532 }
533
534 err = request_bar(pdev);
535 if (err) {
1a91de28 536 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 537 goto err_disable;
538 }
539
540 pci_set_master(pdev);
541
542 err = set_dma_caps(pdev);
543 if (err) {
544 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
545 goto err_clr_master;
546 }
547
548 dev->iseg_base = pci_resource_start(dev->pdev, 0);
549 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
550 if (!dev->iseg) {
551 err = -ENOMEM;
552 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
553 goto err_clr_master;
554 }
555 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
556 fw_rev_min(dev), fw_rev_sub(dev));
557
558 err = mlx5_cmd_init(dev);
559 if (err) {
560 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
561 goto err_unmap;
562 }
563
564 mlx5_pagealloc_init(dev);
cd23b14b
EC		 565
566 err = mlx5_core_enable_hca(dev);
567 if (err) {
568 dev_err(&pdev->dev, "enable hca failed\n");
569 goto err_pagealloc_cleanup;
570 }
571
572 err = mlx5_satisfy_startup_pages(dev, 1);
573 if (err) {
574 dev_err(&pdev->dev, "failed to allocate boot pages\n");
575 goto err_disable_hca;
576 }
577
e126ba97
EC		 578 err = set_hca_ctrl(dev);
579 if (err) {
580 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 581 goto reclaim_boot_pages;
e126ba97
EC		 582 }
583
584 err = handle_hca_cap(dev);
585 if (err) {
586 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 587 goto reclaim_boot_pages;
e126ba97
EC		 588 }
589
cd23b14b 590 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 591 if (err) {
cd23b14b
EC		 592 dev_err(&pdev->dev, "failed to allocate init pages\n");
593 goto reclaim_boot_pages;
e126ba97
EC		 594 }
595
596 err = mlx5_pagealloc_start(dev);
597 if (err) {
598 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 599 goto reclaim_boot_pages;
e126ba97
EC		 600 }
601
602 err = mlx5_cmd_init_hca(dev);
603 if (err) {
604 dev_err(&pdev->dev, "init hca failed\n");
605 goto err_pagealloc_stop;
606 }
607
608 mlx5_start_health_poll(dev);
609
610 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
611 if (err) {
612 dev_err(&pdev->dev, "query hca failed\n");
613 goto err_stop_poll;
614 }
615
616 err = mlx5_cmd_query_adapter(dev);
617 if (err) {
618 dev_err(&pdev->dev, "query adapter failed\n");
619 goto err_stop_poll;
620 }
621
622 err = mlx5_enable_msix(dev);
623 if (err) {
624 dev_err(&pdev->dev, "enable msix failed\n");
625 goto err_stop_poll;
626 }
627
628 err = mlx5_eq_init(dev);
629 if (err) {
630 dev_err(&pdev->dev, "failed to initialize eq\n");
631 goto disable_msix;
632 }
633
634 err = mlx5_alloc_uuars(dev, &priv->uuari);
635 if (err) {
636 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
637 goto err_eq_cleanup;
638 }
639
640 err = mlx5_start_eqs(dev);
641 if (err) {
642 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
643 goto err_free_uar;
644 }
645
646 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
647
648 mlx5_init_cq_table(dev);
649 mlx5_init_qp_table(dev);
650 mlx5_init_srq_table(dev);
3bcdb17a 651 mlx5_init_mr_table(dev);
e126ba97
EC		 652
653 return 0;
654
655err_free_uar:
656 mlx5_free_uuars(dev, &priv->uuari);
657
658err_eq_cleanup:
659 mlx5_eq_cleanup(dev);
660
661disable_msix:
662 mlx5_disable_msix(dev);
663
664err_stop_poll:
665 mlx5_stop_health_poll(dev);
1bde6e30
EC		 666 if (mlx5_cmd_teardown_hca(dev)) {
667 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
668 return err;
669 }
e126ba97
EC		 670
671err_pagealloc_stop:
672 mlx5_pagealloc_stop(dev);
673
cd23b14b 674reclaim_boot_pages:
e126ba97
EC		 675 mlx5_reclaim_startup_pages(dev);
676
cd23b14b
EC		 677err_disable_hca:
678 mlx5_core_disable_hca(dev);
679
e126ba97
EC		 680err_pagealloc_cleanup:
681 mlx5_pagealloc_cleanup(dev);
682 mlx5_cmd_cleanup(dev);
683
684err_unmap:
685 iounmap(dev->iseg);
686
687err_clr_master:
688 pci_clear_master(dev->pdev);
689 release_bar(dev->pdev);
690
691err_disable:
692 pci_disable_device(dev->pdev);
693
694err_dbg:
695 debugfs_remove(priv->dbg_root);
696 return err;
697}
e126ba97 698
9603b61d 699static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 700{
701 struct mlx5_priv *priv = &dev->priv;
702
703 mlx5_cleanup_srq_table(dev);
704 mlx5_cleanup_qp_table(dev);
705 mlx5_cleanup_cq_table(dev);
706 mlx5_stop_eqs(dev);
707 mlx5_free_uuars(dev, &priv->uuari);
708 mlx5_eq_cleanup(dev);
709 mlx5_disable_msix(dev);
710 mlx5_stop_health_poll(dev);
1bde6e30
EC		 711 if (mlx5_cmd_teardown_hca(dev)) {
712 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
713 return;
714 }
e126ba97
EC		 715 mlx5_pagealloc_stop(dev);
716 mlx5_reclaim_startup_pages(dev);
cd23b14b 717 mlx5_core_disable_hca(dev);
e126ba97
EC		 718 mlx5_pagealloc_cleanup(dev);
719 mlx5_cmd_cleanup(dev);
720 iounmap(dev->iseg);
721 pci_clear_master(dev->pdev);
722 release_bar(dev->pdev);
723 pci_disable_device(dev->pdev);
724 debugfs_remove(priv->dbg_root);
725}
9603b61d
JM		 726
727static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
728{
729 struct mlx5_device_context *dev_ctx;
730 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
731
732 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
733 if (!dev_ctx) {
734 pr_warn("mlx5_add_device: alloc context failed\n");
735 return;
736 }
737
738 dev_ctx->intf = intf;
739 dev_ctx->context = intf->add(dev);
740
741 if (dev_ctx->context) {
742 spin_lock_irq(&priv->ctx_lock);
743 list_add_tail(&dev_ctx->list, &priv->ctx_list);
744 spin_unlock_irq(&priv->ctx_lock);
745 } else {
746 kfree(dev_ctx);
747 }
748}
749
750static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
751{
752 struct mlx5_device_context *dev_ctx;
753 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
754
755 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
756 if (dev_ctx->intf == intf) {
757 spin_lock_irq(&priv->ctx_lock);
758 list_del(&dev_ctx->list);
759 spin_unlock_irq(&priv->ctx_lock);
760
761 intf->remove(dev, dev_ctx->context);
762 kfree(dev_ctx);
763 return;
764 }
765}
766static int mlx5_register_device(struct mlx5_core_dev *dev)
767{
768 struct mlx5_priv *priv = &dev->priv;
769 struct mlx5_interface *intf;
770
771 mutex_lock(&intf_mutex);
772 list_add_tail(&priv->dev_list, &dev_list);
773 list_for_each_entry(intf, &intf_list, list)
774 mlx5_add_device(intf, priv);
775 mutex_unlock(&intf_mutex);
776
777 return 0;
778}
779static void mlx5_unregister_device(struct mlx5_core_dev *dev)
780{
781 struct mlx5_priv *priv = &dev->priv;
782 struct mlx5_interface *intf;
783
784 mutex_lock(&intf_mutex);
785 list_for_each_entry(intf, &intf_list, list)
786 mlx5_remove_device(intf, priv);
787 list_del(&priv->dev_list);
788 mutex_unlock(&intf_mutex);
789}
790
791int mlx5_register_interface(struct mlx5_interface *intf)
792{
793 struct mlx5_priv *priv;
794
795 if (!intf->add || !intf->remove)
796 return -EINVAL;
797
798 mutex_lock(&intf_mutex);
799 list_add_tail(&intf->list, &intf_list);
800 list_for_each_entry(priv, &dev_list, dev_list)
801 mlx5_add_device(intf, priv);
802 mutex_unlock(&intf_mutex);
803
804 return 0;
805}
806EXPORT_SYMBOL(mlx5_register_interface);
807
808void mlx5_unregister_interface(struct mlx5_interface *intf)
809{
810 struct mlx5_priv *priv;
811
812 mutex_lock(&intf_mutex);
813 list_for_each_entry(priv, &dev_list, dev_list)
814 mlx5_remove_device(intf, priv);
815 list_del(&intf->list);
816 mutex_unlock(&intf_mutex);
817}
818EXPORT_SYMBOL(mlx5_unregister_interface);
819
820static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 821 unsigned long param)
9603b61d
JM		 822{
823 struct mlx5_priv *priv = &dev->priv;
824 struct mlx5_device_context *dev_ctx;
825 unsigned long flags;
826
827 spin_lock_irqsave(&priv->ctx_lock, flags);
828
829 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
830 if (dev_ctx->intf->event)
4d2f9bbb 831 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 832
833 spin_unlock_irqrestore(&priv->ctx_lock, flags);
834}
835
836struct mlx5_core_event_handler {
837 void (*event)(struct mlx5_core_dev *dev,
838 enum mlx5_dev_event event,
839 void *data);
840};
841
f66f049f
EC		 842#define MLX5_IB_MOD "mlx5_ib"
843
9603b61d
JM		 844static int init_one(struct pci_dev *pdev,
845 const struct pci_device_id *id)
846{
847 struct mlx5_core_dev *dev;
848 struct mlx5_priv *priv;
849 int err;
850
851 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
852 if (!dev) {
853 dev_err(&pdev->dev, "kzalloc failed\n");
854 return -ENOMEM;
855 }
856 priv = &dev->priv;
857
858 pci_set_drvdata(pdev, dev);
859
860 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
861 pr_warn("selected profile out of range, selecting default (%d)\n",
862 MLX5_DEFAULT_PROF);
863 prof_sel = MLX5_DEFAULT_PROF;
864 }
865 dev->profile = &profile[prof_sel];
866 dev->event = mlx5_core_event;
867
364d1798
EC		 868 INIT_LIST_HEAD(&priv->ctx_list);
869 spin_lock_init(&priv->ctx_lock);
9603b61d
JM		 870 err = mlx5_dev_init(dev, pdev);
871 if (err) {
872 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
873 goto out;
874 }
875
9603b61d
JM		 876 err = mlx5_register_device(dev);
877 if (err) {
878 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
879 goto out_init;
880 }
881
f66f049f
EC		 882 err = request_module_nowait(MLX5_IB_MOD);
883 if (err)
884 pr_info("failed request module on %s\n", MLX5_IB_MOD);
885
9603b61d
JM		 886 return 0;
887
888out_init:
889 mlx5_dev_cleanup(dev);
890out:
891 kfree(dev);
892 return err;
893}
894static void remove_one(struct pci_dev *pdev)
895{
896 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
897
898 mlx5_unregister_device(dev);
899 mlx5_dev_cleanup(dev);
900 kfree(dev);
901}
902
903static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 904 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
905 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
906 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
907 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
908 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
909 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 910 { 0, }
911};
912
913MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
914
915static struct pci_driver mlx5_core_driver = {
916 .name = DRIVER_NAME,
917 .id_table = mlx5_core_pci_table,
918 .probe = init_one,
919 .remove = remove_one
920};
e126ba97
EC		 921
922static int __init init(void)
923{
924 int err;
925
926 mlx5_register_debugfs();
927 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
928 if (!mlx5_core_wq) {
929 err = -ENOMEM;
930 goto err_debug;
931 }
932 mlx5_health_init();
933
9603b61d
JM		 934 err = pci_register_driver(&mlx5_core_driver);
935 if (err)
936 goto err_health;
937
e126ba97
EC		 938 return 0;
939
9603b61d
JM		 940err_health:
941 mlx5_health_cleanup();
942 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 943err_debug:
944 mlx5_unregister_debugfs();
945 return err;
946}
947
948static void __exit cleanup(void)
949{
9603b61d 950 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 951 mlx5_health_cleanup();
952 destroy_workqueue(mlx5_core_wq);
953 mlx5_unregister_debugfs();
954}
955
956module_init(init);
957module_exit(cleanup);
Linux kernel - Deliverables
This page took 0.204226 seconds and 5 git commands to generate.