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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <linux/mlx5/driver.h> | |
35 | #include <linux/mlx5/cmd.h> | |
36 | #include "mlx5_core.h" | |
37 | ||
38 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
39 | int size_in, void *data_out, int size_out, | |
40 | u16 reg_num, int arg, int write) | |
41 | { | |
42 | struct mlx5_access_reg_mbox_in *in = NULL; | |
43 | struct mlx5_access_reg_mbox_out *out = NULL; | |
44 | int err = -ENOMEM; | |
45 | ||
46 | in = mlx5_vzalloc(sizeof(*in) + size_in); | |
47 | if (!in) | |
48 | return -ENOMEM; | |
49 | ||
50 | out = mlx5_vzalloc(sizeof(*out) + size_out); | |
51 | if (!out) | |
52 | goto ex1; | |
53 | ||
54 | memcpy(in->data, data_in, size_in); | |
55 | in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG); | |
56 | in->hdr.opmod = cpu_to_be16(!write); | |
57 | in->arg = cpu_to_be32(arg); | |
58 | in->register_id = cpu_to_be16(reg_num); | |
59 | err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out, | |
e08a8761 | 60 | sizeof(*out) + size_out); |
e126ba97 EC |
61 | if (err) |
62 | goto ex2; | |
63 | ||
64 | if (out->hdr.status) | |
65 | err = mlx5_cmd_status_to_err(&out->hdr); | |
66 | ||
67 | if (!err) | |
68 | memcpy(data_out, out->data, size_out); | |
69 | ||
70 | ex2: | |
479163f4 | 71 | kvfree(out); |
e126ba97 | 72 | ex1: |
479163f4 | 73 | kvfree(in); |
e126ba97 EC |
74 | return err; |
75 | } | |
76 | EXPORT_SYMBOL_GPL(mlx5_core_access_reg); | |
77 | ||
78 | ||
79 | struct mlx5_reg_pcap { | |
80 | u8 rsvd0; | |
81 | u8 port_num; | |
82 | u8 rsvd1[2]; | |
83 | __be32 caps_127_96; | |
84 | __be32 caps_95_64; | |
85 | __be32 caps_63_32; | |
86 | __be32 caps_31_0; | |
87 | }; | |
88 | ||
f241e749 | 89 | int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps) |
e126ba97 EC |
90 | { |
91 | struct mlx5_reg_pcap in; | |
92 | struct mlx5_reg_pcap out; | |
93 | int err; | |
94 | ||
95 | memset(&in, 0, sizeof(in)); | |
96 | in.caps_127_96 = cpu_to_be32(caps); | |
97 | in.port_num = port_num; | |
98 | ||
99 | err = mlx5_core_access_reg(dev, &in, sizeof(in), &out, | |
100 | sizeof(out), MLX5_REG_PCAP, 0, 1); | |
101 | ||
102 | return err; | |
103 | } | |
104 | EXPORT_SYMBOL_GPL(mlx5_set_port_caps); | |
adb0c954 SM |
105 | |
106 | int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, | |
a05bdefa | 107 | int ptys_size, int proto_mask, u8 local_port) |
adb0c954 SM |
108 | { |
109 | u32 in[MLX5_ST_SZ_DW(ptys_reg)]; | |
110 | int err; | |
111 | ||
112 | memset(in, 0, sizeof(in)); | |
a05bdefa | 113 | MLX5_SET(ptys_reg, in, local_port, local_port); |
adb0c954 SM |
114 | MLX5_SET(ptys_reg, in, proto_mask, proto_mask); |
115 | ||
116 | err = mlx5_core_access_reg(dev, in, sizeof(in), ptys, | |
117 | ptys_size, MLX5_REG_PTYS, 0, 0); | |
118 | ||
119 | return err; | |
120 | } | |
121 | EXPORT_SYMBOL_GPL(mlx5_query_port_ptys); | |
122 | ||
123 | int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, | |
124 | u32 *proto_cap, int proto_mask) | |
125 | { | |
126 | u32 out[MLX5_ST_SZ_DW(ptys_reg)]; | |
127 | int err; | |
128 | ||
a05bdefa | 129 | err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1); |
adb0c954 SM |
130 | if (err) |
131 | return err; | |
132 | ||
133 | if (proto_mask == MLX5_PTYS_EN) | |
134 | *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability); | |
135 | else | |
136 | *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap); | |
141 | ||
142 | int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, | |
143 | u32 *proto_admin, int proto_mask) | |
144 | { | |
145 | u32 out[MLX5_ST_SZ_DW(ptys_reg)]; | |
146 | int err; | |
147 | ||
a05bdefa | 148 | err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1); |
adb0c954 SM |
149 | if (err) |
150 | return err; | |
151 | ||
152 | if (proto_mask == MLX5_PTYS_EN) | |
153 | *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin); | |
154 | else | |
155 | *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin); | |
160 | ||
a124d13e MD |
161 | int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev, |
162 | u8 *link_width_oper, u8 local_port) | |
163 | { | |
164 | u32 out[MLX5_ST_SZ_DW(ptys_reg)]; | |
165 | int err; | |
166 | ||
167 | err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port); | |
168 | if (err) | |
169 | return err; | |
170 | ||
171 | *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper); | |
176 | ||
177 | int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev, | |
178 | u8 *proto_oper, int proto_mask, | |
179 | u8 local_port) | |
180 | { | |
181 | u32 out[MLX5_ST_SZ_DW(ptys_reg)]; | |
182 | int err; | |
183 | ||
184 | err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port); | |
185 | if (err) | |
186 | return err; | |
187 | ||
188 | if (proto_mask == MLX5_PTYS_EN) | |
189 | *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper); | |
190 | else | |
191 | *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper); | |
196 | ||
adb0c954 SM |
197 | int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, |
198 | int proto_mask) | |
199 | { | |
200 | u32 in[MLX5_ST_SZ_DW(ptys_reg)]; | |
201 | u32 out[MLX5_ST_SZ_DW(ptys_reg)]; | |
202 | int err; | |
203 | ||
204 | memset(in, 0, sizeof(in)); | |
205 | ||
206 | MLX5_SET(ptys_reg, in, local_port, 1); | |
207 | MLX5_SET(ptys_reg, in, proto_mask, proto_mask); | |
208 | if (proto_mask == MLX5_PTYS_EN) | |
209 | MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin); | |
210 | else | |
211 | MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin); | |
212 | ||
213 | err = mlx5_core_access_reg(dev, in, sizeof(in), out, | |
214 | sizeof(out), MLX5_REG_PTYS, 0, 1); | |
215 | return err; | |
216 | } | |
217 | EXPORT_SYMBOL_GPL(mlx5_set_port_proto); | |
4c916a79 | 218 | |
6fa1bcab AS |
219 | int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, |
220 | enum mlx5_port_status status) | |
4c916a79 RS |
221 | { |
222 | u32 in[MLX5_ST_SZ_DW(paos_reg)]; | |
223 | u32 out[MLX5_ST_SZ_DW(paos_reg)]; | |
224 | ||
225 | memset(in, 0, sizeof(in)); | |
226 | ||
6fa1bcab | 227 | MLX5_SET(paos_reg, in, local_port, 1); |
4c916a79 RS |
228 | MLX5_SET(paos_reg, in, admin_status, status); |
229 | MLX5_SET(paos_reg, in, ase, 1); | |
230 | ||
231 | return mlx5_core_access_reg(dev, in, sizeof(in), out, | |
232 | sizeof(out), MLX5_REG_PAOS, 0, 1); | |
233 | } | |
6fa1bcab | 234 | EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status); |
4c916a79 | 235 | |
6fa1bcab AS |
236 | int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, |
237 | enum mlx5_port_status *status) | |
4c916a79 RS |
238 | { |
239 | u32 in[MLX5_ST_SZ_DW(paos_reg)]; | |
240 | u32 out[MLX5_ST_SZ_DW(paos_reg)]; | |
241 | int err; | |
242 | ||
243 | memset(in, 0, sizeof(in)); | |
244 | ||
6fa1bcab AS |
245 | MLX5_SET(paos_reg, in, local_port, 1); |
246 | ||
4c916a79 RS |
247 | err = mlx5_core_access_reg(dev, in, sizeof(in), out, |
248 | sizeof(out), MLX5_REG_PAOS, 0, 0); | |
249 | if (err) | |
250 | return err; | |
251 | ||
6fa1bcab | 252 | *status = MLX5_GET(paos_reg, out, admin_status); |
4c916a79 RS |
253 | return err; |
254 | } | |
6fa1bcab | 255 | EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status); |
e725440e | 256 | |
facc9699 SM |
257 | static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, int *admin_mtu, |
258 | int *max_mtu, int *oper_mtu, u8 port) | |
e725440e SM |
259 | { |
260 | u32 in[MLX5_ST_SZ_DW(pmtu_reg)]; | |
261 | u32 out[MLX5_ST_SZ_DW(pmtu_reg)]; | |
e725440e SM |
262 | |
263 | memset(in, 0, sizeof(in)); | |
264 | ||
facc9699 | 265 | MLX5_SET(pmtu_reg, in, local_port, port); |
e725440e | 266 | |
facc9699 SM |
267 | mlx5_core_access_reg(dev, in, sizeof(in), out, |
268 | sizeof(out), MLX5_REG_PMTU, 0, 0); | |
e725440e SM |
269 | |
270 | if (max_mtu) | |
271 | *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu); | |
272 | if (oper_mtu) | |
273 | *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu); | |
274 | if (admin_mtu) | |
275 | *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu); | |
e725440e SM |
276 | } |
277 | ||
facc9699 | 278 | int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port) |
e725440e SM |
279 | { |
280 | u32 in[MLX5_ST_SZ_DW(pmtu_reg)]; | |
281 | u32 out[MLX5_ST_SZ_DW(pmtu_reg)]; | |
282 | ||
283 | memset(in, 0, sizeof(in)); | |
284 | ||
285 | MLX5_SET(pmtu_reg, in, admin_mtu, mtu); | |
facc9699 | 286 | MLX5_SET(pmtu_reg, in, local_port, port); |
e725440e | 287 | |
facc9699 SM |
288 | return mlx5_core_access_reg(dev, in, sizeof(in), out, |
289 | sizeof(out), MLX5_REG_PMTU, 0, 1); | |
e725440e SM |
290 | } |
291 | EXPORT_SYMBOL_GPL(mlx5_set_port_mtu); | |
292 | ||
facc9699 SM |
293 | void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, |
294 | u8 port) | |
e725440e | 295 | { |
facc9699 | 296 | mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port); |
e725440e SM |
297 | } |
298 | EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu); | |
299 | ||
facc9699 SM |
300 | void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu, |
301 | u8 port) | |
e725440e | 302 | { |
facc9699 | 303 | mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port); |
e725440e SM |
304 | } |
305 | EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu); | |
a124d13e MD |
306 | |
307 | static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc, | |
308 | int pvlc_size, u8 local_port) | |
309 | { | |
310 | u32 in[MLX5_ST_SZ_DW(pvlc_reg)]; | |
311 | int err; | |
312 | ||
313 | memset(in, 0, sizeof(in)); | |
314 | MLX5_SET(ptys_reg, in, local_port, local_port); | |
315 | ||
316 | err = mlx5_core_access_reg(dev, in, sizeof(in), pvlc, | |
317 | pvlc_size, MLX5_REG_PVLC, 0, 0); | |
318 | ||
319 | return err; | |
320 | } | |
321 | ||
322 | int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, | |
323 | u8 *vl_hw_cap, u8 local_port) | |
324 | { | |
325 | u32 out[MLX5_ST_SZ_DW(pvlc_reg)]; | |
326 | int err; | |
327 | ||
328 | err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port); | |
329 | if (err) | |
330 | return err; | |
331 | ||
332 | *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap); | |
3c2d18ef AS |
337 | |
338 | int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause) | |
339 | { | |
340 | u32 in[MLX5_ST_SZ_DW(pfcc_reg)]; | |
341 | u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; | |
342 | int err; | |
343 | ||
344 | memset(in, 0, sizeof(in)); | |
345 | MLX5_SET(pfcc_reg, in, local_port, 1); | |
346 | MLX5_SET(pfcc_reg, in, pptx, tx_pause); | |
347 | MLX5_SET(pfcc_reg, in, pprx, rx_pause); | |
348 | ||
349 | err = mlx5_core_access_reg(dev, in, sizeof(in), out, | |
350 | sizeof(out), MLX5_REG_PFCC, 0, 1); | |
351 | return err; | |
352 | } | |
353 | EXPORT_SYMBOL_GPL(mlx5_set_port_pause); | |
354 | ||
355 | int mlx5_query_port_pause(struct mlx5_core_dev *dev, | |
356 | u32 *rx_pause, u32 *tx_pause) | |
357 | { | |
358 | u32 in[MLX5_ST_SZ_DW(pfcc_reg)]; | |
359 | u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; | |
360 | int err; | |
361 | ||
362 | memset(in, 0, sizeof(in)); | |
363 | MLX5_SET(pfcc_reg, in, local_port, 1); | |
364 | ||
365 | err = mlx5_core_access_reg(dev, in, sizeof(in), out, | |
366 | sizeof(out), MLX5_REG_PFCC, 0, 0); | |
367 | if (err) | |
368 | return err; | |
369 | ||
370 | if (rx_pause) | |
371 | *rx_pause = MLX5_GET(pfcc_reg, out, pprx); | |
372 | ||
373 | if (tx_pause) | |
374 | *tx_pause = MLX5_GET(pfcc_reg, out, pptx); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | EXPORT_SYMBOL_GPL(mlx5_query_port_pause); |