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fc50db98 EC |
1 | /* |
2 | * Copyright (c) 2014, Mellanox Technologies inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/pci.h> | |
34 | #include <linux/mlx5/driver.h> | |
35 | #include "mlx5_core.h" | |
81848731 SM |
36 | #ifdef CONFIG_MLX5_CORE_EN |
37 | #include "eswitch.h" | |
38 | #endif | |
fc50db98 | 39 | |
edb31b16 AH |
40 | bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev) |
41 | { | |
42 | struct mlx5_core_sriov *sriov = &dev->priv.sriov; | |
43 | ||
44 | return !!sriov->num_vfs; | |
45 | } | |
46 | ||
6b6adee3 | 47 | static int mlx5_device_enable_sriov(struct mlx5_core_dev *dev, int num_vfs) |
fc50db98 EC |
48 | { |
49 | struct mlx5_core_sriov *sriov = &dev->priv.sriov; | |
50 | int err; | |
51 | int vf; | |
52 | ||
6b6adee3 MHY |
53 | if (sriov->enabled_vfs) { |
54 | mlx5_core_warn(dev, | |
55 | "failed to enable SRIOV on device, already enabled with %d vfs\n", | |
56 | sriov->enabled_vfs); | |
57 | return -EBUSY; | |
58 | } | |
59 | ||
60 | #ifdef CONFIG_MLX5_CORE_EN | |
61 | err = mlx5_eswitch_enable_sriov(dev->priv.eswitch, num_vfs, SRIOV_LEGACY); | |
62 | if (err) { | |
63 | mlx5_core_warn(dev, | |
64 | "failed to enable eswitch SRIOV (%d)\n", err); | |
65 | return err; | |
66 | } | |
67 | #endif | |
68 | ||
69 | for (vf = 0; vf < num_vfs; vf++) { | |
70 | err = mlx5_core_enable_hca(dev, vf + 1); | |
fc50db98 | 71 | if (err) { |
6b6adee3 MHY |
72 | mlx5_core_warn(dev, "failed to enable VF %d (%d)\n", vf, err); |
73 | continue; | |
fc50db98 | 74 | } |
6b6adee3 MHY |
75 | sriov->vfs_ctx[vf].enabled = 1; |
76 | sriov->enabled_vfs++; | |
77 | mlx5_core_dbg(dev, "successfully enabled VF* %d\n", vf); | |
78 | ||
fc50db98 | 79 | } |
6b6adee3 MHY |
80 | |
81 | return 0; | |
fc50db98 EC |
82 | } |
83 | ||
6b6adee3 | 84 | static void mlx5_device_disable_sriov(struct mlx5_core_dev *dev) |
fc50db98 EC |
85 | { |
86 | struct mlx5_core_sriov *sriov = &dev->priv.sriov; | |
6b6adee3 | 87 | int err; |
fc50db98 EC |
88 | int vf; |
89 | ||
6b6adee3 MHY |
90 | if (!sriov->enabled_vfs) |
91 | return; | |
92 | ||
93 | for (vf = 0; vf < sriov->num_vfs; vf++) { | |
94 | if (!sriov->vfs_ctx[vf].enabled) | |
95 | continue; | |
96 | err = mlx5_core_disable_hca(dev, vf + 1); | |
97 | if (err) { | |
98 | mlx5_core_warn(dev, "failed to disable VF %d\n", vf); | |
99 | continue; | |
fc50db98 | 100 | } |
6b6adee3 MHY |
101 | sriov->vfs_ctx[vf].enabled = 0; |
102 | sriov->enabled_vfs--; | |
fc50db98 | 103 | } |
6b6adee3 MHY |
104 | |
105 | #ifdef CONFIG_MLX5_CORE_EN | |
106 | mlx5_eswitch_disable_sriov(dev->priv.eswitch); | |
107 | #endif | |
108 | ||
109 | if (mlx5_wait_for_vf_pages(dev)) | |
110 | mlx5_core_warn(dev, "timeout reclaiming VFs pages\n"); | |
fc50db98 EC |
111 | } |
112 | ||
6b6adee3 | 113 | static int mlx5_pci_enable_sriov(struct pci_dev *pdev, int num_vfs) |
fc50db98 EC |
114 | { |
115 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
6b6adee3 | 116 | int err = 0; |
fc50db98 | 117 | |
6b6adee3 MHY |
118 | if (pci_num_vf(pdev)) { |
119 | mlx5_core_warn(dev, "Unable to enable pci sriov, already enabled\n"); | |
120 | return -EBUSY; | |
fc50db98 EC |
121 | } |
122 | ||
6b6adee3 MHY |
123 | err = pci_enable_sriov(pdev, num_vfs); |
124 | if (err) | |
125 | mlx5_core_warn(dev, "pci_enable_sriov failed : %d\n", err); | |
fc50db98 | 126 | |
fc50db98 EC |
127 | return err; |
128 | } | |
129 | ||
6b6adee3 MHY |
130 | static void mlx5_pci_disable_sriov(struct pci_dev *pdev) |
131 | { | |
132 | pci_disable_sriov(pdev); | |
133 | } | |
134 | ||
135 | static int mlx5_sriov_enable(struct pci_dev *pdev, int num_vfs) | |
fc50db98 EC |
136 | { |
137 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
138 | struct mlx5_core_sriov *sriov = &dev->priv.sriov; | |
6b6adee3 | 139 | int err = 0; |
fc50db98 | 140 | |
6b6adee3 MHY |
141 | err = mlx5_device_enable_sriov(dev, num_vfs); |
142 | if (err) { | |
143 | mlx5_core_warn(dev, "mlx5_device_enable_sriov failed : %d\n", err); | |
144 | return err; | |
145 | } | |
fc50db98 | 146 | |
6b6adee3 | 147 | err = mlx5_pci_enable_sriov(pdev, num_vfs); |
fc50db98 | 148 | if (err) { |
6b6adee3 MHY |
149 | mlx5_core_warn(dev, "mlx5_pci_enable_sriov failed : %d\n", err); |
150 | mlx5_device_disable_sriov(dev); | |
fc50db98 EC |
151 | return err; |
152 | } | |
153 | ||
6b6adee3 MHY |
154 | sriov->num_vfs = num_vfs; |
155 | ||
fc50db98 EC |
156 | return 0; |
157 | } | |
158 | ||
6b6adee3 | 159 | static void mlx5_sriov_disable(struct pci_dev *pdev) |
fc50db98 | 160 | { |
6b6adee3 | 161 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); |
fc50db98 EC |
162 | struct mlx5_core_sriov *sriov = &dev->priv.sriov; |
163 | ||
6b6adee3 MHY |
164 | mlx5_pci_disable_sriov(pdev); |
165 | mlx5_device_disable_sriov(dev); | |
fc50db98 EC |
166 | sriov->num_vfs = 0; |
167 | } | |
168 | ||
169 | int mlx5_core_sriov_configure(struct pci_dev *pdev, int num_vfs) | |
170 | { | |
171 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
6b6adee3 | 172 | int err = 0; |
fc50db98 | 173 | |
c19ca6cb | 174 | mlx5_core_dbg(dev, "requested num_vfs %d\n", num_vfs); |
fc50db98 EC |
175 | if (!mlx5_core_is_pf(dev)) |
176 | return -EPERM; | |
177 | ||
edb31b16 AH |
178 | if (num_vfs && mlx5_lag_is_active(dev)) { |
179 | mlx5_core_warn(dev, "can't turn sriov on while LAG is active"); | |
180 | return -EINVAL; | |
181 | } | |
182 | ||
6b6adee3 MHY |
183 | if (num_vfs) |
184 | err = mlx5_sriov_enable(pdev, num_vfs); | |
185 | else | |
186 | mlx5_sriov_disable(pdev); | |
fc50db98 | 187 | |
6b6adee3 | 188 | return err ? err : num_vfs; |
fc50db98 EC |
189 | } |
190 | ||
acab721b MHY |
191 | int mlx5_sriov_attach(struct mlx5_core_dev *dev) |
192 | { | |
193 | struct mlx5_core_sriov *sriov = &dev->priv.sriov; | |
194 | ||
195 | if (!mlx5_core_is_pf(dev) || !sriov->num_vfs) | |
196 | return 0; | |
197 | ||
198 | /* If sriov VFs exist in PCI level, enable them in device level */ | |
199 | return mlx5_device_enable_sriov(dev, sriov->num_vfs); | |
200 | } | |
201 | ||
202 | void mlx5_sriov_detach(struct mlx5_core_dev *dev) | |
203 | { | |
204 | if (!mlx5_core_is_pf(dev)) | |
205 | return; | |
206 | ||
207 | mlx5_device_disable_sriov(dev); | |
208 | } | |
209 | ||
fc50db98 EC |
210 | int mlx5_sriov_init(struct mlx5_core_dev *dev) |
211 | { | |
212 | struct mlx5_core_sriov *sriov = &dev->priv.sriov; | |
213 | struct pci_dev *pdev = dev->pdev; | |
6b6adee3 | 214 | int total_vfs; |
fc50db98 EC |
215 | |
216 | if (!mlx5_core_is_pf(dev)) | |
217 | return 0; | |
218 | ||
6b6adee3 MHY |
219 | total_vfs = pci_sriov_get_totalvfs(pdev); |
220 | sriov->num_vfs = pci_num_vf(pdev); | |
221 | sriov->vfs_ctx = kcalloc(total_vfs, sizeof(*sriov->vfs_ctx), GFP_KERNEL); | |
fc50db98 EC |
222 | if (!sriov->vfs_ctx) |
223 | return -ENOMEM; | |
224 | ||
c2d6e31a | 225 | return 0; |
fc50db98 EC |
226 | } |
227 | ||
6b6adee3 | 228 | void mlx5_sriov_cleanup(struct mlx5_core_dev *dev) |
fc50db98 | 229 | { |
6b6adee3 | 230 | struct mlx5_core_sriov *sriov = &dev->priv.sriov; |
fc50db98 EC |
231 | |
232 | if (!mlx5_core_is_pf(dev)) | |
6b6adee3 | 233 | return; |
c2d6e31a | 234 | |
6b6adee3 | 235 | kfree(sriov->vfs_ctx); |
fc50db98 | 236 | } |