[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / uar.c

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io-mapping.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/cmd.h>
#include "mlx5_core.h"

enum {
	NUM_DRIVER_UARS		= 4,
	NUM_LOW_LAT_UUARS	= 4,
};

int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn)
{
	u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0};
	u32 in[MLX5_ST_SZ_DW(alloc_uar_in)]   = {0};
	int err;

	MLX5_SET(alloc_uar_in, in, opcode, MLX5_CMD_OP_ALLOC_UAR);
	err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
	if (!err)
		*uarn = MLX5_GET(alloc_uar_out, out, uar);
	return err;
}
EXPORT_SYMBOL(mlx5_cmd_alloc_uar);

int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn)
{
	u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0};
	u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)]   = {0};

	MLX5_SET(dealloc_uar_in, in, opcode, MLX5_CMD_OP_DEALLOC_UAR);
	MLX5_SET(dealloc_uar_in, in, uar, uarn);
	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
}
EXPORT_SYMBOL(mlx5_cmd_free_uar);

static int need_uuar_lock(int uuarn)
{
	int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;

	if (uuarn == 0 || tot_uuars - NUM_LOW_LAT_UUARS)
		return 0;

	return 1;
}

int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
{
	int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
	struct mlx5_bf *bf;
	phys_addr_t addr;
	int err;
	int i;

	uuari->num_uars = NUM_DRIVER_UARS;
	uuari->num_low_latency_uuars = NUM_LOW_LAT_UUARS;

	mutex_init(&uuari->lock);
	uuari->uars = kcalloc(uuari->num_uars, sizeof(*uuari->uars), GFP_KERNEL);
	if (!uuari->uars)
		return -ENOMEM;

	uuari->bfs = kcalloc(tot_uuars, sizeof(*uuari->bfs), GFP_KERNEL);
	if (!uuari->bfs) {
		err = -ENOMEM;
		goto out_uars;
	}

	uuari->bitmap = kcalloc(BITS_TO_LONGS(tot_uuars), sizeof(*uuari->bitmap),
				GFP_KERNEL);
	if (!uuari->bitmap) {
		err = -ENOMEM;
		goto out_bfs;
	}

	uuari->count = kcalloc(tot_uuars, sizeof(*uuari->count), GFP_KERNEL);
	if (!uuari->count) {
		err = -ENOMEM;
		goto out_bitmap;
	}

	for (i = 0; i < uuari->num_uars; i++) {
		err = mlx5_cmd_alloc_uar(dev, &uuari->uars[i].index);
		if (err)
			goto out_count;

		addr = dev->iseg_base + ((phys_addr_t)(uuari->uars[i].index) << PAGE_SHIFT);
		uuari->uars[i].map = ioremap(addr, PAGE_SIZE);
		if (!uuari->uars[i].map) {
			mlx5_cmd_free_uar(dev, uuari->uars[i].index);
			err = -ENOMEM;
			goto out_count;
		}
		mlx5_core_dbg(dev, "allocated uar index 0x%x, mmaped at %p\n",
			      uuari->uars[i].index, uuari->uars[i].map);
	}

	for (i = 0; i < tot_uuars; i++) {
		bf = &uuari->bfs[i];

		bf->buf_size = (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) / 2;
		bf->uar = &uuari->uars[i / MLX5_BF_REGS_PER_PAGE];
		bf->regreg = uuari->uars[i / MLX5_BF_REGS_PER_PAGE].map;
		bf->reg = NULL; /* Add WC support */
		bf->offset = (i % MLX5_BF_REGS_PER_PAGE) *
			     (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) +
			     MLX5_BF_OFFSET;
		bf->need_lock = need_uuar_lock(i);
		spin_lock_init(&bf->lock);
		spin_lock_init(&bf->lock32);
		bf->uuarn = i;
	}

	return 0;

out_count:
	for (i--; i >= 0; i--) {
		iounmap(uuari->uars[i].map);
		mlx5_cmd_free_uar(dev, uuari->uars[i].index);
	}
	kfree(uuari->count);

out_bitmap:
	kfree(uuari->bitmap);

out_bfs:
	kfree(uuari->bfs);

out_uars:
	kfree(uuari->uars);
	return err;
}

int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
{
	int i = uuari->num_uars;

	for (i--; i >= 0; i--) {
		iounmap(uuari->uars[i].map);
		mlx5_cmd_free_uar(dev, uuari->uars[i].index);
	}

	kfree(uuari->count);
	kfree(uuari->bitmap);
	kfree(uuari->bfs);
	kfree(uuari->uars);

	return 0;
}

int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
		       bool map_wc)
{
	phys_addr_t pfn;
	phys_addr_t uar_bar_start;
	int err;

	err = mlx5_cmd_alloc_uar(mdev, &uar->index);
	if (err) {
		mlx5_core_warn(mdev, "mlx5_cmd_alloc_uar() failed, %d\n", err);
		return err;
	}

	uar_bar_start = pci_resource_start(mdev->pdev, 0);
	pfn           = (uar_bar_start >> PAGE_SHIFT) + uar->index;

	if (map_wc) {
		uar->bf_map = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE);
		if (!uar->bf_map) {
			mlx5_core_warn(mdev, "ioremap_wc() failed\n");
			uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
			if (!uar->map)
				goto err_free_uar;
		}
	} else {
		uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
		if (!uar->map)
			goto err_free_uar;
	}

	return 0;

err_free_uar:
	mlx5_core_warn(mdev, "ioremap() failed\n");
	err = -ENOMEM;
	mlx5_cmd_free_uar(mdev, uar->index);

	return err;
}
EXPORT_SYMBOL(mlx5_alloc_map_uar);

void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar)
{
	if (uar->map)
		iounmap(uar->map);
	else
		iounmap(uar->bf_map);
	mlx5_cmd_free_uar(mdev, uar->index);
}
EXPORT_SYMBOL(mlx5_unmap_free_uar);
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
88a85f99	35	#include <linux/io-mapping.h>
e126ba97 EC	36	#include <linux/mlx5/driver.h>
	37	#include <linux/mlx5/cmd.h>
	38	#include "mlx5_core.h"
	39
	40	enum {
	41	NUM_DRIVER_UARS = 4,
	42	NUM_LOW_LAT_UUARS = 4,
	43	};
	44
e126ba97 EC	45	int mlx5_cmd_alloc_uar(struct mlx5_core_dev dev, u32 uarn)
e126ba97 EC	46	{
732ef5ad SM	47	u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0};
732ef5ad SM	48	u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0};
e126ba97 EC	49	int err;
e126ba97 EC	50
732ef5ad SM	51	MLX5_SET(alloc_uar_in, in, opcode, MLX5_CMD_OP_ALLOC_UAR);
732ef5ad SM	52	err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
c4f287c4 SM	53	if (!err)
c4f287c4 SM	54	*uarn = MLX5_GET(alloc_uar_out, out, uar);
e126ba97 EC	55	return err;
	56	}
	57	EXPORT_SYMBOL(mlx5_cmd_alloc_uar);
	58
	59	int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn)
	60	{
732ef5ad SM	61	u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0};
732ef5ad SM	62	u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0};
e126ba97	63
732ef5ad SM	64	MLX5_SET(dealloc_uar_in, in, opcode, MLX5_CMD_OP_DEALLOC_UAR);
732ef5ad SM	65	MLX5_SET(dealloc_uar_in, in, uar, uarn);
c4f287c4	66	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
e126ba97 EC	67	}
	68	EXPORT_SYMBOL(mlx5_cmd_free_uar);
	69
	70	static int need_uuar_lock(int uuarn)
	71	{
	72	int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
	73
	74	if (uuarn == 0 \|\| tot_uuars - NUM_LOW_LAT_UUARS)
	75	return 0;
	76
	77	return 1;
	78	}
	79
	80	int mlx5_alloc_uuars(struct mlx5_core_dev dev, struct mlx5_uuar_info uuari)
	81	{
	82	int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
	83	struct mlx5_bf *bf;
	84	phys_addr_t addr;
	85	int err;
	86	int i;
	87
	88	uuari->num_uars = NUM_DRIVER_UARS;
	89	uuari->num_low_latency_uuars = NUM_LOW_LAT_UUARS;
	90
	91	mutex_init(&uuari->lock);
	92	uuari->uars = kcalloc(uuari->num_uars, sizeof(*uuari->uars), GFP_KERNEL);
	93	if (!uuari->uars)
	94	return -ENOMEM;
	95
	96	uuari->bfs = kcalloc(tot_uuars, sizeof(*uuari->bfs), GFP_KERNEL);
	97	if (!uuari->bfs) {
	98	err = -ENOMEM;
	99	goto out_uars;
	100	}
	101
	102	uuari->bitmap = kcalloc(BITS_TO_LONGS(tot_uuars), sizeof(*uuari->bitmap),
	103	GFP_KERNEL);
	104	if (!uuari->bitmap) {
	105	err = -ENOMEM;
	106	goto out_bfs;
	107	}
	108
	109	uuari->count = kcalloc(tot_uuars, sizeof(*uuari->count), GFP_KERNEL);
	110	if (!uuari->count) {
	111	err = -ENOMEM;
	112	goto out_bitmap;
	113	}
	114
	115	for (i = 0; i < uuari->num_uars; i++) {
	116	err = mlx5_cmd_alloc_uar(dev, &uuari->uars[i].index);
	117	if (err)
	118	goto out_count;
	119
	120	addr = dev->iseg_base + ((phys_addr_t)(uuari->uars[i].index) << PAGE_SHIFT);
	121	uuari->uars[i].map = ioremap(addr, PAGE_SIZE);
	122	if (!uuari->uars[i].map) {
	123	mlx5_cmd_free_uar(dev, uuari->uars[i].index);
a661b43f	124	err = -ENOMEM;
e126ba97 EC	125	goto out_count;
	126	}
	127	mlx5_core_dbg(dev, "allocated uar index 0x%x, mmaped at %p\n",
	128	uuari->uars[i].index, uuari->uars[i].map);
	129	}
	130
	131	for (i = 0; i < tot_uuars; i++) {
	132	bf = &uuari->bfs[i];
	133
938fe83c	134	bf->buf_size = (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) / 2;
e126ba97 EC	135	bf->uar = &uuari->uars[i / MLX5_BF_REGS_PER_PAGE];
	136	bf->regreg = uuari->uars[i / MLX5_BF_REGS_PER_PAGE].map;
	137	bf->reg = NULL; /* Add WC support */
938fe83c SM	138	bf->offset = (i % MLX5_BF_REGS_PER_PAGE) *
	139	(1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) +
	140	MLX5_BF_OFFSET;
e126ba97 EC	141	bf->need_lock = need_uuar_lock(i);
	142	spin_lock_init(&bf->lock);
	143	spin_lock_init(&bf->lock32);
	144	bf->uuarn = i;
	145	}
	146
	147	return 0;
	148
	149	out_count:
	150	for (i--; i >= 0; i--) {
	151	iounmap(uuari->uars[i].map);
	152	mlx5_cmd_free_uar(dev, uuari->uars[i].index);
	153	}
	154	kfree(uuari->count);
	155
	156	out_bitmap:
	157	kfree(uuari->bitmap);
	158
	159	out_bfs:
	160	kfree(uuari->bfs);
	161
	162	out_uars:
	163	kfree(uuari->uars);
	164	return err;
	165	}
	166
	167	int mlx5_free_uuars(struct mlx5_core_dev dev, struct mlx5_uuar_info uuari)
	168	{
	169	int i = uuari->num_uars;
	170
	171	for (i--; i >= 0; i--) {
	172	iounmap(uuari->uars[i].map);
	173	mlx5_cmd_free_uar(dev, uuari->uars[i].index);
	174	}
	175
	176	kfree(uuari->count);
	177	kfree(uuari->bitmap);
	178	kfree(uuari->bfs);
	179	kfree(uuari->uars);
	180
	181	return 0;
	182	}
e281682b	183
0ba42241 ML	184	int mlx5_alloc_map_uar(struct mlx5_core_dev mdev, struct mlx5_uar uar,
0ba42241 ML	185	bool map_wc)
e281682b SM	186	{
	187	phys_addr_t pfn;
	188	phys_addr_t uar_bar_start;
	189	int err;
	190
	191	err = mlx5_cmd_alloc_uar(mdev, &uar->index);
	192	if (err) {
	193	mlx5_core_warn(mdev, "mlx5_cmd_alloc_uar() failed, %d\n", err);
	194	return err;
	195	}
	196
	197	uar_bar_start = pci_resource_start(mdev->pdev, 0);
	198	pfn = (uar_bar_start >> PAGE_SHIFT) + uar->index;
e281682b	199
0ba42241 ML	200	if (map_wc) {
	201	uar->bf_map = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE);
	202	if (!uar->bf_map) {
	203	mlx5_core_warn(mdev, "ioremap_wc() failed\n");
	204	uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
	205	if (!uar->map)
	206	goto err_free_uar;
	207	}
	208	} else {
	209	uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
	210	if (!uar->map)
	211	goto err_free_uar;
	212	}
88a85f99	213
e281682b SM	214	return 0;
	215
	216	err_free_uar:
0ba42241 ML	217	mlx5_core_warn(mdev, "ioremap() failed\n");
0ba42241 ML	218	err = -ENOMEM;
e281682b SM	219	mlx5_cmd_free_uar(mdev, uar->index);
	220
	221	return err;
	222	}
	223	EXPORT_SYMBOL(mlx5_alloc_map_uar);
	224
	225	void mlx5_unmap_free_uar(struct mlx5_core_dev mdev, struct mlx5_uar uar)
	226	{
5f8a02a4 GP	227	if (uar->map)
	228	iounmap(uar->map);
	229	else
	230	iounmap(uar->bf_map);
e281682b SM	231	mlx5_cmd_free_uar(mdev, uar->index);
	232	}
	233	EXPORT_SYMBOL(mlx5_unmap_free_uar);