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93c1edb2 JP |
1 | /* |
2 | * drivers/net/ethernet/mellanox/mlxsw/core.h | |
3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. | |
4 | * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> | |
5 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> | |
6 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * | |
11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. Neither the names of the copyright holders nor the names of its | |
17 | * contributors may be used to endorse or promote products derived from | |
18 | * this software without specific prior written permission. | |
19 | * | |
20 | * Alternatively, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") version 2 as published by the Free | |
22 | * Software Foundation. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
34 | * POSSIBILITY OF SUCH DAMAGE. | |
35 | */ | |
36 | ||
37 | #ifndef _MLXSW_CORE_H | |
38 | #define _MLXSW_CORE_H | |
39 | ||
40 | #include <linux/module.h> | |
41 | #include <linux/device.h> | |
42 | #include <linux/slab.h> | |
43 | #include <linux/gfp.h> | |
44 | #include <linux/types.h> | |
45 | #include <linux/skbuff.h> | |
dd9bdb04 | 46 | #include <linux/workqueue.h> |
932762b6 | 47 | #include <net/devlink.h> |
93c1edb2 | 48 | |
4ec14b76 IS |
49 | #include "trap.h" |
50 | #include "reg.h" | |
51 | ||
93c1edb2 JP |
52 | #include "cmd.h" |
53 | ||
54 | #define MLXSW_MODULE_ALIAS_PREFIX "mlxsw-driver-" | |
55 | #define MODULE_MLXSW_DRIVER_ALIAS(kind) \ | |
56 | MODULE_ALIAS(MLXSW_MODULE_ALIAS_PREFIX kind) | |
57 | ||
31557f0f | 58 | #define MLXSW_DEVICE_KIND_SWITCHX2 "switchx2" |
56ade8fe | 59 | #define MLXSW_DEVICE_KIND_SPECTRUM "spectrum" |
31557f0f | 60 | |
93c1edb2 JP |
61 | struct mlxsw_core; |
62 | struct mlxsw_driver; | |
63 | struct mlxsw_bus; | |
64 | struct mlxsw_bus_info; | |
65 | ||
b2f10571 JP |
66 | void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core); |
67 | ||
93c1edb2 JP |
68 | int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver); |
69 | void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver); | |
70 | ||
71 | int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, | |
72 | const struct mlxsw_bus *mlxsw_bus, | |
73 | void *bus_priv); | |
74 | void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core); | |
75 | ||
76 | struct mlxsw_tx_info { | |
77 | u8 local_port; | |
78 | bool is_emad; | |
79 | }; | |
80 | ||
307c2431 | 81 | bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, |
d003462a | 82 | const struct mlxsw_tx_info *tx_info); |
307c2431 | 83 | int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, |
93c1edb2 JP |
84 | const struct mlxsw_tx_info *tx_info); |
85 | ||
86 | struct mlxsw_rx_listener { | |
87 | void (*func)(struct sk_buff *skb, u8 local_port, void *priv); | |
88 | u8 local_port; | |
89 | u16 trap_id; | |
63a81141 | 90 | enum mlxsw_reg_hpkt_action action; |
93c1edb2 JP |
91 | }; |
92 | ||
4ec14b76 IS |
93 | struct mlxsw_event_listener { |
94 | void (*func)(const struct mlxsw_reg_info *reg, | |
95 | char *payload, void *priv); | |
96 | enum mlxsw_event_trap_id trap_id; | |
97 | }; | |
98 | ||
93c1edb2 JP |
99 | int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, |
100 | const struct mlxsw_rx_listener *rxl, | |
101 | void *priv); | |
102 | void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, | |
103 | const struct mlxsw_rx_listener *rxl, | |
104 | void *priv); | |
105 | ||
4ec14b76 IS |
106 | int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, |
107 | const struct mlxsw_event_listener *el, | |
108 | void *priv); | |
109 | void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, | |
110 | const struct mlxsw_event_listener *el, | |
111 | void *priv); | |
112 | ||
caf7297e JP |
113 | typedef void mlxsw_reg_trans_cb_t(struct mlxsw_core *mlxsw_core, char *payload, |
114 | size_t payload_len, unsigned long cb_priv); | |
115 | ||
116 | int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, | |
117 | const struct mlxsw_reg_info *reg, char *payload, | |
118 | struct list_head *bulk_list, | |
119 | mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv); | |
120 | int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, | |
121 | const struct mlxsw_reg_info *reg, char *payload, | |
122 | struct list_head *bulk_list, | |
123 | mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv); | |
124 | int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list); | |
125 | ||
4ec14b76 IS |
126 | int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, |
127 | const struct mlxsw_reg_info *reg, char *payload); | |
128 | int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, | |
129 | const struct mlxsw_reg_info *reg, char *payload); | |
130 | ||
93c1edb2 | 131 | struct mlxsw_rx_info { |
8060646a JP |
132 | bool is_lag; |
133 | union { | |
134 | u16 sys_port; | |
135 | u16 lag_id; | |
136 | } u; | |
137 | u8 lag_port_index; | |
93c1edb2 JP |
138 | int trap_id; |
139 | }; | |
140 | ||
141 | void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, | |
142 | struct mlxsw_rx_info *rx_info); | |
143 | ||
8060646a JP |
144 | void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, |
145 | u16 lag_id, u8 port_index, u8 local_port); | |
146 | u8 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, | |
147 | u16 lag_id, u8 port_index); | |
148 | void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, | |
149 | u16 lag_id, u8 local_port); | |
150 | ||
932762b6 JP |
151 | struct mlxsw_core_port { |
152 | struct devlink_port devlink_port; | |
153 | }; | |
154 | ||
325f2f19 JP |
155 | static inline void * |
156 | mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) | |
157 | { | |
158 | /* mlxsw_core_port is ensured to always be the first field in driver | |
159 | * port structure. | |
160 | */ | |
161 | return mlxsw_core_port; | |
162 | } | |
163 | ||
932762b6 JP |
164 | int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, |
165 | struct mlxsw_core_port *mlxsw_core_port, u8 local_port, | |
166 | struct net_device *dev, bool split, u32 split_group); | |
167 | void mlxsw_core_port_fini(struct mlxsw_core_port *mlxsw_core_port); | |
168 | ||
dd9bdb04 JP |
169 | int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay); |
170 | ||
93c1edb2 JP |
171 | #define MLXSW_CONFIG_PROFILE_SWID_COUNT 8 |
172 | ||
173 | struct mlxsw_swid_config { | |
174 | u8 used_type:1, | |
175 | used_properties:1; | |
176 | u8 type; | |
177 | u8 properties; | |
178 | }; | |
179 | ||
180 | struct mlxsw_config_profile { | |
181 | u16 used_max_vepa_channels:1, | |
182 | used_max_lag:1, | |
183 | used_max_port_per_lag:1, | |
184 | used_max_mid:1, | |
185 | used_max_pgt:1, | |
186 | used_max_system_port:1, | |
187 | used_max_vlan_groups:1, | |
188 | used_max_regions:1, | |
189 | used_flood_tables:1, | |
190 | used_flood_mode:1, | |
191 | used_max_ib_mc:1, | |
192 | used_max_pkey:1, | |
193 | used_ar_sec:1, | |
489107bd JP |
194 | used_adaptive_routing_group_cap:1, |
195 | used_kvd_sizes:1; | |
93c1edb2 JP |
196 | u8 max_vepa_channels; |
197 | u16 max_lag; | |
198 | u16 max_port_per_lag; | |
199 | u16 max_mid; | |
200 | u16 max_pgt; | |
201 | u16 max_system_port; | |
202 | u16 max_vlan_groups; | |
203 | u16 max_regions; | |
204 | u8 max_flood_tables; | |
205 | u8 max_vid_flood_tables; | |
206 | u8 flood_mode; | |
12fd35ab IS |
207 | u8 max_fid_offset_flood_tables; |
208 | u16 fid_offset_flood_table_size; | |
453b6a8d IS |
209 | u8 max_fid_flood_tables; |
210 | u16 fid_flood_table_size; | |
93c1edb2 JP |
211 | u16 max_ib_mc; |
212 | u16 max_pkey; | |
213 | u8 ar_sec; | |
214 | u16 adaptive_routing_group_cap; | |
215 | u8 arn; | |
489107bd JP |
216 | u32 kvd_linear_size; |
217 | u32 kvd_hash_single_size; | |
218 | u32 kvd_hash_double_size; | |
57d316ba | 219 | u8 resource_query_enable; |
93c1edb2 JP |
220 | struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT]; |
221 | }; | |
222 | ||
223 | struct mlxsw_driver { | |
224 | struct list_head list; | |
225 | const char *kind; | |
226 | struct module *owner; | |
227 | size_t priv_size; | |
b2f10571 | 228 | int (*init)(struct mlxsw_core *mlxsw_core, |
93c1edb2 | 229 | const struct mlxsw_bus_info *mlxsw_bus_info); |
b2f10571 JP |
230 | void (*fini)(struct mlxsw_core *mlxsw_core); |
231 | int (*port_split)(struct mlxsw_core *mlxsw_core, u8 local_port, | |
232 | unsigned int count); | |
233 | int (*port_unsplit)(struct mlxsw_core *mlxsw_core, u8 local_port); | |
a6179bf0 JP |
234 | int (*sb_pool_get)(struct mlxsw_core *mlxsw_core, |
235 | unsigned int sb_index, u16 pool_index, | |
236 | struct devlink_sb_pool_info *pool_info); | |
237 | int (*sb_pool_set)(struct mlxsw_core *mlxsw_core, | |
238 | unsigned int sb_index, u16 pool_index, u32 size, | |
239 | enum devlink_sb_threshold_type threshold_type); | |
240 | int (*sb_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port, | |
241 | unsigned int sb_index, u16 pool_index, | |
242 | u32 *p_threshold); | |
243 | int (*sb_port_pool_set)(struct mlxsw_core_port *mlxsw_core_port, | |
244 | unsigned int sb_index, u16 pool_index, | |
245 | u32 threshold); | |
246 | int (*sb_tc_pool_bind_get)(struct mlxsw_core_port *mlxsw_core_port, | |
247 | unsigned int sb_index, u16 tc_index, | |
248 | enum devlink_sb_pool_type pool_type, | |
249 | u16 *p_pool_index, u32 *p_threshold); | |
250 | int (*sb_tc_pool_bind_set)(struct mlxsw_core_port *mlxsw_core_port, | |
251 | unsigned int sb_index, u16 tc_index, | |
252 | enum devlink_sb_pool_type pool_type, | |
253 | u16 pool_index, u32 threshold); | |
1ceecc88 JP |
254 | int (*sb_occ_snapshot)(struct mlxsw_core *mlxsw_core, |
255 | unsigned int sb_index); | |
256 | int (*sb_occ_max_clear)(struct mlxsw_core *mlxsw_core, | |
257 | unsigned int sb_index); | |
258 | int (*sb_occ_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port, | |
259 | unsigned int sb_index, u16 pool_index, | |
260 | u32 *p_cur, u32 *p_max); | |
261 | int (*sb_occ_tc_port_bind_get)(struct mlxsw_core_port *mlxsw_core_port, | |
262 | unsigned int sb_index, u16 tc_index, | |
263 | enum devlink_sb_pool_type pool_type, | |
264 | u32 *p_cur, u32 *p_max); | |
93c1edb2 JP |
265 | void (*txhdr_construct)(struct sk_buff *skb, |
266 | const struct mlxsw_tx_info *tx_info); | |
267 | u8 txhdr_len; | |
268 | const struct mlxsw_config_profile *profile; | |
269 | }; | |
270 | ||
57d316ba | 271 | struct mlxsw_resources { |
ded821c8 NF |
272 | u8 max_span_valid:1; |
273 | u8 max_span; | |
57d316ba NF |
274 | }; |
275 | ||
276 | struct mlxsw_resources *mlxsw_core_resources_get(struct mlxsw_core *mlxsw_core); | |
277 | ||
93c1edb2 JP |
278 | struct mlxsw_bus { |
279 | const char *kind; | |
280 | int (*init)(void *bus_priv, struct mlxsw_core *mlxsw_core, | |
57d316ba NF |
281 | const struct mlxsw_config_profile *profile, |
282 | struct mlxsw_resources *resources); | |
93c1edb2 | 283 | void (*fini)(void *bus_priv); |
d003462a IS |
284 | bool (*skb_transmit_busy)(void *bus_priv, |
285 | const struct mlxsw_tx_info *tx_info); | |
93c1edb2 JP |
286 | int (*skb_transmit)(void *bus_priv, struct sk_buff *skb, |
287 | const struct mlxsw_tx_info *tx_info); | |
288 | int (*cmd_exec)(void *bus_priv, u16 opcode, u8 opcode_mod, | |
289 | u32 in_mod, bool out_mbox_direct, | |
290 | char *in_mbox, size_t in_mbox_size, | |
291 | char *out_mbox, size_t out_mbox_size, | |
292 | u8 *p_status); | |
293 | }; | |
294 | ||
295 | struct mlxsw_bus_info { | |
296 | const char *device_kind; | |
297 | const char *device_name; | |
298 | struct device *dev; | |
299 | struct { | |
300 | u16 major; | |
301 | u16 minor; | |
302 | u16 subminor; | |
303 | } fw_rev; | |
304 | u8 vsd[MLXSW_CMD_BOARDINFO_VSD_LEN]; | |
305 | u8 psid[MLXSW_CMD_BOARDINFO_PSID_LEN]; | |
306 | }; | |
307 | ||
89309da3 JP |
308 | struct mlxsw_hwmon; |
309 | ||
310 | #ifdef CONFIG_MLXSW_CORE_HWMON | |
311 | ||
312 | int mlxsw_hwmon_init(struct mlxsw_core *mlxsw_core, | |
313 | const struct mlxsw_bus_info *mlxsw_bus_info, | |
314 | struct mlxsw_hwmon **p_hwmon); | |
315 | void mlxsw_hwmon_fini(struct mlxsw_hwmon *mlxsw_hwmon); | |
316 | ||
317 | #else | |
318 | ||
319 | static inline int mlxsw_hwmon_init(struct mlxsw_core *mlxsw_core, | |
320 | const struct mlxsw_bus_info *mlxsw_bus_info, | |
321 | struct mlxsw_hwmon **p_hwmon) | |
322 | { | |
323 | return 0; | |
324 | } | |
325 | ||
89309da3 JP |
326 | #endif |
327 | ||
93c1edb2 | 328 | #endif |