[deliverable/linux.git] / drivers / net / ethernet / moxa / moxart_ether.c

/* MOXA ART Ethernet (RTL8201CP) driver.
 *
 * Copyright (C) 2013 Jonas Jensen
 *
 * Jonas Jensen <jonas.jensen@gmail.com>
 *
 * Based on code from
 * Moxa Technology Co., Ltd. <www.moxa.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/dma-mapping.h>
#include <linux/ethtool.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/crc32.h>
#include <linux/crc32c.h>

#include "moxart_ether.h"

static inline void moxart_desc_write(u32 data, u32 *desc)
{
	*desc = cpu_to_le32(data);
}

static inline u32 moxart_desc_read(u32 *desc)
{
	return le32_to_cpu(*desc);
}

static inline void moxart_emac_write(struct net_device *ndev,
				     unsigned int reg, unsigned long value)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);

	writel(value, priv->base + reg);
}

static void moxart_update_mac_address(struct net_device *ndev)
{
	moxart_emac_write(ndev, REG_MAC_MS_ADDRESS,
			  ((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])));
	moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4,
			  ((ndev->dev_addr[2] << 24) |
			   (ndev->dev_addr[3] << 16) |
			   (ndev->dev_addr[4] << 8) |
			   (ndev->dev_addr[5])));
}

static int moxart_set_mac_address(struct net_device *ndev, void *addr)
{
	struct sockaddr *address = addr;

	if (!is_valid_ether_addr(address->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len);
	moxart_update_mac_address(ndev);

	return 0;
}

static void moxart_mac_free_memory(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	int i;

	for (i = 0; i < RX_DESC_NUM; i++)
		dma_unmap_single(&ndev->dev, priv->rx_mapping[i],
				 priv->rx_buf_size, DMA_FROM_DEVICE);

	if (priv->tx_desc_base)
		dma_free_coherent(NULL, TX_REG_DESC_SIZE * TX_DESC_NUM,
				  priv->tx_desc_base, priv->tx_base);

	if (priv->rx_desc_base)
		dma_free_coherent(NULL, RX_REG_DESC_SIZE * RX_DESC_NUM,
				  priv->rx_desc_base, priv->rx_base);

	kfree(priv->tx_buf_base);
	kfree(priv->rx_buf_base);
}

static void moxart_mac_reset(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);

	writel(SW_RST, priv->base + REG_MAC_CTRL);
	while (readl(priv->base + REG_MAC_CTRL) & SW_RST)
		mdelay(10);

	writel(0, priv->base + REG_INTERRUPT_MASK);

	priv->reg_maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL;
}

static void moxart_mac_enable(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);

	writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
	writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
	writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);

	priv->reg_imr |= (RPKT_FINISH_M | XPKT_FINISH_M);
	writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);

	priv->reg_maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN);
	writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
}

static void moxart_mac_setup_desc_ring(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	void *desc;
	int i;

	for (i = 0; i < TX_DESC_NUM; i++) {
		desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE;
		memset(desc, 0, TX_REG_DESC_SIZE);

		priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i;
	}
	moxart_desc_write(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1);

	priv->tx_head = 0;
	priv->tx_tail = 0;

	for (i = 0; i < RX_DESC_NUM; i++) {
		desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE;
		memset(desc, 0, RX_REG_DESC_SIZE);
		moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
		moxart_desc_write(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK,
		       desc + RX_REG_OFFSET_DESC1);

		priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i;
		priv->rx_mapping[i] = dma_map_single(&ndev->dev,
						     priv->rx_buf[i],
						     priv->rx_buf_size,
						     DMA_FROM_DEVICE);
		if (dma_mapping_error(&ndev->dev, priv->rx_mapping[i]))
			netdev_err(ndev, "DMA mapping error\n");

		moxart_desc_write(priv->rx_mapping[i],
		       desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS);
		moxart_desc_write((uintptr_t)priv->rx_buf[i],
		       desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT);
	}
	moxart_desc_write(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1);

	priv->rx_head = 0;

	/* reset the MAC controller TX/RX desciptor base address */
	writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
	writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
}

static int moxart_mac_open(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);

	if (!is_valid_ether_addr(ndev->dev_addr))
		return -EADDRNOTAVAIL;

	napi_enable(&priv->napi);

	moxart_mac_reset(ndev);
	moxart_update_mac_address(ndev);
	moxart_mac_setup_desc_ring(ndev);
	moxart_mac_enable(ndev);
	netif_start_queue(ndev);

	netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n",
		   __func__, readl(priv->base + REG_INTERRUPT_MASK),
		   readl(priv->base + REG_MAC_CTRL));

	return 0;
}

static int moxart_mac_stop(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);

	napi_disable(&priv->napi);

	netif_stop_queue(ndev);

	/* disable all interrupts */
	writel(0, priv->base + REG_INTERRUPT_MASK);

	/* disable all functions */
	writel(0, priv->base + REG_MAC_CTRL);

	return 0;
}

static int moxart_rx_poll(struct napi_struct *napi, int budget)
{
	struct moxart_mac_priv_t *priv = container_of(napi,
						      struct moxart_mac_priv_t,
						      napi);
	struct net_device *ndev = priv->ndev;
	struct sk_buff *skb;
	void *desc;
	unsigned int desc0, len;
	int rx_head = priv->rx_head;
	int rx = 0;

	while (rx < budget) {
		desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head);
		desc0 = moxart_desc_read(desc + RX_REG_OFFSET_DESC0);
		rmb(); /* ensure desc0 is up to date */

		if (desc0 & RX_DESC0_DMA_OWN)
			break;

		if (desc0 & (RX_DESC0_ERR | RX_DESC0_CRC_ERR | RX_DESC0_FTL |
			     RX_DESC0_RUNT | RX_DESC0_ODD_NB)) {
			net_dbg_ratelimited("packet error\n");
			priv->stats.rx_dropped++;
			priv->stats.rx_errors++;
			goto rx_next;
		}

		len = desc0 & RX_DESC0_FRAME_LEN_MASK;

		if (len > RX_BUF_SIZE)
			len = RX_BUF_SIZE;

		dma_sync_single_for_cpu(&ndev->dev,
					priv->rx_mapping[rx_head],
					priv->rx_buf_size, DMA_FROM_DEVICE);
		skb = netdev_alloc_skb_ip_align(ndev, len);

		if (unlikely(!skb)) {
			net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n");
			priv->stats.rx_dropped++;
			priv->stats.rx_errors++;
			goto rx_next;
		}

		memcpy(skb->data, priv->rx_buf[rx_head], len);
		skb_put(skb, len);
		skb->protocol = eth_type_trans(skb, ndev);
		napi_gro_receive(&priv->napi, skb);
		rx++;

		priv->stats.rx_packets++;
		priv->stats.rx_bytes += len;
		if (desc0 & RX_DESC0_MULTICAST)
			priv->stats.multicast++;

rx_next:
		wmb(); /* prevent setting ownership back too early */
		moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);

		rx_head = RX_NEXT(rx_head);
		priv->rx_head = rx_head;
	}

	if (rx < budget) {
		napi_complete(napi);
	}

	priv->reg_imr |= RPKT_FINISH_M;
	writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);

	return rx;
}

static void moxart_tx_finished(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	unsigned tx_head = priv->tx_head;
	unsigned tx_tail = priv->tx_tail;

	while (tx_tail != tx_head) {
		dma_unmap_single(&ndev->dev, priv->tx_mapping[tx_tail],
				 priv->tx_len[tx_tail], DMA_TO_DEVICE);

		priv->stats.tx_packets++;
		priv->stats.tx_bytes += priv->tx_skb[tx_tail]->len;

		dev_kfree_skb_irq(priv->tx_skb[tx_tail]);
		priv->tx_skb[tx_tail] = NULL;

		tx_tail = TX_NEXT(tx_tail);
	}
	priv->tx_tail = tx_tail;
}

static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id)
{
	struct net_device *ndev = (struct net_device *) dev_id;
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS);

	if (ists & XPKT_OK_INT_STS)
		moxart_tx_finished(ndev);

	if (ists & RPKT_FINISH) {
		if (napi_schedule_prep(&priv->napi)) {
			priv->reg_imr &= ~RPKT_FINISH_M;
			writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
			__napi_schedule(&priv->napi);
		}
	}

	return IRQ_HANDLED;
}

static int moxart_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	void *desc;
	unsigned int len;
	unsigned int tx_head = priv->tx_head;
	u32 txdes1;
	int ret = NETDEV_TX_BUSY;

	desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head);

	spin_lock_irq(&priv->txlock);
	if (moxart_desc_read(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) {
		net_dbg_ratelimited("no TX space for packet\n");
		priv->stats.tx_dropped++;
		goto out_unlock;
	}
	rmb(); /* ensure data is only read that had TX_DESC0_DMA_OWN cleared */

	len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len;

	priv->tx_mapping[tx_head] = dma_map_single(&ndev->dev, skb->data,
						   len, DMA_TO_DEVICE);
	if (dma_mapping_error(&ndev->dev, priv->tx_mapping[tx_head])) {
		netdev_err(ndev, "DMA mapping error\n");
		goto out_unlock;
	}

	priv->tx_len[tx_head] = len;
	priv->tx_skb[tx_head] = skb;

	moxart_desc_write(priv->tx_mapping[tx_head],
	       desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS);
	moxart_desc_write((uintptr_t)skb->data,
	       desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT);

	if (skb->len < ETH_ZLEN) {
		memset(&skb->data[skb->len],
		       0, ETH_ZLEN - skb->len);
		len = ETH_ZLEN;
	}

	dma_sync_single_for_device(&ndev->dev, priv->tx_mapping[tx_head],
				   priv->tx_buf_size, DMA_TO_DEVICE);

	txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK);
	if (tx_head == TX_DESC_NUM_MASK)
		txdes1 |= TX_DESC1_END;
	moxart_desc_write(txdes1, desc + TX_REG_OFFSET_DESC1);
	wmb(); /* flush descriptor before transferring ownership */
	moxart_desc_write(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0);

	/* start to send packet */
	writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND);

	priv->tx_head = TX_NEXT(tx_head);

	ndev->trans_start = jiffies;
	ret = NETDEV_TX_OK;
out_unlock:
	spin_unlock_irq(&priv->txlock);

	return ret;
}

static struct net_device_stats *moxart_mac_get_stats(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);

	return &priv->stats;
}

static void moxart_mac_setmulticast(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	struct netdev_hw_addr *ha;
	int crc_val;

	netdev_for_each_mc_addr(ha, ndev) {
		crc_val = crc32_le(~0, ha->addr, ETH_ALEN);
		crc_val = (crc_val >> 26) & 0x3f;
		if (crc_val >= 32) {
			writel(readl(priv->base + REG_MCAST_HASH_TABLE1) |
			       (1UL << (crc_val - 32)),
			       priv->base + REG_MCAST_HASH_TABLE1);
		} else {
			writel(readl(priv->base + REG_MCAST_HASH_TABLE0) |
			       (1UL << crc_val),
			       priv->base + REG_MCAST_HASH_TABLE0);
		}
	}
}

static void moxart_mac_set_rx_mode(struct net_device *ndev)
{
	struct moxart_mac_priv_t *priv = netdev_priv(ndev);

	spin_lock_irq(&priv->txlock);

	(ndev->flags & IFF_PROMISC) ? (priv->reg_maccr |= RCV_ALL) :
				      (priv->reg_maccr &= ~RCV_ALL);

	(ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr |= RX_MULTIPKT) :
				       (priv->reg_maccr &= ~RX_MULTIPKT);

	if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) {
		priv->reg_maccr |= HT_MULTI_EN;
		moxart_mac_setmulticast(ndev);
	} else {
		priv->reg_maccr &= ~HT_MULTI_EN;
	}

	writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);

	spin_unlock_irq(&priv->txlock);
}

static struct net_device_ops moxart_netdev_ops = {
	.ndo_open		= moxart_mac_open,
	.ndo_stop		= moxart_mac_stop,
	.ndo_start_xmit		= moxart_mac_start_xmit,
	.ndo_get_stats		= moxart_mac_get_stats,
	.ndo_set_rx_mode	= moxart_mac_set_rx_mode,
	.ndo_set_mac_address	= moxart_set_mac_address,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_change_mtu		= eth_change_mtu,
};

static int moxart_mac_probe(struct platform_device *pdev)
{
	struct device *p_dev = &pdev->dev;
	struct device_node *node = p_dev->of_node;
	struct net_device *ndev;
	struct moxart_mac_priv_t *priv;
	struct resource *res;
	unsigned int irq;
	int ret;

	ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t));
	if (!ndev)
		return -ENOMEM;

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0) {
		netdev_err(ndev, "irq_of_parse_and_map failed\n");
		ret = -EINVAL;
		goto irq_map_fail;
	}

	priv = netdev_priv(ndev);
	priv->ndev = ndev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ndev->base_addr = res->start;
	priv->base = devm_ioremap_resource(p_dev, res);
	if (IS_ERR(priv->base)) {
		dev_err(p_dev, "devm_ioremap_resource failed\n");
		ret = PTR_ERR(priv->base);
		goto init_fail;
	}

	spin_lock_init(&priv->txlock);

	priv->tx_buf_size = TX_BUF_SIZE;
	priv->rx_buf_size = RX_BUF_SIZE;

	priv->tx_desc_base = dma_alloc_coherent(NULL, TX_REG_DESC_SIZE *
						TX_DESC_NUM, &priv->tx_base,
						GFP_DMA | GFP_KERNEL);
	if (priv->tx_desc_base == NULL) {
		ret = -ENOMEM;
		goto init_fail;
	}

	priv->rx_desc_base = dma_alloc_coherent(NULL, RX_REG_DESC_SIZE *
						RX_DESC_NUM, &priv->rx_base,
						GFP_DMA | GFP_KERNEL);
	if (priv->rx_desc_base == NULL) {
		ret = -ENOMEM;
		goto init_fail;
	}

	priv->tx_buf_base = kmalloc(priv->tx_buf_size * TX_DESC_NUM,
				    GFP_ATOMIC);
	if (!priv->tx_buf_base) {
		ret = -ENOMEM;
		goto init_fail;
	}

	priv->rx_buf_base = kmalloc(priv->rx_buf_size * RX_DESC_NUM,
				    GFP_ATOMIC);
	if (!priv->rx_buf_base) {
		ret = -ENOMEM;
		goto init_fail;
	}

	platform_set_drvdata(pdev, ndev);

	ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0,
			       pdev->name, ndev);
	if (ret) {
		netdev_err(ndev, "devm_request_irq failed\n");
		goto init_fail;
	}

	ndev->netdev_ops = &moxart_netdev_ops;
	netif_napi_add(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM);
	ndev->priv_flags |= IFF_UNICAST_FLT;
	ndev->irq = irq;

	SET_NETDEV_DEV(ndev, &pdev->dev);

	ret = register_netdev(ndev);
	if (ret) {
		free_netdev(ndev);
		goto init_fail;
	}

	netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n",
		   __func__, ndev->irq, ndev->dev_addr);

	return 0;

init_fail:
	netdev_err(ndev, "init failed\n");
	moxart_mac_free_memory(ndev);
irq_map_fail:
	free_netdev(ndev);
	return ret;
}

static int moxart_remove(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);

	unregister_netdev(ndev);
	free_irq(ndev->irq, ndev);
	moxart_mac_free_memory(ndev);
	free_netdev(ndev);

	return 0;
}

static const struct of_device_id moxart_mac_match[] = {
	{ .compatible = "moxa,moxart-mac" },
	{ }
};
MODULE_DEVICE_TABLE(of, moxart_mac_match);

static struct platform_driver moxart_mac_driver = {
	.probe	= moxart_mac_probe,
	.remove	= moxart_remove,
	.driver	= {
		.name		= "moxart-ethernet",
		.of_match_table	= moxart_mac_match,
	},
};
module_platform_driver(moxart_mac_driver);

MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
Commit	Line	Data
6c821bd9 JJ	1	/* MOXA ART Ethernet (RTL8201CP) driver.
	2	*
	3	* Copyright (C) 2013 Jonas Jensen
	4	*
	5	* Jonas Jensen <jonas.jensen@gmail.com>
	6	*
	7	* Based on code from
	8	* Moxa Technology Co., Ltd. <www.moxa.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*/
	14
	15	#include <linux/module.h>
6c821bd9 JJ	16	#include <linux/netdevice.h>
	17	#include <linux/etherdevice.h>
	18	#include <linux/skbuff.h>
	19	#include <linux/dma-mapping.h>
	20	#include <linux/ethtool.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/irq.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
	26	#include <linux/crc32.h>
	27	#include <linux/crc32c.h>
6c821bd9 JJ	28
	29	#include "moxart_ether.h"
	30
59a557be AB	31	static inline void moxart_desc_write(u32 data, u32 *desc)
	32	{
	33	*desc = cpu_to_le32(data);
	34	}
	35
	36	static inline u32 moxart_desc_read(u32 *desc)
	37	{
	38	return le32_to_cpu(*desc);
	39	}
	40
6c821bd9 JJ	41	static inline void moxart_emac_write(struct net_device *ndev,
	42	unsigned int reg, unsigned long value)
	43	{
	44	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	45
	46	writel(value, priv->base + reg);
	47	}
	48
	49	static void moxart_update_mac_address(struct net_device *ndev)
	50	{
	51	moxart_emac_write(ndev, REG_MAC_MS_ADDRESS,
	52	((ndev->dev_addr[0] << 8) \| (ndev->dev_addr[1])));
	53	moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4,
	54	((ndev->dev_addr[2] << 24) \|
	55	(ndev->dev_addr[3] << 16) \|
	56	(ndev->dev_addr[4] << 8) \|
	57	(ndev->dev_addr[5])));
	58	}
	59
	60	static int moxart_set_mac_address(struct net_device ndev, void addr)
	61	{
	62	struct sockaddr *address = addr;
	63
	64	if (!is_valid_ether_addr(address->sa_data))
	65	return -EADDRNOTAVAIL;
	66
	67	memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len);
	68	moxart_update_mac_address(ndev);
	69
	70	return 0;
	71	}
	72
	73	static void moxart_mac_free_memory(struct net_device *ndev)
	74	{
	75	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	76	int i;
	77
	78	for (i = 0; i < RX_DESC_NUM; i++)
	79	dma_unmap_single(&ndev->dev, priv->rx_mapping[i],
	80	priv->rx_buf_size, DMA_FROM_DEVICE);
	81
	82	if (priv->tx_desc_base)
	83	dma_free_coherent(NULL, TX_REG_DESC_SIZE * TX_DESC_NUM,
	84	priv->tx_desc_base, priv->tx_base);
	85
	86	if (priv->rx_desc_base)
	87	dma_free_coherent(NULL, RX_REG_DESC_SIZE * RX_DESC_NUM,
	88	priv->rx_desc_base, priv->rx_base);
	89
	90	kfree(priv->tx_buf_base);
	91	kfree(priv->rx_buf_base);
	92	}
	93
	94	static void moxart_mac_reset(struct net_device *ndev)
	95	{
	96	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	97
	98	writel(SW_RST, priv->base + REG_MAC_CTRL);
	99	while (readl(priv->base + REG_MAC_CTRL) & SW_RST)
	100	mdelay(10);
	101
	102	writel(0, priv->base + REG_INTERRUPT_MASK);
	103
	104	priv->reg_maccr = RX_BROADPKT \| FULLDUP \| CRC_APD \| RX_FTL;
105	}
106
107	static void moxart_mac_enable(struct net_device *ndev)
108	{
109	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
110
111	writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
112	writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
113	writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);
114
115	priv->reg_imr \|= (RPKT_FINISH_M \| XPKT_FINISH_M);
116	writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
117
118	priv->reg_maccr \|= (RCV_EN \| XMT_EN \| RDMA_EN \| XDMA_EN);
119	writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
120	}
121
122	static void moxart_mac_setup_desc_ring(struct net_device *ndev)
123	{
124	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
59a557be	125	void *desc;
6c821bd9 JJ	126	int i;
	127
	128	for (i = 0; i < TX_DESC_NUM; i++) {
	129	desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE;
	130	memset(desc, 0, TX_REG_DESC_SIZE);
	131
	132	priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i;
	133	}
59a557be	134	moxart_desc_write(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1);
6c821bd9 JJ	135
	136	priv->tx_head = 0;
	137	priv->tx_tail = 0;
	138
	139	for (i = 0; i < RX_DESC_NUM; i++) {
	140	desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE;
	141	memset(desc, 0, RX_REG_DESC_SIZE);
59a557be AB	142	moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
59a557be AB	143	moxart_desc_write(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK,
6c821bd9 JJ	144	desc + RX_REG_OFFSET_DESC1);
	145
	146	priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i;
	147	priv->rx_mapping[i] = dma_map_single(&ndev->dev,
	148	priv->rx_buf[i],
	149	priv->rx_buf_size,
	150	DMA_FROM_DEVICE);
	151	if (dma_mapping_error(&ndev->dev, priv->rx_mapping[i]))
	152	netdev_err(ndev, "DMA mapping error\n");
	153
59a557be	154	moxart_desc_write(priv->rx_mapping[i],
6c821bd9	155	desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS);
59a557be	156	moxart_desc_write((uintptr_t)priv->rx_buf[i],
6c821bd9 JJ	157	desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT);
6c821bd9 JJ	158	}
59a557be	159	moxart_desc_write(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1);
6c821bd9 JJ	160
	161	priv->rx_head = 0;
	162
dbedd44e	163	/* reset the MAC controller TX/RX desciptor base address */
6c821bd9 JJ	164	writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
	165	writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
	166	}
	167
	168	static int moxart_mac_open(struct net_device *ndev)
	169	{
	170	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	171
	172	if (!is_valid_ether_addr(ndev->dev_addr))
	173	return -EADDRNOTAVAIL;
	174
	175	napi_enable(&priv->napi);
	176
	177	moxart_mac_reset(ndev);
	178	moxart_update_mac_address(ndev);
	179	moxart_mac_setup_desc_ring(ndev);
	180	moxart_mac_enable(ndev);
	181	netif_start_queue(ndev);
	182
	183	netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n",
	184	__func__, readl(priv->base + REG_INTERRUPT_MASK),
	185	readl(priv->base + REG_MAC_CTRL));
	186
	187	return 0;
	188	}
	189
	190	static int moxart_mac_stop(struct net_device *ndev)
	191	{
	192	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	193
	194	napi_disable(&priv->napi);
	195
	196	netif_stop_queue(ndev);
	197
	198	/* disable all interrupts */
	199	writel(0, priv->base + REG_INTERRUPT_MASK);
	200
	201	/* disable all functions */
	202	writel(0, priv->base + REG_MAC_CTRL);
	203
	204	return 0;
	205	}
	206
	207	static int moxart_rx_poll(struct napi_struct *napi, int budget)
	208	{
	209	struct moxart_mac_priv_t *priv = container_of(napi,
	210	struct moxart_mac_priv_t,
	211	napi);
	212	struct net_device *ndev = priv->ndev;
	213	struct sk_buff *skb;
59a557be	214	void *desc;
6c821bd9 JJ	215	unsigned int desc0, len;
	216	int rx_head = priv->rx_head;
	217	int rx = 0;
	218
2b7890e7	219	while (rx < budget) {
6c821bd9	220	desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head);
59a557be AB	221	desc0 = moxart_desc_read(desc + RX_REG_OFFSET_DESC0);
59a557be AB	222	rmb(); /* ensure desc0 is up to date */
6c821bd9 JJ	223
	224	if (desc0 & RX_DESC0_DMA_OWN)
	225	break;
	226
	227	if (desc0 & (RX_DESC0_ERR \| RX_DESC0_CRC_ERR \| RX_DESC0_FTL \|
	228	RX_DESC0_RUNT \| RX_DESC0_ODD_NB)) {
	229	net_dbg_ratelimited("packet error\n");
	230	priv->stats.rx_dropped++;
	231	priv->stats.rx_errors++;
2b7890e7	232	goto rx_next;
6c821bd9 JJ	233	}
	234
	235	len = desc0 & RX_DESC0_FRAME_LEN_MASK;
	236
	237	if (len > RX_BUF_SIZE)
	238	len = RX_BUF_SIZE;
	239
777fbc31 JJ	240	dma_sync_single_for_cpu(&ndev->dev,
	241	priv->rx_mapping[rx_head],
	242	priv->rx_buf_size, DMA_FROM_DEVICE);
9fe1b3bc JJ	243	skb = netdev_alloc_skb_ip_align(ndev, len);
9fe1b3bc JJ	244
6c821bd9	245	if (unlikely(!skb)) {
9fe1b3bc	246	net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n");
6c821bd9 JJ	247	priv->stats.rx_dropped++;
6c821bd9 JJ	248	priv->stats.rx_errors++;
2b7890e7	249	goto rx_next;
6c821bd9 JJ	250	}
6c821bd9 JJ	251
9fe1b3bc	252	memcpy(skb->data, priv->rx_buf[rx_head], len);
6c821bd9 JJ	253	skb_put(skb, len);
	254	skb->protocol = eth_type_trans(skb, ndev);
	255	napi_gro_receive(&priv->napi, skb);
	256	rx++;
	257
6c821bd9 JJ	258	priv->stats.rx_packets++;
	259	priv->stats.rx_bytes += len;
	260	if (desc0 & RX_DESC0_MULTICAST)
	261	priv->stats.multicast++;
	262
2b7890e7	263	rx_next:
59a557be AB	264	wmb(); /* prevent setting ownership back too early */
59a557be AB	265	moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
6c821bd9 JJ	266
	267	rx_head = RX_NEXT(rx_head);
	268	priv->rx_head = rx_head;
6c821bd9 JJ	269	}
	270
	271	if (rx < budget) {
2b7890e7	272	napi_complete(napi);
6c821bd9 JJ	273	}
	274
	275	priv->reg_imr \|= RPKT_FINISH_M;
	276	writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
	277
	278	return rx;
	279	}
	280
	281	static void moxart_tx_finished(struct net_device *ndev)
	282	{
	283	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	284	unsigned tx_head = priv->tx_head;
	285	unsigned tx_tail = priv->tx_tail;
	286
	287	while (tx_tail != tx_head) {
	288	dma_unmap_single(&ndev->dev, priv->tx_mapping[tx_tail],
	289	priv->tx_len[tx_tail], DMA_TO_DEVICE);
	290
	291	priv->stats.tx_packets++;
	292	priv->stats.tx_bytes += priv->tx_skb[tx_tail]->len;
	293
	294	dev_kfree_skb_irq(priv->tx_skb[tx_tail]);
	295	priv->tx_skb[tx_tail] = NULL;
	296
	297	tx_tail = TX_NEXT(tx_tail);
	298	}
	299	priv->tx_tail = tx_tail;
	300	}
	301
	302	static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id)
	303	{
	304	struct net_device ndev = (struct net_device ) dev_id;
	305	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	306	unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS);
	307
	308	if (ists & XPKT_OK_INT_STS)
	309	moxart_tx_finished(ndev);
	310
	311	if (ists & RPKT_FINISH) {
	312	if (napi_schedule_prep(&priv->napi)) {
	313	priv->reg_imr &= ~RPKT_FINISH_M;
	314	writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
	315	__napi_schedule(&priv->napi);
	316	}
	317	}
	318
	319	return IRQ_HANDLED;
	320	}
	321
	322	static int moxart_mac_start_xmit(struct sk_buff skb, struct net_device ndev)
	323	{
	324	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
59a557be	325	void *desc;
6c821bd9 JJ	326	unsigned int len;
	327	unsigned int tx_head = priv->tx_head;
	328	u32 txdes1;
0aa857f8	329	int ret = NETDEV_TX_BUSY;
6c821bd9 JJ	330
	331	desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head);
	332
	333	spin_lock_irq(&priv->txlock);
59a557be	334	if (moxart_desc_read(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) {
6c821bd9 JJ	335	net_dbg_ratelimited("no TX space for packet\n");
6c821bd9 JJ	336	priv->stats.tx_dropped++;
0aa857f8	337	goto out_unlock;
6c821bd9	338	}
59a557be	339	rmb(); /* ensure data is only read that had TX_DESC0_DMA_OWN cleared */
6c821bd9 JJ	340
	341	len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len;
	342
	343	priv->tx_mapping[tx_head] = dma_map_single(&ndev->dev, skb->data,
	344	len, DMA_TO_DEVICE);
	345	if (dma_mapping_error(&ndev->dev, priv->tx_mapping[tx_head])) {
	346	netdev_err(ndev, "DMA mapping error\n");
0aa857f8	347	goto out_unlock;
6c821bd9 JJ	348	}
	349
	350	priv->tx_len[tx_head] = len;
	351	priv->tx_skb[tx_head] = skb;
	352
59a557be	353	moxart_desc_write(priv->tx_mapping[tx_head],
6c821bd9	354	desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS);
59a557be	355	moxart_desc_write((uintptr_t)skb->data,
6c821bd9 JJ	356	desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT);
	357
	358	if (skb->len < ETH_ZLEN) {
	359	memset(&skb->data[skb->len],
	360	0, ETH_ZLEN - skb->len);
	361	len = ETH_ZLEN;
	362	}
	363
777fbc31 JJ	364	dma_sync_single_for_device(&ndev->dev, priv->tx_mapping[tx_head],
	365	priv->tx_buf_size, DMA_TO_DEVICE);
	366
b853f319 JJ	367	txdes1 = TX_DESC1_LTS \| TX_DESC1_FTS \| (len & TX_DESC1_BUF_SIZE_MASK);
	368	if (tx_head == TX_DESC_NUM_MASK)
	369	txdes1 \|= TX_DESC1_END;
59a557be AB	370	moxart_desc_write(txdes1, desc + TX_REG_OFFSET_DESC1);
	371	wmb(); /* flush descriptor before transferring ownership */
	372	moxart_desc_write(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0);
6c821bd9 JJ	373
	374	/* start to send packet */
	375	writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND);
	376
	377	priv->tx_head = TX_NEXT(tx_head);
	378
	379	ndev->trans_start = jiffies;
0aa857f8 WY	380	ret = NETDEV_TX_OK;
0aa857f8 WY	381	out_unlock:
6c821bd9 JJ	382	spin_unlock_irq(&priv->txlock);
6c821bd9 JJ	383
0aa857f8	384	return ret;
6c821bd9 JJ	385	}
	386
	387	static struct net_device_stats moxart_mac_get_stats(struct net_device ndev)
	388	{
	389	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	390
	391	return &priv->stats;
	392	}
	393
	394	static void moxart_mac_setmulticast(struct net_device *ndev)
	395	{
	396	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	397	struct netdev_hw_addr *ha;
	398	int crc_val;
	399
	400	netdev_for_each_mc_addr(ha, ndev) {
	401	crc_val = crc32_le(~0, ha->addr, ETH_ALEN);
	402	crc_val = (crc_val >> 26) & 0x3f;
	403	if (crc_val >= 32) {
	404	writel(readl(priv->base + REG_MCAST_HASH_TABLE1) \|
	405	(1UL << (crc_val - 32)),
	406	priv->base + REG_MCAST_HASH_TABLE1);
	407	} else {
	408	writel(readl(priv->base + REG_MCAST_HASH_TABLE0) \|
	409	(1UL << crc_val),
	410	priv->base + REG_MCAST_HASH_TABLE0);
	411	}
	412	}
	413	}
	414
	415	static void moxart_mac_set_rx_mode(struct net_device *ndev)
	416	{
	417	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
	418
	419	spin_lock_irq(&priv->txlock);
	420
	421	(ndev->flags & IFF_PROMISC) ? (priv->reg_maccr \|= RCV_ALL) :
	422	(priv->reg_maccr &= ~RCV_ALL);
	423
	424	(ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr \|= RX_MULTIPKT) :
	425	(priv->reg_maccr &= ~RX_MULTIPKT);
	426
	427	if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) {
	428	priv->reg_maccr \|= HT_MULTI_EN;
	429	moxart_mac_setmulticast(ndev);
	430	} else {
	431	priv->reg_maccr &= ~HT_MULTI_EN;
	432	}
	433
	434	writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
	435
	436	spin_unlock_irq(&priv->txlock);
	437	}
	438
	439	static struct net_device_ops moxart_netdev_ops = {
	440	.ndo_open = moxart_mac_open,
	441	.ndo_stop = moxart_mac_stop,
	442	.ndo_start_xmit = moxart_mac_start_xmit,
	443	.ndo_get_stats = moxart_mac_get_stats,
	444	.ndo_set_rx_mode = moxart_mac_set_rx_mode,
	445	.ndo_set_mac_address = moxart_set_mac_address,
	446	.ndo_validate_addr = eth_validate_addr,
	447	.ndo_change_mtu = eth_change_mtu,
	448	};
449
450	static int moxart_mac_probe(struct platform_device *pdev)
451	{
452	struct device *p_dev = &pdev->dev;
453	struct device_node *node = p_dev->of_node;
454	struct net_device *ndev;
455	struct moxart_mac_priv_t *priv;
456	struct resource *res;
457	unsigned int irq;
458	int ret;
459
460	ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t));
461	if (!ndev)
462	return -ENOMEM;
463
464	irq = irq_of_parse_and_map(node, 0);
465	if (irq <= 0) {
466	netdev_err(ndev, "irq_of_parse_and_map failed\n");
bdfd6304 WY	467	ret = -EINVAL;
bdfd6304 WY	468	goto irq_map_fail;
6c821bd9 JJ	469	}
	470
	471	priv = netdev_priv(ndev);
	472	priv->ndev = ndev;
	473
	474	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	475	ndev->base_addr = res->start;
	476	priv->base = devm_ioremap_resource(p_dev, res);
1d3cd177	477	if (IS_ERR(priv->base)) {
6c821bd9	478	dev_err(p_dev, "devm_ioremap_resource failed\n");
1d3cd177	479	ret = PTR_ERR(priv->base);
6c821bd9 JJ	480	goto init_fail;
	481	}
	482
	483	spin_lock_init(&priv->txlock);
	484
	485	priv->tx_buf_size = TX_BUF_SIZE;
9fe1b3bc	486	priv->rx_buf_size = RX_BUF_SIZE;
6c821bd9 JJ	487
	488	priv->tx_desc_base = dma_alloc_coherent(NULL, TX_REG_DESC_SIZE *
	489	TX_DESC_NUM, &priv->tx_base,
	490	GFP_DMA \| GFP_KERNEL);
bdfd6304 WY	491	if (priv->tx_desc_base == NULL) {
bdfd6304 WY	492	ret = -ENOMEM;
6c821bd9	493	goto init_fail;
bdfd6304	494	}
6c821bd9 JJ	495
	496	priv->rx_desc_base = dma_alloc_coherent(NULL, RX_REG_DESC_SIZE *
	497	RX_DESC_NUM, &priv->rx_base,
	498	GFP_DMA \| GFP_KERNEL);
bdfd6304 WY	499	if (priv->rx_desc_base == NULL) {
bdfd6304 WY	500	ret = -ENOMEM;
6c821bd9	501	goto init_fail;
bdfd6304	502	}
6c821bd9 JJ	503
	504	priv->tx_buf_base = kmalloc(priv->tx_buf_size * TX_DESC_NUM,
	505	GFP_ATOMIC);
bdfd6304 WY	506	if (!priv->tx_buf_base) {
bdfd6304 WY	507	ret = -ENOMEM;
6c821bd9	508	goto init_fail;
bdfd6304	509	}
6c821bd9 JJ	510
	511	priv->rx_buf_base = kmalloc(priv->rx_buf_size * RX_DESC_NUM,
	512	GFP_ATOMIC);
bdfd6304 WY	513	if (!priv->rx_buf_base) {
bdfd6304 WY	514	ret = -ENOMEM;
6c821bd9	515	goto init_fail;
bdfd6304	516	}
6c821bd9 JJ	517
	518	platform_set_drvdata(pdev, ndev);
	519
	520	ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0,
	521	pdev->name, ndev);
	522	if (ret) {
	523	netdev_err(ndev, "devm_request_irq failed\n");
	524	goto init_fail;
	525	}
	526
6c821bd9 JJ	527	ndev->netdev_ops = &moxart_netdev_ops;
	528	netif_napi_add(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM);
	529	ndev->priv_flags \|= IFF_UNICAST_FLT;
	530	ndev->irq = irq;
	531
	532	SET_NETDEV_DEV(ndev, &pdev->dev);
	533
	534	ret = register_netdev(ndev);
	535	if (ret) {
	536	free_netdev(ndev);
	537	goto init_fail;
	538	}
	539
	540	netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n",
	541	__func__, ndev->irq, ndev->dev_addr);
	542
	543	return 0;
	544
	545	init_fail:
	546	netdev_err(ndev, "init failed\n");
	547	moxart_mac_free_memory(ndev);
bdfd6304 WY	548	irq_map_fail:
bdfd6304 WY	549	free_netdev(ndev);
6c821bd9 JJ	550	return ret;
	551	}
	552
	553	static int moxart_remove(struct platform_device *pdev)
	554	{
	555	struct net_device *ndev = platform_get_drvdata(pdev);
	556
	557	unregister_netdev(ndev);
	558	free_irq(ndev->irq, ndev);
	559	moxart_mac_free_memory(ndev);
6c821bd9 JJ	560	free_netdev(ndev);
	561
	562	return 0;
	563	}
	564
	565	static const struct of_device_id moxart_mac_match[] = {
	566	{ .compatible = "moxa,moxart-mac" },
	567	{ }
	568	};
ebd8ebf0	569	MODULE_DEVICE_TABLE(of, moxart_mac_match);
6c821bd9	570
437a3ae1	571	static struct platform_driver moxart_mac_driver = {
6c821bd9 JJ	572	.probe = moxart_mac_probe,
	573	.remove = moxart_remove,
	574	.driver = {
	575	.name = "moxart-ethernet",
6c821bd9 JJ	576	.of_match_table = moxart_mac_match,
	577	},
	578	};
	579	module_platform_driver(moxart_mac_driver);
	580
	581	MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
	582	MODULE_LICENSE("GPL v2");
	583	MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");