[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed.h

/* QLogic qed NIC Driver
 * Copyright (c) 2015 QLogic Corporation
 *
 * This software is available under the terms of the GNU General Public License
 * (GPL) Version 2, available from the file COPYING in the main directory of
 * this source tree.
 */

#ifndef _QED_H
#define _QED_H

#include <linux/types.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/workqueue.h>
#include <linux/zlib.h>
#include <linux/hashtable.h>
#include <linux/qed/qed_if.h>
#include "qed_debug.h"
#include "qed_hsi.h"

extern const struct qed_common_ops qed_common_ops_pass;
#define DRV_MODULE_VERSION "8.10.9.20"

#define MAX_HWFNS_PER_DEVICE    (4)
#define NAME_SIZE 16
#define VER_SIZE 16

#define QED_WFQ_UNIT	100

/* cau states */
enum qed_coalescing_mode {
	QED_COAL_MODE_DISABLE,
	QED_COAL_MODE_ENABLE
};

struct qed_eth_cb_ops;
struct qed_dev_info;
union qed_mcp_protocol_stats;
enum qed_mcp_protocol_type;

/* helpers */
static inline u32 qed_db_addr(u32 cid, u32 DEMS)
{
	u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
		      FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);

	return db_addr;
}

#define ALIGNED_TYPE_SIZE(type_name, p_hwfn)				     \
	((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
	 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))

#define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)

#define D_TRINE(val, cond1, cond2, true1, true2, def) \
	(val == (cond1) ? true1 :		      \
	 (val == (cond2) ? true2 : def))

/* forward */
struct qed_ptt_pool;
struct qed_spq;
struct qed_sb_info;
struct qed_sb_attn_info;
struct qed_cxt_mngr;
struct qed_sb_sp_info;
struct qed_mcp_info;

struct qed_rt_data {
	u32	*init_val;
	bool	*b_valid;
};

enum qed_tunn_mode {
	QED_MODE_L2GENEVE_TUNN,
	QED_MODE_IPGENEVE_TUNN,
	QED_MODE_L2GRE_TUNN,
	QED_MODE_IPGRE_TUNN,
	QED_MODE_VXLAN_TUNN,
};

enum qed_tunn_clss {
	QED_TUNN_CLSS_MAC_VLAN,
	QED_TUNN_CLSS_MAC_VNI,
	QED_TUNN_CLSS_INNER_MAC_VLAN,
	QED_TUNN_CLSS_INNER_MAC_VNI,
	MAX_QED_TUNN_CLSS,
};

struct qed_tunn_start_params {
	unsigned long	tunn_mode;
	u16		vxlan_udp_port;
	u16		geneve_udp_port;
	u8		update_vxlan_udp_port;
	u8		update_geneve_udp_port;
	u8		tunn_clss_vxlan;
	u8		tunn_clss_l2geneve;
	u8		tunn_clss_ipgeneve;
	u8		tunn_clss_l2gre;
	u8		tunn_clss_ipgre;
};

struct qed_tunn_update_params {
	unsigned long	tunn_mode_update_mask;
	unsigned long	tunn_mode;
	u16		vxlan_udp_port;
	u16		geneve_udp_port;
	u8		update_rx_pf_clss;
	u8		update_tx_pf_clss;
	u8		update_vxlan_udp_port;
	u8		update_geneve_udp_port;
	u8		tunn_clss_vxlan;
	u8		tunn_clss_l2geneve;
	u8		tunn_clss_ipgeneve;
	u8		tunn_clss_l2gre;
	u8		tunn_clss_ipgre;
};

/* The PCI personality is not quite synonymous to protocol ID:
 * 1. All personalities need CORE connections
 * 2. The Ethernet personality may support also the RoCE protocol
 */
enum qed_pci_personality {
	QED_PCI_ETH,
	QED_PCI_ISCSI,
	QED_PCI_ETH_ROCE,
	QED_PCI_DEFAULT /* default in shmem */
};

/* All VFs are symmetric, all counters are PF + all VFs */
struct qed_qm_iids {
	u32 cids;
	u32 vf_cids;
	u32 tids;
};

enum QED_RESOURCES {
	QED_SB,
	QED_L2_QUEUE,
	QED_VPORT,
	QED_RSS_ENG,
	QED_PQ,
	QED_RL,
	QED_MAC,
	QED_VLAN,
	QED_ILT,
	QED_MAX_RESC,
};

enum QED_FEATURE {
	QED_PF_L2_QUE,
	QED_VF,
	QED_MAX_FEATURES,
};

enum QED_PORT_MODE {
	QED_PORT_MODE_DE_2X40G,
	QED_PORT_MODE_DE_2X50G,
	QED_PORT_MODE_DE_1X100G,
	QED_PORT_MODE_DE_4X10G_F,
	QED_PORT_MODE_DE_4X10G_E,
	QED_PORT_MODE_DE_4X20G,
	QED_PORT_MODE_DE_1X40G,
	QED_PORT_MODE_DE_2X25G,
	QED_PORT_MODE_DE_1X25G
};

enum qed_dev_cap {
	QED_DEV_CAP_ETH,
	QED_DEV_CAP_ISCSI,
	QED_DEV_CAP_ROCE,
};

struct qed_hw_info {
	/* PCI personality */
	enum qed_pci_personality	personality;

	/* Resource Allocation scheme results */
	u32				resc_start[QED_MAX_RESC];
	u32				resc_num[QED_MAX_RESC];
	u32				feat_num[QED_MAX_FEATURES];

#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
				 RESC_NUM(_p_hwfn, resc))
#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])

	u8				num_tc;
	u8				offload_tc;
	u8				non_offload_tc;

	u32				concrete_fid;
	u16				opaque_fid;
	u16				ovlan;
	u32				part_num[4];

	unsigned char			hw_mac_addr[ETH_ALEN];

	struct qed_igu_info		*p_igu_info;

	u32				port_mode;
	u32				hw_mode;
	unsigned long		device_capabilities;
};

struct qed_hw_cid_data {
	u32	cid;
	bool	b_cid_allocated;

	/* Additional identifiers */
	u16	opaque_fid;
	u8	vport_id;
};

/* maximun size of read/write commands (HW limit) */
#define DMAE_MAX_RW_SIZE        0x2000

struct qed_dmae_info {
	/* Mutex for synchronizing access to functions */
	struct mutex	mutex;

	u8		channel;

	dma_addr_t	completion_word_phys_addr;

	/* The memory location where the DMAE writes the completion
	 * value when an operation is finished on this context.
	 */
	u32		*p_completion_word;

	dma_addr_t	intermediate_buffer_phys_addr;

	/* An intermediate buffer for DMAE operations that use virtual
	 * addresses - data is DMA'd to/from this buffer and then
	 * memcpy'd to/from the virtual address
	 */
	u32		*p_intermediate_buffer;

	dma_addr_t	dmae_cmd_phys_addr;
	struct dmae_cmd *p_dmae_cmd;
};

struct qed_wfq_data {
	/* when feature is configured for at least 1 vport */
	u32	min_speed;
	bool	configured;
};

struct qed_qm_info {
	struct init_qm_pq_params	*qm_pq_params;
	struct init_qm_vport_params	*qm_vport_params;
	struct init_qm_port_params	*qm_port_params;
	u16				start_pq;
	u8				start_vport;
	u8				pure_lb_pq;
	u8				offload_pq;
	u8				pure_ack_pq;
	u8 ooo_pq;
	u8				vf_queues_offset;
	u16				num_pqs;
	u16				num_vf_pqs;
	u8				num_vports;
	u8				max_phys_tcs_per_port;
	bool				pf_rl_en;
	bool				pf_wfq_en;
	bool				vport_rl_en;
	bool				vport_wfq_en;
	u8				pf_wfq;
	u32				pf_rl;
	struct qed_wfq_data		*wfq_data;
	u8 num_pf_rls;
};

struct storm_stats {
	u32     address;
	u32     len;
};

struct qed_storm_stats {
	struct storm_stats mstats;
	struct storm_stats pstats;
	struct storm_stats tstats;
	struct storm_stats ustats;
};

struct qed_fw_data {
	struct fw_ver_info	*fw_ver_info;
	const u8		*modes_tree_buf;
	union init_op		*init_ops;
	const u32		*arr_data;
	u32			init_ops_size;
};

struct qed_simd_fp_handler {
	void	*token;
	void	(*func)(void *);
};

struct qed_hwfn {
	struct qed_dev			*cdev;
	u8				my_id;          /* ID inside the PF */
#define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
	u8				rel_pf_id;      /* Relative to engine*/
	u8				abs_pf_id;
#define QED_PATH_ID(_p_hwfn)		((_p_hwfn)->abs_pf_id & 1)
	u8				port_id;
	bool				b_active;

	u32				dp_module;
	u8				dp_level;
	char				name[NAME_SIZE];

	bool				first_on_engine;
	bool				hw_init_done;

	u8				num_funcs_on_engine;
	u8 enabled_func_idx;

	/* BAR access */
	void __iomem			*regview;
	void __iomem			*doorbells;
	u64				db_phys_addr;
	unsigned long			db_size;

	/* PTT pool */
	struct qed_ptt_pool		*p_ptt_pool;

	/* HW info */
	struct qed_hw_info		hw_info;

	/* rt_array (for init-tool) */
	struct qed_rt_data		rt_data;

	/* SPQ */
	struct qed_spq			*p_spq;

	/* EQ */
	struct qed_eq			*p_eq;

	/* Consolidate Q*/
	struct qed_consq		*p_consq;

	/* Slow-Path definitions */
	struct tasklet_struct		*sp_dpc;
	bool				b_sp_dpc_enabled;

	struct qed_ptt			*p_main_ptt;
	struct qed_ptt			*p_dpc_ptt;

	struct qed_sb_sp_info		*p_sp_sb;
	struct qed_sb_attn_info		*p_sb_attn;

	/* Protocol related */
	struct qed_pf_params		pf_params;

	bool b_rdma_enabled_in_prs;
	u32 rdma_prs_search_reg;

	/* Array of sb_info of all status blocks */
	struct qed_sb_info		*sbs_info[MAX_SB_PER_PF_MIMD];
	u16				num_sbs;

	struct qed_cxt_mngr		*p_cxt_mngr;

	/* Flag indicating whether interrupts are enabled or not*/
	bool				b_int_enabled;
	bool				b_int_requested;

	/* True if the driver requests for the link */
	bool				b_drv_link_init;

	struct qed_vf_iov		*vf_iov_info;
	struct qed_pf_iov		*pf_iov_info;
	struct qed_mcp_info		*mcp_info;

	struct qed_dcbx_info		*p_dcbx_info;

	struct qed_hw_cid_data		*p_tx_cids;
	struct qed_hw_cid_data		*p_rx_cids;

	struct qed_dmae_info		dmae_info;

	/* QM init */
	struct qed_qm_info		qm_info;
	struct qed_storm_stats		storm_stats;

	/* Buffer for unzipping firmware data */
	void				*unzip_buf;

	struct dbg_tools_data		dbg_info;

	struct qed_simd_fp_handler	simd_proto_handler[64];

#ifdef CONFIG_QED_SRIOV
	struct workqueue_struct *iov_wq;
	struct delayed_work iov_task;
	unsigned long iov_task_flags;
#endif

	struct z_stream_s		*stream;
};

struct pci_params {
	int		pm_cap;

	unsigned long	mem_start;
	unsigned long	mem_end;
	unsigned int	irq;
	u8		pf_num;
};

struct qed_int_param {
	u32	int_mode;
	u8	num_vectors;
	u8	min_msix_cnt; /* for minimal functionality */
};

struct qed_int_params {
	struct qed_int_param	in;
	struct qed_int_param	out;
	struct msix_entry	*msix_table;
	bool			fp_initialized;
	u8			fp_msix_base;
	u8			fp_msix_cnt;
};

struct qed_dbg_feature {
	struct dentry *dentry;
	u8 *dump_buf;
	u32 buf_size;
	u32 dumped_dwords;
};

struct qed_dbg_params {
	struct qed_dbg_feature features[DBG_FEATURE_NUM];
	u8 engine_for_debug;
	bool print_data;
};

struct qed_dev {
	u32	dp_module;
	u8	dp_level;
	char	name[NAME_SIZE];

	u8	type;
#define QED_DEV_TYPE_BB (0 << 0)
#define QED_DEV_TYPE_AH BIT(0)
/* Translate type/revision combo into the proper conditions */
#define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
#define QED_IS_BB_A0(dev)       (QED_IS_BB(dev) && \
				 CHIP_REV_IS_A0(dev))
#define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
				 CHIP_REV_IS_B0(dev))
#define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
#define QED_IS_K2(dev)  QED_IS_AH(dev)

#define QED_GET_TYPE(dev)       (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
				 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)

	u16	vendor_id;
	u16	device_id;

	u16	chip_num;
#define CHIP_NUM_MASK                   0xffff
#define CHIP_NUM_SHIFT                  16

	u16	chip_rev;
#define CHIP_REV_MASK                   0xf
#define CHIP_REV_SHIFT                  12
#define CHIP_REV_IS_A0(_cdev)   (!(_cdev)->chip_rev)
#define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)

	u16				chip_metal;
#define CHIP_METAL_MASK                 0xff
#define CHIP_METAL_SHIFT                4

	u16				chip_bond_id;
#define CHIP_BOND_ID_MASK               0xf
#define CHIP_BOND_ID_SHIFT              0

	u8				num_engines;
	u8				num_ports_in_engines;
	u8				num_funcs_in_port;

	u8				path_id;
	enum qed_mf_mode		mf_mode;
#define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
#define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
#define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)

	int				pcie_width;
	int				pcie_speed;
	u8				ver_str[VER_SIZE];

	/* Add MF related configuration */
	u8				mcp_rev;
	u8				boot_mode;

	u8				wol;

	u32				int_mode;
	enum qed_coalescing_mode	int_coalescing_mode;
	u16				rx_coalesce_usecs;
	u16				tx_coalesce_usecs;

	/* Start Bar offset of first hwfn */
	void __iomem			*regview;
	void __iomem			*doorbells;
	u64				db_phys_addr;
	unsigned long			db_size;

	/* PCI */
	u8				cache_shift;

	/* Init */
	const struct iro		*iro_arr;
#define IRO (p_hwfn->cdev->iro_arr)

	/* HW functions */
	u8				num_hwfns;
	struct qed_hwfn			hwfns[MAX_HWFNS_PER_DEVICE];

	/* SRIOV */
	struct qed_hw_sriov_info *p_iov_info;
#define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)

	unsigned long			tunn_mode;

	bool				b_is_vf;
	u32				drv_type;

	struct qed_eth_stats		*reset_stats;
	struct qed_fw_data		*fw_data;

	u32				mcp_nvm_resp;

	/* Linux specific here */
	struct  qede_dev		*edev;
	struct  pci_dev			*pdev;
	int				msg_enable;

	struct pci_params		pci_params;

	struct qed_int_params		int_params;

	u8				protocol;
#define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)

	/* Callbacks to protocol driver */
	union {
		struct qed_common_cb_ops	*common;
		struct qed_eth_cb_ops		*eth;
	} protocol_ops;
	void				*ops_cookie;

	struct qed_dbg_params		dbg_params;

	const struct firmware		*firmware;
};

#define NUM_OF_VFS(dev)         MAX_NUM_VFS_BB
#define NUM_OF_L2_QUEUES(dev)	MAX_NUM_L2_QUEUES_BB
#define NUM_OF_SBS(dev)         MAX_SB_PER_PATH_BB
#define NUM_OF_ENG_PFS(dev)     MAX_NUM_PFS_BB

/**
 * @brief qed_concrete_to_sw_fid - get the sw function id from
 *        the concrete value.
 *
 * @param concrete_fid
 *
 * @return inline u8
 */
static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
					u32 concrete_fid)
{
	u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
	u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
	u8 vf_valid = GET_FIELD(concrete_fid,
				PXP_CONCRETE_FID_VFVALID);
	u8 sw_fid;

	if (vf_valid)
		sw_fid = vfid + MAX_NUM_PFS;
	else
		sw_fid = pfid;

	return sw_fid;
}

#define PURE_LB_TC 8
#define OOO_LB_TC 9

int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);

void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
#define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])

/* Other Linux specific common definitions */
#define DP_NAME(cdev) ((cdev)->name)

#define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
						(cdev->regview) + \
							 (offset))

#define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
#define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
#define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))

#define DOORBELL(cdev, db_addr, val)			 \
	writel((u32)val, (void __iomem *)((u8 __iomem *)\
					  (cdev->doorbells) + (db_addr)))

/* Prototypes */
int qed_fill_dev_info(struct qed_dev *cdev,
		      struct qed_dev_info *dev_info);
void qed_link_update(struct qed_hwfn *hwfn);
u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
		   u32 input_len, u8 *input_buf,
		   u32 max_size, u8 *unzip_buf);
void qed_get_protocol_stats(struct qed_dev *cdev,
			    enum qed_mcp_protocol_type type,
			    union qed_mcp_protocol_stats *stats);
int qed_slowpath_irq_req(struct qed_hwfn *hwfn);

#endif /* _QED_H */
Commit	Line	Data
fe56b9e6 YM	1	/* QLogic qed NIC Driver
	2	* Copyright (c) 2015 QLogic Corporation
	3	*
	4	* This software is available under the terms of the GNU General Public License
	5	* (GPL) Version 2, available from the file COPYING in the main directory of
	6	* this source tree.
	7	*/
	8
	9	#ifndef _QED_H
	10	#define _QED_H
	11
	12	#include <linux/types.h>
	13	#include <linux/io.h>
	14	#include <linux/delay.h>
	15	#include <linux/firmware.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/list.h>
	18	#include <linux/mutex.h>
	19	#include <linux/pci.h>
	20	#include <linux/slab.h>
	21	#include <linux/string.h>
	22	#include <linux/workqueue.h>
	23	#include <linux/zlib.h>
	24	#include <linux/hashtable.h>
	25	#include <linux/qed/qed_if.h>
c965db44	26	#include "qed_debug.h"
fe56b9e6 YM	27	#include "qed_hsi.h"
fe56b9e6 YM	28
25c089d7	29	extern const struct qed_common_ops qed_common_ops_pass;
05fafbfb	30	#define DRV_MODULE_VERSION "8.10.9.20"
fe56b9e6 YM	31
	32	#define MAX_HWFNS_PER_DEVICE (4)
	33	#define NAME_SIZE 16
	34	#define VER_SIZE 16
	35
bcd197c8 MC	36	#define QED_WFQ_UNIT 100
bcd197c8 MC	37
fe56b9e6 YM	38	/* cau states */
	39	enum qed_coalescing_mode {
	40	QED_COAL_MODE_DISABLE,
	41	QED_COAL_MODE_ENABLE
	42	};
	43
	44	struct qed_eth_cb_ops;
	45	struct qed_dev_info;
6c754246 SRK	46	union qed_mcp_protocol_stats;
6c754246 SRK	47	enum qed_mcp_protocol_type;
fe56b9e6 YM	48
	49	/* helpers */
	50	static inline u32 qed_db_addr(u32 cid, u32 DEMS)
	51	{
	52	u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) \|
	53	FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
	54
	55	return db_addr;
	56	}
	57
	58	#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
	59	((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
	60	~((1 << (p_hwfn->cdev->cache_shift)) - 1))
	61
	62	#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
	63
	64	#define D_TRINE(val, cond1, cond2, true1, true2, def) \
	65	(val == (cond1) ? true1 : \
	66	(val == (cond2) ? true2 : def))
	67
	68	/* forward */
	69	struct qed_ptt_pool;
	70	struct qed_spq;
	71	struct qed_sb_info;
	72	struct qed_sb_attn_info;
	73	struct qed_cxt_mngr;
	74	struct qed_sb_sp_info;
	75	struct qed_mcp_info;
	76
	77	struct qed_rt_data {
fc48b7a6 YM	78	u32 *init_val;
fc48b7a6 YM	79	bool *b_valid;
fe56b9e6 YM	80	};
fe56b9e6 YM	81
464f6645 MC	82	enum qed_tunn_mode {
	83	QED_MODE_L2GENEVE_TUNN,
	84	QED_MODE_IPGENEVE_TUNN,
	85	QED_MODE_L2GRE_TUNN,
	86	QED_MODE_IPGRE_TUNN,
	87	QED_MODE_VXLAN_TUNN,
	88	};
	89
	90	enum qed_tunn_clss {
	91	QED_TUNN_CLSS_MAC_VLAN,
	92	QED_TUNN_CLSS_MAC_VNI,
	93	QED_TUNN_CLSS_INNER_MAC_VLAN,
	94	QED_TUNN_CLSS_INNER_MAC_VNI,
	95	MAX_QED_TUNN_CLSS,
	96	};
	97
	98	struct qed_tunn_start_params {
	99	unsigned long tunn_mode;
	100	u16 vxlan_udp_port;
	101	u16 geneve_udp_port;
	102	u8 update_vxlan_udp_port;
	103	u8 update_geneve_udp_port;
	104	u8 tunn_clss_vxlan;
	105	u8 tunn_clss_l2geneve;
	106	u8 tunn_clss_ipgeneve;
	107	u8 tunn_clss_l2gre;
	108	u8 tunn_clss_ipgre;
	109	};
	110
	111	struct qed_tunn_update_params {
	112	unsigned long tunn_mode_update_mask;
	113	unsigned long tunn_mode;
	114	u16 vxlan_udp_port;
	115	u16 geneve_udp_port;
	116	u8 update_rx_pf_clss;
	117	u8 update_tx_pf_clss;
	118	u8 update_vxlan_udp_port;
	119	u8 update_geneve_udp_port;
	120	u8 tunn_clss_vxlan;
	121	u8 tunn_clss_l2geneve;
	122	u8 tunn_clss_ipgeneve;
	123	u8 tunn_clss_l2gre;
	124	u8 tunn_clss_ipgre;
	125	};
	126
fe56b9e6 YM	127	/* The PCI personality is not quite synonymous to protocol ID:
	128	* 1. All personalities need CORE connections
	129	* 2. The Ethernet personality may support also the RoCE protocol
	130	*/
	131	enum qed_pci_personality {
	132	QED_PCI_ETH,
c5ac9319 YM	133	QED_PCI_ISCSI,
c5ac9319 YM	134	QED_PCI_ETH_ROCE,
fe56b9e6 YM	135	QED_PCI_DEFAULT /* default in shmem */
	136	};
	137
	138	/* All VFs are symmetric, all counters are PF + all VFs */
	139	struct qed_qm_iids {
	140	u32 cids;
	141	u32 vf_cids;
	142	u32 tids;
	143	};
	144
	145	enum QED_RESOURCES {
	146	QED_SB,
25c089d7	147	QED_L2_QUEUE,
fe56b9e6	148	QED_VPORT,
25c089d7	149	QED_RSS_ENG,
fe56b9e6 YM	150	QED_PQ,
fe56b9e6 YM	151	QED_RL,
25c089d7 YM	152	QED_MAC,
25c089d7 YM	153	QED_VLAN,
fe56b9e6 YM	154	QED_ILT,
	155	QED_MAX_RESC,
	156	};
	157
25c089d7 YM	158	enum QED_FEATURE {
25c089d7 YM	159	QED_PF_L2_QUE,
32a47e72	160	QED_VF,
25c089d7 YM	161	QED_MAX_FEATURES,
	162	};
	163
cc875c2e YM	164	enum QED_PORT_MODE {
	165	QED_PORT_MODE_DE_2X40G,
	166	QED_PORT_MODE_DE_2X50G,
	167	QED_PORT_MODE_DE_1X100G,
	168	QED_PORT_MODE_DE_4X10G_F,
	169	QED_PORT_MODE_DE_4X10G_E,
	170	QED_PORT_MODE_DE_4X20G,
	171	QED_PORT_MODE_DE_1X40G,
	172	QED_PORT_MODE_DE_2X25G,
	173	QED_PORT_MODE_DE_1X25G
	174	};
	175
fc48b7a6 YM	176	enum qed_dev_cap {
fc48b7a6 YM	177	QED_DEV_CAP_ETH,
c5ac9319 YM	178	QED_DEV_CAP_ISCSI,
c5ac9319 YM	179	QED_DEV_CAP_ROCE,
fc48b7a6 YM	180	};
fc48b7a6 YM	181
fe56b9e6 YM	182	struct qed_hw_info {
	183	/* PCI personality */
	184	enum qed_pci_personality personality;
	185
	186	/* Resource Allocation scheme results */
	187	u32 resc_start[QED_MAX_RESC];
	188	u32 resc_num[QED_MAX_RESC];
25c089d7	189	u32 feat_num[QED_MAX_FEATURES];
fe56b9e6 YM	190
	191	#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
	192	#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
dbb799c3 YM	193	#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
dbb799c3 YM	194	RESC_NUM(_p_hwfn, resc))
fe56b9e6 YM	195	#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
	196
	197	u8 num_tc;
	198	u8 offload_tc;
	199	u8 non_offload_tc;
	200
	201	u32 concrete_fid;
	202	u16 opaque_fid;
	203	u16 ovlan;
	204	u32 part_num[4];
	205
fe56b9e6 YM	206	unsigned char hw_mac_addr[ETH_ALEN];
	207
	208	struct qed_igu_info *p_igu_info;
	209
	210	u32 port_mode;
	211	u32 hw_mode;
fc48b7a6	212	unsigned long device_capabilities;
fe56b9e6 YM	213	};
	214
	215	struct qed_hw_cid_data {
	216	u32 cid;
	217	bool b_cid_allocated;
	218
	219	/* Additional identifiers */
	220	u16 opaque_fid;
	221	u8 vport_id;
	222	};
	223
	224	/* maximun size of read/write commands (HW limit) */
	225	#define DMAE_MAX_RW_SIZE 0x2000
	226
	227	struct qed_dmae_info {
	228	/* Mutex for synchronizing access to functions */
	229	struct mutex mutex;
	230
	231	u8 channel;
	232
	233	dma_addr_t completion_word_phys_addr;
	234
	235	/* The memory location where the DMAE writes the completion
	236	* value when an operation is finished on this context.
	237	*/
	238	u32 *p_completion_word;
	239
	240	dma_addr_t intermediate_buffer_phys_addr;
	241
	242	/* An intermediate buffer for DMAE operations that use virtual
	243	* addresses - data is DMA'd to/from this buffer and then
	244	* memcpy'd to/from the virtual address
	245	*/
	246	u32 *p_intermediate_buffer;
	247
	248	dma_addr_t dmae_cmd_phys_addr;
	249	struct dmae_cmd *p_dmae_cmd;
	250	};
	251
bcd197c8 MC	252	struct qed_wfq_data {
	253	/* when feature is configured for at least 1 vport */
	254	u32 min_speed;
	255	bool configured;
	256	};
	257
fe56b9e6 YM	258	struct qed_qm_info {
	259	struct init_qm_pq_params *qm_pq_params;
	260	struct init_qm_vport_params *qm_vport_params;
	261	struct init_qm_port_params *qm_port_params;
	262	u16 start_pq;
	263	u8 start_vport;
	264	u8 pure_lb_pq;
	265	u8 offload_pq;
	266	u8 pure_ack_pq;
dbb799c3	267	u8 ooo_pq;
fe56b9e6 YM	268	u8 vf_queues_offset;
	269	u16 num_pqs;
	270	u16 num_vf_pqs;
	271	u8 num_vports;
	272	u8 max_phys_tcs_per_port;
	273	bool pf_rl_en;
	274	bool pf_wfq_en;
	275	bool vport_rl_en;
	276	bool vport_wfq_en;
	277	u8 pf_wfq;
	278	u32 pf_rl;
bcd197c8	279	struct qed_wfq_data *wfq_data;
dbb799c3	280	u8 num_pf_rls;
fe56b9e6 YM	281	};
fe56b9e6 YM	282
9df2ed04 MC	283	struct storm_stats {
	284	u32 address;
	285	u32 len;
	286	};
	287
	288	struct qed_storm_stats {
	289	struct storm_stats mstats;
	290	struct storm_stats pstats;
	291	struct storm_stats tstats;
	292	struct storm_stats ustats;
	293	};
	294
fe56b9e6	295	struct qed_fw_data {
9df2ed04	296	struct fw_ver_info *fw_ver_info;
fe56b9e6 YM	297	const u8 *modes_tree_buf;
	298	union init_op *init_ops;
	299	const u32 *arr_data;
	300	u32 init_ops_size;
	301	};
	302
	303	struct qed_simd_fp_handler {
	304	void *token;
	305	void (func)(void );
	306	};
	307
	308	struct qed_hwfn {
	309	struct qed_dev *cdev;
	310	u8 my_id; /* ID inside the PF */
	311	#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
	312	u8 rel_pf_id; /* Relative to engine*/
	313	u8 abs_pf_id;
	314	#define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
	315	u8 port_id;
	316	bool b_active;
	317
	318	u32 dp_module;
	319	u8 dp_level;
	320	char name[NAME_SIZE];
	321
	322	bool first_on_engine;
	323	bool hw_init_done;
	324
1408cc1f	325	u8 num_funcs_on_engine;
dbb799c3	326	u8 enabled_func_idx;
1408cc1f	327
fe56b9e6 YM	328	/* BAR access */
	329	void __iomem *regview;
	330	void __iomem *doorbells;
	331	u64 db_phys_addr;
	332	unsigned long db_size;
	333
	334	/* PTT pool */
	335	struct qed_ptt_pool *p_ptt_pool;
	336
	337	/* HW info */
	338	struct qed_hw_info hw_info;
	339
	340	/* rt_array (for init-tool) */
fc48b7a6	341	struct qed_rt_data rt_data;
fe56b9e6 YM	342
	343	/* SPQ */
	344	struct qed_spq *p_spq;
	345
	346	/* EQ */
	347	struct qed_eq *p_eq;
	348
	349	/* Consolidate Q*/
	350	struct qed_consq *p_consq;
	351
	352	/* Slow-Path definitions */
	353	struct tasklet_struct *sp_dpc;
	354	bool b_sp_dpc_enabled;
	355
	356	struct qed_ptt *p_main_ptt;
	357	struct qed_ptt *p_dpc_ptt;
	358
	359	struct qed_sb_sp_info *p_sp_sb;
	360	struct qed_sb_attn_info *p_sb_attn;
	361
	362	/* Protocol related */
	363	struct qed_pf_params pf_params;
	364
dbb799c3 YM	365	bool b_rdma_enabled_in_prs;
	366	u32 rdma_prs_search_reg;
	367
fe56b9e6 YM	368	/* Array of sb_info of all status blocks */
	369	struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
	370	u16 num_sbs;
	371
	372	struct qed_cxt_mngr *p_cxt_mngr;
	373
	374	/* Flag indicating whether interrupts are enabled or not*/
	375	bool b_int_enabled;
8f16bc97	376	bool b_int_requested;
fe56b9e6	377
fc916ff2 SRK	378	/* True if the driver requests for the link */
	379	bool b_drv_link_init;
	380
1408cc1f	381	struct qed_vf_iov *vf_iov_info;
32a47e72	382	struct qed_pf_iov *pf_iov_info;
fe56b9e6 YM	383	struct qed_mcp_info *mcp_info;
fe56b9e6 YM	384
39651abd SRK	385	struct qed_dcbx_info *p_dcbx_info;
39651abd SRK	386
25c089d7 YM	387	struct qed_hw_cid_data *p_tx_cids;
	388	struct qed_hw_cid_data *p_rx_cids;
	389
fe56b9e6 YM	390	struct qed_dmae_info dmae_info;
	391
	392	/* QM init */
	393	struct qed_qm_info qm_info;
9df2ed04	394	struct qed_storm_stats storm_stats;
fe56b9e6 YM	395
	396	/* Buffer for unzipping firmware data */
	397	void *unzip_buf;
	398
c965db44 TT	399	struct dbg_tools_data dbg_info;
c965db44 TT	400
fe56b9e6 YM	401	struct qed_simd_fp_handler simd_proto_handler[64];
fe56b9e6 YM	402
37bff2b9 YM	403	#ifdef CONFIG_QED_SRIOV
	404	struct workqueue_struct *iov_wq;
	405	struct delayed_work iov_task;
	406	unsigned long iov_task_flags;
	407	#endif
	408
fe56b9e6 YM	409	struct z_stream_s *stream;
	410	};
	411
	412	struct pci_params {
	413	int pm_cap;
	414
	415	unsigned long mem_start;
	416	unsigned long mem_end;
	417	unsigned int irq;
	418	u8 pf_num;
	419	};
	420
	421	struct qed_int_param {
	422	u32 int_mode;
	423	u8 num_vectors;
	424	u8 min_msix_cnt; /* for minimal functionality */
	425	};
	426
	427	struct qed_int_params {
	428	struct qed_int_param in;
	429	struct qed_int_param out;
	430	struct msix_entry *msix_table;
	431	bool fp_initialized;
	432	u8 fp_msix_base;
	433	u8 fp_msix_cnt;
	434	};
	435
c965db44 TT	436	struct qed_dbg_feature {
	437	struct dentry *dentry;
	438	u8 *dump_buf;
	439	u32 buf_size;
	440	u32 dumped_dwords;
	441	};
	442
	443	struct qed_dbg_params {
	444	struct qed_dbg_feature features[DBG_FEATURE_NUM];
	445	u8 engine_for_debug;
	446	bool print_data;
	447	};
	448
fe56b9e6 YM	449	struct qed_dev {
	450	u32 dp_module;
	451	u8 dp_level;
	452	char name[NAME_SIZE];
	453
	454	u8 type;
fc48b7a6 YM	455	#define QED_DEV_TYPE_BB (0 << 0)
	456	#define QED_DEV_TYPE_AH BIT(0)
	457	/* Translate type/revision combo into the proper conditions */
	458	#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
	459	#define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
	460	CHIP_REV_IS_A0(dev))
	461	#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
	462	CHIP_REV_IS_B0(dev))
c965db44 TT	463	#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
c965db44 TT	464	#define QED_IS_K2(dev) QED_IS_AH(dev)
fc48b7a6 YM	465
	466	#define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
	467	QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
	468
	469	u16 vendor_id;
	470	u16 device_id;
fe56b9e6 YM	471
	472	u16 chip_num;
	473	#define CHIP_NUM_MASK 0xffff
	474	#define CHIP_NUM_SHIFT 16
	475
	476	u16 chip_rev;
	477	#define CHIP_REV_MASK 0xf
	478	#define CHIP_REV_SHIFT 12
fc48b7a6 YM	479	#define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
fc48b7a6 YM	480	#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
fe56b9e6 YM	481
	482	u16 chip_metal;
	483	#define CHIP_METAL_MASK 0xff
	484	#define CHIP_METAL_SHIFT 4
	485
	486	u16 chip_bond_id;
	487	#define CHIP_BOND_ID_MASK 0xf
	488	#define CHIP_BOND_ID_SHIFT 0
	489
	490	u8 num_engines;
	491	u8 num_ports_in_engines;
	492	u8 num_funcs_in_port;
	493
	494	u8 path_id;
fc48b7a6 YM	495	enum qed_mf_mode mf_mode;
	496	#define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
	497	#define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
	498	#define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
fe56b9e6 YM	499
	500	int pcie_width;
	501	int pcie_speed;
	502	u8 ver_str[VER_SIZE];
	503
	504	/* Add MF related configuration */
	505	u8 mcp_rev;
	506	u8 boot_mode;
	507
	508	u8 wol;
	509
	510	u32 int_mode;
	511	enum qed_coalescing_mode int_coalescing_mode;
51d99880 SRK	512	u16 rx_coalesce_usecs;
51d99880 SRK	513	u16 tx_coalesce_usecs;
fe56b9e6 YM	514
	515	/* Start Bar offset of first hwfn */
	516	void __iomem *regview;
	517	void __iomem *doorbells;
	518	u64 db_phys_addr;
	519	unsigned long db_size;
	520
	521	/* PCI */
	522	u8 cache_shift;
	523
	524	/* Init */
	525	const struct iro *iro_arr;
	526	#define IRO (p_hwfn->cdev->iro_arr)
	527
	528	/* HW functions */
	529	u8 num_hwfns;
	530	struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
	531
32a47e72 YM	532	/* SRIOV */
	533	struct qed_hw_sriov_info *p_iov_info;
	534	#define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
	535
464f6645	536	unsigned long tunn_mode;
1408cc1f YM	537
1408cc1f YM	538	bool b_is_vf;
fe56b9e6 YM	539	u32 drv_type;
	540
	541	struct qed_eth_stats *reset_stats;
	542	struct qed_fw_data *fw_data;
	543
	544	u32 mcp_nvm_resp;
	545
	546	/* Linux specific here */
	547	struct qede_dev *edev;
	548	struct pci_dev *pdev;
	549	int msg_enable;
	550
	551	struct pci_params pci_params;
	552
	553	struct qed_int_params int_params;
	554
	555	u8 protocol;
	556	#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
	557
cc875c2e YM	558	/* Callbacks to protocol driver */
	559	union {
	560	struct qed_common_cb_ops *common;
	561	struct qed_eth_cb_ops *eth;
	562	} protocol_ops;
	563	void *ops_cookie;
	564
c965db44 TT	565	struct qed_dbg_params dbg_params;
c965db44 TT	566
fe56b9e6 YM	567	const struct firmware *firmware;
	568	};
	569
32a47e72	570	#define NUM_OF_VFS(dev) MAX_NUM_VFS_BB
dacd88d6	571	#define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB
fe56b9e6 YM	572	#define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
	573	#define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
	574
	575	/**
	576	* @brief qed_concrete_to_sw_fid - get the sw function id from
	577	* the concrete value.
	578	*
	579	* @param concrete_fid
	580	*
	581	* @return inline u8
	582	*/
	583	static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
	584	u32 concrete_fid)
	585	{
4870e704	586	u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
fe56b9e6	587	u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
4870e704 YM	588	u8 vf_valid = GET_FIELD(concrete_fid,
	589	PXP_CONCRETE_FID_VFVALID);
	590	u8 sw_fid;
fe56b9e6	591
4870e704 YM	592	if (vf_valid)
	593	sw_fid = vfid + MAX_NUM_PFS;
	594	else
	595	sw_fid = pfid;
	596
	597	return sw_fid;
fe56b9e6 YM	598	}
	599
	600	#define PURE_LB_TC 8
dbb799c3	601	#define OOO_LB_TC 9
fe56b9e6	602
733def6a	603	int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
bcd197c8 MC	604	void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
bcd197c8 MC	605
733def6a	606	void qed_clean_wfq_db(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt);
fe56b9e6 YM	607	#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
	608
	609	/* Other Linux specific common definitions */
	610	#define DP_NAME(cdev) ((cdev)->name)
	611
	612	#define REG_ADDR(cdev, offset) (void __iomem )((u8 __iomem )\
	613	(cdev->regview) + \
	614	(offset))
	615
	616	#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
	617	#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
	618	#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
	619
	620	#define DOORBELL(cdev, db_addr, val) \
	621	writel((u32)val, (void __iomem )((u8 __iomem )\
	622	(cdev->doorbells) + (db_addr)))
	623
	624	/* Prototypes */
	625	int qed_fill_dev_info(struct qed_dev *cdev,
	626	struct qed_dev_info *dev_info);
cc875c2e	627	void qed_link_update(struct qed_hwfn *hwfn);
fe56b9e6 YM	628	u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
	629	u32 input_len, u8 *input_buf,
	630	u32 max_size, u8 *unzip_buf);
6c754246 SRK	631	void qed_get_protocol_stats(struct qed_dev *cdev,
	632	enum qed_mcp_protocol_type type,
	633	union qed_mcp_protocol_stats *stats);
8f16bc97 SK	634	int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
8f16bc97 SK	635
fe56b9e6	636	#endif /* _QED_H */