[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_init_ops.c

/* QLogic qed NIC Driver
 * Copyright (c) 2015 QLogic Corporation
 *
 * This software is available under the terms of the GNU General Public License
 * (GPL) Version 2, available from the file COPYING in the main directory of
 * this source tree.
 */

#include <linux/types.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include "qed.h"
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_init_ops.h"
#include "qed_reg_addr.h"
#include "qed_sriov.h"

#define QED_INIT_MAX_POLL_COUNT 100
#define QED_INIT_POLL_PERIOD_US 500

static u32 pxp_global_win[] = {
	0,
	0,
	0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
	0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
	0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
	0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
	0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */
	0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */
	0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */
	0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */
	0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */
	0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */
	0,
	0,
	0,
	0,
	0,
	0,
	0,
};

void qed_init_iro_array(struct qed_dev *cdev)
{
	cdev->iro_arr = iro_arr;
}

/* Runtime configuration helpers */
void qed_init_clear_rt_data(struct qed_hwfn *p_hwfn)
{
	int i;

	for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
		p_hwfn->rt_data.b_valid[i] = false;
}

void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, u32 rt_offset, u32 val)
{
	p_hwfn->rt_data.init_val[rt_offset] = val;
	p_hwfn->rt_data.b_valid[rt_offset] = true;
}

void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn,
			   u32 rt_offset, u32 *p_val, size_t size)
{
	size_t i;

	for (i = 0; i < size / sizeof(u32); i++) {
		p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
		p_hwfn->rt_data.b_valid[rt_offset + i]	= true;
	}
}

static int qed_init_rt(struct qed_hwfn	*p_hwfn,
		       struct qed_ptt *p_ptt,
		       u32 addr, u16 rt_offset, u16 size, bool b_must_dmae)
{
	u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
	bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
	u16 i, segment;
	int rc = 0;

	/* Since not all RT entries are initialized, go over the RT and
	 * for each segment of initialized values use DMA.
	 */
	for (i = 0; i < size; i++) {
		if (!p_valid[i])
			continue;

		/* In case there isn't any wide-bus configuration here,
		 * simply write the data instead of using dmae.
		 */
		if (!b_must_dmae) {
			qed_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
			continue;
		}

		/* Start of a new segment */
		for (segment = 1; i + segment < size; segment++)
			if (!p_valid[i + segment])
				break;

		rc = qed_dmae_host2grc(p_hwfn, p_ptt,
				       (uintptr_t)(p_init_val + i),
				       addr + (i << 2), segment, 0);
		if (rc)
			return rc;

		/* Jump over the entire segment, including invalid entry */
		i += segment;
	}

	return rc;
}

int qed_init_alloc(struct qed_hwfn *p_hwfn)
{
	struct qed_rt_data *rt_data = &p_hwfn->rt_data;

	if (IS_VF(p_hwfn->cdev))
		return 0;

	rt_data->b_valid = kzalloc(sizeof(bool) * RUNTIME_ARRAY_SIZE,
				   GFP_KERNEL);
	if (!rt_data->b_valid)
		return -ENOMEM;

	rt_data->init_val = kzalloc(sizeof(u32) * RUNTIME_ARRAY_SIZE,
				    GFP_KERNEL);
	if (!rt_data->init_val) {
		kfree(rt_data->b_valid);
		return -ENOMEM;
	}

	return 0;
}

void qed_init_free(struct qed_hwfn *p_hwfn)
{
	kfree(p_hwfn->rt_data.init_val);
	kfree(p_hwfn->rt_data.b_valid);
}

static int qed_init_array_dmae(struct qed_hwfn *p_hwfn,
			       struct qed_ptt *p_ptt,
			       u32 addr,
			       u32 dmae_data_offset,
			       u32 size,
			       const u32 *buf,
			       bool b_must_dmae,
			       bool b_can_dmae)
{
	int rc = 0;

	/* Perform DMAE only for lengthy enough sections or for wide-bus */
	if (!b_can_dmae || (!b_must_dmae && (size < 16))) {
		const u32 *data = buf + dmae_data_offset;
		u32 i;

		for (i = 0; i < size; i++)
			qed_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
	} else {
		rc = qed_dmae_host2grc(p_hwfn, p_ptt,
				       (uintptr_t)(buf + dmae_data_offset),
				       addr, size, 0);
	}

	return rc;
}

static int qed_init_fill_dmae(struct qed_hwfn *p_hwfn,
			      struct qed_ptt *p_ptt,
			      u32 addr, u32 fill, u32 fill_count)
{
	static u32 zero_buffer[DMAE_MAX_RW_SIZE];

	memset(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);

	/* invoke the DMAE virtual/physical buffer API with
	 * 1. DMAE init channel
	 * 2. addr,
	 * 3. p_hwfb->temp_data,
	 * 4. fill_count
	 */

	return qed_dmae_host2grc(p_hwfn, p_ptt,
				 (uintptr_t)(&zero_buffer[0]),
				 addr, fill_count, QED_DMAE_FLAG_RW_REPL_SRC);
}

static void qed_init_fill(struct qed_hwfn *p_hwfn,
			  struct qed_ptt *p_ptt,
			  u32 addr, u32 fill, u32 fill_count)
{
	u32 i;

	for (i = 0; i < fill_count; i++, addr += sizeof(u32))
		qed_wr(p_hwfn, p_ptt, addr, fill);
}

static int qed_init_cmd_array(struct qed_hwfn *p_hwfn,
			      struct qed_ptt *p_ptt,
			      struct init_write_op *cmd,
			      bool b_must_dmae, bool b_can_dmae)
{
	u32 dmae_array_offset = le32_to_cpu(cmd->args.array_offset);
	u32 data = le32_to_cpu(cmd->data);
	u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;

	u32 offset, output_len, input_len, max_size;
	struct qed_dev *cdev = p_hwfn->cdev;
	union init_array_hdr *hdr;
	const u32 *array_data;
	int rc = 0;
	u32 size;

	array_data = cdev->fw_data->arr_data;

	hdr = (union init_array_hdr *)(array_data + dmae_array_offset);
	data = le32_to_cpu(hdr->raw.data);
	switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
	case INIT_ARR_ZIPPED:
		offset = dmae_array_offset + 1;
		input_len = GET_FIELD(data,
				      INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
		max_size = MAX_ZIPPED_SIZE * 4;
		memset(p_hwfn->unzip_buf, 0, max_size);

		output_len = qed_unzip_data(p_hwfn, input_len,
					    (u8 *)&array_data[offset],
					    max_size, (u8 *)p_hwfn->unzip_buf);
		if (output_len) {
			rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 0,
						 output_len,
						 p_hwfn->unzip_buf,
						 b_must_dmae, b_can_dmae);
		} else {
			DP_NOTICE(p_hwfn, "Failed to unzip dmae data\n");
			rc = -EINVAL;
		}
		break;
	case INIT_ARR_PATTERN:
	{
		u32 repeats = GET_FIELD(data,
					INIT_ARRAY_PATTERN_HDR_REPETITIONS);
		u32 i;

		size = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);

		for (i = 0; i < repeats; i++, addr += size << 2) {
			rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
						 dmae_array_offset + 1,
						 size, array_data,
						 b_must_dmae, b_can_dmae);
			if (rc)
				break;
		}
		break;
	}
	case INIT_ARR_STANDARD:
		size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
		rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
					 dmae_array_offset + 1,
					 size, array_data,
					 b_must_dmae, b_can_dmae);
		break;
	}

	return rc;
}

/* init_ops write command */
static int qed_init_cmd_wr(struct qed_hwfn *p_hwfn,
			   struct qed_ptt *p_ptt,
			   struct init_write_op *p_cmd, bool b_can_dmae)
{
	u32 data = le32_to_cpu(p_cmd->data);
	bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
	u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
	union init_write_args *arg = &p_cmd->args;
	int rc = 0;

	/* Sanitize */
	if (b_must_dmae && !b_can_dmae) {
		DP_NOTICE(p_hwfn,
			  "Need to write to %08x for Wide-bus but DMAE isn't allowed\n",
			  addr);
		return -EINVAL;
	}

	switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
	case INIT_SRC_INLINE:
		data = le32_to_cpu(p_cmd->args.inline_val);
		qed_wr(p_hwfn, p_ptt, addr, data);
		break;
	case INIT_SRC_ZEROS:
		data = le32_to_cpu(p_cmd->args.zeros_count);
		if (b_must_dmae || (b_can_dmae && (data >= 64)))
			rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
		else
			qed_init_fill(p_hwfn, p_ptt, addr, 0, data);
		break;
	case INIT_SRC_ARRAY:
		rc = qed_init_cmd_array(p_hwfn, p_ptt, p_cmd,
					b_must_dmae, b_can_dmae);
		break;
	case INIT_SRC_RUNTIME:
		qed_init_rt(p_hwfn, p_ptt, addr,
			    le16_to_cpu(arg->runtime.offset),
			    le16_to_cpu(arg->runtime.size),
			    b_must_dmae);
		break;
	}

	return rc;
}

static inline bool comp_eq(u32 val, u32 expected_val)
{
	return val == expected_val;
}

static inline bool comp_and(u32 val, u32 expected_val)
{
	return (val & expected_val) == expected_val;
}

static inline bool comp_or(u32 val, u32 expected_val)
{
	return (val | expected_val) > 0;
}

/* init_ops read/poll commands */
static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn,
			    struct qed_ptt *p_ptt, struct init_read_op *cmd)
{
	bool (*comp_check)(u32 val, u32 expected_val);
	u32 delay = QED_INIT_POLL_PERIOD_US, val;
	u32 data, addr, poll;
	int i;

	data = le32_to_cpu(cmd->op_data);
	addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
	poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);


	val = qed_rd(p_hwfn, p_ptt, addr);

	if (poll == INIT_POLL_NONE)
		return;

	switch (poll) {
	case INIT_POLL_EQ:
		comp_check = comp_eq;
		break;
	case INIT_POLL_OR:
		comp_check = comp_or;
		break;
	case INIT_POLL_AND:
		comp_check = comp_and;
		break;
	default:
		DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
		       cmd->op_data);
		return;
	}

	data = le32_to_cpu(cmd->expected_val);
	for (i = 0;
	     i < QED_INIT_MAX_POLL_COUNT && !comp_check(val, data);
	     i++) {
		udelay(delay);
		val = qed_rd(p_hwfn, p_ptt, addr);
	}

	if (i == QED_INIT_MAX_POLL_COUNT) {
		DP_ERR(p_hwfn,
		       "Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparsion %08x)]\n",
		       addr, le32_to_cpu(cmd->expected_val),
		       val, le32_to_cpu(cmd->op_data));
	}
}

/* init_ops callbacks entry point */
static void qed_init_cmd_cb(struct qed_hwfn *p_hwfn,
			    struct qed_ptt *p_ptt,
			    struct init_callback_op *p_cmd)
{
	DP_NOTICE(p_hwfn, "Currently init values have no need of callbacks\n");
}

static u8 qed_init_cmd_mode_match(struct qed_hwfn *p_hwfn,
				  u16 *p_offset, int modes)
{
	struct qed_dev *cdev = p_hwfn->cdev;
	const u8 *modes_tree_buf;
	u8 arg1, arg2, tree_val;

	modes_tree_buf = cdev->fw_data->modes_tree_buf;
	tree_val = modes_tree_buf[(*p_offset)++];
	switch (tree_val) {
	case INIT_MODE_OP_NOT:
		return qed_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
	case INIT_MODE_OP_OR:
		arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
		arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
		return arg1 | arg2;
	case INIT_MODE_OP_AND:
		arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
		arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
		return arg1 & arg2;
	default:
		tree_val -= MAX_INIT_MODE_OPS;
		return (modes & BIT(tree_val)) ? 1 : 0;
	}
}

static u32 qed_init_cmd_mode(struct qed_hwfn *p_hwfn,
			     struct init_if_mode_op *p_cmd, int modes)
{
	u16 offset = le16_to_cpu(p_cmd->modes_buf_offset);

	if (qed_init_cmd_mode_match(p_hwfn, &offset, modes))
		return 0;
	else
		return GET_FIELD(le32_to_cpu(p_cmd->op_data),
				 INIT_IF_MODE_OP_CMD_OFFSET);
}

static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn,
			      struct init_if_phase_op *p_cmd,
			      u32 phase, u32 phase_id)
{
	u32 data = le32_to_cpu(p_cmd->phase_data);
	u32 op_data = le32_to_cpu(p_cmd->op_data);

	if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
	      (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID ||
	       GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
		return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET);
	else
		return 0;
}

int qed_init_run(struct qed_hwfn *p_hwfn,
		 struct qed_ptt *p_ptt, int phase, int phase_id, int modes)
{
	struct qed_dev *cdev = p_hwfn->cdev;
	u32 cmd_num, num_init_ops;
	union init_op *init_ops;
	bool b_dmae = false;
	int rc = 0;

	num_init_ops = cdev->fw_data->init_ops_size;
	init_ops = cdev->fw_data->init_ops;

	p_hwfn->unzip_buf = kzalloc(MAX_ZIPPED_SIZE * 4, GFP_ATOMIC);
	if (!p_hwfn->unzip_buf)
		return -ENOMEM;

	for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
		union init_op *cmd = &init_ops[cmd_num];
		u32 data = le32_to_cpu(cmd->raw.op_data);

		switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
		case INIT_OP_WRITE:
			rc = qed_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
					     b_dmae);
			break;
		case INIT_OP_READ:
			qed_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
			break;
		case INIT_OP_IF_MODE:
			cmd_num += qed_init_cmd_mode(p_hwfn, &cmd->if_mode,
						     modes);
			break;
		case INIT_OP_IF_PHASE:
			cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase,
						      phase, phase_id);
			b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
			break;
		case INIT_OP_DELAY:
			/* qed_init_run is always invoked from
			 * sleep-able context
			 */
			udelay(le32_to_cpu(cmd->delay.delay));
			break;

		case INIT_OP_CALLBACK:
			qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
			break;
		}

		if (rc)
			break;
	}

	kfree(p_hwfn->unzip_buf);
	return rc;
}

void qed_gtt_init(struct qed_hwfn *p_hwfn)
{
	u32 gtt_base;
	u32 i;

	/* Set the global windows */
	gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;

	for (i = 0; i < ARRAY_SIZE(pxp_global_win); i++)
		if (pxp_global_win[i])
			REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
			       pxp_global_win[i]);
}

int qed_init_fw_data(struct qed_dev *cdev, const u8 *data)
{
	struct qed_fw_data *fw = cdev->fw_data;
	struct bin_buffer_hdr *buf_hdr;
	u32 offset, len;

	if (!data) {
		DP_NOTICE(cdev, "Invalid fw data\n");
		return -EINVAL;
	}

	/* First Dword contains metadata and should be skipped */
	buf_hdr = (struct bin_buffer_hdr *)(data + sizeof(u32));

	offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
	fw->fw_ver_info = (struct fw_ver_info *)(data + offset);

	offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
	fw->init_ops = (union init_op *)(data + offset);

	offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
	fw->arr_data = (u32 *)(data + offset);

	offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
	fw->modes_tree_buf = (u8 *)(data + offset);
	len = buf_hdr[BIN_BUF_INIT_CMD].length;
	fw->init_ops_size = len / sizeof(struct init_raw_op);

	return 0;
}
Commit	Line	Data
fe56b9e6 YM	1	/* QLogic qed NIC Driver
	2	* Copyright (c) 2015 QLogic Corporation
	3	*
	4	* This software is available under the terms of the GNU General Public License
	5	* (GPL) Version 2, available from the file COPYING in the main directory of
	6	* this source tree.
	7	*/
	8
	9	#include <linux/types.h>
	10	#include <linux/io.h>
	11	#include <linux/delay.h>
	12	#include <linux/errno.h>
	13	#include <linux/kernel.h>
	14	#include <linux/slab.h>
	15	#include <linux/string.h>
	16	#include "qed.h"
	17	#include "qed_hsi.h"
	18	#include "qed_hw.h"
	19	#include "qed_init_ops.h"
	20	#include "qed_reg_addr.h"
1408cc1f	21	#include "qed_sriov.h"
fe56b9e6 YM	22
	23	#define QED_INIT_MAX_POLL_COUNT 100
	24	#define QED_INIT_POLL_PERIOD_US 500
	25
	26	static u32 pxp_global_win[] = {
	27	0,
	28	0,
	29	0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
	30	0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
	31	0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
	32	0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
	33	0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */
	34	0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */
	35	0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */
	36	0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */
	37	0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */
	38	0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */
	39	0,
	40	0,
	41	0,
	42	0,
	43	0,
	44	0,
	45	0,
	46	};
	47
	48	void qed_init_iro_array(struct qed_dev *cdev)
	49	{
	50	cdev->iro_arr = iro_arr;
	51	}
	52
	53	/* Runtime configuration helpers */
	54	void qed_init_clear_rt_data(struct qed_hwfn *p_hwfn)
	55	{
	56	int i;
	57
	58	for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
fc48b7a6	59	p_hwfn->rt_data.b_valid[i] = false;
fe56b9e6 YM	60	}
fe56b9e6 YM	61
1a635e48	62	void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, u32 rt_offset, u32 val)
fe56b9e6	63	{
fc48b7a6 YM	64	p_hwfn->rt_data.init_val[rt_offset] = val;
fc48b7a6 YM	65	p_hwfn->rt_data.b_valid[rt_offset] = true;
fe56b9e6 YM	66	}
	67
	68	void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn,
1a635e48	69	u32 rt_offset, u32 *p_val, size_t size)
fe56b9e6 YM	70	{
	71	size_t i;
	72
	73	for (i = 0; i < size / sizeof(u32); i++) {
fc48b7a6 YM	74	p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
fc48b7a6 YM	75	p_hwfn->rt_data.b_valid[rt_offset + i] = true;
fe56b9e6 YM	76	}
	77	}
	78
fc48b7a6 YM	79	static int qed_init_rt(struct qed_hwfn *p_hwfn,
fc48b7a6 YM	80	struct qed_ptt *p_ptt,
1a635e48	81	u32 addr, u16 rt_offset, u16 size, bool b_must_dmae)
fe56b9e6	82	{
fc48b7a6 YM	83	u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
	84	bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
	85	u16 i, segment;
	86	int rc = 0;
fe56b9e6	87
fc48b7a6 YM	88	/* Since not all RT entries are initialized, go over the RT and
	89	* for each segment of initialized values use DMA.
	90	*/
fe56b9e6	91	for (i = 0; i < size; i++) {
fc48b7a6	92	if (!p_valid[i])
fe56b9e6	93	continue;
fc48b7a6 YM	94
	95	/* In case there isn't any wide-bus configuration here,
	96	* simply write the data instead of using dmae.
	97	*/
	98	if (!b_must_dmae) {
1a635e48	99	qed_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
fc48b7a6 YM	100	continue;
	101	}
	102
	103	/* Start of a new segment */
	104	for (segment = 1; i + segment < size; segment++)
	105	if (!p_valid[i + segment])
	106	break;
	107
	108	rc = qed_dmae_host2grc(p_hwfn, p_ptt,
	109	(uintptr_t)(p_init_val + i),
	110	addr + (i << 2), segment, 0);
1a635e48	111	if (rc)
fc48b7a6 YM	112	return rc;
	113
	114	/* Jump over the entire segment, including invalid entry */
	115	i += segment;
fe56b9e6	116	}
fc48b7a6 YM	117
fc48b7a6 YM	118	return rc;
fe56b9e6 YM	119	}
	120
	121	int qed_init_alloc(struct qed_hwfn *p_hwfn)
	122	{
fc48b7a6	123	struct qed_rt_data *rt_data = &p_hwfn->rt_data;
fe56b9e6	124
1408cc1f YM	125	if (IS_VF(p_hwfn->cdev))
	126	return 0;
	127
fc48b7a6 YM	128	rt_data->b_valid = kzalloc(sizeof(bool) * RUNTIME_ARRAY_SIZE,
	129	GFP_KERNEL);
	130	if (!rt_data->b_valid)
fe56b9e6 YM	131	return -ENOMEM;
fe56b9e6 YM	132
fc48b7a6 YM	133	rt_data->init_val = kzalloc(sizeof(u32) * RUNTIME_ARRAY_SIZE,
	134	GFP_KERNEL);
	135	if (!rt_data->init_val) {
	136	kfree(rt_data->b_valid);
	137	return -ENOMEM;
	138	}
fe56b9e6 YM	139
	140	return 0;
	141	}
	142
	143	void qed_init_free(struct qed_hwfn *p_hwfn)
	144	{
fc48b7a6 YM	145	kfree(p_hwfn->rt_data.init_val);
fc48b7a6 YM	146	kfree(p_hwfn->rt_data.b_valid);
fe56b9e6 YM	147	}
	148
	149	static int qed_init_array_dmae(struct qed_hwfn *p_hwfn,
	150	struct qed_ptt *p_ptt,
	151	u32 addr,
	152	u32 dmae_data_offset,
	153	u32 size,
	154	const u32 *buf,
	155	bool b_must_dmae,
	156	bool b_can_dmae)
	157	{
	158	int rc = 0;
	159
	160	/* Perform DMAE only for lengthy enough sections or for wide-bus */
	161	if (!b_can_dmae \|\| (!b_must_dmae && (size < 16))) {
	162	const u32 *data = buf + dmae_data_offset;
	163	u32 i;
	164
	165	for (i = 0; i < size; i++)
	166	qed_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
	167	} else {
	168	rc = qed_dmae_host2grc(p_hwfn, p_ptt,
	169	(uintptr_t)(buf + dmae_data_offset),
	170	addr, size, 0);
	171	}
	172
	173	return rc;
	174	}
	175
	176	static int qed_init_fill_dmae(struct qed_hwfn *p_hwfn,
	177	struct qed_ptt *p_ptt,
1a635e48	178	u32 addr, u32 fill, u32 fill_count)
fe56b9e6 YM	179	{
	180	static u32 zero_buffer[DMAE_MAX_RW_SIZE];
	181
	182	memset(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
	183
	184	/* invoke the DMAE virtual/physical buffer API with
	185	* 1. DMAE init channel
	186	* 2. addr,
	187	* 3. p_hwfb->temp_data,
	188	* 4. fill_count
	189	*/
	190
	191	return qed_dmae_host2grc(p_hwfn, p_ptt,
	192	(uintptr_t)(&zero_buffer[0]),
1a635e48	193	addr, fill_count, QED_DMAE_FLAG_RW_REPL_SRC);
fe56b9e6 YM	194	}
	195
	196	static void qed_init_fill(struct qed_hwfn *p_hwfn,
	197	struct qed_ptt *p_ptt,
1a635e48	198	u32 addr, u32 fill, u32 fill_count)
fe56b9e6 YM	199	{
	200	u32 i;
	201
	202	for (i = 0; i < fill_count; i++, addr += sizeof(u32))
	203	qed_wr(p_hwfn, p_ptt, addr, fill);
	204	}
	205
	206	static int qed_init_cmd_array(struct qed_hwfn *p_hwfn,
	207	struct qed_ptt *p_ptt,
	208	struct init_write_op *cmd,
1a635e48	209	bool b_must_dmae, bool b_can_dmae)
fe56b9e6	210	{
1a635e48	211	u32 dmae_array_offset = le32_to_cpu(cmd->args.array_offset);
fe56b9e6 YM	212	u32 data = le32_to_cpu(cmd->data);
fe56b9e6 YM	213	u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
1a635e48	214
fe56b9e6 YM	215	u32 offset, output_len, input_len, max_size;
	216	struct qed_dev *cdev = p_hwfn->cdev;
	217	union init_array_hdr *hdr;
	218	const u32 *array_data;
	219	int rc = 0;
	220	u32 size;
	221
	222	array_data = cdev->fw_data->arr_data;
	223
1a635e48	224	hdr = (union init_array_hdr *)(array_data + dmae_array_offset);
fe56b9e6 YM	225	data = le32_to_cpu(hdr->raw.data);
	226	switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
	227	case INIT_ARR_ZIPPED:
	228	offset = dmae_array_offset + 1;
	229	input_len = GET_FIELD(data,
	230	INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
	231	max_size = MAX_ZIPPED_SIZE * 4;
	232	memset(p_hwfn->unzip_buf, 0, max_size);
	233
	234	output_len = qed_unzip_data(p_hwfn, input_len,
	235	(u8 *)&array_data[offset],
	236	max_size, (u8 *)p_hwfn->unzip_buf);
	237	if (output_len) {
	238	rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 0,
	239	output_len,
	240	p_hwfn->unzip_buf,
	241	b_must_dmae, b_can_dmae);
	242	} else {
	243	DP_NOTICE(p_hwfn, "Failed to unzip dmae data\n");
	244	rc = -EINVAL;
	245	}
	246	break;
	247	case INIT_ARR_PATTERN:
	248	{
	249	u32 repeats = GET_FIELD(data,
	250	INIT_ARRAY_PATTERN_HDR_REPETITIONS);
	251	u32 i;
	252
	253	size = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);
	254
	255	for (i = 0; i < repeats; i++, addr += size << 2) {
	256	rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
	257	dmae_array_offset + 1,
	258	size, array_data,
	259	b_must_dmae, b_can_dmae);
	260	if (rc)
	261	break;
	262	}
	263	break;
	264	}
	265	case INIT_ARR_STANDARD:
	266	size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
	267	rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
	268	dmae_array_offset + 1,
	269	size, array_data,
	270	b_must_dmae, b_can_dmae);
	271	break;
	272	}
	273
	274	return rc;
	275	}
	276
	277	/* init_ops write command */
	278	static int qed_init_cmd_wr(struct qed_hwfn *p_hwfn,
	279	struct qed_ptt *p_ptt,
1a635e48	280	struct init_write_op *p_cmd, bool b_can_dmae)
fe56b9e6	281	{
1a635e48	282	u32 data = le32_to_cpu(p_cmd->data);
fe56b9e6	283	bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
1a635e48 YM	284	u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
1a635e48 YM	285	union init_write_args *arg = &p_cmd->args;
fe56b9e6 YM	286	int rc = 0;
	287
	288	/* Sanitize */
	289	if (b_must_dmae && !b_can_dmae) {
	290	DP_NOTICE(p_hwfn,
	291	"Need to write to %08x for Wide-bus but DMAE isn't allowed\n",
	292	addr);
	293	return -EINVAL;
	294	}
	295
	296	switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
	297	case INIT_SRC_INLINE:
83aeb933 YM	298	data = le32_to_cpu(p_cmd->args.inline_val);
83aeb933 YM	299	qed_wr(p_hwfn, p_ptt, addr, data);
fe56b9e6 YM	300	break;
fe56b9e6 YM	301	case INIT_SRC_ZEROS:
83aeb933 YM	302	data = le32_to_cpu(p_cmd->args.zeros_count);
	303	if (b_must_dmae \|\| (b_can_dmae && (data >= 64)))
	304	rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
fe56b9e6	305	else
83aeb933	306	qed_init_fill(p_hwfn, p_ptt, addr, 0, data);
fe56b9e6 YM	307	break;
fe56b9e6 YM	308	case INIT_SRC_ARRAY:
1a635e48	309	rc = qed_init_cmd_array(p_hwfn, p_ptt, p_cmd,
fe56b9e6 YM	310	b_must_dmae, b_can_dmae);
	311	break;
	312	case INIT_SRC_RUNTIME:
	313	qed_init_rt(p_hwfn, p_ptt, addr,
	314	le16_to_cpu(arg->runtime.offset),
fc48b7a6 YM	315	le16_to_cpu(arg->runtime.size),
fc48b7a6 YM	316	b_must_dmae);
fe56b9e6 YM	317	break;
	318	}
	319
	320	return rc;
	321	}
	322
	323	static inline bool comp_eq(u32 val, u32 expected_val)
	324	{
	325	return val == expected_val;
	326	}
	327
	328	static inline bool comp_and(u32 val, u32 expected_val)
	329	{
	330	return (val & expected_val) == expected_val;
	331	}
	332
	333	static inline bool comp_or(u32 val, u32 expected_val)
	334	{
	335	return (val \| expected_val) > 0;
	336	}
	337
	338	/* init_ops read/poll commands */
	339	static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn,
1a635e48	340	struct qed_ptt p_ptt, struct init_read_op cmd)
fe56b9e6	341	{
fc48b7a6 YM	342	bool (*comp_check)(u32 val, u32 expected_val);
	343	u32 delay = QED_INIT_POLL_PERIOD_US, val;
	344	u32 data, addr, poll;
	345	int i;
	346
	347	data = le32_to_cpu(cmd->op_data);
	348	addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
	349	poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);
fe56b9e6	350
fe56b9e6 YM	351
	352	val = qed_rd(p_hwfn, p_ptt, addr);
	353
fc48b7a6 YM	354	if (poll == INIT_POLL_NONE)
fc48b7a6 YM	355	return;
fe56b9e6	356
fc48b7a6 YM	357	switch (poll) {
	358	case INIT_POLL_EQ:
	359	comp_check = comp_eq;
	360	break;
	361	case INIT_POLL_OR:
	362	comp_check = comp_or;
	363	break;
	364	case INIT_POLL_AND:
	365	comp_check = comp_and;
	366	break;
	367	default:
	368	DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
	369	cmd->op_data);
	370	return;
	371	}
	372
	373	data = le32_to_cpu(cmd->expected_val);
	374	for (i = 0;
	375	i < QED_INIT_MAX_POLL_COUNT && !comp_check(val, data);
	376	i++) {
	377	udelay(delay);
	378	val = qed_rd(p_hwfn, p_ptt, addr);
	379	}
fe56b9e6	380
fc48b7a6 YM	381	if (i == QED_INIT_MAX_POLL_COUNT) {
	382	DP_ERR(p_hwfn,
	383	"Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparsion %08x)]\n",
	384	addr, le32_to_cpu(cmd->expected_val),
	385	val, le32_to_cpu(cmd->op_data));
fe56b9e6 YM	386	}
	387	}
	388
	389	/* init_ops callbacks entry point */
	390	static void qed_init_cmd_cb(struct qed_hwfn *p_hwfn,
	391	struct qed_ptt *p_ptt,
	392	struct init_callback_op *p_cmd)
	393	{
	394	DP_NOTICE(p_hwfn, "Currently init values have no need of callbacks\n");
	395	}
	396
	397	static u8 qed_init_cmd_mode_match(struct qed_hwfn *p_hwfn,
1a635e48	398	u16 *p_offset, int modes)
fe56b9e6 YM	399	{
	400	struct qed_dev *cdev = p_hwfn->cdev;
	401	const u8 *modes_tree_buf;
	402	u8 arg1, arg2, tree_val;
	403
	404	modes_tree_buf = cdev->fw_data->modes_tree_buf;
1a635e48	405	tree_val = modes_tree_buf[(*p_offset)++];
fe56b9e6 YM	406	switch (tree_val) {
fe56b9e6 YM	407	case INIT_MODE_OP_NOT:
1a635e48	408	return qed_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
fe56b9e6	409	case INIT_MODE_OP_OR:
1a635e48 YM	410	arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
1a635e48 YM	411	arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
fe56b9e6 YM	412	return arg1 \| arg2;
fe56b9e6 YM	413	case INIT_MODE_OP_AND:
1a635e48 YM	414	arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
1a635e48 YM	415	arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
fe56b9e6 YM	416	return arg1 & arg2;
	417	default:
	418	tree_val -= MAX_INIT_MODE_OPS;
1a635e48	419	return (modes & BIT(tree_val)) ? 1 : 0;
fe56b9e6 YM	420	}
	421	}
	422
	423	static u32 qed_init_cmd_mode(struct qed_hwfn *p_hwfn,
1a635e48	424	struct init_if_mode_op *p_cmd, int modes)
fe56b9e6 YM	425	{
	426	u16 offset = le16_to_cpu(p_cmd->modes_buf_offset);
	427
	428	if (qed_init_cmd_mode_match(p_hwfn, &offset, modes))
	429	return 0;
	430	else
	431	return GET_FIELD(le32_to_cpu(p_cmd->op_data),
	432	INIT_IF_MODE_OP_CMD_OFFSET);
	433	}
	434
	435	static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn,
	436	struct init_if_phase_op *p_cmd,
1a635e48	437	u32 phase, u32 phase_id)
fe56b9e6 YM	438	{
	439	u32 data = le32_to_cpu(p_cmd->phase_data);
	440	u32 op_data = le32_to_cpu(p_cmd->op_data);
	441
	442	if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
	443	(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID \|\|
	444	GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
	445	return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET);
	446	else
	447	return 0;
	448	}
	449
	450	int qed_init_run(struct qed_hwfn *p_hwfn,
1a635e48	451	struct qed_ptt *p_ptt, int phase, int phase_id, int modes)
fe56b9e6 YM	452	{
	453	struct qed_dev *cdev = p_hwfn->cdev;
	454	u32 cmd_num, num_init_ops;
	455	union init_op *init_ops;
	456	bool b_dmae = false;
	457	int rc = 0;
	458
	459	num_init_ops = cdev->fw_data->init_ops_size;
	460	init_ops = cdev->fw_data->init_ops;
	461
	462	p_hwfn->unzip_buf = kzalloc(MAX_ZIPPED_SIZE * 4, GFP_ATOMIC);
2591c280	463	if (!p_hwfn->unzip_buf)
fe56b9e6	464	return -ENOMEM;
fe56b9e6 YM	465
	466	for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
	467	union init_op *cmd = &init_ops[cmd_num];
	468	u32 data = le32_to_cpu(cmd->raw.op_data);
	469
	470	switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
	471	case INIT_OP_WRITE:
	472	rc = qed_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
	473	b_dmae);
	474	break;
	475	case INIT_OP_READ:
	476	qed_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
	477	break;
	478	case INIT_OP_IF_MODE:
	479	cmd_num += qed_init_cmd_mode(p_hwfn, &cmd->if_mode,
	480	modes);
	481	break;
	482	case INIT_OP_IF_PHASE:
	483	cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase,
	484	phase, phase_id);
	485	b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
	486	break;
	487	case INIT_OP_DELAY:
	488	/* qed_init_run is always invoked from
	489	* sleep-able context
	490	*/
	491	udelay(le32_to_cpu(cmd->delay.delay));
	492	break;
	493
	494	case INIT_OP_CALLBACK:
	495	qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
	496	break;
	497	}
	498
	499	if (rc)
	500	break;
	501	}
	502
	503	kfree(p_hwfn->unzip_buf);
	504	return rc;
	505	}
	506
	507	void qed_gtt_init(struct qed_hwfn *p_hwfn)
	508	{
	509	u32 gtt_base;
	510	u32 i;
	511
	512	/* Set the global windows */
	513	gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
	514
	515	for (i = 0; i < ARRAY_SIZE(pxp_global_win); i++)
	516	if (pxp_global_win[i])
	517	REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
	518	pxp_global_win[i]);
	519	}
	520
351a4ded	521	int qed_init_fw_data(struct qed_dev cdev, const u8 data)
fe56b9e6 YM	522	{
	523	struct qed_fw_data *fw = cdev->fw_data;
	524	struct bin_buffer_hdr *buf_hdr;
	525	u32 offset, len;
	526
	527	if (!data) {
	528	DP_NOTICE(cdev, "Invalid fw data\n");
	529	return -EINVAL;
	530	}
	531
351a4ded YM	532	/* First Dword contains metadata and should be skipped */
	533	buf_hdr = (struct bin_buffer_hdr *)(data + sizeof(u32));
	534
05fafbfb	535	offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
351a4ded	536	fw->fw_ver_info = (struct fw_ver_info *)(data + offset);
fe56b9e6 YM	537
	538	offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
	539	fw->init_ops = (union init_op *)(data + offset);
	540
	541	offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
	542	fw->arr_data = (u32 *)(data + offset);
	543
	544	offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
	545	fw->modes_tree_buf = (u8 *)(data + offset);
	546	len = buf_hdr[BIN_BUF_INIT_CMD].length;
	547	fw->init_ops_size = len / sizeof(struct init_raw_op);
	548
	549	return 0;
	550	}