[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_sp_commands.c

/* QLogic qed NIC Driver
 * Copyright (c) 2015 QLogic Corporation
 *
 * This software is available under the terms of the GNU General Public License
 * (GPL) Version 2, available from the file COPYING in the main directory of
 * this source tree.
 */

#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include "qed.h"
#include <linux/qed/qed_chain.h>
#include "qed_cxt.h"
#include "qed_dcbx.h"
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_int.h"
#include "qed_reg_addr.h"
#include "qed_sp.h"
#include "qed_sriov.h"

int qed_sp_init_request(struct qed_hwfn *p_hwfn,
			struct qed_spq_entry **pp_ent,
			u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
{
	u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
	struct qed_spq_entry *p_ent = NULL;
	int rc;

	if (!pp_ent)
		return -ENOMEM;

	rc = qed_spq_get_entry(p_hwfn, pp_ent);

	if (rc)
		return rc;

	p_ent = *pp_ent;

	p_ent->elem.hdr.cid		= cpu_to_le32(opaque_cid);
	p_ent->elem.hdr.cmd_id		= cmd;
	p_ent->elem.hdr.protocol_id	= protocol;

	p_ent->priority		= QED_SPQ_PRIORITY_NORMAL;
	p_ent->comp_mode	= p_data->comp_mode;
	p_ent->comp_done.done	= 0;

	switch (p_ent->comp_mode) {
	case QED_SPQ_MODE_EBLOCK:
		p_ent->comp_cb.cookie = &p_ent->comp_done;
		break;

	case QED_SPQ_MODE_BLOCK:
		if (!p_data->p_comp_data)
			return -EINVAL;

		p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
		break;

	case QED_SPQ_MODE_CB:
		if (!p_data->p_comp_data)
			p_ent->comp_cb.function = NULL;
		else
			p_ent->comp_cb = *p_data->p_comp_data;
		break;

	default:
		DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
			  p_ent->comp_mode);
		return -EINVAL;
	}

	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
		   "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
		   opaque_cid, cmd, protocol,
		   (unsigned long)&p_ent->ramrod,
		   D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
			   QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
			   "MODE_CB"));

	memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));

	return 0;
}

static enum tunnel_clss qed_tunn_get_clss_type(u8 type)
{
	switch (type) {
	case QED_TUNN_CLSS_MAC_VLAN:
		return TUNNEL_CLSS_MAC_VLAN;
	case QED_TUNN_CLSS_MAC_VNI:
		return TUNNEL_CLSS_MAC_VNI;
	case QED_TUNN_CLSS_INNER_MAC_VLAN:
		return TUNNEL_CLSS_INNER_MAC_VLAN;
	case QED_TUNN_CLSS_INNER_MAC_VNI:
		return TUNNEL_CLSS_INNER_MAC_VNI;
	default:
		return TUNNEL_CLSS_MAC_VLAN;
	}
}

static void
qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn,
			      struct qed_tunn_update_params *p_src,
			      struct pf_update_tunnel_config *p_tunn_cfg)
{
	unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode;
	unsigned long update_mask = p_src->tunn_mode_update_mask;
	unsigned long tunn_mode = p_src->tunn_mode;
	unsigned long new_tunn_mode = 0;

	if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
			__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
	}

	if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
			__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
	}

	if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
			__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
	}

	if (p_src->update_geneve_udp_port) {
		p_tunn_cfg->set_geneve_udp_port_flg = 1;
		p_tunn_cfg->geneve_udp_port =
				cpu_to_le16(p_src->geneve_udp_port);
	}

	if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
			__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
	}

	if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) {
		if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
			__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
	} else {
		if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode))
			__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
	}

	p_src->tunn_mode = new_tunn_mode;
}

static void
qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
			      struct qed_tunn_update_params *p_src,
			      struct pf_update_tunnel_config *p_tunn_cfg)
{
	unsigned long tunn_mode = p_src->tunn_mode;
	enum tunnel_clss type;

	qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);
	p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;
	p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
	p_tunn_cfg->tunnel_clss_vxlan  = type;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
	p_tunn_cfg->tunnel_clss_l2gre = type;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
	p_tunn_cfg->tunnel_clss_ipgre = type;

	if (p_src->update_vxlan_udp_port) {
		p_tunn_cfg->set_vxlan_udp_port_flg = 1;
		p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
	}

	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_l2gre = 1;

	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_ipgre = 1;

	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_vxlan = 1;

	if (p_src->update_geneve_udp_port) {
		p_tunn_cfg->set_geneve_udp_port_flg = 1;
		p_tunn_cfg->geneve_udp_port =
				cpu_to_le16(p_src->geneve_udp_port);
	}

	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_l2geneve = 1;

	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_ipgeneve = 1;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
	p_tunn_cfg->tunnel_clss_l2geneve = type;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
	p_tunn_cfg->tunnel_clss_ipgeneve = type;
}

static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
				 struct qed_ptt *p_ptt,
				 unsigned long tunn_mode)
{
	u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0;
	u8 l2geneve_enable = 0, ipgeneve_enable = 0;

	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
		l2gre_enable = 1;

	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
		ipgre_enable = 1;

	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
		vxlan_enable = 1;

	qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable);
	qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable);

	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
		l2geneve_enable = 1;

	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
		ipgeneve_enable = 1;

	qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable,
			      ipgeneve_enable);
}

static void
qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
			     struct qed_tunn_start_params *p_src,
			     struct pf_start_tunnel_config *p_tunn_cfg)
{
	unsigned long tunn_mode;
	enum tunnel_clss type;

	if (!p_src)
		return;

	tunn_mode = p_src->tunn_mode;
	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
	p_tunn_cfg->tunnel_clss_vxlan = type;
	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
	p_tunn_cfg->tunnel_clss_l2gre = type;
	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
	p_tunn_cfg->tunnel_clss_ipgre = type;

	if (p_src->update_vxlan_udp_port) {
		p_tunn_cfg->set_vxlan_udp_port_flg = 1;
		p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
	}

	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_l2gre = 1;

	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_ipgre = 1;

	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_vxlan = 1;

	if (p_src->update_geneve_udp_port) {
		p_tunn_cfg->set_geneve_udp_port_flg = 1;
		p_tunn_cfg->geneve_udp_port =
				cpu_to_le16(p_src->geneve_udp_port);
	}

	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_l2geneve = 1;

	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
		p_tunn_cfg->tx_enable_ipgeneve = 1;

	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
	p_tunn_cfg->tunnel_clss_l2geneve = type;
	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
	p_tunn_cfg->tunnel_clss_ipgeneve = type;
}

int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
		    struct qed_tunn_start_params *p_tunn,
		    enum qed_mf_mode mode, bool allow_npar_tx_switch)
{
	struct pf_start_ramrod_data *p_ramrod = NULL;
	u16 sb = qed_int_get_sp_sb_id(p_hwfn);
	u8 sb_index = p_hwfn->p_eq->eq_sb_index;
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;
	u8 page_cnt;

	/* update initial eq producer */
	qed_eq_prod_update(p_hwfn,
			   qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));

	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_START,
				 PROTOCOLID_COMMON, &init_data);
	if (rc)
		return rc;

	p_ramrod = &p_ent->ramrod.pf_start;

	p_ramrod->event_ring_sb_id	= cpu_to_le16(sb);
	p_ramrod->event_ring_sb_index	= sb_index;
	p_ramrod->path_id		= QED_PATH_ID(p_hwfn);
	p_ramrod->dont_log_ramrods	= 0;
	p_ramrod->log_type_mask		= cpu_to_le16(0xf);

	switch (mode) {
	case QED_MF_DEFAULT:
	case QED_MF_NPAR:
		p_ramrod->mf_mode = MF_NPAR;
		break;
	case QED_MF_OVLAN:
		p_ramrod->mf_mode = MF_OVLAN;
		break;
	default:
		DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
		p_ramrod->mf_mode = MF_NPAR;
	}
	p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;

	/* Place EQ address in RAMROD */
	DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
		       p_hwfn->p_eq->chain.pbl.p_phys_table);
	page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
	p_ramrod->event_ring_num_pages = page_cnt;
	DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
		       p_hwfn->p_consq->chain.pbl.p_phys_table);

	qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);

	if (IS_MF_SI(p_hwfn))
		p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;

	switch (p_hwfn->hw_info.personality) {
	case QED_PCI_ETH:
		p_ramrod->personality = PERSONALITY_ETH;
		break;
	case QED_PCI_ISCSI:
		p_ramrod->personality = PERSONALITY_ISCSI;
		break;
	case QED_PCI_ETH_ROCE:
		p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
		break;
	default:
		DP_NOTICE(p_hwfn, "Unkown personality %d\n",
			  p_hwfn->hw_info.personality);
		p_ramrod->personality = PERSONALITY_ETH;
	}

	if (p_hwfn->cdev->p_iov_info) {
		struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;

		p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
		p_ramrod->num_vfs = (u8) p_iov->total_vfs;
	}
	p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
	p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;

	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
		   "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
		   sb, sb_index, p_ramrod->outer_tag);

	rc = qed_spq_post(p_hwfn, p_ent, NULL);

	if (p_tunn) {
		qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
				     p_tunn->tunn_mode);
		p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
	}

	return rc;
}

int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_CB;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
				      &p_ent->ramrod.pf_update);

	return qed_spq_post(p_hwfn, p_ent, NULL);
}

/* Set pf update ramrod command params */
int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
			      struct qed_tunn_update_params *p_tunn,
			      enum spq_mode comp_mode,
			      struct qed_spq_comp_cb *p_comp_data)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = comp_mode;
	init_data.p_comp_data = p_comp_data;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
				      &p_ent->ramrod.pf_update.tunnel_config);

	rc = qed_spq_post(p_hwfn, p_ent, NULL);
	if (rc)
		return rc;

	if (p_tunn->update_vxlan_udp_port)
		qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
					p_tunn->vxlan_udp_port);
	if (p_tunn->update_geneve_udp_port)
		qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
					 p_tunn->geneve_udp_port);

	qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
	p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;

	return rc;
}

int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc = -EINVAL;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	return qed_spq_post(p_hwfn, p_ent, NULL);
}

int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
{
	struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;
	int rc;

	/* Get SPQ entry */
	memset(&init_data, 0, sizeof(init_data));
	init_data.cid = qed_spq_get_cid(p_hwfn);
	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;

	rc = qed_sp_init_request(p_hwfn, &p_ent,
				 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
				 &init_data);
	if (rc)
		return rc;

	return qed_spq_post(p_hwfn, p_ent, NULL);
}
Commit	Line	Data
fe56b9e6 YM	1	/* QLogic qed NIC Driver
	2	* Copyright (c) 2015 QLogic Corporation
	3	*
	4	* This software is available under the terms of the GNU General Public License
	5	* (GPL) Version 2, available from the file COPYING in the main directory of
	6	* this source tree.
	7	*/
	8
	9	#include <linux/types.h>
	10	#include <asm/byteorder.h>
	11	#include <linux/bitops.h>
	12	#include <linux/errno.h>
	13	#include <linux/kernel.h>
	14	#include <linux/string.h>
	15	#include "qed.h"
	16	#include <linux/qed/qed_chain.h>
	17	#include "qed_cxt.h"
39651abd	18	#include "qed_dcbx.h"
fe56b9e6 YM	19	#include "qed_hsi.h"
	20	#include "qed_hw.h"
	21	#include "qed_int.h"
	22	#include "qed_reg_addr.h"
	23	#include "qed_sp.h"
1408cc1f	24	#include "qed_sriov.h"
fe56b9e6 YM	25
	26	int qed_sp_init_request(struct qed_hwfn *p_hwfn,
	27	struct qed_spq_entry **pp_ent,
1a635e48	28	u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
fe56b9e6	29	{
06f56b81	30	u32 opaque_cid = p_data->opaque_fid << 16 \| p_data->cid;
fe56b9e6	31	struct qed_spq_entry *p_ent = NULL;
06f56b81	32	int rc;
fe56b9e6 YM	33
	34	if (!pp_ent)
	35	return -ENOMEM;
	36
	37	rc = qed_spq_get_entry(p_hwfn, pp_ent);
	38
1a635e48	39	if (rc)
fe56b9e6 YM	40	return rc;
	41
	42	p_ent = *pp_ent;
	43
	44	p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid);
	45	p_ent->elem.hdr.cmd_id = cmd;
	46	p_ent->elem.hdr.protocol_id = protocol;
	47
	48	p_ent->priority = QED_SPQ_PRIORITY_NORMAL;
06f56b81	49	p_ent->comp_mode = p_data->comp_mode;
fe56b9e6 YM	50	p_ent->comp_done.done = 0;
	51
	52	switch (p_ent->comp_mode) {
	53	case QED_SPQ_MODE_EBLOCK:
	54	p_ent->comp_cb.cookie = &p_ent->comp_done;
	55	break;
	56
	57	case QED_SPQ_MODE_BLOCK:
06f56b81	58	if (!p_data->p_comp_data)
fe56b9e6 YM	59	return -EINVAL;
fe56b9e6 YM	60
06f56b81	61	p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
fe56b9e6 YM	62	break;
	63
	64	case QED_SPQ_MODE_CB:
06f56b81	65	if (!p_data->p_comp_data)
fe56b9e6 YM	66	p_ent->comp_cb.function = NULL;
fe56b9e6 YM	67	else
06f56b81	68	p_ent->comp_cb = *p_data->p_comp_data;
fe56b9e6 YM	69	break;
	70
	71	default:
	72	DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
	73	p_ent->comp_mode);
	74	return -EINVAL;
	75	}
	76
	77	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
	78	"Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
	79	opaque_cid, cmd, protocol,
	80	(unsigned long)&p_ent->ramrod,
	81	D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
	82	QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
	83	"MODE_CB"));
06f56b81 YM	84
06f56b81 YM	85	memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
fe56b9e6 YM	86
	87	return 0;
	88	}
	89
464f6645 MC	90	static enum tunnel_clss qed_tunn_get_clss_type(u8 type)
	91	{
	92	switch (type) {
	93	case QED_TUNN_CLSS_MAC_VLAN:
	94	return TUNNEL_CLSS_MAC_VLAN;
	95	case QED_TUNN_CLSS_MAC_VNI:
	96	return TUNNEL_CLSS_MAC_VNI;
	97	case QED_TUNN_CLSS_INNER_MAC_VLAN:
	98	return TUNNEL_CLSS_INNER_MAC_VLAN;
	99	case QED_TUNN_CLSS_INNER_MAC_VNI:
	100	return TUNNEL_CLSS_INNER_MAC_VNI;
	101	default:
	102	return TUNNEL_CLSS_MAC_VLAN;
	103	}
	104	}
	105
	106	static void
	107	qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn,
	108	struct qed_tunn_update_params *p_src,
	109	struct pf_update_tunnel_config *p_tunn_cfg)
	110	{
	111	unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode;
	112	unsigned long update_mask = p_src->tunn_mode_update_mask;
	113	unsigned long tunn_mode = p_src->tunn_mode;
	114	unsigned long new_tunn_mode = 0;
	115
	116	if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) {
	117	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
	118	__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
	119	} else {
	120	if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode))
	121	__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
	122	}
	123
	124	if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) {
	125	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
	126	__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
	127	} else {
	128	if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode))
	129	__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
	130	}
	131
	132	if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) {
	133	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
	134	__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
	135	} else {
	136	if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode))
	137	__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
	138	}
	139
	140	if (p_src->update_geneve_udp_port) {
	141	p_tunn_cfg->set_geneve_udp_port_flg = 1;
	142	p_tunn_cfg->geneve_udp_port =
	143	cpu_to_le16(p_src->geneve_udp_port);
	144	}
	145
	146	if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) {
	147	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
	148	__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
	149	} else {
	150	if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode))
	151	__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
	152	}
	153
154	if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) {
155	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
156	__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
157	} else {
158	if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode))
159	__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
160	}
161
162	p_src->tunn_mode = new_tunn_mode;
163	}
164
165	static void
166	qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
167	struct qed_tunn_update_params *p_src,
168	struct pf_update_tunnel_config *p_tunn_cfg)
169	{
170	unsigned long tunn_mode = p_src->tunn_mode;
171	enum tunnel_clss type;
172
173	qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);
174	p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;
175	p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;
176
177	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
178	p_tunn_cfg->tunnel_clss_vxlan = type;
179
180	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
181	p_tunn_cfg->tunnel_clss_l2gre = type;
182
183	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
184	p_tunn_cfg->tunnel_clss_ipgre = type;
185
186	if (p_src->update_vxlan_udp_port) {
187	p_tunn_cfg->set_vxlan_udp_port_flg = 1;
188	p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
189	}
190
191	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
192	p_tunn_cfg->tx_enable_l2gre = 1;
193
194	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
195	p_tunn_cfg->tx_enable_ipgre = 1;
196
197	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
198	p_tunn_cfg->tx_enable_vxlan = 1;
199
200	if (p_src->update_geneve_udp_port) {
201	p_tunn_cfg->set_geneve_udp_port_flg = 1;
202	p_tunn_cfg->geneve_udp_port =
203	cpu_to_le16(p_src->geneve_udp_port);
204	}
205
206	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
207	p_tunn_cfg->tx_enable_l2geneve = 1;
208
209	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
210	p_tunn_cfg->tx_enable_ipgeneve = 1;
211
212	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
213	p_tunn_cfg->tunnel_clss_l2geneve = type;
214
215	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
216	p_tunn_cfg->tunnel_clss_ipgeneve = type;
217	}
218
219	static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
220	struct qed_ptt *p_ptt,
221	unsigned long tunn_mode)
222	{
223	u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0;
224	u8 l2geneve_enable = 0, ipgeneve_enable = 0;
225
226	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
227	l2gre_enable = 1;
228
229	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
230	ipgre_enable = 1;
231
232	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
233	vxlan_enable = 1;
234
235	qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable);
236	qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable);
237
238	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
239	l2geneve_enable = 1;
240
241	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
242	ipgeneve_enable = 1;
243
244	qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable,
245	ipgeneve_enable);
246	}
247
248	static void
249	qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
250	struct qed_tunn_start_params *p_src,
251	struct pf_start_tunnel_config *p_tunn_cfg)
252	{
253	unsigned long tunn_mode;
254	enum tunnel_clss type;
255
256	if (!p_src)
257	return;
258
259	tunn_mode = p_src->tunn_mode;
260	type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
261	p_tunn_cfg->tunnel_clss_vxlan = type;
262	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
263	p_tunn_cfg->tunnel_clss_l2gre = type;
264	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
265	p_tunn_cfg->tunnel_clss_ipgre = type;
266
267	if (p_src->update_vxlan_udp_port) {
268	p_tunn_cfg->set_vxlan_udp_port_flg = 1;
269	p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
270	}
271
272	if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
273	p_tunn_cfg->tx_enable_l2gre = 1;
274
275	if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
276	p_tunn_cfg->tx_enable_ipgre = 1;
277
278	if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
279	p_tunn_cfg->tx_enable_vxlan = 1;
280
281	if (p_src->update_geneve_udp_port) {
282	p_tunn_cfg->set_geneve_udp_port_flg = 1;
283	p_tunn_cfg->geneve_udp_port =
284	cpu_to_le16(p_src->geneve_udp_port);
285	}
286
287	if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
288	p_tunn_cfg->tx_enable_l2geneve = 1;
289
290	if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
291	p_tunn_cfg->tx_enable_ipgeneve = 1;
292
293	type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
294	p_tunn_cfg->tunnel_clss_l2geneve = type;
295	type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
296	p_tunn_cfg->tunnel_clss_ipgeneve = type;
297	}
298
fe56b9e6	299	int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
464f6645	300	struct qed_tunn_start_params *p_tunn,
831bfb0e	301	enum qed_mf_mode mode, bool allow_npar_tx_switch)
fe56b9e6	302	{
fe56b9e6 YM	303	struct pf_start_ramrod_data *p_ramrod = NULL;
	304	u16 sb = qed_int_get_sp_sb_id(p_hwfn);
	305	u8 sb_index = p_hwfn->p_eq->eq_sb_index;
	306	struct qed_spq_entry *p_ent = NULL;
06f56b81	307	struct qed_sp_init_data init_data;
fe56b9e6	308	int rc = -EINVAL;
a91eb52a	309	u8 page_cnt;
fe56b9e6 YM	310
	311	/* update initial eq producer */
	312	qed_eq_prod_update(p_hwfn,
	313	qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
	314
06f56b81 YM	315	memset(&init_data, 0, sizeof(init_data));
	316	init_data.cid = qed_spq_get_cid(p_hwfn);
	317	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	318	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
fe56b9e6	319
06f56b81	320	rc = qed_sp_init_request(p_hwfn, &p_ent,
fe56b9e6	321	COMMON_RAMROD_PF_START,
1a635e48	322	PROTOCOLID_COMMON, &init_data);
fe56b9e6 YM	323	if (rc)
	324	return rc;
	325
	326	p_ramrod = &p_ent->ramrod.pf_start;
	327
	328	p_ramrod->event_ring_sb_id = cpu_to_le16(sb);
	329	p_ramrod->event_ring_sb_index = sb_index;
	330	p_ramrod->path_id = QED_PATH_ID(p_hwfn);
	331	p_ramrod->dont_log_ramrods = 0;
	332	p_ramrod->log_type_mask = cpu_to_le16(0xf);
351a4ded	333
fc48b7a6 YM	334	switch (mode) {
	335	case QED_MF_DEFAULT:
	336	case QED_MF_NPAR:
	337	p_ramrod->mf_mode = MF_NPAR;
	338	break;
	339	case QED_MF_OVLAN:
	340	p_ramrod->mf_mode = MF_OVLAN;
	341	break;
	342	default:
	343	DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
	344	p_ramrod->mf_mode = MF_NPAR;
	345	}
fe56b9e6 YM	346	p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
	347
	348	/* Place EQ address in RAMROD */
94494598 YM	349	DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
94494598 YM	350	p_hwfn->p_eq->chain.pbl.p_phys_table);
a91eb52a YM	351	page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
a91eb52a YM	352	p_ramrod->event_ring_num_pages = page_cnt;
94494598 YM	353	DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
94494598 YM	354	p_hwfn->p_consq->chain.pbl.p_phys_table);
fe56b9e6	355
1a635e48	356	qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);
fe56b9e6	357
831bfb0e YM	358	if (IS_MF_SI(p_hwfn))
	359	p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
	360
c5ac9319 YM	361	switch (p_hwfn->hw_info.personality) {
	362	case QED_PCI_ETH:
	363	p_ramrod->personality = PERSONALITY_ETH;
	364	break;
	365	case QED_PCI_ISCSI:
	366	p_ramrod->personality = PERSONALITY_ISCSI;
	367	break;
	368	case QED_PCI_ETH_ROCE:
	369	p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
	370	break;
	371	default:
	372	DP_NOTICE(p_hwfn, "Unkown personality %d\n",
	373	p_hwfn->hw_info.personality);
	374	p_ramrod->personality = PERSONALITY_ETH;
	375	}
	376
1408cc1f YM	377	if (p_hwfn->cdev->p_iov_info) {
	378	struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
	379
	380	p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
	381	p_ramrod->num_vfs = (u8) p_iov->total_vfs;
	382	}
351a4ded YM	383	p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
351a4ded YM	384	p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
1408cc1f	385
fe56b9e6	386	DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
fc48b7a6	387	"Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
1a635e48	388	sb, sb_index, p_ramrod->outer_tag);
fe56b9e6	389
c0f31a05 MC	390	rc = qed_spq_post(p_hwfn, p_ent, NULL);
	391
	392	if (p_tunn) {
	393	qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
	394	p_tunn->tunn_mode);
	395	p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
	396	}
	397
	398	return rc;
fe56b9e6 YM	399	}
fe56b9e6 YM	400
39651abd SRK	401	int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
	402	{
	403	struct qed_spq_entry *p_ent = NULL;
	404	struct qed_sp_init_data init_data;
	405	int rc = -EINVAL;
	406
	407	/* Get SPQ entry */
	408	memset(&init_data, 0, sizeof(init_data));
	409	init_data.cid = qed_spq_get_cid(p_hwfn);
	410	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	411	init_data.comp_mode = QED_SPQ_MODE_CB;
	412
	413	rc = qed_sp_init_request(p_hwfn, &p_ent,
	414	COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
	415	&init_data);
	416	if (rc)
	417	return rc;
	418
	419	qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
	420	&p_ent->ramrod.pf_update);
	421
	422	return qed_spq_post(p_hwfn, p_ent, NULL);
	423	}
	424
464f6645 MC	425	/* Set pf update ramrod command params */
	426	int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
	427	struct qed_tunn_update_params *p_tunn,
	428	enum spq_mode comp_mode,
	429	struct qed_spq_comp_cb *p_comp_data)
	430	{
	431	struct qed_spq_entry *p_ent = NULL;
	432	struct qed_sp_init_data init_data;
	433	int rc = -EINVAL;
	434
	435	/* Get SPQ entry */
	436	memset(&init_data, 0, sizeof(init_data));
	437	init_data.cid = qed_spq_get_cid(p_hwfn);
	438	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	439	init_data.comp_mode = comp_mode;
	440	init_data.p_comp_data = p_comp_data;
	441
	442	rc = qed_sp_init_request(p_hwfn, &p_ent,
	443	COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
	444	&init_data);
	445	if (rc)
	446	return rc;
	447
	448	qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
	449	&p_ent->ramrod.pf_update.tunnel_config);
	450
	451	rc = qed_spq_post(p_hwfn, p_ent, NULL);
	452	if (rc)
	453	return rc;
	454
	455	if (p_tunn->update_vxlan_udp_port)
	456	qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
	457	p_tunn->vxlan_udp_port);
	458	if (p_tunn->update_geneve_udp_port)
	459	qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
	460	p_tunn->geneve_udp_port);
	461
	462	qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
	463	p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
	464
	465	return rc;
	466	}
	467
fe56b9e6 YM	468	int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
fe56b9e6 YM	469	{
fe56b9e6	470	struct qed_spq_entry *p_ent = NULL;
06f56b81	471	struct qed_sp_init_data init_data;
fe56b9e6 YM	472	int rc = -EINVAL;
fe56b9e6 YM	473
06f56b81 YM	474	/* Get SPQ entry */
	475	memset(&init_data, 0, sizeof(init_data));
	476	init_data.cid = qed_spq_get_cid(p_hwfn);
	477	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	478	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
fe56b9e6	479
06f56b81	480	rc = qed_sp_init_request(p_hwfn, &p_ent,
fe56b9e6	481	COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
06f56b81	482	&init_data);
fe56b9e6 YM	483	if (rc)
	484	return rc;
	485
	486	return qed_spq_post(p_hwfn, p_ent, NULL);
	487	}
03dc76ca SRK	488
	489	int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
	490	{
	491	struct qed_spq_entry *p_ent = NULL;
	492	struct qed_sp_init_data init_data;
	493	int rc;
	494
	495	/* Get SPQ entry */
	496	memset(&init_data, 0, sizeof(init_data));
	497	init_data.cid = qed_spq_get_cid(p_hwfn);
	498	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
	499	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
	500
	501	rc = qed_sp_init_request(p_hwfn, &p_ent,
	502	COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
	503	&init_data);
	504	if (rc)
	505	return rc;
	506
	507	return qed_spq_post(p_hwfn, p_ent, NULL);
	508	}