[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede.h

/* QLogic qede NIC Driver
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/

#ifndef _QEDE_H_
#define _QEDE_H_
#include <linux/compiler.h>
#include <linux/version.h>
#include <linux/workqueue.h>
#include <linux/netdevice.h>
#include <linux/interrupt.h>
#include <linux/bitmap.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/qed/common_hsi.h>
#include <linux/qed/eth_common.h>
#include <linux/qed/qed_if.h>
#include <linux/qed/qed_chain.h>
#include <linux/qed/qed_eth_if.h>

#define QEDE_MAJOR_VERSION		8
#define QEDE_MINOR_VERSION		10
#define QEDE_REVISION_VERSION		9
#define QEDE_ENGINEERING_VERSION	20
#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "."	\
		__stringify(QEDE_MINOR_VERSION) "."		\
		__stringify(QEDE_REVISION_VERSION) "."		\
		__stringify(QEDE_ENGINEERING_VERSION)

#define DRV_MODULE_SYM		qede

struct qede_stats {
	u64 no_buff_discards;
	u64 packet_too_big_discard;
	u64 ttl0_discard;
	u64 rx_ucast_bytes;
	u64 rx_mcast_bytes;
	u64 rx_bcast_bytes;
	u64 rx_ucast_pkts;
	u64 rx_mcast_pkts;
	u64 rx_bcast_pkts;
	u64 mftag_filter_discards;
	u64 mac_filter_discards;
	u64 tx_ucast_bytes;
	u64 tx_mcast_bytes;
	u64 tx_bcast_bytes;
	u64 tx_ucast_pkts;
	u64 tx_mcast_pkts;
	u64 tx_bcast_pkts;
	u64 tx_err_drop_pkts;
	u64 coalesced_pkts;
	u64 coalesced_events;
	u64 coalesced_aborts_num;
	u64 non_coalesced_pkts;
	u64 coalesced_bytes;

	/* port */
	u64 rx_64_byte_packets;
	u64 rx_65_to_127_byte_packets;
	u64 rx_128_to_255_byte_packets;
	u64 rx_256_to_511_byte_packets;
	u64 rx_512_to_1023_byte_packets;
	u64 rx_1024_to_1518_byte_packets;
	u64 rx_1519_to_1522_byte_packets;
	u64 rx_1519_to_2047_byte_packets;
	u64 rx_2048_to_4095_byte_packets;
	u64 rx_4096_to_9216_byte_packets;
	u64 rx_9217_to_16383_byte_packets;
	u64 rx_crc_errors;
	u64 rx_mac_crtl_frames;
	u64 rx_pause_frames;
	u64 rx_pfc_frames;
	u64 rx_align_errors;
	u64 rx_carrier_errors;
	u64 rx_oversize_packets;
	u64 rx_jabbers;
	u64 rx_undersize_packets;
	u64 rx_fragments;
	u64 tx_64_byte_packets;
	u64 tx_65_to_127_byte_packets;
	u64 tx_128_to_255_byte_packets;
	u64 tx_256_to_511_byte_packets;
	u64 tx_512_to_1023_byte_packets;
	u64 tx_1024_to_1518_byte_packets;
	u64 tx_1519_to_2047_byte_packets;
	u64 tx_2048_to_4095_byte_packets;
	u64 tx_4096_to_9216_byte_packets;
	u64 tx_9217_to_16383_byte_packets;
	u64 tx_pause_frames;
	u64 tx_pfc_frames;
	u64 tx_lpi_entry_count;
	u64 tx_total_collisions;
	u64 brb_truncates;
	u64 brb_discards;
	u64 tx_mac_ctrl_frames;
};

struct qede_vlan {
	struct list_head list;
	u16 vid;
	bool configured;
};

struct qede_dev {
	struct qed_dev			*cdev;
	struct net_device		*ndev;
	struct pci_dev			*pdev;

	u32				dp_module;
	u8				dp_level;

	u32 flags;
#define QEDE_FLAG_IS_VF	BIT(0)
#define IS_VF(edev)	(!!((edev)->flags & QEDE_FLAG_IS_VF))

	const struct qed_eth_ops	*ops;

	struct qed_dev_eth_info	dev_info;
#define QEDE_MAX_RSS_CNT(edev)	((edev)->dev_info.num_queues)
#define QEDE_MAX_TSS_CNT(edev)	((edev)->dev_info.num_queues * \
				 (edev)->dev_info.num_tc)

	struct qede_fastpath		*fp_array;
	u8				req_num_tx;
	u8				fp_num_tx;
	u8				req_num_rx;
	u8				fp_num_rx;
	u16				req_queues;
	u16				num_queues;
	u8				num_tc;
#define QEDE_QUEUE_CNT(edev)	((edev)->num_queues)
#define QEDE_RSS_COUNT(edev)	((edev)->num_queues - (edev)->fp_num_tx)
#define QEDE_TSS_COUNT(edev)	(((edev)->num_queues - (edev)->fp_num_rx) * \
				 (edev)->num_tc)
#define QEDE_TX_IDX(edev, txqidx)	((edev)->fp_num_rx + (txqidx) % \
					 QEDE_TSS_COUNT(edev))
#define QEDE_TC_IDX(edev, txqidx)	((txqidx) / QEDE_TSS_COUNT(edev))
#define QEDE_TX_QUEUE(edev, txqidx)	\
	(&(edev)->fp_array[QEDE_TX_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX(\
							(edev), (txqidx))])

	struct qed_int_info		int_info;
	unsigned char			primary_mac[ETH_ALEN];

	/* Smaller private varaiant of the RTNL lock */
	struct mutex			qede_lock;
	u32				state; /* Protected by qede_lock */
	u16				rx_buf_size;
	u32				rx_copybreak;

	/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
#define ETH_OVERHEAD			(ETH_HLEN + 8 + 8)
	/* Max supported alignment is 256 (8 shift)
	 * minimal alignment shift 6 is optimal for 57xxx HW performance
	 */
#define QEDE_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
	/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
	 * at the end of skb->data, to avoid wasting a full cache line.
	 * This reduces memory use (skb->truesize).
	 */
#define QEDE_FW_RX_ALIGN_END					\
	max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT,			\
	      SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))

	struct qede_stats		stats;
#define QEDE_RSS_INDIR_INITED	BIT(0)
#define QEDE_RSS_KEY_INITED	BIT(1)
#define QEDE_RSS_CAPS_INITED	BIT(2)
	u32 rss_params_inited; /* bit-field to track initialized rss params */
	struct qed_update_vport_rss_params	rss_params;
	u16			q_num_rx_buffers; /* Must be a power of two */
	u16			q_num_tx_buffers; /* Must be a power of two */

	bool gro_disable;
	struct list_head vlan_list;
	u16 configured_vlans;
	u16 non_configured_vlans;
	bool accept_any_vlan;
	struct delayed_work		sp_task;
	unsigned long			sp_flags;
	u16				vxlan_dst_port;
	u16				geneve_dst_port;
};

enum QEDE_STATE {
	QEDE_STATE_CLOSED,
	QEDE_STATE_OPEN,
};

#define HILO_U64(hi, lo)		((((u64)(hi)) << 32) + (lo))

#define	MAX_NUM_TC	8
#define	MAX_NUM_PRI	8

/* The driver supports the new build_skb() API:
 * RX ring buffer contains pointer to kmalloc() data only,
 * skb are built only after the frame was DMA-ed.
 */
struct sw_rx_data {
	struct page *data;
	dma_addr_t mapping;
	unsigned int page_offset;
};

enum qede_agg_state {
	QEDE_AGG_STATE_NONE  = 0,
	QEDE_AGG_STATE_START = 1,
	QEDE_AGG_STATE_ERROR = 2
};

struct qede_agg_info {
	struct sw_rx_data replace_buf;
	dma_addr_t replace_buf_mapping;
	struct sw_rx_data start_buf;
	dma_addr_t start_buf_mapping;
	struct eth_fast_path_rx_tpa_start_cqe start_cqe;
	enum qede_agg_state agg_state;
	struct sk_buff *skb;
	int frag_id;
	u16 vlan_tag;
};

struct qede_rx_queue {
	__le16			*hw_cons_ptr;
	struct sw_rx_data	*sw_rx_ring;
	u16			sw_rx_cons;
	u16			sw_rx_prod;
	struct qed_chain	rx_bd_ring;
	struct qed_chain	rx_comp_ring;
	void __iomem		*hw_rxq_prod_addr;

	/* GRO */
	struct qede_agg_info	tpa_info[ETH_TPA_MAX_AGGS_NUM];

	int			rx_buf_size;
	unsigned int		rx_buf_seg_size;

	u16			num_rx_buffers;
	u16			rxq_id;

	u64			rcv_pkts;
	u64			rx_hw_errors;
	u64			rx_alloc_errors;
	u64			rx_ip_frags;
};

union db_prod {
	struct eth_db_data data;
	u32		raw;
};

struct sw_tx_bd {
	struct sk_buff *skb;
	u8 flags;
/* Set on the first BD descriptor when there is a split BD */
#define QEDE_TSO_SPLIT_BD		BIT(0)
};

struct qede_tx_queue {
	int			index; /* Queue index */
	__le16			*hw_cons_ptr;
	struct sw_tx_bd		*sw_tx_ring;
	u16			sw_tx_cons;
	u16			sw_tx_prod;
	struct qed_chain	tx_pbl;
	void __iomem		*doorbell_addr;
	union db_prod		tx_db;

	u16			num_tx_buffers;
	u64			xmit_pkts;
	u64			stopped_cnt;

	bool			is_legacy;
};

#define BD_UNMAP_ADDR(bd)		HILO_U64(le32_to_cpu((bd)->addr.hi), \
						 le32_to_cpu((bd)->addr.lo))
#define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len)				\
	do {								\
		(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr));	\
		(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr));	\
		(bd)->nbytes = cpu_to_le16(len);			\
	} while (0)
#define BD_UNMAP_LEN(bd)		(le16_to_cpu((bd)->nbytes))

struct qede_fastpath {
	struct qede_dev	*edev;
#define QEDE_FASTPATH_TX	BIT(0)
#define QEDE_FASTPATH_RX	BIT(1)
#define QEDE_FASTPATH_COMBINED	(QEDE_FASTPATH_TX | QEDE_FASTPATH_RX)
	u8			type;
	u8			id;
	struct napi_struct	napi;
	struct qed_sb_info	*sb_info;
	struct qede_rx_queue	*rxq;
	struct qede_tx_queue	*txqs;

#define VEC_NAME_SIZE	(sizeof(((struct net_device *)0)->name) + 8)
	char	name[VEC_NAME_SIZE];
};

/* Debug print definitions */
#define DP_NAME(edev) ((edev)->ndev->name)

#define XMIT_PLAIN		0
#define XMIT_L4_CSUM		BIT(0)
#define XMIT_LSO		BIT(1)
#define XMIT_ENC		BIT(2)

#define QEDE_CSUM_ERROR			BIT(0)
#define QEDE_CSUM_UNNECESSARY		BIT(1)
#define QEDE_TUNN_CSUM_UNNECESSARY	BIT(2)

#define QEDE_SP_RX_MODE			1
#define QEDE_SP_VXLAN_PORT_CONFIG	2
#define QEDE_SP_GENEVE_PORT_CONFIG	3

union qede_reload_args {
	u16 mtu;
};

#ifdef CONFIG_DCB
void qede_set_dcbnl_ops(struct net_device *ndev);
#endif
void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
void qede_set_ethtool_ops(struct net_device *netdev);
void qede_reload(struct qede_dev *edev,
		 void (*func)(struct qede_dev *edev,
			      union qede_reload_args *args),
		 union qede_reload_args *args);
int qede_change_mtu(struct net_device *dev, int new_mtu);
void qede_fill_by_demand_stats(struct qede_dev *edev);
bool qede_has_rx_work(struct qede_rx_queue *rxq);
int qede_txq_has_work(struct qede_tx_queue *txq);
void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, struct qede_dev *edev,
			     u8 count);

#define RX_RING_SIZE_POW	13
#define RX_RING_SIZE		((u16)BIT(RX_RING_SIZE_POW))
#define NUM_RX_BDS_MAX		(RX_RING_SIZE - 1)
#define NUM_RX_BDS_MIN		128
#define NUM_RX_BDS_DEF		NUM_RX_BDS_MAX

#define TX_RING_SIZE_POW	13
#define TX_RING_SIZE		((u16)BIT(TX_RING_SIZE_POW))
#define NUM_TX_BDS_MAX		(TX_RING_SIZE - 1)
#define NUM_TX_BDS_MIN		128
#define NUM_TX_BDS_DEF		NUM_TX_BDS_MAX

#define QEDE_MIN_PKT_LEN	64
#define QEDE_RX_HDR_SIZE	256
#define	for_each_queue(i) for (i = 0; i < edev->num_queues; i++)

#endif /* _QEDE_H_ */
Commit	Line	Data
e712d52b YM	1	/* QLogic qede NIC Driver
	2	* Copyright (c) 2015 QLogic Corporation
	3	*
	4	* This software is available under the terms of the GNU General Public License
	5	* (GPL) Version 2, available from the file COPYING in the main directory of
	6	* this source tree.
	7	*/
	8
	9	#ifndef _QEDE_H_
	10	#define _QEDE_H_
	11	#include <linux/compiler.h>
	12	#include <linux/version.h>
	13	#include <linux/workqueue.h>
	14	#include <linux/netdevice.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/bitmap.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mutex.h>
	19	#include <linux/io.h>
	20	#include <linux/qed/common_hsi.h>
	21	#include <linux/qed/eth_common.h>
	22	#include <linux/qed/qed_if.h>
	23	#include <linux/qed/qed_chain.h>
	24	#include <linux/qed/qed_eth_if.h>
	25
	26	#define QEDE_MAJOR_VERSION 8
831a8e6c	27	#define QEDE_MINOR_VERSION 10
05fafbfb	28	#define QEDE_REVISION_VERSION 9
7c2d7d74	29	#define QEDE_ENGINEERING_VERSION 20
e712d52b YM	30	#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
	31	__stringify(QEDE_MINOR_VERSION) "." \
	32	__stringify(QEDE_REVISION_VERSION) "." \
	33	__stringify(QEDE_ENGINEERING_VERSION)
	34
e712d52b YM	35	#define DRV_MODULE_SYM qede
e712d52b YM	36
133fac0e SK	37	struct qede_stats {
133fac0e SK	38	u64 no_buff_discards;
1a5a366f SRK	39	u64 packet_too_big_discard;
1a5a366f SRK	40	u64 ttl0_discard;
133fac0e SK	41	u64 rx_ucast_bytes;
	42	u64 rx_mcast_bytes;
	43	u64 rx_bcast_bytes;
	44	u64 rx_ucast_pkts;
	45	u64 rx_mcast_pkts;
	46	u64 rx_bcast_pkts;
	47	u64 mftag_filter_discards;
	48	u64 mac_filter_discards;
	49	u64 tx_ucast_bytes;
	50	u64 tx_mcast_bytes;
	51	u64 tx_bcast_bytes;
	52	u64 tx_ucast_pkts;
	53	u64 tx_mcast_pkts;
	54	u64 tx_bcast_pkts;
	55	u64 tx_err_drop_pkts;
	56	u64 coalesced_pkts;
	57	u64 coalesced_events;
	58	u64 coalesced_aborts_num;
	59	u64 non_coalesced_pkts;
	60	u64 coalesced_bytes;
	61
	62	/* port */
	63	u64 rx_64_byte_packets;
d4967cf3 YM	64	u64 rx_65_to_127_byte_packets;
	65	u64 rx_128_to_255_byte_packets;
	66	u64 rx_256_to_511_byte_packets;
	67	u64 rx_512_to_1023_byte_packets;
	68	u64 rx_1024_to_1518_byte_packets;
	69	u64 rx_1519_to_1522_byte_packets;
	70	u64 rx_1519_to_2047_byte_packets;
	71	u64 rx_2048_to_4095_byte_packets;
	72	u64 rx_4096_to_9216_byte_packets;
	73	u64 rx_9217_to_16383_byte_packets;
133fac0e SK	74	u64 rx_crc_errors;
	75	u64 rx_mac_crtl_frames;
	76	u64 rx_pause_frames;
	77	u64 rx_pfc_frames;
	78	u64 rx_align_errors;
	79	u64 rx_carrier_errors;
	80	u64 rx_oversize_packets;
	81	u64 rx_jabbers;
	82	u64 rx_undersize_packets;
	83	u64 rx_fragments;
	84	u64 tx_64_byte_packets;
	85	u64 tx_65_to_127_byte_packets;
	86	u64 tx_128_to_255_byte_packets;
	87	u64 tx_256_to_511_byte_packets;
	88	u64 tx_512_to_1023_byte_packets;
	89	u64 tx_1024_to_1518_byte_packets;
	90	u64 tx_1519_to_2047_byte_packets;
	91	u64 tx_2048_to_4095_byte_packets;
	92	u64 tx_4096_to_9216_byte_packets;
	93	u64 tx_9217_to_16383_byte_packets;
	94	u64 tx_pause_frames;
	95	u64 tx_pfc_frames;
	96	u64 tx_lpi_entry_count;
	97	u64 tx_total_collisions;
	98	u64 brb_truncates;
	99	u64 brb_discards;
	100	u64 tx_mac_ctrl_frames;
	101	};
	102
7c1bfcad SRK	103	struct qede_vlan {
	104	struct list_head list;
	105	u16 vid;
	106	bool configured;
	107	};
	108
e712d52b YM	109	struct qede_dev {
	110	struct qed_dev *cdev;
	111	struct net_device *ndev;
	112	struct pci_dev *pdev;
	113
	114	u32 dp_module;
	115	u8 dp_level;
	116
fefb0202 YM	117	u32 flags;
	118	#define QEDE_FLAG_IS_VF BIT(0)
	119	#define IS_VF(edev) (!!((edev)->flags & QEDE_FLAG_IS_VF))
	120
e712d52b YM	121	const struct qed_eth_ops *ops;
	122
	123	struct qed_dev_eth_info dev_info;
	124	#define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
	125	#define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \
	126	(edev)->dev_info.num_tc)
	127
2950219d	128	struct qede_fastpath *fp_array;
9a4d7e86 SRK	129	u8 req_num_tx;
	130	u8 fp_num_tx;
	131	u8 req_num_rx;
	132	u8 fp_num_rx;
	133	u16 req_queues;
	134	u16 num_queues;
e712d52b	135	u8 num_tc;
9a4d7e86 SRK	136	#define QEDE_QUEUE_CNT(edev) ((edev)->num_queues)
	137	#define QEDE_RSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_tx)
	138	#define QEDE_TSS_COUNT(edev) (((edev)->num_queues - (edev)->fp_num_rx) * \
	139	(edev)->num_tc)
	140	#define QEDE_TX_IDX(edev, txqidx) ((edev)->fp_num_rx + (txqidx) % \
	141	QEDE_TSS_COUNT(edev))
	142	#define QEDE_TC_IDX(edev, txqidx) ((txqidx) / QEDE_TSS_COUNT(edev))
2950219d	143	#define QEDE_TX_QUEUE(edev, txqidx) \
9a4d7e86	144	(&(edev)->fp_array[QEDE_TX_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX(\
2950219d	145	(edev), (txqidx))])
e712d52b YM	146
	147	struct qed_int_info int_info;
	148	unsigned char primary_mac[ETH_ALEN];
	149
	150	/* Smaller private varaiant of the RTNL lock */
	151	struct mutex qede_lock;
	152	u32 state; /* Protected by qede_lock */
2950219d	153	u16 rx_buf_size;
3d789994 MC	154	u32 rx_copybreak;
3d789994 MC	155
2950219d YM	156	/* L2 header size + 2VLANs (8 bytes) + LLC SNAP (8 bytes) /
	157	#define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
	158	/* Max supported alignment is 256 (8 shift)
	159	* minimal alignment shift 6 is optimal for 57xxx HW performance
	160	*/
	161	#define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
	162	/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
	163	* at the end of skb->data, to avoid wasting a full cache line.
	164	* This reduces memory use (skb->truesize).
	165	*/
	166	#define QEDE_FW_RX_ALIGN_END \
	167	max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \
	168	SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
	169
133fac0e	170	struct qede_stats stats;
961acdea SRK	171	#define QEDE_RSS_INDIR_INITED BIT(0)
	172	#define QEDE_RSS_KEY_INITED BIT(1)
	173	#define QEDE_RSS_CAPS_INITED BIT(2)
	174	u32 rss_params_inited; /* bit-field to track initialized rss params */
2950219d YM	175	struct qed_update_vport_rss_params rss_params;
	176	u16 q_num_rx_buffers; /* Must be a power of two */
	177	u16 q_num_tx_buffers; /* Must be a power of two */
0d8e0aa0	178
55482edc	179	bool gro_disable;
7c1bfcad SRK	180	struct list_head vlan_list;
	181	u16 configured_vlans;
	182	u16 non_configured_vlans;
	183	bool accept_any_vlan;
0d8e0aa0 SK	184	struct delayed_work sp_task;
0d8e0aa0 SK	185	unsigned long sp_flags;
b18e170c	186	u16 vxlan_dst_port;
9a109dd0	187	u16 geneve_dst_port;
2950219d YM	188	};
	189
	190	enum QEDE_STATE {
	191	QEDE_STATE_CLOSED,
	192	QEDE_STATE_OPEN,
	193	};
	194
	195	#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
	196
	197	#define MAX_NUM_TC 8
	198	#define MAX_NUM_PRI 8
	199
	200	/* The driver supports the new build_skb() API:
	201	* RX ring buffer contains pointer to kmalloc() data only,
	202	* skb are built only after the frame was DMA-ed.
	203	*/
	204	struct sw_rx_data {
fc48b7a6 YM	205	struct page *data;
	206	dma_addr_t mapping;
	207	unsigned int page_offset;
2950219d YM	208	};
2950219d YM	209
55482edc MC	210	enum qede_agg_state {
	211	QEDE_AGG_STATE_NONE = 0,
	212	QEDE_AGG_STATE_START = 1,
	213	QEDE_AGG_STATE_ERROR = 2
	214	};
	215
	216	struct qede_agg_info {
	217	struct sw_rx_data replace_buf;
	218	dma_addr_t replace_buf_mapping;
	219	struct sw_rx_data start_buf;
	220	dma_addr_t start_buf_mapping;
	221	struct eth_fast_path_rx_tpa_start_cqe start_cqe;
	222	enum qede_agg_state agg_state;
	223	struct sk_buff *skb;
	224	int frag_id;
	225	u16 vlan_tag;
	226	};
	227
2950219d YM	228	struct qede_rx_queue {
	229	__le16 *hw_cons_ptr;
	230	struct sw_rx_data *sw_rx_ring;
	231	u16 sw_rx_cons;
	232	u16 sw_rx_prod;
	233	struct qed_chain rx_bd_ring;
	234	struct qed_chain rx_comp_ring;
	235	void __iomem *hw_rxq_prod_addr;
	236
55482edc MC	237	/* GRO */
	238	struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
	239
2950219d	240	int rx_buf_size;
fc48b7a6	241	unsigned int rx_buf_seg_size;
2950219d YM	242
	243	u16 num_rx_buffers;
	244	u16 rxq_id;
	245
68db9ec2	246	u64 rcv_pkts;
2950219d YM	247	u64 rx_hw_errors;
2950219d YM	248	u64 rx_alloc_errors;
c72a6125	249	u64 rx_ip_frags;
2950219d YM	250	};
	251
	252	union db_prod {
	253	struct eth_db_data data;
	254	u32 raw;
	255	};
	256
	257	struct sw_tx_bd {
	258	struct sk_buff *skb;
	259	u8 flags;
	260	/* Set on the first BD descriptor when there is a split BD */
	261	#define QEDE_TSO_SPLIT_BD BIT(0)
	262	};
	263
	264	struct qede_tx_queue {
	265	int index; /* Queue index */
	266	__le16 *hw_cons_ptr;
	267	struct sw_tx_bd *sw_tx_ring;
	268	u16 sw_tx_cons;
	269	u16 sw_tx_prod;
	270	struct qed_chain tx_pbl;
	271	void __iomem *doorbell_addr;
	272	union db_prod tx_db;
	273
	274	u16 num_tx_buffers;
68db9ec2 SRK	275	u64 xmit_pkts;
68db9ec2 SRK	276	u64 stopped_cnt;
d8c2c7e3 YM	277
d8c2c7e3 YM	278	bool is_legacy;
2950219d YM	279	};
	280
	281	#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \
	282	le32_to_cpu((bd)->addr.lo))
	283	#define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \
	284	do { \
	285	(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \
	286	(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \
	287	(bd)->nbytes = cpu_to_le16(len); \
	288	} while (0)
	289	#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
	290
	291	struct qede_fastpath {
	292	struct qede_dev *edev;
9a4d7e86 SRK	293	#define QEDE_FASTPATH_TX BIT(0)
	294	#define QEDE_FASTPATH_RX BIT(1)
	295	#define QEDE_FASTPATH_COMBINED (QEDE_FASTPATH_TX \| QEDE_FASTPATH_RX)
	296	u8 type;
	297	u8 id;
2950219d YM	298	struct napi_struct napi;
	299	struct qed_sb_info *sb_info;
	300	struct qede_rx_queue *rxq;
	301	struct qede_tx_queue *txqs;
	302
	303	#define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
	304	char name[VEC_NAME_SIZE];
e712d52b YM	305	};
	306
	307	/* Debug print definitions */
	308	#define DP_NAME(edev) ((edev)->ndev->name)
	309
2950219d YM	310	#define XMIT_PLAIN 0
	311	#define XMIT_L4_CSUM BIT(0)
	312	#define XMIT_LSO BIT(1)
	313	#define XMIT_ENC BIT(2)
	314
	315	#define QEDE_CSUM_ERROR BIT(0)
	316	#define QEDE_CSUM_UNNECESSARY BIT(1)
14db81de	317	#define QEDE_TUNN_CSUM_UNNECESSARY BIT(2)
0d8e0aa0	318
b18e170c MC	319	#define QEDE_SP_RX_MODE 1
b18e170c MC	320	#define QEDE_SP_VXLAN_PORT_CONFIG 2
9a109dd0	321	#define QEDE_SP_GENEVE_PORT_CONFIG 3
0d8e0aa0 SK	322
	323	union qede_reload_args {
	324	u16 mtu;
	325	};
	326
489e45ae SRK	327	#ifdef CONFIG_DCB
	328	void qede_set_dcbnl_ops(struct net_device *ndev);
	329	#endif
133fac0e SK	330	void qede_config_debug(uint debug, u32 p_dp_module, u8 p_dp_level);
	331	void qede_set_ethtool_ops(struct net_device *netdev);
	332	void qede_reload(struct qede_dev *edev,
	333	void (func)(struct qede_dev edev,
	334	union qede_reload_args *args),
	335	union qede_reload_args *args);
	336	int qede_change_mtu(struct net_device *dev, int new_mtu);
	337	void qede_fill_by_demand_stats(struct qede_dev *edev);
16f46bf0 SRK	338	bool qede_has_rx_work(struct qede_rx_queue *rxq);
	339	int qede_txq_has_work(struct qede_tx_queue *txq);
	340	void qede_recycle_rx_bd_ring(struct qede_rx_queue rxq, struct qede_dev edev,
	341	u8 count);
133fac0e	342
2950219d	343	#define RX_RING_SIZE_POW 13
01ef7e05	344	#define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW))
2950219d YM	345	#define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
	346	#define NUM_RX_BDS_MIN 128
	347	#define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
	348
	349	#define TX_RING_SIZE_POW 13
01ef7e05	350	#define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW))
2950219d YM	351	#define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
	352	#define NUM_TX_BDS_MIN 128
	353	#define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
	354
3d789994	355	#define QEDE_MIN_PKT_LEN 64
fc48b7a6	356	#define QEDE_RX_HDR_SIZE 256
9a4d7e86	357	#define for_each_queue(i) for (i = 0; i < edev->num_queues; i++)
2950219d	358
e712d52b	359	#endif /* _QEDE_H_ */