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c156633f SS |
1 | /* Renesas Ethernet AVB device driver |
2 | * | |
3 | * Copyright (C) 2014-2015 Renesas Electronics Corporation | |
4 | * Copyright (C) 2015 Renesas Solutions Corp. | |
568b3ce7 | 5 | * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> |
c156633f SS |
6 | * |
7 | * Based on the SuperH Ethernet driver | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License version 2, | |
11 | * as published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #ifndef __RAVB_H__ | |
15 | #define __RAVB_H__ | |
16 | ||
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mdio-bitbang.h> | |
21 | #include <linux/netdevice.h> | |
22 | #include <linux/phy.h> | |
a0d2f206 SS |
23 | #include <linux/platform_device.h> |
24 | #include <linux/ptp_clock_kernel.h> | |
c156633f SS |
25 | |
26 | #define BE_TX_RING_SIZE 64 /* TX ring size for Best Effort */ | |
27 | #define BE_RX_RING_SIZE 1024 /* RX ring size for Best Effort */ | |
28 | #define NC_TX_RING_SIZE 64 /* TX ring size for Network Control */ | |
29 | #define NC_RX_RING_SIZE 64 /* RX ring size for Network Control */ | |
30 | #define BE_TX_RING_MIN 64 | |
31 | #define BE_RX_RING_MIN 64 | |
32 | #define BE_TX_RING_MAX 1024 | |
33 | #define BE_RX_RING_MAX 2048 | |
34 | ||
35 | #define PKT_BUF_SZ 1538 | |
36 | ||
37 | /* Driver's parameters */ | |
38 | #define RAVB_ALIGN 128 | |
39 | ||
40 | /* Hardware time stamp */ | |
41 | #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */ | |
42 | #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */ | |
43 | ||
44 | #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */ | |
45 | #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */ | |
46 | #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002 | |
47 | #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006 | |
48 | #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */ | |
49 | ||
50 | enum ravb_reg { | |
51 | /* AVB-DMAC registers */ | |
52 | CCC = 0x0000, | |
53 | DBAT = 0x0004, | |
54 | DLR = 0x0008, | |
55 | CSR = 0x000C, | |
56 | CDAR0 = 0x0010, | |
57 | CDAR1 = 0x0014, | |
58 | CDAR2 = 0x0018, | |
59 | CDAR3 = 0x001C, | |
60 | CDAR4 = 0x0020, | |
61 | CDAR5 = 0x0024, | |
62 | CDAR6 = 0x0028, | |
63 | CDAR7 = 0x002C, | |
64 | CDAR8 = 0x0030, | |
65 | CDAR9 = 0x0034, | |
66 | CDAR10 = 0x0038, | |
67 | CDAR11 = 0x003C, | |
68 | CDAR12 = 0x0040, | |
69 | CDAR13 = 0x0044, | |
70 | CDAR14 = 0x0048, | |
71 | CDAR15 = 0x004C, | |
72 | CDAR16 = 0x0050, | |
73 | CDAR17 = 0x0054, | |
74 | CDAR18 = 0x0058, | |
75 | CDAR19 = 0x005C, | |
76 | CDAR20 = 0x0060, | |
77 | CDAR21 = 0x0064, | |
78 | ESR = 0x0088, | |
79 | RCR = 0x0090, | |
80 | RQC0 = 0x0094, | |
81 | RQC1 = 0x0098, | |
82 | RQC2 = 0x009C, | |
83 | RQC3 = 0x00A0, | |
84 | RQC4 = 0x00A4, | |
85 | RPC = 0x00B0, | |
86 | UFCW = 0x00BC, | |
87 | UFCS = 0x00C0, | |
88 | UFCV0 = 0x00C4, | |
89 | UFCV1 = 0x00C8, | |
90 | UFCV2 = 0x00CC, | |
91 | UFCV3 = 0x00D0, | |
92 | UFCV4 = 0x00D4, | |
93 | UFCD0 = 0x00E0, | |
94 | UFCD1 = 0x00E4, | |
95 | UFCD2 = 0x00E8, | |
96 | UFCD3 = 0x00EC, | |
97 | UFCD4 = 0x00F0, | |
98 | SFO = 0x00FC, | |
99 | SFP0 = 0x0100, | |
100 | SFP1 = 0x0104, | |
101 | SFP2 = 0x0108, | |
102 | SFP3 = 0x010C, | |
103 | SFP4 = 0x0110, | |
104 | SFP5 = 0x0114, | |
105 | SFP6 = 0x0118, | |
106 | SFP7 = 0x011C, | |
107 | SFP8 = 0x0120, | |
108 | SFP9 = 0x0124, | |
109 | SFP10 = 0x0128, | |
110 | SFP11 = 0x012C, | |
111 | SFP12 = 0x0130, | |
112 | SFP13 = 0x0134, | |
113 | SFP14 = 0x0138, | |
114 | SFP15 = 0x013C, | |
115 | SFP16 = 0x0140, | |
116 | SFP17 = 0x0144, | |
117 | SFP18 = 0x0148, | |
118 | SFP19 = 0x014C, | |
119 | SFP20 = 0x0150, | |
120 | SFP21 = 0x0154, | |
121 | SFP22 = 0x0158, | |
122 | SFP23 = 0x015C, | |
123 | SFP24 = 0x0160, | |
124 | SFP25 = 0x0164, | |
125 | SFP26 = 0x0168, | |
126 | SFP27 = 0x016C, | |
127 | SFP28 = 0x0170, | |
128 | SFP29 = 0x0174, | |
129 | SFP30 = 0x0178, | |
130 | SFP31 = 0x017C, | |
131 | SFM0 = 0x01C0, | |
132 | SFM1 = 0x01C4, | |
133 | TGC = 0x0300, | |
134 | TCCR = 0x0304, | |
135 | TSR = 0x0308, | |
136 | TFA0 = 0x0310, | |
137 | TFA1 = 0x0314, | |
138 | TFA2 = 0x0318, | |
139 | CIVR0 = 0x0320, | |
140 | CIVR1 = 0x0324, | |
141 | CDVR0 = 0x0328, | |
142 | CDVR1 = 0x032C, | |
143 | CUL0 = 0x0330, | |
144 | CUL1 = 0x0334, | |
145 | CLL0 = 0x0338, | |
146 | CLL1 = 0x033C, | |
147 | DIC = 0x0350, | |
148 | DIS = 0x0354, | |
149 | EIC = 0x0358, | |
150 | EIS = 0x035C, | |
151 | RIC0 = 0x0360, | |
152 | RIS0 = 0x0364, | |
153 | RIC1 = 0x0368, | |
154 | RIS1 = 0x036C, | |
155 | RIC2 = 0x0370, | |
156 | RIS2 = 0x0374, | |
157 | TIC = 0x0378, | |
158 | TIS = 0x037C, | |
159 | ISS = 0x0380, | |
f51bdc23 | 160 | CIE = 0x0384, /* R-Car Gen3 only */ |
c156633f SS |
161 | GCCR = 0x0390, |
162 | GMTT = 0x0394, | |
163 | GPTC = 0x0398, | |
164 | GTI = 0x039C, | |
165 | GTO0 = 0x03A0, | |
166 | GTO1 = 0x03A4, | |
167 | GTO2 = 0x03A8, | |
168 | GIC = 0x03AC, | |
169 | GIS = 0x03B0, | |
170 | GCPT = 0x03B4, /* Undocumented? */ | |
171 | GCT0 = 0x03B8, | |
172 | GCT1 = 0x03BC, | |
173 | GCT2 = 0x03C0, | |
f51bdc23 KM |
174 | GIE = 0x03CC, /* R-Car Gen3 only */ |
175 | GID = 0x03D0, /* R-Car Gen3 only */ | |
176 | DIL = 0x0440, /* R-Car Gen3 only */ | |
177 | RIE0 = 0x0460, /* R-Car Gen3 only */ | |
178 | RID0 = 0x0464, /* R-Car Gen3 only */ | |
179 | RIE2 = 0x0470, /* R-Car Gen3 only */ | |
180 | RID2 = 0x0474, /* R-Car Gen3 only */ | |
181 | TIE = 0x0478, /* R-Car Gen3 only */ | |
182 | TID = 0x047c, /* R-Car Gen3 only */ | |
c156633f SS |
183 | |
184 | /* E-MAC registers */ | |
185 | ECMR = 0x0500, | |
186 | RFLR = 0x0508, | |
187 | ECSR = 0x0510, | |
188 | ECSIPR = 0x0518, | |
189 | PIR = 0x0520, | |
190 | PSR = 0x0528, | |
191 | PIPR = 0x052c, | |
192 | MPR = 0x0558, | |
193 | PFTCR = 0x055c, | |
194 | PFRCR = 0x0560, | |
195 | GECMR = 0x05b0, | |
196 | MAHR = 0x05c0, | |
197 | MALR = 0x05c8, | |
198 | TROCR = 0x0700, /* Undocumented? */ | |
199 | CDCR = 0x0708, /* Undocumented? */ | |
200 | LCCR = 0x0710, /* Undocumented? */ | |
201 | CEFCR = 0x0740, | |
202 | FRECR = 0x0748, | |
203 | TSFRCR = 0x0750, | |
204 | TLFRCR = 0x0758, | |
205 | RFCR = 0x0760, | |
206 | CERCR = 0x0768, /* Undocumented? */ | |
207 | CEECR = 0x0770, /* Undocumented? */ | |
208 | MAFCR = 0x0778, | |
209 | }; | |
210 | ||
211 | ||
212 | /* Register bits of the Ethernet AVB */ | |
213 | /* CCC */ | |
214 | enum CCC_BIT { | |
215 | CCC_OPC = 0x00000003, | |
216 | CCC_OPC_RESET = 0x00000000, | |
217 | CCC_OPC_CONFIG = 0x00000001, | |
218 | CCC_OPC_OPERATION = 0x00000002, | |
f5d7837f | 219 | CCC_GAC = 0x00000080, |
c156633f SS |
220 | CCC_DTSR = 0x00000100, |
221 | CCC_CSEL = 0x00030000, | |
222 | CCC_CSEL_HPB = 0x00010000, | |
223 | CCC_CSEL_ETH_TX = 0x00020000, | |
224 | CCC_CSEL_GMII_REF = 0x00030000, | |
225 | CCC_BOC = 0x00100000, /* Undocumented? */ | |
226 | CCC_LBME = 0x01000000, | |
227 | }; | |
228 | ||
229 | /* CSR */ | |
230 | enum CSR_BIT { | |
231 | CSR_OPS = 0x0000000F, | |
232 | CSR_OPS_RESET = 0x00000001, | |
233 | CSR_OPS_CONFIG = 0x00000002, | |
234 | CSR_OPS_OPERATION = 0x00000004, | |
235 | CSR_OPS_STANDBY = 0x00000008, /* Undocumented? */ | |
236 | CSR_DTS = 0x00000100, | |
237 | CSR_TPO0 = 0x00010000, | |
238 | CSR_TPO1 = 0x00020000, | |
239 | CSR_TPO2 = 0x00040000, | |
240 | CSR_TPO3 = 0x00080000, | |
241 | CSR_RPO = 0x00100000, | |
242 | }; | |
243 | ||
244 | /* ESR */ | |
245 | enum ESR_BIT { | |
246 | ESR_EQN = 0x0000001F, | |
247 | ESR_ET = 0x00000F00, | |
248 | ESR_EIL = 0x00001000, | |
249 | }; | |
250 | ||
251 | /* RCR */ | |
252 | enum RCR_BIT { | |
253 | RCR_EFFS = 0x00000001, | |
254 | RCR_ENCF = 0x00000002, | |
255 | RCR_ESF = 0x0000000C, | |
256 | RCR_ETS0 = 0x00000010, | |
257 | RCR_ETS2 = 0x00000020, | |
258 | RCR_RFCL = 0x1FFF0000, | |
259 | }; | |
260 | ||
261 | /* RQC0/1/2/3/4 */ | |
262 | enum RQC_BIT { | |
263 | RQC_RSM0 = 0x00000003, | |
264 | RQC_UFCC0 = 0x00000030, | |
265 | RQC_RSM1 = 0x00000300, | |
266 | RQC_UFCC1 = 0x00003000, | |
267 | RQC_RSM2 = 0x00030000, | |
268 | RQC_UFCC2 = 0x00300000, | |
269 | RQC_RSM3 = 0x03000000, | |
270 | RQC_UFCC3 = 0x30000000, | |
271 | }; | |
272 | ||
273 | /* RPC */ | |
274 | enum RPC_BIT { | |
275 | RPC_PCNT = 0x00000700, | |
276 | RPC_DCNT = 0x00FF0000, | |
277 | }; | |
278 | ||
279 | /* UFCW */ | |
280 | enum UFCW_BIT { | |
281 | UFCW_WL0 = 0x0000003F, | |
282 | UFCW_WL1 = 0x00003F00, | |
283 | UFCW_WL2 = 0x003F0000, | |
284 | UFCW_WL3 = 0x3F000000, | |
285 | }; | |
286 | ||
287 | /* UFCS */ | |
288 | enum UFCS_BIT { | |
289 | UFCS_SL0 = 0x0000003F, | |
290 | UFCS_SL1 = 0x00003F00, | |
291 | UFCS_SL2 = 0x003F0000, | |
292 | UFCS_SL3 = 0x3F000000, | |
293 | }; | |
294 | ||
295 | /* UFCV0/1/2/3/4 */ | |
296 | enum UFCV_BIT { | |
297 | UFCV_CV0 = 0x0000003F, | |
298 | UFCV_CV1 = 0x00003F00, | |
299 | UFCV_CV2 = 0x003F0000, | |
300 | UFCV_CV3 = 0x3F000000, | |
301 | }; | |
302 | ||
303 | /* UFCD0/1/2/3/4 */ | |
304 | enum UFCD_BIT { | |
305 | UFCD_DV0 = 0x0000003F, | |
306 | UFCD_DV1 = 0x00003F00, | |
307 | UFCD_DV2 = 0x003F0000, | |
308 | UFCD_DV3 = 0x3F000000, | |
309 | }; | |
310 | ||
311 | /* SFO */ | |
312 | enum SFO_BIT { | |
313 | SFO_FPB = 0x0000003F, | |
314 | }; | |
315 | ||
316 | /* RTC */ | |
317 | enum RTC_BIT { | |
318 | RTC_MFL0 = 0x00000FFF, | |
319 | RTC_MFL1 = 0x0FFF0000, | |
320 | }; | |
321 | ||
322 | /* TGC */ | |
323 | enum TGC_BIT { | |
324 | TGC_TSM0 = 0x00000001, | |
325 | TGC_TSM1 = 0x00000002, | |
326 | TGC_TSM2 = 0x00000004, | |
327 | TGC_TSM3 = 0x00000008, | |
328 | TGC_TQP = 0x00000030, | |
329 | TGC_TQP_NONAVB = 0x00000000, | |
330 | TGC_TQP_AVBMODE1 = 0x00000010, | |
331 | TGC_TQP_AVBMODE2 = 0x00000030, | |
332 | TGC_TBD0 = 0x00000300, | |
333 | TGC_TBD1 = 0x00003000, | |
334 | TGC_TBD2 = 0x00030000, | |
335 | TGC_TBD3 = 0x00300000, | |
336 | }; | |
337 | ||
338 | /* TCCR */ | |
339 | enum TCCR_BIT { | |
340 | TCCR_TSRQ0 = 0x00000001, | |
341 | TCCR_TSRQ1 = 0x00000002, | |
342 | TCCR_TSRQ2 = 0x00000004, | |
343 | TCCR_TSRQ3 = 0x00000008, | |
344 | TCCR_TFEN = 0x00000100, | |
345 | TCCR_TFR = 0x00000200, | |
346 | }; | |
347 | ||
348 | /* TSR */ | |
349 | enum TSR_BIT { | |
350 | TSR_CCS0 = 0x00000003, | |
351 | TSR_CCS1 = 0x0000000C, | |
352 | TSR_TFFL = 0x00000700, | |
353 | }; | |
354 | ||
355 | /* TFA2 */ | |
356 | enum TFA2_BIT { | |
357 | TFA2_TSV = 0x0000FFFF, | |
358 | TFA2_TST = 0x03FF0000, | |
359 | }; | |
360 | ||
361 | /* DIC */ | |
362 | enum DIC_BIT { | |
363 | DIC_DPE1 = 0x00000002, | |
364 | DIC_DPE2 = 0x00000004, | |
365 | DIC_DPE3 = 0x00000008, | |
366 | DIC_DPE4 = 0x00000010, | |
367 | DIC_DPE5 = 0x00000020, | |
368 | DIC_DPE6 = 0x00000040, | |
369 | DIC_DPE7 = 0x00000080, | |
370 | DIC_DPE8 = 0x00000100, | |
371 | DIC_DPE9 = 0x00000200, | |
372 | DIC_DPE10 = 0x00000400, | |
373 | DIC_DPE11 = 0x00000800, | |
374 | DIC_DPE12 = 0x00001000, | |
375 | DIC_DPE13 = 0x00002000, | |
376 | DIC_DPE14 = 0x00004000, | |
377 | DIC_DPE15 = 0x00008000, | |
378 | }; | |
379 | ||
380 | /* DIS */ | |
381 | enum DIS_BIT { | |
382 | DIS_DPF1 = 0x00000002, | |
383 | DIS_DPF2 = 0x00000004, | |
384 | DIS_DPF3 = 0x00000008, | |
385 | DIS_DPF4 = 0x00000010, | |
386 | DIS_DPF5 = 0x00000020, | |
387 | DIS_DPF6 = 0x00000040, | |
388 | DIS_DPF7 = 0x00000080, | |
389 | DIS_DPF8 = 0x00000100, | |
390 | DIS_DPF9 = 0x00000200, | |
391 | DIS_DPF10 = 0x00000400, | |
392 | DIS_DPF11 = 0x00000800, | |
393 | DIS_DPF12 = 0x00001000, | |
394 | DIS_DPF13 = 0x00002000, | |
395 | DIS_DPF14 = 0x00004000, | |
396 | DIS_DPF15 = 0x00008000, | |
397 | }; | |
398 | ||
399 | /* EIC */ | |
400 | enum EIC_BIT { | |
401 | EIC_MREE = 0x00000001, | |
402 | EIC_MTEE = 0x00000002, | |
403 | EIC_QEE = 0x00000004, | |
404 | EIC_SEE = 0x00000008, | |
405 | EIC_CLLE0 = 0x00000010, | |
406 | EIC_CLLE1 = 0x00000020, | |
407 | EIC_CULE0 = 0x00000040, | |
408 | EIC_CULE1 = 0x00000080, | |
409 | EIC_TFFE = 0x00000100, | |
410 | }; | |
411 | ||
412 | /* EIS */ | |
413 | enum EIS_BIT { | |
414 | EIS_MREF = 0x00000001, | |
415 | EIS_MTEF = 0x00000002, | |
416 | EIS_QEF = 0x00000004, | |
417 | EIS_SEF = 0x00000008, | |
418 | EIS_CLLF0 = 0x00000010, | |
419 | EIS_CLLF1 = 0x00000020, | |
420 | EIS_CULF0 = 0x00000040, | |
421 | EIS_CULF1 = 0x00000080, | |
422 | EIS_TFFF = 0x00000100, | |
423 | EIS_QFS = 0x00010000, | |
424 | }; | |
425 | ||
426 | /* RIC0 */ | |
427 | enum RIC0_BIT { | |
428 | RIC0_FRE0 = 0x00000001, | |
429 | RIC0_FRE1 = 0x00000002, | |
430 | RIC0_FRE2 = 0x00000004, | |
431 | RIC0_FRE3 = 0x00000008, | |
432 | RIC0_FRE4 = 0x00000010, | |
433 | RIC0_FRE5 = 0x00000020, | |
434 | RIC0_FRE6 = 0x00000040, | |
435 | RIC0_FRE7 = 0x00000080, | |
436 | RIC0_FRE8 = 0x00000100, | |
437 | RIC0_FRE9 = 0x00000200, | |
438 | RIC0_FRE10 = 0x00000400, | |
439 | RIC0_FRE11 = 0x00000800, | |
440 | RIC0_FRE12 = 0x00001000, | |
441 | RIC0_FRE13 = 0x00002000, | |
442 | RIC0_FRE14 = 0x00004000, | |
443 | RIC0_FRE15 = 0x00008000, | |
444 | RIC0_FRE16 = 0x00010000, | |
445 | RIC0_FRE17 = 0x00020000, | |
446 | }; | |
447 | ||
448 | /* RIC0 */ | |
449 | enum RIS0_BIT { | |
450 | RIS0_FRF0 = 0x00000001, | |
451 | RIS0_FRF1 = 0x00000002, | |
452 | RIS0_FRF2 = 0x00000004, | |
453 | RIS0_FRF3 = 0x00000008, | |
454 | RIS0_FRF4 = 0x00000010, | |
455 | RIS0_FRF5 = 0x00000020, | |
456 | RIS0_FRF6 = 0x00000040, | |
457 | RIS0_FRF7 = 0x00000080, | |
458 | RIS0_FRF8 = 0x00000100, | |
459 | RIS0_FRF9 = 0x00000200, | |
460 | RIS0_FRF10 = 0x00000400, | |
461 | RIS0_FRF11 = 0x00000800, | |
462 | RIS0_FRF12 = 0x00001000, | |
463 | RIS0_FRF13 = 0x00002000, | |
464 | RIS0_FRF14 = 0x00004000, | |
465 | RIS0_FRF15 = 0x00008000, | |
466 | RIS0_FRF16 = 0x00010000, | |
467 | RIS0_FRF17 = 0x00020000, | |
468 | }; | |
469 | ||
470 | /* RIC1 */ | |
471 | enum RIC1_BIT { | |
472 | RIC1_RFWE = 0x80000000, | |
473 | }; | |
474 | ||
475 | /* RIS1 */ | |
476 | enum RIS1_BIT { | |
477 | RIS1_RFWF = 0x80000000, | |
478 | }; | |
479 | ||
480 | /* RIC2 */ | |
481 | enum RIC2_BIT { | |
482 | RIC2_QFE0 = 0x00000001, | |
483 | RIC2_QFE1 = 0x00000002, | |
484 | RIC2_QFE2 = 0x00000004, | |
485 | RIC2_QFE3 = 0x00000008, | |
486 | RIC2_QFE4 = 0x00000010, | |
487 | RIC2_QFE5 = 0x00000020, | |
488 | RIC2_QFE6 = 0x00000040, | |
489 | RIC2_QFE7 = 0x00000080, | |
490 | RIC2_QFE8 = 0x00000100, | |
491 | RIC2_QFE9 = 0x00000200, | |
492 | RIC2_QFE10 = 0x00000400, | |
493 | RIC2_QFE11 = 0x00000800, | |
494 | RIC2_QFE12 = 0x00001000, | |
495 | RIC2_QFE13 = 0x00002000, | |
496 | RIC2_QFE14 = 0x00004000, | |
497 | RIC2_QFE15 = 0x00008000, | |
498 | RIC2_QFE16 = 0x00010000, | |
499 | RIC2_QFE17 = 0x00020000, | |
500 | RIC2_RFFE = 0x80000000, | |
501 | }; | |
502 | ||
503 | /* RIS2 */ | |
504 | enum RIS2_BIT { | |
505 | RIS2_QFF0 = 0x00000001, | |
506 | RIS2_QFF1 = 0x00000002, | |
507 | RIS2_QFF2 = 0x00000004, | |
508 | RIS2_QFF3 = 0x00000008, | |
509 | RIS2_QFF4 = 0x00000010, | |
510 | RIS2_QFF5 = 0x00000020, | |
511 | RIS2_QFF6 = 0x00000040, | |
512 | RIS2_QFF7 = 0x00000080, | |
513 | RIS2_QFF8 = 0x00000100, | |
514 | RIS2_QFF9 = 0x00000200, | |
515 | RIS2_QFF10 = 0x00000400, | |
516 | RIS2_QFF11 = 0x00000800, | |
517 | RIS2_QFF12 = 0x00001000, | |
518 | RIS2_QFF13 = 0x00002000, | |
519 | RIS2_QFF14 = 0x00004000, | |
520 | RIS2_QFF15 = 0x00008000, | |
521 | RIS2_QFF16 = 0x00010000, | |
522 | RIS2_QFF17 = 0x00020000, | |
523 | RIS2_RFFF = 0x80000000, | |
524 | }; | |
525 | ||
526 | /* TIC */ | |
527 | enum TIC_BIT { | |
528 | TIC_FTE0 = 0x00000001, /* Undocumented? */ | |
529 | TIC_FTE1 = 0x00000002, /* Undocumented? */ | |
530 | TIC_TFUE = 0x00000100, | |
531 | TIC_TFWE = 0x00000200, | |
532 | }; | |
533 | ||
534 | /* TIS */ | |
535 | enum TIS_BIT { | |
536 | TIS_FTF0 = 0x00000001, /* Undocumented? */ | |
537 | TIS_FTF1 = 0x00000002, /* Undocumented? */ | |
538 | TIS_TFUF = 0x00000100, | |
539 | TIS_TFWF = 0x00000200, | |
540 | }; | |
541 | ||
542 | /* ISS */ | |
543 | enum ISS_BIT { | |
544 | ISS_FRS = 0x00000001, /* Undocumented? */ | |
545 | ISS_FTS = 0x00000004, /* Undocumented? */ | |
546 | ISS_ES = 0x00000040, | |
547 | ISS_MS = 0x00000080, | |
548 | ISS_TFUS = 0x00000100, | |
549 | ISS_TFWS = 0x00000200, | |
550 | ISS_RFWS = 0x00001000, | |
551 | ISS_CGIS = 0x00002000, | |
552 | ISS_DPS1 = 0x00020000, | |
553 | ISS_DPS2 = 0x00040000, | |
554 | ISS_DPS3 = 0x00080000, | |
555 | ISS_DPS4 = 0x00100000, | |
556 | ISS_DPS5 = 0x00200000, | |
557 | ISS_DPS6 = 0x00400000, | |
558 | ISS_DPS7 = 0x00800000, | |
559 | ISS_DPS8 = 0x01000000, | |
560 | ISS_DPS9 = 0x02000000, | |
561 | ISS_DPS10 = 0x04000000, | |
562 | ISS_DPS11 = 0x08000000, | |
563 | ISS_DPS12 = 0x10000000, | |
564 | ISS_DPS13 = 0x20000000, | |
565 | ISS_DPS14 = 0x40000000, | |
566 | ISS_DPS15 = 0x80000000, | |
567 | }; | |
568 | ||
f51bdc23 KM |
569 | /* CIE (R-Car Gen3 only) */ |
570 | enum CIE_BIT { | |
571 | CIE_CRIE = 0x00000001, | |
572 | CIE_CTIE = 0x00000100, | |
573 | CIE_RQFM = 0x00010000, | |
574 | CIE_CL0M = 0x00020000, | |
575 | CIE_RFWL = 0x00040000, | |
576 | CIE_RFFL = 0x00080000, | |
577 | }; | |
578 | ||
c156633f SS |
579 | /* GCCR */ |
580 | enum GCCR_BIT { | |
581 | GCCR_TCR = 0x00000003, | |
582 | GCCR_TCR_NOREQ = 0x00000000, /* No request */ | |
583 | GCCR_TCR_RESET = 0x00000001, /* gPTP/AVTP presentation timer reset */ | |
584 | GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */ | |
585 | GCCR_LTO = 0x00000004, | |
586 | GCCR_LTI = 0x00000008, | |
587 | GCCR_LPTC = 0x00000010, | |
588 | GCCR_LMTT = 0x00000020, | |
589 | GCCR_TCSS = 0x00000300, | |
590 | GCCR_TCSS_GPTP = 0x00000000, /* gPTP timer value */ | |
591 | GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */ | |
592 | GCCR_TCSS_AVTP = 0x00000200, /* AVTP presentation time value */ | |
593 | }; | |
594 | ||
595 | /* GTI */ | |
596 | enum GTI_BIT { | |
597 | GTI_TIV = 0x0FFFFFFF, | |
598 | }; | |
599 | ||
b3d39a88 SH |
600 | #define GTI_TIV_MAX GTI_TIV |
601 | #define GTI_TIV_MIN 0x20 | |
602 | ||
c156633f SS |
603 | /* GIC */ |
604 | enum GIC_BIT { | |
605 | GIC_PTCE = 0x00000001, /* Undocumented? */ | |
606 | GIC_PTME = 0x00000004, | |
607 | }; | |
608 | ||
609 | /* GIS */ | |
610 | enum GIS_BIT { | |
611 | GIS_PTCF = 0x00000001, /* Undocumented? */ | |
612 | GIS_PTMF = 0x00000004, | |
613 | }; | |
614 | ||
f51bdc23 KM |
615 | /* GIE (R-Car Gen3 only) */ |
616 | enum GIE_BIT { | |
617 | GIE_PTCS = 0x00000001, | |
618 | GIE_PTOS = 0x00000002, | |
619 | GIE_PTMS0 = 0x00000004, | |
620 | GIE_PTMS1 = 0x00000008, | |
621 | GIE_PTMS2 = 0x00000010, | |
622 | GIE_PTMS3 = 0x00000020, | |
623 | GIE_PTMS4 = 0x00000040, | |
624 | GIE_PTMS5 = 0x00000080, | |
625 | GIE_PTMS6 = 0x00000100, | |
626 | GIE_PTMS7 = 0x00000200, | |
627 | GIE_ATCS0 = 0x00010000, | |
628 | GIE_ATCS1 = 0x00020000, | |
629 | GIE_ATCS2 = 0x00040000, | |
630 | GIE_ATCS3 = 0x00080000, | |
631 | GIE_ATCS4 = 0x00100000, | |
632 | GIE_ATCS5 = 0x00200000, | |
633 | GIE_ATCS6 = 0x00400000, | |
634 | GIE_ATCS7 = 0x00800000, | |
635 | GIE_ATCS8 = 0x01000000, | |
636 | GIE_ATCS9 = 0x02000000, | |
637 | GIE_ATCS10 = 0x04000000, | |
638 | GIE_ATCS11 = 0x08000000, | |
639 | GIE_ATCS12 = 0x10000000, | |
640 | GIE_ATCS13 = 0x20000000, | |
641 | GIE_ATCS14 = 0x40000000, | |
642 | GIE_ATCS15 = 0x80000000, | |
643 | }; | |
644 | ||
645 | /* GID (R-Car Gen3 only) */ | |
646 | enum GID_BIT { | |
647 | GID_PTCD = 0x00000001, | |
648 | GID_PTOD = 0x00000002, | |
649 | GID_PTMD0 = 0x00000004, | |
650 | GID_PTMD1 = 0x00000008, | |
651 | GID_PTMD2 = 0x00000010, | |
652 | GID_PTMD3 = 0x00000020, | |
653 | GID_PTMD4 = 0x00000040, | |
654 | GID_PTMD5 = 0x00000080, | |
655 | GID_PTMD6 = 0x00000100, | |
656 | GID_PTMD7 = 0x00000200, | |
657 | GID_ATCD0 = 0x00010000, | |
658 | GID_ATCD1 = 0x00020000, | |
659 | GID_ATCD2 = 0x00040000, | |
660 | GID_ATCD3 = 0x00080000, | |
661 | GID_ATCD4 = 0x00100000, | |
662 | GID_ATCD5 = 0x00200000, | |
663 | GID_ATCD6 = 0x00400000, | |
664 | GID_ATCD7 = 0x00800000, | |
665 | GID_ATCD8 = 0x01000000, | |
666 | GID_ATCD9 = 0x02000000, | |
667 | GID_ATCD10 = 0x04000000, | |
668 | GID_ATCD11 = 0x08000000, | |
669 | GID_ATCD12 = 0x10000000, | |
670 | GID_ATCD13 = 0x20000000, | |
671 | GID_ATCD14 = 0x40000000, | |
672 | GID_ATCD15 = 0x80000000, | |
673 | }; | |
674 | ||
675 | /* RIE0 (R-Car Gen3 only) */ | |
676 | enum RIE0_BIT { | |
677 | RIE0_FRS0 = 0x00000001, | |
678 | RIE0_FRS1 = 0x00000002, | |
679 | RIE0_FRS2 = 0x00000004, | |
680 | RIE0_FRS3 = 0x00000008, | |
681 | RIE0_FRS4 = 0x00000010, | |
682 | RIE0_FRS5 = 0x00000020, | |
683 | RIE0_FRS6 = 0x00000040, | |
684 | RIE0_FRS7 = 0x00000080, | |
685 | RIE0_FRS8 = 0x00000100, | |
686 | RIE0_FRS9 = 0x00000200, | |
687 | RIE0_FRS10 = 0x00000400, | |
688 | RIE0_FRS11 = 0x00000800, | |
689 | RIE0_FRS12 = 0x00001000, | |
690 | RIE0_FRS13 = 0x00002000, | |
691 | RIE0_FRS14 = 0x00004000, | |
692 | RIE0_FRS15 = 0x00008000, | |
693 | RIE0_FRS16 = 0x00010000, | |
694 | RIE0_FRS17 = 0x00020000, | |
695 | }; | |
696 | ||
697 | /* RID0 (R-Car Gen3 only) */ | |
698 | enum RID0_BIT { | |
699 | RID0_FRD0 = 0x00000001, | |
700 | RID0_FRD1 = 0x00000002, | |
701 | RID0_FRD2 = 0x00000004, | |
702 | RID0_FRD3 = 0x00000008, | |
703 | RID0_FRD4 = 0x00000010, | |
704 | RID0_FRD5 = 0x00000020, | |
705 | RID0_FRD6 = 0x00000040, | |
706 | RID0_FRD7 = 0x00000080, | |
707 | RID0_FRD8 = 0x00000100, | |
708 | RID0_FRD9 = 0x00000200, | |
709 | RID0_FRD10 = 0x00000400, | |
710 | RID0_FRD11 = 0x00000800, | |
711 | RID0_FRD12 = 0x00001000, | |
712 | RID0_FRD13 = 0x00002000, | |
713 | RID0_FRD14 = 0x00004000, | |
714 | RID0_FRD15 = 0x00008000, | |
715 | RID0_FRD16 = 0x00010000, | |
716 | RID0_FRD17 = 0x00020000, | |
717 | }; | |
718 | ||
719 | /* RIE2 (R-Car Gen3 only) */ | |
720 | enum RIE2_BIT { | |
721 | RIE2_QFS0 = 0x00000001, | |
722 | RIE2_QFS1 = 0x00000002, | |
723 | RIE2_QFS2 = 0x00000004, | |
724 | RIE2_QFS3 = 0x00000008, | |
725 | RIE2_QFS4 = 0x00000010, | |
726 | RIE2_QFS5 = 0x00000020, | |
727 | RIE2_QFS6 = 0x00000040, | |
728 | RIE2_QFS7 = 0x00000080, | |
729 | RIE2_QFS8 = 0x00000100, | |
730 | RIE2_QFS9 = 0x00000200, | |
731 | RIE2_QFS10 = 0x00000400, | |
732 | RIE2_QFS11 = 0x00000800, | |
733 | RIE2_QFS12 = 0x00001000, | |
734 | RIE2_QFS13 = 0x00002000, | |
735 | RIE2_QFS14 = 0x00004000, | |
736 | RIE2_QFS15 = 0x00008000, | |
737 | RIE2_QFS16 = 0x00010000, | |
738 | RIE2_QFS17 = 0x00020000, | |
739 | RIE2_RFFS = 0x80000000, | |
740 | }; | |
741 | ||
742 | /* RID2 (R-Car Gen3 only) */ | |
743 | enum RID2_BIT { | |
744 | RID2_QFD0 = 0x00000001, | |
745 | RID2_QFD1 = 0x00000002, | |
746 | RID2_QFD2 = 0x00000004, | |
747 | RID2_QFD3 = 0x00000008, | |
748 | RID2_QFD4 = 0x00000010, | |
749 | RID2_QFD5 = 0x00000020, | |
750 | RID2_QFD6 = 0x00000040, | |
751 | RID2_QFD7 = 0x00000080, | |
752 | RID2_QFD8 = 0x00000100, | |
753 | RID2_QFD9 = 0x00000200, | |
754 | RID2_QFD10 = 0x00000400, | |
755 | RID2_QFD11 = 0x00000800, | |
756 | RID2_QFD12 = 0x00001000, | |
757 | RID2_QFD13 = 0x00002000, | |
758 | RID2_QFD14 = 0x00004000, | |
759 | RID2_QFD15 = 0x00008000, | |
760 | RID2_QFD16 = 0x00010000, | |
761 | RID2_QFD17 = 0x00020000, | |
762 | RID2_RFFD = 0x80000000, | |
763 | }; | |
764 | ||
765 | /* TIE (R-Car Gen3 only) */ | |
766 | enum TIE_BIT { | |
767 | TIE_FTS0 = 0x00000001, | |
768 | TIE_FTS1 = 0x00000002, | |
769 | TIE_FTS2 = 0x00000004, | |
770 | TIE_FTS3 = 0x00000008, | |
771 | TIE_TFUS = 0x00000100, | |
772 | TIE_TFWS = 0x00000200, | |
773 | TIE_MFUS = 0x00000400, | |
774 | TIE_MFWS = 0x00000800, | |
775 | TIE_TDPS0 = 0x00010000, | |
776 | TIE_TDPS1 = 0x00020000, | |
777 | TIE_TDPS2 = 0x00040000, | |
778 | TIE_TDPS3 = 0x00080000, | |
779 | }; | |
780 | ||
781 | /* TID (R-Car Gen3 only) */ | |
782 | enum TID_BIT { | |
783 | TID_FTD0 = 0x00000001, | |
784 | TID_FTD1 = 0x00000002, | |
785 | TID_FTD2 = 0x00000004, | |
786 | TID_FTD3 = 0x00000008, | |
787 | TID_TFUD = 0x00000100, | |
788 | TID_TFWD = 0x00000200, | |
789 | TID_MFUD = 0x00000400, | |
790 | TID_MFWD = 0x00000800, | |
791 | TID_TDPD0 = 0x00010000, | |
792 | TID_TDPD1 = 0x00020000, | |
793 | TID_TDPD2 = 0x00040000, | |
794 | TID_TDPD3 = 0x00080000, | |
795 | }; | |
796 | ||
c156633f SS |
797 | /* ECMR */ |
798 | enum ECMR_BIT { | |
799 | ECMR_PRM = 0x00000001, | |
800 | ECMR_DM = 0x00000002, | |
801 | ECMR_TE = 0x00000020, | |
802 | ECMR_RE = 0x00000040, | |
803 | ECMR_MPDE = 0x00000200, | |
804 | ECMR_TXF = 0x00010000, /* Undocumented? */ | |
805 | ECMR_RXF = 0x00020000, | |
806 | ECMR_PFR = 0x00040000, | |
807 | ECMR_ZPF = 0x00080000, /* Undocumented? */ | |
808 | ECMR_RZPF = 0x00100000, | |
809 | ECMR_DPAD = 0x00200000, | |
810 | ECMR_RCSC = 0x00800000, | |
811 | ECMR_TRCCM = 0x04000000, | |
812 | }; | |
813 | ||
814 | /* ECSR */ | |
815 | enum ECSR_BIT { | |
816 | ECSR_ICD = 0x00000001, | |
817 | ECSR_MPD = 0x00000002, | |
818 | ECSR_LCHNG = 0x00000004, | |
819 | ECSR_PHYI = 0x00000008, | |
820 | }; | |
821 | ||
822 | /* ECSIPR */ | |
823 | enum ECSIPR_BIT { | |
824 | ECSIPR_ICDIP = 0x00000001, | |
825 | ECSIPR_MPDIP = 0x00000002, | |
826 | ECSIPR_LCHNGIP = 0x00000004, /* Undocumented? */ | |
827 | }; | |
828 | ||
829 | /* PIR */ | |
830 | enum PIR_BIT { | |
831 | PIR_MDC = 0x00000001, | |
832 | PIR_MMD = 0x00000002, | |
833 | PIR_MDO = 0x00000004, | |
834 | PIR_MDI = 0x00000008, | |
835 | }; | |
836 | ||
837 | /* PSR */ | |
838 | enum PSR_BIT { | |
839 | PSR_LMON = 0x00000001, | |
840 | }; | |
841 | ||
842 | /* PIPR */ | |
843 | enum PIPR_BIT { | |
844 | PIPR_PHYIP = 0x00000001, | |
845 | }; | |
846 | ||
847 | /* MPR */ | |
848 | enum MPR_BIT { | |
849 | MPR_MP = 0x0000ffff, | |
850 | }; | |
851 | ||
852 | /* GECMR */ | |
853 | enum GECMR_BIT { | |
854 | GECMR_SPEED = 0x00000001, | |
855 | GECMR_SPEED_100 = 0x00000000, | |
856 | GECMR_SPEED_1000 = 0x00000001, | |
857 | }; | |
858 | ||
859 | /* The Ethernet AVB descriptor definitions. */ | |
860 | struct ravb_desc { | |
861 | __le16 ds; /* Descriptor size */ | |
862 | u8 cc; /* Content control MSBs (reserved) */ | |
863 | u8 die_dt; /* Descriptor interrupt enable and type */ | |
864 | __le32 dptr; /* Descriptor pointer */ | |
865 | }; | |
866 | ||
2f45d190 SS |
867 | #define DPTR_ALIGN 4 /* Required descriptor pointer alignment */ |
868 | ||
c156633f SS |
869 | enum DIE_DT { |
870 | /* Frame data */ | |
871 | DT_FMID = 0x40, | |
872 | DT_FSTART = 0x50, | |
873 | DT_FEND = 0x60, | |
874 | DT_FSINGLE = 0x70, | |
875 | /* Chain control */ | |
876 | DT_LINK = 0x80, | |
877 | DT_LINKFIX = 0x90, | |
878 | DT_EOS = 0xa0, | |
879 | /* HW/SW arbitration */ | |
880 | DT_FEMPTY = 0xc0, | |
881 | DT_FEMPTY_IS = 0xd0, | |
882 | DT_FEMPTY_IC = 0xe0, | |
883 | DT_FEMPTY_ND = 0xf0, | |
884 | DT_LEMPTY = 0x20, | |
885 | DT_EEMPTY = 0x30, | |
886 | }; | |
887 | ||
888 | struct ravb_rx_desc { | |
889 | __le16 ds_cc; /* Descriptor size and content control LSBs */ | |
890 | u8 msc; /* MAC status code */ | |
891 | u8 die_dt; /* Descriptor interrupt enable and type */ | |
892 | __le32 dptr; /* Descpriptor pointer */ | |
893 | }; | |
894 | ||
895 | struct ravb_ex_rx_desc { | |
896 | __le16 ds_cc; /* Descriptor size and content control lower bits */ | |
897 | u8 msc; /* MAC status code */ | |
898 | u8 die_dt; /* Descriptor interrupt enable and type */ | |
899 | __le32 dptr; /* Descpriptor pointer */ | |
900 | __le32 ts_n; /* Timestampe nsec */ | |
901 | __le32 ts_sl; /* Timestamp low */ | |
902 | __le16 ts_sh; /* Timestamp high */ | |
903 | __le16 res; /* Reserved bits */ | |
904 | }; | |
905 | ||
906 | enum RX_DS_CC_BIT { | |
907 | RX_DS = 0x0fff, /* Data size */ | |
908 | RX_TR = 0x1000, /* Truncation indication */ | |
909 | RX_EI = 0x2000, /* Error indication */ | |
910 | RX_PS = 0xc000, /* Padding selection */ | |
911 | }; | |
912 | ||
913 | /* E-MAC status code */ | |
914 | enum MSC_BIT { | |
915 | MSC_CRC = 0x01, /* Frame CRC error */ | |
916 | MSC_RFE = 0x02, /* Frame reception error (flagged by PHY) */ | |
917 | MSC_RTSF = 0x04, /* Frame length error (frame too short) */ | |
918 | MSC_RTLF = 0x08, /* Frame length error (frame too long) */ | |
919 | MSC_FRE = 0x10, /* Fraction error (not a multiple of 8 bits) */ | |
920 | MSC_CRL = 0x20, /* Carrier lost */ | |
921 | MSC_CEEF = 0x40, /* Carrier extension error */ | |
922 | MSC_MC = 0x80, /* Multicast frame reception */ | |
923 | }; | |
924 | ||
925 | struct ravb_tx_desc { | |
926 | __le16 ds_tagl; /* Descriptor size and frame tag LSBs */ | |
927 | u8 tagh_tsr; /* Frame tag MSBs and timestamp storage request bit */ | |
928 | u8 die_dt; /* Descriptor interrupt enable and type */ | |
929 | __le32 dptr; /* Descpriptor pointer */ | |
930 | }; | |
931 | ||
932 | enum TX_DS_TAGL_BIT { | |
933 | TX_DS = 0x0fff, /* Data size */ | |
934 | TX_TAGL = 0xf000, /* Frame tag LSBs */ | |
935 | }; | |
936 | ||
937 | enum TX_TAGH_TSR_BIT { | |
938 | TX_TAGH = 0x3f, /* Frame tag MSBs */ | |
939 | TX_TSR = 0x40, /* Timestamp storage request */ | |
940 | }; | |
941 | enum RAVB_QUEUE { | |
942 | RAVB_BE = 0, /* Best Effort Queue */ | |
943 | RAVB_NC, /* Network Control Queue */ | |
944 | }; | |
945 | ||
946 | #define DBAT_ENTRY_NUM 22 | |
947 | #define RX_QUEUE_OFFSET 4 | |
948 | #define NUM_RX_QUEUE 2 | |
949 | #define NUM_TX_QUEUE 2 | |
2f45d190 | 950 | #define NUM_TX_DESC 2 /* TX descriptors per packet */ |
c156633f SS |
951 | |
952 | struct ravb_tstamp_skb { | |
953 | struct list_head list; | |
954 | struct sk_buff *skb; | |
955 | u16 tag; | |
956 | }; | |
957 | ||
a0d2f206 SS |
958 | struct ravb_ptp_perout { |
959 | u32 target; | |
960 | u32 period; | |
961 | }; | |
962 | ||
963 | #define N_EXT_TS 1 | |
964 | #define N_PER_OUT 1 | |
965 | ||
966 | struct ravb_ptp { | |
967 | struct ptp_clock *clock; | |
968 | struct ptp_clock_info info; | |
969 | u32 default_addend; | |
970 | u32 current_addend; | |
971 | int extts[N_EXT_TS]; | |
972 | struct ravb_ptp_perout perout[N_PER_OUT]; | |
973 | }; | |
974 | ||
22d4df8f KM |
975 | enum ravb_chip_id { |
976 | RCAR_GEN2, | |
977 | RCAR_GEN3, | |
978 | }; | |
979 | ||
c156633f SS |
980 | struct ravb_private { |
981 | struct net_device *ndev; | |
982 | struct platform_device *pdev; | |
983 | void __iomem *addr; | |
984 | struct mdiobb_ctrl mdiobb; | |
985 | u32 num_rx_ring[NUM_RX_QUEUE]; | |
986 | u32 num_tx_ring[NUM_TX_QUEUE]; | |
987 | u32 desc_bat_size; | |
988 | dma_addr_t desc_bat_dma; | |
989 | struct ravb_desc *desc_bat; | |
990 | dma_addr_t rx_desc_dma[NUM_RX_QUEUE]; | |
991 | dma_addr_t tx_desc_dma[NUM_TX_QUEUE]; | |
992 | struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE]; | |
993 | struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE]; | |
2f45d190 | 994 | void *tx_align[NUM_TX_QUEUE]; |
c156633f SS |
995 | struct sk_buff **rx_skb[NUM_RX_QUEUE]; |
996 | struct sk_buff **tx_skb[NUM_TX_QUEUE]; | |
c156633f SS |
997 | u32 rx_over_errors; |
998 | u32 rx_fifo_errors; | |
999 | struct net_device_stats stats[NUM_RX_QUEUE]; | |
1000 | u32 tstamp_tx_ctrl; | |
1001 | u32 tstamp_rx_ctrl; | |
1002 | struct list_head ts_skb_list; | |
1003 | u32 ts_skb_tag; | |
a0d2f206 | 1004 | struct ravb_ptp ptp; |
c156633f SS |
1005 | spinlock_t lock; /* Register access lock */ |
1006 | u32 cur_rx[NUM_RX_QUEUE]; /* Consumer ring indices */ | |
1007 | u32 dirty_rx[NUM_RX_QUEUE]; /* Producer ring indices */ | |
1008 | u32 cur_tx[NUM_TX_QUEUE]; | |
1009 | u32 dirty_tx[NUM_TX_QUEUE]; | |
1010 | struct napi_struct napi[NUM_RX_QUEUE]; | |
1011 | struct work_struct work; | |
1012 | /* MII transceiver section. */ | |
1013 | struct mii_bus *mii_bus; /* MDIO bus control */ | |
c156633f SS |
1014 | int link; |
1015 | phy_interface_t phy_interface; | |
1016 | int msg_enable; | |
1017 | int speed; | |
1018 | int duplex; | |
22d4df8f KM |
1019 | int emac_irq; |
1020 | enum ravb_chip_id chip_id; | |
f51bdc23 KM |
1021 | int rx_irqs[NUM_RX_QUEUE]; |
1022 | int tx_irqs[NUM_TX_QUEUE]; | |
c156633f SS |
1023 | |
1024 | unsigned no_avb_link:1; | |
1025 | unsigned avb_link_active_low:1; | |
1026 | }; | |
1027 | ||
1028 | static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg) | |
1029 | { | |
1030 | struct ravb_private *priv = netdev_priv(ndev); | |
1031 | ||
1032 | return ioread32(priv->addr + reg); | |
1033 | } | |
1034 | ||
1035 | static inline void ravb_write(struct net_device *ndev, u32 data, | |
1036 | enum ravb_reg reg) | |
1037 | { | |
1038 | struct ravb_private *priv = netdev_priv(ndev); | |
1039 | ||
1040 | iowrite32(data, priv->addr + reg); | |
1041 | } | |
1042 | ||
568b3ce7 SS |
1043 | void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, |
1044 | u32 set); | |
a0d2f206 SS |
1045 | int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value); |
1046 | ||
d0988a5f | 1047 | void ravb_ptp_interrupt(struct net_device *ndev); |
a0d2f206 SS |
1048 | void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev); |
1049 | void ravb_ptp_stop(struct net_device *ndev); | |
1050 | ||
c156633f | 1051 | #endif /* #ifndef __RAVB_H__ */ |