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Merge branches 'acpi-soc', 'acpi-misc', 'acpi-pci' and 'device-properties'
[deliverable/linux.git] / drivers / net / ethernet / renesas / ravb_main.c
CommitLineData
c156633f
SS		 1/* Renesas Ethernet AVB device driver
2 *
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14#include <linux/cache.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/etherdevice.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/net_tstamp.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_irq.h>
29#include <linux/of_mdio.h>
30#include <linux/of_net.h>
c156633f
SS		 31#include <linux/pm_runtime.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
b3d39a88
SH		 35#include <asm/div64.h>
36
c156633f
SS		 37#include "ravb.h"
38
39#define RAVB_DEF_MSG_ENABLE \
40 (NETIF_MSG_LINK | \
41 NETIF_MSG_TIMER | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
a0d2f206 45int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
c156633f
SS		 46{
47 int i;
48
49 for (i = 0; i < 10000; i++) {
50 if ((ravb_read(ndev, reg) & mask) == value)
51 return 0;
52 udelay(10);
53 }
54 return -ETIMEDOUT;
55}
56
57static int ravb_config(struct net_device *ndev)
58{
59 int error;
60
61 /* Set config mode */
62 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
63 CCC);
64 /* Check if the operating mode is changed to the config mode */
65 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
66 if (error)
67 netdev_err(ndev, "failed to switch device to config mode\n");
68
69 return error;
70}
71
72static void ravb_set_duplex(struct net_device *ndev)
73{
74 struct ravb_private *priv = netdev_priv(ndev);
75 u32 ecmr = ravb_read(ndev, ECMR);
76
77 if (priv->duplex) /* Full */
78 ecmr |= ECMR_DM;
79 else /* Half */
80 ecmr &= ~ECMR_DM;
81 ravb_write(ndev, ecmr, ECMR);
82}
83
84static void ravb_set_rate(struct net_device *ndev)
85{
86 struct ravb_private *priv = netdev_priv(ndev);
87
88 switch (priv->speed) {
89 case 100: /* 100BASE */
90 ravb_write(ndev, GECMR_SPEED_100, GECMR);
91 break;
92 case 1000: /* 1000BASE */
93 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
94 break;
95 default:
96 break;
97 }
98}
99
100static void ravb_set_buffer_align(struct sk_buff *skb)
101{
102 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
103
104 if (reserve)
105 skb_reserve(skb, RAVB_ALIGN - reserve);
106}
107
108/* Get MAC address from the MAC address registers
109 *
110 * Ethernet AVB device doesn't have ROM for MAC address.
111 * This function gets the MAC address that was used by a bootloader.
112 */
113static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
114{
115 if (mac) {
116 ether_addr_copy(ndev->dev_addr, mac);
117 } else {
d9660638
SS		 118 u32 mahr = ravb_read(ndev, MAHR);
119 u32 malr = ravb_read(ndev, MALR);
120
121 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
122 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
123 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
124 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
125 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
126 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
c156633f
SS		 127 }
128}
129
130static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
131{
132 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
133 mdiobb);
134 u32 pir = ravb_read(priv->ndev, PIR);
135
136 if (set)
137 pir |= mask;
138 else
139 pir &= ~mask;
140 ravb_write(priv->ndev, pir, PIR);
141}
142
143/* MDC pin control */
144static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
145{
146 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
147}
148
149/* Data I/O pin control */
150static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
151{
152 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
153}
154
155/* Set data bit */
156static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
157{
158 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
159}
160
161/* Get data bit */
162static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
163{
164 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
165 mdiobb);
166
167 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
168}
169
170/* MDIO bus control struct */
171static struct mdiobb_ops bb_ops = {
172 .owner = THIS_MODULE,
173 .set_mdc = ravb_set_mdc,
174 .set_mdio_dir = ravb_set_mdio_dir,
175 .set_mdio_data = ravb_set_mdio_data,
176 .get_mdio_data = ravb_get_mdio_data,
177};
178
179/* Free skb's and DMA buffers for Ethernet AVB */
180static void ravb_ring_free(struct net_device *ndev, int q)
181{
182 struct ravb_private *priv = netdev_priv(ndev);
183 int ring_size;
184 int i;
185
186 /* Free RX skb ringbuffer */
187 if (priv->rx_skb[q]) {
188 for (i = 0; i < priv->num_rx_ring[q]; i++)
189 dev_kfree_skb(priv->rx_skb[q][i]);
190 }
191 kfree(priv->rx_skb[q]);
192 priv->rx_skb[q] = NULL;
193
194 /* Free TX skb ringbuffer */
195 if (priv->tx_skb[q]) {
196 for (i = 0; i < priv->num_tx_ring[q]; i++)
197 dev_kfree_skb(priv->tx_skb[q][i]);
198 }
199 kfree(priv->tx_skb[q]);
200 priv->tx_skb[q] = NULL;
201
202 /* Free aligned TX buffers */
2f45d190
SS		 203 kfree(priv->tx_align[q]);
204 priv->tx_align[q] = NULL;
c156633f
SS		 205
206 if (priv->rx_ring[q]) {
207 ring_size = sizeof(struct ravb_ex_rx_desc) *
208 (priv->num_rx_ring[q] + 1);
e2dbb33a 209 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
c156633f
SS		 210 priv->rx_desc_dma[q]);
211 priv->rx_ring[q] = NULL;
212 }
213
214 if (priv->tx_ring[q]) {
215 ring_size = sizeof(struct ravb_tx_desc) *
2f45d190 216 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
e2dbb33a 217 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
c156633f
SS		 218 priv->tx_desc_dma[q]);
219 priv->tx_ring[q] = NULL;
220 }
221}
222
223/* Format skb and descriptor buffer for Ethernet AVB */
224static void ravb_ring_format(struct net_device *ndev, int q)
225{
226 struct ravb_private *priv = netdev_priv(ndev);
aad0d51e
SS		 227 struct ravb_ex_rx_desc *rx_desc;
228 struct ravb_tx_desc *tx_desc;
229 struct ravb_desc *desc;
c156633f 230 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
2f45d190
SS		 231 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
232 NUM_TX_DESC;
c156633f 233 dma_addr_t dma_addr;
c156633f
SS		 234 int i;
235
236 priv->cur_rx[q] = 0;
237 priv->cur_tx[q] = 0;
238 priv->dirty_rx[q] = 0;
239 priv->dirty_tx[q] = 0;
240
241 memset(priv->rx_ring[q], 0, rx_ring_size);
242 /* Build RX ring buffer */
243 for (i = 0; i < priv->num_rx_ring[q]; i++) {
c156633f
SS		 244 /* RX descriptor */
245 rx_desc = &priv->rx_ring[q][i];
246 /* The size of the buffer should be on 16-byte boundary. */
247 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
e2dbb33a 248 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
c156633f
SS		 249 ALIGN(PKT_BUF_SZ, 16),
250 DMA_FROM_DEVICE);
d8b48911
SS		 251 /* We just set the data size to 0 for a failed mapping which
252 * should prevent DMA from happening...
253 */
e2dbb33a 254 if (dma_mapping_error(ndev->dev.parent, dma_addr))
d8b48911 255 rx_desc->ds_cc = cpu_to_le16(0);
c156633f
SS		 256 rx_desc->dptr = cpu_to_le32(dma_addr);
257 rx_desc->die_dt = DT_FEMPTY;
258 }
259 rx_desc = &priv->rx_ring[q][i];
260 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
261 rx_desc->die_dt = DT_LINKFIX; /* type */
c156633f
SS		 262
263 memset(priv->tx_ring[q], 0, tx_ring_size);
264 /* Build TX ring buffer */
2f45d190
SS		 265 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
266 i++, tx_desc++) {
267 tx_desc->die_dt = DT_EEMPTY;
268 tx_desc++;
c156633f
SS		 269 tx_desc->die_dt = DT_EEMPTY;
270 }
c156633f
SS		 271 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
272 tx_desc->die_dt = DT_LINKFIX; /* type */
273
274 /* RX descriptor base address for best effort */
275 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
276 desc->die_dt = DT_LINKFIX; /* type */
277 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
278
279 /* TX descriptor base address for best effort */
280 desc = &priv->desc_bat[q];
281 desc->die_dt = DT_LINKFIX; /* type */
282 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
283}
284
285/* Init skb and descriptor buffer for Ethernet AVB */
286static int ravb_ring_init(struct net_device *ndev, int q)
287{
288 struct ravb_private *priv = netdev_priv(ndev);
d8b48911 289 struct sk_buff *skb;
c156633f 290 int ring_size;
d8b48911 291 int i;
c156633f
SS		 292
293 /* Allocate RX and TX skb rings */
294 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
295 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
296 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
297 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
298 if (!priv->rx_skb[q] || !priv->tx_skb[q])
299 goto error;
300
d8b48911
SS		 301 for (i = 0; i < priv->num_rx_ring[q]; i++) {
302 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
303 if (!skb)
304 goto error;
305 ravb_set_buffer_align(skb);
306 priv->rx_skb[q][i] = skb;
307 }
308
c156633f 309 /* Allocate rings for the aligned buffers */
2f45d190
SS		 310 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
311 DPTR_ALIGN - 1, GFP_KERNEL);
312 if (!priv->tx_align[q])
c156633f
SS		 313 goto error;
314
315 /* Allocate all RX descriptors. */
316 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
e2dbb33a 317 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
c156633f
SS		 318 &priv->rx_desc_dma[q],
319 GFP_KERNEL);
320 if (!priv->rx_ring[q])
321 goto error;
322
323 priv->dirty_rx[q] = 0;
324
325 /* Allocate all TX descriptors. */
2f45d190
SS		 326 ring_size = sizeof(struct ravb_tx_desc) *
327 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
e2dbb33a 328 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
c156633f
SS		 329 &priv->tx_desc_dma[q],
330 GFP_KERNEL);
331 if (!priv->tx_ring[q])
332 goto error;
333
334 return 0;
335
336error:
337 ravb_ring_free(ndev, q);
338
339 return -ENOMEM;
340}
341
342/* E-MAC init function */
343static void ravb_emac_init(struct net_device *ndev)
344{
345 struct ravb_private *priv = netdev_priv(ndev);
c156633f
SS		 346
347 /* Receive frame limit set register */
348 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
349
350 /* PAUSE prohibition */
1c1fa821
SS		 351 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
352 ECMR_TE | ECMR_RE, ECMR);
c156633f
SS		 353
354 ravb_set_rate(ndev);
355
356 /* Set MAC address */
357 ravb_write(ndev,
358 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
359 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
360 ravb_write(ndev,
361 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
362
363 ravb_write(ndev, 1, MPR);
364
365 /* E-MAC status register clear */
366 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
367
368 /* E-MAC interrupt enable register */
369 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
370}
371
372/* Device init function for Ethernet AVB */
373static int ravb_dmac_init(struct net_device *ndev)
374{
375 int error;
376
377 /* Set CONFIG mode */
378 error = ravb_config(ndev);
379 if (error)
380 return error;
381
382 error = ravb_ring_init(ndev, RAVB_BE);
383 if (error)
384 return error;
385 error = ravb_ring_init(ndev, RAVB_NC);
386 if (error) {
387 ravb_ring_free(ndev, RAVB_BE);
388 return error;
389 }
390
391 /* Descriptor format */
392 ravb_ring_format(ndev, RAVB_BE);
393 ravb_ring_format(ndev, RAVB_NC);
394
395#if defined(__LITTLE_ENDIAN)
396 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);
397#else
398 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);
399#endif
400
401 /* Set AVB RX */
402 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
403
404 /* Set FIFO size */
405 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
406
407 /* Timestamp enable */
408 ravb_write(ndev, TCCR_TFEN, TCCR);
409
6474de5f 410 /* Interrupt init: */
c156633f
SS		 411 /* Frame receive */
412 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
6474de5f
KM		 413 /* Disable FIFO full warning */
414 ravb_write(ndev, 0, RIC1);
c156633f
SS		 415 /* Receive FIFO full error, descriptor empty */
416 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
417 /* Frame transmitted, timestamp FIFO updated */
418 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
419
420 /* Setting the control will start the AVB-DMAC process. */
421 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,
422 CCC);
423
424 return 0;
425}
426
427/* Free TX skb function for AVB-IP */
428static int ravb_tx_free(struct net_device *ndev, int q)
429{
430 struct ravb_private *priv = netdev_priv(ndev);
431 struct net_device_stats *stats = &priv->stats[q];
432 struct ravb_tx_desc *desc;
433 int free_num = 0;
aad0d51e 434 int entry;
c156633f
SS		 435 u32 size;
436
437 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
2f45d190
SS		 438 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
439 NUM_TX_DESC);
c156633f
SS		 440 desc = &priv->tx_ring[q][entry];
441 if (desc->die_dt != DT_FEMPTY)
442 break;
443 /* Descriptor type must be checked before all other reads */
444 dma_rmb();
445 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
446 /* Free the original skb. */
2f45d190 447 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
e2dbb33a 448 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
c156633f 449 size, DMA_TO_DEVICE);
2f45d190
SS		 450 /* Last packet descriptor? */
451 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
452 entry /= NUM_TX_DESC;
453 dev_kfree_skb_any(priv->tx_skb[q][entry]);
454 priv->tx_skb[q][entry] = NULL;
455 stats->tx_packets++;
456 }
c156633f
SS		 457 free_num++;
458 }
c156633f
SS		 459 stats->tx_bytes += size;
460 desc->die_dt = DT_EEMPTY;
461 }
462 return free_num;
463}
464
465static void ravb_get_tx_tstamp(struct net_device *ndev)
466{
467 struct ravb_private *priv = netdev_priv(ndev);
468 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
469 struct skb_shared_hwtstamps shhwtstamps;
470 struct sk_buff *skb;
471 struct timespec64 ts;
472 u16 tag, tfa_tag;
473 int count;
474 u32 tfa2;
475
476 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
477 while (count--) {
478 tfa2 = ravb_read(ndev, TFA2);
479 tfa_tag = (tfa2 & TFA2_TST) >> 16;
480 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
481 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
482 ravb_read(ndev, TFA1);
483 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
484 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
485 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
486 list) {
487 skb = ts_skb->skb;
488 tag = ts_skb->tag;
489 list_del(&ts_skb->list);
490 kfree(ts_skb);
491 if (tag == tfa_tag) {
492 skb_tstamp_tx(skb, &shhwtstamps);
493 break;
494 }
495 }
496 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);
497 }
498}
499
500/* Packet receive function for Ethernet AVB */
501static bool ravb_rx(struct net_device *ndev, int *quota, int q)
502{
503 struct ravb_private *priv = netdev_priv(ndev);
504 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
505 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
506 priv->cur_rx[q];
507 struct net_device_stats *stats = &priv->stats[q];
508 struct ravb_ex_rx_desc *desc;
509 struct sk_buff *skb;
510 dma_addr_t dma_addr;
511 struct timespec64 ts;
c156633f 512 u8 desc_status;
aad0d51e 513 u16 pkt_len;
c156633f
SS		 514 int limit;
515
516 boguscnt = min(boguscnt, *quota);
517 limit = boguscnt;
518 desc = &priv->rx_ring[q][entry];
519 while (desc->die_dt != DT_FEMPTY) {
520 /* Descriptor type must be checked before all other reads */
521 dma_rmb();
522 desc_status = desc->msc;
523 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
524
525 if (--boguscnt < 0)
526 break;
527
d8b48911
SS		 528 /* We use 0-byte descriptors to mark the DMA mapping errors */
529 if (!pkt_len)
530 continue;
531
c156633f
SS		 532 if (desc_status & MSC_MC)
533 stats->multicast++;
534
535 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
536 MSC_CEEF)) {
537 stats->rx_errors++;
538 if (desc_status & MSC_CRC)
539 stats->rx_crc_errors++;
540 if (desc_status & MSC_RFE)
541 stats->rx_frame_errors++;
542 if (desc_status & (MSC_RTLF | MSC_RTSF))
543 stats->rx_length_errors++;
544 if (desc_status & MSC_CEEF)
545 stats->rx_missed_errors++;
546 } else {
547 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
548
549 skb = priv->rx_skb[q][entry];
550 priv->rx_skb[q][entry] = NULL;
e2dbb33a 551 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
e2370f07
SS		 552 ALIGN(PKT_BUF_SZ, 16),
553 DMA_FROM_DEVICE);
c156633f
SS		 554 get_ts &= (q == RAVB_NC) ?
555 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
556 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
557 if (get_ts) {
558 struct skb_shared_hwtstamps *shhwtstamps;
559
560 shhwtstamps = skb_hwtstamps(skb);
561 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
562 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
563 32) | le32_to_cpu(desc->ts_sl);
564 ts.tv_nsec = le32_to_cpu(desc->ts_n);
565 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
566 }
567 skb_put(skb, pkt_len);
568 skb->protocol = eth_type_trans(skb, ndev);
569 napi_gro_receive(&priv->napi[q], skb);
570 stats->rx_packets++;
571 stats->rx_bytes += pkt_len;
572 }
573
574 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
575 desc = &priv->rx_ring[q][entry];
576 }
577
578 /* Refill the RX ring buffers. */
579 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
580 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
581 desc = &priv->rx_ring[q][entry];
582 /* The size of the buffer should be on 16-byte boundary. */
583 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
584
585 if (!priv->rx_skb[q][entry]) {
586 skb = netdev_alloc_skb(ndev,
587 PKT_BUF_SZ + RAVB_ALIGN - 1);
588 if (!skb)
589 break; /* Better luck next round. */
590 ravb_set_buffer_align(skb);
e2dbb33a 591 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
c156633f
SS		 592 le16_to_cpu(desc->ds_cc),
593 DMA_FROM_DEVICE);
594 skb_checksum_none_assert(skb);
d8b48911
SS		 595 /* We just set the data size to 0 for a failed mapping
596 * which should prevent DMA from happening...
597 */
e2dbb33a 598 if (dma_mapping_error(ndev->dev.parent, dma_addr))
d8b48911 599 desc->ds_cc = cpu_to_le16(0);
c156633f
SS		 600 desc->dptr = cpu_to_le32(dma_addr);
601 priv->rx_skb[q][entry] = skb;
602 }
603 /* Descriptor type must be set after all the above writes */
604 dma_wmb();
605 desc->die_dt = DT_FEMPTY;
606 }
607
608 *quota -= limit - (++boguscnt);
609
610 return boguscnt <= 0;
611}
612
613static void ravb_rcv_snd_disable(struct net_device *ndev)
614{
615 /* Disable TX and RX */
616 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);
617}
618
619static void ravb_rcv_snd_enable(struct net_device *ndev)
620{
621 /* Enable TX and RX */
622 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);
623}
624
625/* function for waiting dma process finished */
626static int ravb_stop_dma(struct net_device *ndev)
627{
628 int error;
629
630 /* Wait for stopping the hardware TX process */
631 error = ravb_wait(ndev, TCCR,
632 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
633 if (error)
634 return error;
635
636 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
637 0);
638 if (error)
639 return error;
640
641 /* Stop the E-MAC's RX/TX processes. */
642 ravb_rcv_snd_disable(ndev);
643
644 /* Wait for stopping the RX DMA process */
645 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
646 if (error)
647 return error;
648
649 /* Stop AVB-DMAC process */
650 return ravb_config(ndev);
651}
652
653/* E-MAC interrupt handler */
654static void ravb_emac_interrupt(struct net_device *ndev)
655{
656 struct ravb_private *priv = netdev_priv(ndev);
657 u32 ecsr, psr;
658
659 ecsr = ravb_read(ndev, ECSR);
660 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
661 if (ecsr & ECSR_ICD)
662 ndev->stats.tx_carrier_errors++;
663 if (ecsr & ECSR_LCHNG) {
664 /* Link changed */
665 if (priv->no_avb_link)
666 return;
667 psr = ravb_read(ndev, PSR);
668 if (priv->avb_link_active_low)
669 psr ^= PSR_LMON;
670 if (!(psr & PSR_LMON)) {
671 /* DIsable RX and TX */
672 ravb_rcv_snd_disable(ndev);
673 } else {
674 /* Enable RX and TX */
675 ravb_rcv_snd_enable(ndev);
676 }
677 }
678}
679
680/* Error interrupt handler */
681static void ravb_error_interrupt(struct net_device *ndev)
682{
683 struct ravb_private *priv = netdev_priv(ndev);
684 u32 eis, ris2;
685
686 eis = ravb_read(ndev, EIS);
687 ravb_write(ndev, ~EIS_QFS, EIS);
688 if (eis & EIS_QFS) {
689 ris2 = ravb_read(ndev, RIS2);
690 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
691
692 /* Receive Descriptor Empty int */
693 if (ris2 & RIS2_QFF0)
694 priv->stats[RAVB_BE].rx_over_errors++;
695
696 /* Receive Descriptor Empty int */
697 if (ris2 & RIS2_QFF1)
698 priv->stats[RAVB_NC].rx_over_errors++;
699
700 /* Receive FIFO Overflow int */
701 if (ris2 & RIS2_RFFF)
702 priv->rx_fifo_errors++;
703 }
704}
705
706static irqreturn_t ravb_interrupt(int irq, void *dev_id)
707{
708 struct net_device *ndev = dev_id;
709 struct ravb_private *priv = netdev_priv(ndev);
710 irqreturn_t result = IRQ_NONE;
711 u32 iss;
712
713 spin_lock(&priv->lock);
714 /* Get interrupt status */
715 iss = ravb_read(ndev, ISS);
716
717 /* Received and transmitted interrupts */
718 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
719 u32 ris0 = ravb_read(ndev, RIS0);
720 u32 ric0 = ravb_read(ndev, RIC0);
721 u32 tis = ravb_read(ndev, TIS);
722 u32 tic = ravb_read(ndev, TIC);
723 int q;
724
725 /* Timestamp updated */
726 if (tis & TIS_TFUF) {
727 ravb_write(ndev, ~TIS_TFUF, TIS);
728 ravb_get_tx_tstamp(ndev);
729 result = IRQ_HANDLED;
730 }
731
732 /* Network control and best effort queue RX/TX */
733 for (q = RAVB_NC; q >= RAVB_BE; q--) {
734 if (((ris0 & ric0) & BIT(q)) ||
735 ((tis & tic) & BIT(q))) {
736 if (napi_schedule_prep(&priv->napi[q])) {
737 /* Mask RX and TX interrupts */
2452cb0c
MN		 738 ric0 &= ~BIT(q);
739 tic &= ~BIT(q);
740 ravb_write(ndev, ric0, RIC0);
741 ravb_write(ndev, tic, TIC);
c156633f
SS		 742 __napi_schedule(&priv->napi[q]);
743 } else {
744 netdev_warn(ndev,
745 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
746 ris0, ric0);
747 netdev_warn(ndev,
748 " tx status 0x%08x, tx mask 0x%08x.\n",
749 tis, tic);
750 }
751 result = IRQ_HANDLED;
752 }
753 }
754 }
755
756 /* E-MAC status summary */
757 if (iss & ISS_MS) {
758 ravb_emac_interrupt(ndev);
759 result = IRQ_HANDLED;
760 }
761
762 /* Error status summary */
763 if (iss & ISS_ES) {
764 ravb_error_interrupt(ndev);
765 result = IRQ_HANDLED;
766 }
767
a0d2f206
SS		 768 if (iss & ISS_CGIS)
769 result = ravb_ptp_interrupt(ndev);
770
c156633f
SS		 771 mmiowb();
772 spin_unlock(&priv->lock);
773 return result;
774}
775
776static int ravb_poll(struct napi_struct *napi, int budget)
777{
778 struct net_device *ndev = napi->dev;
779 struct ravb_private *priv = netdev_priv(ndev);
780 unsigned long flags;
781 int q = napi - priv->napi;
782 int mask = BIT(q);
783 int quota = budget;
784 u32 ris0, tis;
785
786 for (;;) {
787 tis = ravb_read(ndev, TIS);
788 ris0 = ravb_read(ndev, RIS0);
789 if (!((ris0 & mask) || (tis & mask)))
790 break;
791
792 /* Processing RX Descriptor Ring */
793 if (ris0 & mask) {
794 /* Clear RX interrupt */
795 ravb_write(ndev, ~mask, RIS0);
796 if (ravb_rx(ndev, &quota, q))
797 goto out;
798 }
799 /* Processing TX Descriptor Ring */
800 if (tis & mask) {
801 spin_lock_irqsave(&priv->lock, flags);
802 /* Clear TX interrupt */
803 ravb_write(ndev, ~mask, TIS);
804 ravb_tx_free(ndev, q);
805 netif_wake_subqueue(ndev, q);
806 mmiowb();
807 spin_unlock_irqrestore(&priv->lock, flags);
808 }
809 }
810
811 napi_complete(napi);
812
813 /* Re-enable RX/TX interrupts */
814 spin_lock_irqsave(&priv->lock, flags);
815 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);
816 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC);
817 mmiowb();
818 spin_unlock_irqrestore(&priv->lock, flags);
819
820 /* Receive error message handling */
821 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
822 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
823 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
824 ndev->stats.rx_over_errors = priv->rx_over_errors;
825 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
826 }
827 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
828 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
829 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
830 }
831out:
832 return budget - quota;
833}
834
835/* PHY state control function */
836static void ravb_adjust_link(struct net_device *ndev)
837{
838 struct ravb_private *priv = netdev_priv(ndev);
839 struct phy_device *phydev = priv->phydev;
840 bool new_state = false;
841
842 if (phydev->link) {
843 if (phydev->duplex != priv->duplex) {
844 new_state = true;
845 priv->duplex = phydev->duplex;
846 ravb_set_duplex(ndev);
847 }
848
849 if (phydev->speed != priv->speed) {
850 new_state = true;
851 priv->speed = phydev->speed;
852 ravb_set_rate(ndev);
853 }
854 if (!priv->link) {
855 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,
856 ECMR);
857 new_state = true;
858 priv->link = phydev->link;
859 if (priv->no_avb_link)
860 ravb_rcv_snd_enable(ndev);
861 }
862 } else if (priv->link) {
863 new_state = true;
864 priv->link = 0;
865 priv->speed = 0;
866 priv->duplex = -1;
867 if (priv->no_avb_link)
868 ravb_rcv_snd_disable(ndev);
869 }
870
871 if (new_state && netif_msg_link(priv))
872 phy_print_status(phydev);
873}
874
875/* PHY init function */
876static int ravb_phy_init(struct net_device *ndev)
877{
878 struct device_node *np = ndev->dev.parent->of_node;
879 struct ravb_private *priv = netdev_priv(ndev);
880 struct phy_device *phydev;
881 struct device_node *pn;
b4bc88a8 882 int err;
c156633f
SS		 883
884 priv->link = 0;
885 priv->speed = 0;
886 priv->duplex = -1;
887
888 /* Try connecting to PHY */
889 pn = of_parse_phandle(np, "phy-handle", 0);
b4bc88a8
KM		 890 if (!pn) {
891 /* In the case of a fixed PHY, the DT node associated
892 * to the PHY is the Ethernet MAC DT node.
893 */
894 if (of_phy_is_fixed_link(np)) {
895 err = of_phy_register_fixed_link(np);
896 if (err)
897 return err;
898 }
899 pn = of_node_get(np);
900 }
c156633f
SS		 901 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
902 priv->phy_interface);
903 if (!phydev) {
904 netdev_err(ndev, "failed to connect PHY\n");
905 return -ENOENT;
906 }
907
22d4df8f
KM		 908 /* This driver only support 10/100Mbit speeds on Gen3
909 * at this time.
910 */
911 if (priv->chip_id == RCAR_GEN3) {
912 int err;
913
914 err = phy_set_max_speed(phydev, SPEED_100);
915 if (err) {
916 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
917 phy_disconnect(phydev);
918 return err;
919 }
920
921 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
922 }
923
54499969
KM		 924 /* 10BASE is not supported */
925 phydev->supported &= ~PHY_10BT_FEATURES;
926
2220943a 927 phy_attached_info(phydev);
c156633f
SS		 928
929 priv->phydev = phydev;
930
931 return 0;
932}
933
934/* PHY control start function */
935static int ravb_phy_start(struct net_device *ndev)
936{
937 struct ravb_private *priv = netdev_priv(ndev);
938 int error;
939
940 error = ravb_phy_init(ndev);
941 if (error)
942 return error;
943
944 phy_start(priv->phydev);
945
946 return 0;
947}
948
949static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
950{
951 struct ravb_private *priv = netdev_priv(ndev);
952 int error = -ENODEV;
953 unsigned long flags;
954
955 if (priv->phydev) {
956 spin_lock_irqsave(&priv->lock, flags);
957 error = phy_ethtool_gset(priv->phydev, ecmd);
958 spin_unlock_irqrestore(&priv->lock, flags);
959 }
960
961 return error;
962}
963
964static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
965{
966 struct ravb_private *priv = netdev_priv(ndev);
967 unsigned long flags;
968 int error;
969
970 if (!priv->phydev)
971 return -ENODEV;
972
973 spin_lock_irqsave(&priv->lock, flags);
974
975 /* Disable TX and RX */
976 ravb_rcv_snd_disable(ndev);
977
978 error = phy_ethtool_sset(priv->phydev, ecmd);
979 if (error)
980 goto error_exit;
981
982 if (ecmd->duplex == DUPLEX_FULL)
983 priv->duplex = 1;
984 else
985 priv->duplex = 0;
986
987 ravb_set_duplex(ndev);
988
989error_exit:
990 mdelay(1);
991
992 /* Enable TX and RX */
993 ravb_rcv_snd_enable(ndev);
994
995 mmiowb();
996 spin_unlock_irqrestore(&priv->lock, flags);
997
998 return error;
999}
1000
1001static int ravb_nway_reset(struct net_device *ndev)
1002{
1003 struct ravb_private *priv = netdev_priv(ndev);
1004 int error = -ENODEV;
1005 unsigned long flags;
1006
1007 if (priv->phydev) {
1008 spin_lock_irqsave(&priv->lock, flags);
1009 error = phy_start_aneg(priv->phydev);
1010 spin_unlock_irqrestore(&priv->lock, flags);
1011 }
1012
1013 return error;
1014}
1015
1016static u32 ravb_get_msglevel(struct net_device *ndev)
1017{
1018 struct ravb_private *priv = netdev_priv(ndev);
1019
1020 return priv->msg_enable;
1021}
1022
1023static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1024{
1025 struct ravb_private *priv = netdev_priv(ndev);
1026
1027 priv->msg_enable = value;
1028}
1029
1030static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1031 "rx_queue_0_current",
1032 "tx_queue_0_current",
1033 "rx_queue_0_dirty",
1034 "tx_queue_0_dirty",
1035 "rx_queue_0_packets",
1036 "tx_queue_0_packets",
1037 "rx_queue_0_bytes",
1038 "tx_queue_0_bytes",
1039 "rx_queue_0_mcast_packets",
1040 "rx_queue_0_errors",
1041 "rx_queue_0_crc_errors",
1042 "rx_queue_0_frame_errors",
1043 "rx_queue_0_length_errors",
1044 "rx_queue_0_missed_errors",
1045 "rx_queue_0_over_errors",
1046
1047 "rx_queue_1_current",
1048 "tx_queue_1_current",
1049 "rx_queue_1_dirty",
1050 "tx_queue_1_dirty",
1051 "rx_queue_1_packets",
1052 "tx_queue_1_packets",
1053 "rx_queue_1_bytes",
1054 "tx_queue_1_bytes",
1055 "rx_queue_1_mcast_packets",
1056 "rx_queue_1_errors",
1057 "rx_queue_1_crc_errors",
b17c1d9a 1058 "rx_queue_1_frame_errors",
c156633f
SS		 1059 "rx_queue_1_length_errors",
1060 "rx_queue_1_missed_errors",
1061 "rx_queue_1_over_errors",
1062};
1063
1064#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1065
1066static int ravb_get_sset_count(struct net_device *netdev, int sset)
1067{
1068 switch (sset) {
1069 case ETH_SS_STATS:
1070 return RAVB_STATS_LEN;
1071 default:
1072 return -EOPNOTSUPP;
1073 }
1074}
1075
1076static void ravb_get_ethtool_stats(struct net_device *ndev,
1077 struct ethtool_stats *stats, u64 *data)
1078{
1079 struct ravb_private *priv = netdev_priv(ndev);
1080 int i = 0;
1081 int q;
1082
1083 /* Device-specific stats */
1084 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1085 struct net_device_stats *stats = &priv->stats[q];
1086
1087 data[i++] = priv->cur_rx[q];
1088 data[i++] = priv->cur_tx[q];
1089 data[i++] = priv->dirty_rx[q];
1090 data[i++] = priv->dirty_tx[q];
1091 data[i++] = stats->rx_packets;
1092 data[i++] = stats->tx_packets;
1093 data[i++] = stats->rx_bytes;
1094 data[i++] = stats->tx_bytes;
1095 data[i++] = stats->multicast;
1096 data[i++] = stats->rx_errors;
1097 data[i++] = stats->rx_crc_errors;
1098 data[i++] = stats->rx_frame_errors;
1099 data[i++] = stats->rx_length_errors;
1100 data[i++] = stats->rx_missed_errors;
1101 data[i++] = stats->rx_over_errors;
1102 }
1103}
1104
1105static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1106{
1107 switch (stringset) {
1108 case ETH_SS_STATS:
1109 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1110 break;
1111 }
1112}
1113
1114static void ravb_get_ringparam(struct net_device *ndev,
1115 struct ethtool_ringparam *ring)
1116{
1117 struct ravb_private *priv = netdev_priv(ndev);
1118
1119 ring->rx_max_pending = BE_RX_RING_MAX;
1120 ring->tx_max_pending = BE_TX_RING_MAX;
1121 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1122 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1123}
1124
1125static int ravb_set_ringparam(struct net_device *ndev,
1126 struct ethtool_ringparam *ring)
1127{
1128 struct ravb_private *priv = netdev_priv(ndev);
1129 int error;
1130
1131 if (ring->tx_pending > BE_TX_RING_MAX ||
1132 ring->rx_pending > BE_RX_RING_MAX ||
1133 ring->tx_pending < BE_TX_RING_MIN ||
1134 ring->rx_pending < BE_RX_RING_MIN)
1135 return -EINVAL;
1136 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1137 return -EINVAL;
1138
1139 if (netif_running(ndev)) {
1140 netif_device_detach(ndev);
a0d2f206 1141 /* Stop PTP Clock driver */
50bfd838
SS		 1142 if (priv->chip_id == RCAR_GEN2)
1143 ravb_ptp_stop(ndev);
c156633f
SS		 1144 /* Wait for DMA stopping */
1145 error = ravb_stop_dma(ndev);
1146 if (error) {
1147 netdev_err(ndev,
1148 "cannot set ringparam! Any AVB processes are still running?\n");
1149 return error;
1150 }
1151 synchronize_irq(ndev->irq);
1152
1153 /* Free all the skb's in the RX queue and the DMA buffers. */
1154 ravb_ring_free(ndev, RAVB_BE);
1155 ravb_ring_free(ndev, RAVB_NC);
1156 }
1157
1158 /* Set new parameters */
1159 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1160 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1161
1162 if (netif_running(ndev)) {
1163 error = ravb_dmac_init(ndev);
1164 if (error) {
1165 netdev_err(ndev,
1166 "%s: ravb_dmac_init() failed, error %d\n",
1167 __func__, error);
1168 return error;
1169 }
1170
1171 ravb_emac_init(ndev);
1172
a0d2f206 1173 /* Initialise PTP Clock driver */
50bfd838
SS		 1174 if (priv->chip_id == RCAR_GEN2)
1175 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1176
c156633f
SS		 1177 netif_device_attach(ndev);
1178 }
1179
1180 return 0;
1181}
1182
1183static int ravb_get_ts_info(struct net_device *ndev,
1184 struct ethtool_ts_info *info)
1185{
a0d2f206
SS		 1186 struct ravb_private *priv = netdev_priv(ndev);
1187
c156633f
SS		 1188 info->so_timestamping =
1189 SOF_TIMESTAMPING_TX_SOFTWARE |
1190 SOF_TIMESTAMPING_RX_SOFTWARE |
1191 SOF_TIMESTAMPING_SOFTWARE |
1192 SOF_TIMESTAMPING_TX_HARDWARE |
1193 SOF_TIMESTAMPING_RX_HARDWARE |
1194 SOF_TIMESTAMPING_RAW_HARDWARE;
1195 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1196 info->rx_filters =
1197 (1 << HWTSTAMP_FILTER_NONE) |
1198 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1199 (1 << HWTSTAMP_FILTER_ALL);
a0d2f206 1200 info->phc_index = ptp_clock_index(priv->ptp.clock);
c156633f
SS		 1201
1202 return 0;
1203}
1204
1205static const struct ethtool_ops ravb_ethtool_ops = {
1206 .get_settings = ravb_get_settings,
1207 .set_settings = ravb_set_settings,
1208 .nway_reset = ravb_nway_reset,
1209 .get_msglevel = ravb_get_msglevel,
1210 .set_msglevel = ravb_set_msglevel,
1211 .get_link = ethtool_op_get_link,
1212 .get_strings = ravb_get_strings,
1213 .get_ethtool_stats = ravb_get_ethtool_stats,
1214 .get_sset_count = ravb_get_sset_count,
1215 .get_ringparam = ravb_get_ringparam,
1216 .set_ringparam = ravb_set_ringparam,
1217 .get_ts_info = ravb_get_ts_info,
1218};
1219
1220/* Network device open function for Ethernet AVB */
1221static int ravb_open(struct net_device *ndev)
1222{
1223 struct ravb_private *priv = netdev_priv(ndev);
1224 int error;
1225
1226 napi_enable(&priv->napi[RAVB_BE]);
1227 napi_enable(&priv->napi[RAVB_NC]);
1228
1229 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name,
1230 ndev);
1231 if (error) {
1232 netdev_err(ndev, "cannot request IRQ\n");
1233 goto out_napi_off;
1234 }
1235
22d4df8f
KM		 1236 if (priv->chip_id == RCAR_GEN3) {
1237 error = request_irq(priv->emac_irq, ravb_interrupt,
1238 IRQF_SHARED, ndev->name, ndev);
1239 if (error) {
1240 netdev_err(ndev, "cannot request IRQ\n");
1241 goto out_free_irq;
1242 }
1243 }
1244
c156633f
SS		 1245 /* Device init */
1246 error = ravb_dmac_init(ndev);
1247 if (error)
508dc064 1248 goto out_free_irq2;
c156633f
SS		 1249 ravb_emac_init(ndev);
1250
a0d2f206 1251 /* Initialise PTP Clock driver */
f5d7837f
KM		 1252 if (priv->chip_id == RCAR_GEN2)
1253 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1254
c156633f
SS		 1255 netif_tx_start_all_queues(ndev);
1256
1257 /* PHY control start */
1258 error = ravb_phy_start(ndev);
1259 if (error)
a0d2f206 1260 goto out_ptp_stop;
c156633f
SS		 1261
1262 return 0;
1263
a0d2f206
SS		 1264out_ptp_stop:
1265 /* Stop PTP Clock driver */
f5d7837f
KM		 1266 if (priv->chip_id == RCAR_GEN2)
1267 ravb_ptp_stop(ndev);
508dc064
SS		 1268out_free_irq2:
1269 if (priv->chip_id == RCAR_GEN3)
1270 free_irq(priv->emac_irq, ndev);
c156633f
SS		 1271out_free_irq:
1272 free_irq(ndev->irq, ndev);
1273out_napi_off:
1274 napi_disable(&priv->napi[RAVB_NC]);
1275 napi_disable(&priv->napi[RAVB_BE]);
1276 return error;
1277}
1278
1279/* Timeout function for Ethernet AVB */
1280static void ravb_tx_timeout(struct net_device *ndev)
1281{
1282 struct ravb_private *priv = netdev_priv(ndev);
1283
1284 netif_err(priv, tx_err, ndev,
1285 "transmit timed out, status %08x, resetting...\n",
1286 ravb_read(ndev, ISS));
1287
1288 /* tx_errors count up */
1289 ndev->stats.tx_errors++;
1290
1291 schedule_work(&priv->work);
1292}
1293
1294static void ravb_tx_timeout_work(struct work_struct *work)
1295{
1296 struct ravb_private *priv = container_of(work, struct ravb_private,
1297 work);
1298 struct net_device *ndev = priv->ndev;
1299
1300 netif_tx_stop_all_queues(ndev);
1301
a0d2f206 1302 /* Stop PTP Clock driver */
50bfd838
SS		 1303 if (priv->chip_id == RCAR_GEN2)
1304 ravb_ptp_stop(ndev);
a0d2f206 1305
c156633f
SS		 1306 /* Wait for DMA stopping */
1307 ravb_stop_dma(ndev);
1308
1309 ravb_ring_free(ndev, RAVB_BE);
1310 ravb_ring_free(ndev, RAVB_NC);
1311
1312 /* Device init */
1313 ravb_dmac_init(ndev);
1314 ravb_emac_init(ndev);
1315
a0d2f206 1316 /* Initialise PTP Clock driver */
50bfd838
SS		 1317 if (priv->chip_id == RCAR_GEN2)
1318 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1319
c156633f
SS		 1320 netif_tx_start_all_queues(ndev);
1321}
1322
1323/* Packet transmit function for Ethernet AVB */
1324static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1325{
1326 struct ravb_private *priv = netdev_priv(ndev);
c156633f 1327 u16 q = skb_get_queue_mapping(skb);
aad0d51e 1328 struct ravb_tstamp_skb *ts_skb;
c156633f
SS		 1329 struct ravb_tx_desc *desc;
1330 unsigned long flags;
1331 u32 dma_addr;
1332 void *buffer;
1333 u32 entry;
2f45d190 1334 u32 len;
c156633f
SS		 1335
1336 spin_lock_irqsave(&priv->lock, flags);
2f45d190
SS		 1337 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1338 NUM_TX_DESC) {
c156633f
SS		 1339 netif_err(priv, tx_queued, ndev,
1340 "still transmitting with the full ring!\n");
1341 netif_stop_subqueue(ndev, q);
1342 spin_unlock_irqrestore(&priv->lock, flags);
1343 return NETDEV_TX_BUSY;
1344 }
2f45d190
SS		 1345 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1346 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
c156633f
SS		 1347
1348 if (skb_put_padto(skb, ETH_ZLEN))
1349 goto drop;
1350
2f45d190
SS		 1351 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1352 entry / NUM_TX_DESC * DPTR_ALIGN;
1353 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1354 memcpy(buffer, skb->data, len);
e2dbb33a
KM		 1355 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1356 if (dma_mapping_error(ndev->dev.parent, dma_addr))
c156633f 1357 goto drop;
2f45d190
SS		 1358
1359 desc = &priv->tx_ring[q][entry];
1360 desc->ds_tagl = cpu_to_le16(len);
1361 desc->dptr = cpu_to_le32(dma_addr);
1362
1363 buffer = skb->data + len;
1364 len = skb->len - len;
e2dbb33a
KM		 1365 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1366 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2f45d190
SS		 1367 goto unmap;
1368
1369 desc++;
1370 desc->ds_tagl = cpu_to_le16(len);
c156633f
SS		 1371 desc->dptr = cpu_to_le32(dma_addr);
1372
1373 /* TX timestamp required */
1374 if (q == RAVB_NC) {
1375 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1376 if (!ts_skb) {
2f45d190 1377 desc--;
e2dbb33a 1378 dma_unmap_single(ndev->dev.parent, dma_addr, len,
c156633f 1379 DMA_TO_DEVICE);
2f45d190 1380 goto unmap;
c156633f
SS		 1381 }
1382 ts_skb->skb = skb;
1383 ts_skb->tag = priv->ts_skb_tag++;
1384 priv->ts_skb_tag &= 0x3ff;
1385 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1386
1387 /* TAG and timestamp required flag */
1388 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1389 skb_tx_timestamp(skb);
1390 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1391 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1392 }
1393
1394 /* Descriptor type must be set after all the above writes */
1395 dma_wmb();
2f45d190
SS		 1396 desc->die_dt = DT_FEND;
1397 desc--;
1398 desc->die_dt = DT_FSTART;
c156633f 1399
06613e38 1400 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
c156633f 1401
2f45d190
SS		 1402 priv->cur_tx[q] += NUM_TX_DESC;
1403 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1404 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
c156633f
SS		 1405 netif_stop_subqueue(ndev, q);
1406
1407exit:
1408 mmiowb();
1409 spin_unlock_irqrestore(&priv->lock, flags);
1410 return NETDEV_TX_OK;
1411
2f45d190 1412unmap:
e2dbb33a 1413 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2f45d190 1414 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
c156633f
SS		 1415drop:
1416 dev_kfree_skb_any(skb);
2f45d190 1417 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
c156633f
SS		 1418 goto exit;
1419}
1420
1421static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1422 void *accel_priv, select_queue_fallback_t fallback)
1423{
1424 /* If skb needs TX timestamp, it is handled in network control queue */
1425 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1426 RAVB_BE;
1427
1428}
1429
1430static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1431{
1432 struct ravb_private *priv = netdev_priv(ndev);
1433 struct net_device_stats *nstats, *stats0, *stats1;
1434
1435 nstats = &ndev->stats;
1436 stats0 = &priv->stats[RAVB_BE];
1437 stats1 = &priv->stats[RAVB_NC];
1438
1439 nstats->tx_dropped += ravb_read(ndev, TROCR);
1440 ravb_write(ndev, 0, TROCR); /* (write clear) */
1441 nstats->collisions += ravb_read(ndev, CDCR);
1442 ravb_write(ndev, 0, CDCR); /* (write clear) */
1443 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1444 ravb_write(ndev, 0, LCCR); /* (write clear) */
1445
1446 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1447 ravb_write(ndev, 0, CERCR); /* (write clear) */
1448 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1449 ravb_write(ndev, 0, CEECR); /* (write clear) */
1450
1451 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1452 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1453 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1454 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1455 nstats->multicast = stats0->multicast + stats1->multicast;
1456 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1457 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1458 nstats->rx_frame_errors =
1459 stats0->rx_frame_errors + stats1->rx_frame_errors;
1460 nstats->rx_length_errors =
1461 stats0->rx_length_errors + stats1->rx_length_errors;
1462 nstats->rx_missed_errors =
1463 stats0->rx_missed_errors + stats1->rx_missed_errors;
1464 nstats->rx_over_errors =
1465 stats0->rx_over_errors + stats1->rx_over_errors;
1466
1467 return nstats;
1468}
1469
1470/* Update promiscuous bit */
1471static void ravb_set_rx_mode(struct net_device *ndev)
1472{
1473 struct ravb_private *priv = netdev_priv(ndev);
1474 unsigned long flags;
1475 u32 ecmr;
1476
1477 spin_lock_irqsave(&priv->lock, flags);
1478 ecmr = ravb_read(ndev, ECMR);
1479 if (ndev->flags & IFF_PROMISC)
1480 ecmr |= ECMR_PRM;
1481 else
1482 ecmr &= ~ECMR_PRM;
1483 ravb_write(ndev, ecmr, ECMR);
1484 mmiowb();
1485 spin_unlock_irqrestore(&priv->lock, flags);
1486}
1487
1488/* Device close function for Ethernet AVB */
1489static int ravb_close(struct net_device *ndev)
1490{
1491 struct ravb_private *priv = netdev_priv(ndev);
1492 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1493
1494 netif_tx_stop_all_queues(ndev);
1495
1496 /* Disable interrupts by clearing the interrupt masks. */
1497 ravb_write(ndev, 0, RIC0);
c156633f
SS		 1498 ravb_write(ndev, 0, RIC2);
1499 ravb_write(ndev, 0, TIC);
1500
a0d2f206 1501 /* Stop PTP Clock driver */
f5d7837f
KM		 1502 if (priv->chip_id == RCAR_GEN2)
1503 ravb_ptp_stop(ndev);
a0d2f206 1504
c156633f
SS		 1505 /* Set the config mode to stop the AVB-DMAC's processes */
1506 if (ravb_stop_dma(ndev) < 0)
1507 netdev_err(ndev,
1508 "device will be stopped after h/w processes are done.\n");
1509
1510 /* Clear the timestamp list */
1511 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1512 list_del(&ts_skb->list);
1513 kfree(ts_skb);
1514 }
1515
1516 /* PHY disconnect */
1517 if (priv->phydev) {
1518 phy_stop(priv->phydev);
1519 phy_disconnect(priv->phydev);
1520 priv->phydev = NULL;
1521 }
1522
1523 free_irq(ndev->irq, ndev);
1524
1525 napi_disable(&priv->napi[RAVB_NC]);
1526 napi_disable(&priv->napi[RAVB_BE]);
1527
1528 /* Free all the skb's in the RX queue and the DMA buffers. */
1529 ravb_ring_free(ndev, RAVB_BE);
1530 ravb_ring_free(ndev, RAVB_NC);
1531
1532 return 0;
1533}
1534
1535static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1536{
1537 struct ravb_private *priv = netdev_priv(ndev);
1538 struct hwtstamp_config config;
1539
1540 config.flags = 0;
1541 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1542 HWTSTAMP_TX_OFF;
1543 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1544 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1545 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1546 config.rx_filter = HWTSTAMP_FILTER_ALL;
1547 else
1548 config.rx_filter = HWTSTAMP_FILTER_NONE;
1549
1550 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1551 -EFAULT : 0;
1552}
1553
1554/* Control hardware time stamping */
1555static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1556{
1557 struct ravb_private *priv = netdev_priv(ndev);
1558 struct hwtstamp_config config;
1559 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1560 u32 tstamp_tx_ctrl;
1561
1562 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1563 return -EFAULT;
1564
1565 /* Reserved for future extensions */
1566 if (config.flags)
1567 return -EINVAL;
1568
1569 switch (config.tx_type) {
1570 case HWTSTAMP_TX_OFF:
1571 tstamp_tx_ctrl = 0;
1572 break;
1573 case HWTSTAMP_TX_ON:
1574 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1575 break;
1576 default:
1577 return -ERANGE;
1578 }
1579
1580 switch (config.rx_filter) {
1581 case HWTSTAMP_FILTER_NONE:
1582 tstamp_rx_ctrl = 0;
1583 break;
1584 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1585 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1586 break;
1587 default:
1588 config.rx_filter = HWTSTAMP_FILTER_ALL;
1589 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1590 }
1591
1592 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1593 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1594
1595 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1596 -EFAULT : 0;
1597}
1598
1599/* ioctl to device function */
1600static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1601{
1602 struct ravb_private *priv = netdev_priv(ndev);
1603 struct phy_device *phydev = priv->phydev;
1604
1605 if (!netif_running(ndev))
1606 return -EINVAL;
1607
1608 if (!phydev)
1609 return -ENODEV;
1610
1611 switch (cmd) {
1612 case SIOCGHWTSTAMP:
1613 return ravb_hwtstamp_get(ndev, req);
1614 case SIOCSHWTSTAMP:
1615 return ravb_hwtstamp_set(ndev, req);
1616 }
1617
1618 return phy_mii_ioctl(phydev, req, cmd);
1619}
1620
1621static const struct net_device_ops ravb_netdev_ops = {
1622 .ndo_open = ravb_open,
1623 .ndo_stop = ravb_close,
1624 .ndo_start_xmit = ravb_start_xmit,
1625 .ndo_select_queue = ravb_select_queue,
1626 .ndo_get_stats = ravb_get_stats,
1627 .ndo_set_rx_mode = ravb_set_rx_mode,
1628 .ndo_tx_timeout = ravb_tx_timeout,
1629 .ndo_do_ioctl = ravb_do_ioctl,
1630 .ndo_validate_addr = eth_validate_addr,
1631 .ndo_set_mac_address = eth_mac_addr,
1632 .ndo_change_mtu = eth_change_mtu,
1633};
1634
1635/* MDIO bus init function */
1636static int ravb_mdio_init(struct ravb_private *priv)
1637{
1638 struct platform_device *pdev = priv->pdev;
1639 struct device *dev = &pdev->dev;
1640 int error;
1641
1642 /* Bitbang init */
1643 priv->mdiobb.ops = &bb_ops;
1644
1645 /* MII controller setting */
1646 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1647 if (!priv->mii_bus)
1648 return -ENOMEM;
1649
1650 /* Hook up MII support for ethtool */
1651 priv->mii_bus->name = "ravb_mii";
1652 priv->mii_bus->parent = dev;
1653 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1654 pdev->name, pdev->id);
1655
1656 /* Register MDIO bus */
1657 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1658 if (error)
1659 goto out_free_bus;
1660
1661 return 0;
1662
1663out_free_bus:
1664 free_mdio_bitbang(priv->mii_bus);
1665 return error;
1666}
1667
1668/* MDIO bus release function */
1669static int ravb_mdio_release(struct ravb_private *priv)
1670{
1671 /* Unregister mdio bus */
1672 mdiobus_unregister(priv->mii_bus);
1673
1674 /* Free bitbang info */
1675 free_mdio_bitbang(priv->mii_bus);
1676
1677 return 0;
1678}
1679
22d4df8f
KM		 1680static const struct of_device_id ravb_match_table[] = {
1681 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1682 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
0e874361 1683 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
22d4df8f 1684 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
0e874361 1685 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
22d4df8f
KM		 1686 { }
1687};
1688MODULE_DEVICE_TABLE(of, ravb_match_table);
1689
b3d39a88
SH		 1690static int ravb_set_gti(struct net_device *ndev)
1691{
1692
1693 struct device *dev = ndev->dev.parent;
1694 struct device_node *np = dev->of_node;
1695 unsigned long rate;
1696 struct clk *clk;
1697 uint64_t inc;
1698
1699 clk = of_clk_get(np, 0);
1700 if (IS_ERR(clk)) {
1701 dev_err(dev, "could not get clock\n");
1702 return PTR_ERR(clk);
1703 }
1704
1705 rate = clk_get_rate(clk);
1706 clk_put(clk);
1707
1708 inc = 1000000000ULL << 20;
1709 do_div(inc, rate);
1710
1711 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1712 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1713 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1714 return -EINVAL;
1715 }
1716
1717 ravb_write(ndev, inc, GTI);
1718
1719 return 0;
1720}
1721
c156633f
SS		 1722static int ravb_probe(struct platform_device *pdev)
1723{
1724 struct device_node *np = pdev->dev.of_node;
1725 struct ravb_private *priv;
22d4df8f 1726 enum ravb_chip_id chip_id;
c156633f
SS		 1727 struct net_device *ndev;
1728 int error, irq, q;
1729 struct resource *res;
1730
1731 if (!np) {
1732 dev_err(&pdev->dev,
1733 "this driver is required to be instantiated from device tree\n");
1734 return -EINVAL;
1735 }
1736
1737 /* Get base address */
1738 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1739 if (!res) {
1740 dev_err(&pdev->dev, "invalid resource\n");
1741 return -EINVAL;
1742 }
1743
1744 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1745 NUM_TX_QUEUE, NUM_RX_QUEUE);
1746 if (!ndev)
1747 return -ENOMEM;
1748
1749 pm_runtime_enable(&pdev->dev);
1750 pm_runtime_get_sync(&pdev->dev);
1751
1752 /* The Ether-specific entries in the device structure. */
1753 ndev->base_addr = res->start;
1754 ndev->dma = -1;
22d4df8f 1755
e8668630 1756 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
22d4df8f
KM		 1757
1758 if (chip_id == RCAR_GEN3)
1759 irq = platform_get_irq_byname(pdev, "ch22");
1760 else
1761 irq = platform_get_irq(pdev, 0);
c156633f 1762 if (irq < 0) {
f375339e 1763 error = irq;
c156633f
SS		 1764 goto out_release;
1765 }
1766 ndev->irq = irq;
1767
1768 SET_NETDEV_DEV(ndev, &pdev->dev);
1769
1770 priv = netdev_priv(ndev);
1771 priv->ndev = ndev;
1772 priv->pdev = pdev;
1773 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1774 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1775 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1776 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1777 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1778 if (IS_ERR(priv->addr)) {
1779 error = PTR_ERR(priv->addr);
1780 goto out_release;
1781 }
1782
1783 spin_lock_init(&priv->lock);
1784 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1785
1786 priv->phy_interface = of_get_phy_mode(np);
1787
1788 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1789 priv->avb_link_active_low =
1790 of_property_read_bool(np, "renesas,ether-link-active-low");
1791
22d4df8f
KM		 1792 if (chip_id == RCAR_GEN3) {
1793 irq = platform_get_irq_byname(pdev, "ch24");
1794 if (irq < 0) {
1795 error = irq;
1796 goto out_release;
1797 }
1798 priv->emac_irq = irq;
1799 }
1800
1801 priv->chip_id = chip_id;
1802
c156633f
SS		 1803 /* Set function */
1804 ndev->netdev_ops = &ravb_netdev_ops;
1805 ndev->ethtool_ops = &ravb_ethtool_ops;
1806
1807 /* Set AVB config mode */
f5d7837f
KM		 1808 if (chip_id == RCAR_GEN2) {
1809 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) |
1810 CCC_OPC_CONFIG, CCC);
1811 /* Set CSEL value */
1812 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) |
1813 CCC_CSEL_HPB, CCC);
1814 } else {
1815 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) |
1816 CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB, CCC);
1817 }
c156633f 1818
c156633f 1819 /* Set GTI value */
b3d39a88
SH		 1820 error = ravb_set_gti(ndev);
1821 if (error)
1822 goto out_release;
c156633f
SS		 1823
1824 /* Request GTI loading */
1825 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);
1826
1827 /* Allocate descriptor base address table */
1828 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
e2dbb33a 1829 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
c156633f
SS		 1830 &priv->desc_bat_dma, GFP_KERNEL);
1831 if (!priv->desc_bat) {
c4511132 1832 dev_err(&pdev->dev,
c156633f
SS		 1833 "Cannot allocate desc base address table (size %d bytes)\n",
1834 priv->desc_bat_size);
1835 error = -ENOMEM;
1836 goto out_release;
1837 }
1838 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
1839 priv->desc_bat[q].die_dt = DT_EOS;
1840 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1841
1842 /* Initialise HW timestamp list */
1843 INIT_LIST_HEAD(&priv->ts_skb_list);
1844
f5d7837f
KM		 1845 /* Initialise PTP Clock driver */
1846 if (chip_id != RCAR_GEN2)
1847 ravb_ptp_init(ndev, pdev);
1848
c156633f
SS		 1849 /* Debug message level */
1850 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
1851
1852 /* Read and set MAC address */
1853 ravb_read_mac_address(ndev, of_get_mac_address(np));
1854 if (!is_valid_ether_addr(ndev->dev_addr)) {
1855 dev_warn(&pdev->dev,
1856 "no valid MAC address supplied, using a random one\n");
1857 eth_hw_addr_random(ndev);
1858 }
1859
1860 /* MDIO bus init */
1861 error = ravb_mdio_init(priv);
1862 if (error) {
c4511132 1863 dev_err(&pdev->dev, "failed to initialize MDIO\n");
c156633f
SS		 1864 goto out_dma_free;
1865 }
1866
1867 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
1868 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
1869
1870 /* Network device register */
1871 error = register_netdev(ndev);
1872 if (error)
1873 goto out_napi_del;
1874
1875 /* Print device information */
1876 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
1877 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1878
1879 platform_set_drvdata(pdev, ndev);
1880
1881 return 0;
1882
1883out_napi_del:
1884 netif_napi_del(&priv->napi[RAVB_NC]);
1885 netif_napi_del(&priv->napi[RAVB_BE]);
1886 ravb_mdio_release(priv);
1887out_dma_free:
e2dbb33a 1888 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
c156633f 1889 priv->desc_bat_dma);
f5d7837f
KM		 1890
1891 /* Stop PTP Clock driver */
1892 if (chip_id != RCAR_GEN2)
1893 ravb_ptp_stop(ndev);
c156633f
SS		 1894out_release:
1895 if (ndev)
1896 free_netdev(ndev);
1897
1898 pm_runtime_put(&pdev->dev);
1899 pm_runtime_disable(&pdev->dev);
1900 return error;
1901}
1902
1903static int ravb_remove(struct platform_device *pdev)
1904{
1905 struct net_device *ndev = platform_get_drvdata(pdev);
1906 struct ravb_private *priv = netdev_priv(ndev);
1907
f5d7837f
KM		 1908 /* Stop PTP Clock driver */
1909 if (priv->chip_id != RCAR_GEN2)
1910 ravb_ptp_stop(ndev);
1911
e2dbb33a 1912 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
c156633f
SS		 1913 priv->desc_bat_dma);
1914 /* Set reset mode */
1915 ravb_write(ndev, CCC_OPC_RESET, CCC);
1916 pm_runtime_put_sync(&pdev->dev);
1917 unregister_netdev(ndev);
1918 netif_napi_del(&priv->napi[RAVB_NC]);
1919 netif_napi_del(&priv->napi[RAVB_BE]);
1920 ravb_mdio_release(priv);
1921 pm_runtime_disable(&pdev->dev);
1922 free_netdev(ndev);
1923 platform_set_drvdata(pdev, NULL);
1924
1925 return 0;
1926}
1927
1928#ifdef CONFIG_PM
1929static int ravb_runtime_nop(struct device *dev)
1930{
1931 /* Runtime PM callback shared between ->runtime_suspend()
1932 * and ->runtime_resume(). Simply returns success.
1933 *
1934 * This driver re-initializes all registers after
1935 * pm_runtime_get_sync() anyway so there is no need
1936 * to save and restore registers here.
1937 */
1938 return 0;
1939}
1940
1941static const struct dev_pm_ops ravb_dev_pm_ops = {
1942 .runtime_suspend = ravb_runtime_nop,
1943 .runtime_resume = ravb_runtime_nop,
1944};
1945
1946#define RAVB_PM_OPS (&ravb_dev_pm_ops)
1947#else
1948#define RAVB_PM_OPS NULL
1949#endif
1950
c156633f
SS		 1951static struct platform_driver ravb_driver = {
1952 .probe = ravb_probe,
1953 .remove = ravb_remove,
1954 .driver = {
1955 .name = "ravb",
1956 .pm = RAVB_PM_OPS,
1957 .of_match_table = ravb_match_table,
1958 },
1959};
1960
1961module_platform_driver(ravb_driver);
1962
1963MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1964MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1965MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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