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Merge remote-tracking branch 'xen-tip/linux-next'
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
b2b14d2f 6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
2274d375
SS		 55#define SH_ETH_OFFSET_INVALID ((u16)~0)
56
3365711d
BH		 57#define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
c0013f6f 60static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 61 SH_ETH_OFFSET_DEFAULTS,
62
c0013f6f
SS		 63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155};
156
db893473 157static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 158 SH_ETH_OFFSET_DEFAULTS,
159
db893473
SH		 160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
e1487888 204 [TSU_FWSLC] = 0x0038,
db893473
SH		 205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
e1487888
CB		 208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
db893473 212 [TSU_ADRH0] = 0x0100,
db893473
SH		 213
214 [TXNLCR0] = 0x0080,
215 [TXALCR0] = 0x0084,
216 [RXNLCR0] = 0x0088,
217 [RXALCR0] = 0x008C,
218};
219
a3f109bd 220static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 221 SH_ETH_OFFSET_DEFAULTS,
222
a3f109bd
SS		 223 [ECMR] = 0x0300,
224 [RFLR] = 0x0308,
225 [ECSR] = 0x0310,
226 [ECSIPR] = 0x0318,
227 [PIR] = 0x0320,
228 [PSR] = 0x0328,
229 [RDMLR] = 0x0340,
230 [IPGR] = 0x0350,
231 [APR] = 0x0354,
232 [MPR] = 0x0358,
233 [RFCF] = 0x0360,
234 [TPAUSER] = 0x0364,
235 [TPAUSECR] = 0x0368,
236 [MAHR] = 0x03c0,
237 [MALR] = 0x03c8,
238 [TROCR] = 0x03d0,
239 [CDCR] = 0x03d4,
240 [LCCR] = 0x03d8,
241 [CNDCR] = 0x03dc,
242 [CEFCR] = 0x03e4,
243 [FRECR] = 0x03e8,
244 [TSFRCR] = 0x03ec,
245 [TLFRCR] = 0x03f0,
246 [RFCR] = 0x03f4,
247 [MAFCR] = 0x03f8,
248
249 [EDMR] = 0x0200,
250 [EDTRR] = 0x0208,
251 [EDRRR] = 0x0210,
252 [TDLAR] = 0x0218,
253 [RDLAR] = 0x0220,
254 [EESR] = 0x0228,
255 [EESIPR] = 0x0230,
256 [TRSCER] = 0x0238,
257 [RMFCR] = 0x0240,
258 [TFTR] = 0x0248,
259 [FDR] = 0x0250,
260 [RMCR] = 0x0258,
261 [TFUCR] = 0x0264,
262 [RFOCR] = 0x0268,
55754f19 263 [RMIIMODE] = 0x026c,
a3f109bd
SS		 264 [FCFTR] = 0x0270,
265 [TRIMD] = 0x027c,
266};
267
c0013f6f 268static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 269 SH_ETH_OFFSET_DEFAULTS,
270
c0013f6f
SS		 271 [ECMR] = 0x0100,
272 [RFLR] = 0x0108,
273 [ECSR] = 0x0110,
274 [ECSIPR] = 0x0118,
275 [PIR] = 0x0120,
276 [PSR] = 0x0128,
277 [RDMLR] = 0x0140,
278 [IPGR] = 0x0150,
279 [APR] = 0x0154,
280 [MPR] = 0x0158,
281 [TPAUSER] = 0x0164,
282 [RFCF] = 0x0160,
283 [TPAUSECR] = 0x0168,
284 [BCFRR] = 0x016c,
285 [MAHR] = 0x01c0,
286 [MALR] = 0x01c8,
287 [TROCR] = 0x01d0,
288 [CDCR] = 0x01d4,
289 [LCCR] = 0x01d8,
290 [CNDCR] = 0x01dc,
291 [CEFCR] = 0x01e4,
292 [FRECR] = 0x01e8,
293 [TSFRCR] = 0x01ec,
294 [TLFRCR] = 0x01f0,
295 [RFCR] = 0x01f4,
296 [MAFCR] = 0x01f8,
297 [RTRATE] = 0x01fc,
298
299 [EDMR] = 0x0000,
300 [EDTRR] = 0x0008,
301 [EDRRR] = 0x0010,
302 [TDLAR] = 0x0018,
303 [RDLAR] = 0x0020,
304 [EESR] = 0x0028,
305 [EESIPR] = 0x0030,
306 [TRSCER] = 0x0038,
307 [RMFCR] = 0x0040,
308 [TFTR] = 0x0048,
309 [FDR] = 0x0050,
310 [RMCR] = 0x0058,
311 [TFUCR] = 0x0064,
312 [RFOCR] = 0x0068,
313 [FCFTR] = 0x0070,
314 [RPADIR] = 0x0078,
315 [TRIMD] = 0x007c,
316 [RBWAR] = 0x00c8,
317 [RDFAR] = 0x00cc,
318 [TBRAR] = 0x00d4,
319 [TDFAR] = 0x00d8,
320};
321
322static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 323 SH_ETH_OFFSET_DEFAULTS,
324
d8b0426a
SS		 325 [EDMR] = 0x0000,
326 [EDTRR] = 0x0004,
327 [EDRRR] = 0x0008,
328 [TDLAR] = 0x000c,
329 [RDLAR] = 0x0010,
330 [EESR] = 0x0014,
331 [EESIPR] = 0x0018,
332 [TRSCER] = 0x001c,
333 [RMFCR] = 0x0020,
334 [TFTR] = 0x0024,
335 [FDR] = 0x0028,
336 [RMCR] = 0x002c,
337 [EDOCR] = 0x0030,
338 [FCFTR] = 0x0034,
339 [RPADIR] = 0x0038,
340 [TRIMD] = 0x003c,
341 [RBWAR] = 0x0040,
342 [RDFAR] = 0x0044,
343 [TBRAR] = 0x004c,
344 [TDFAR] = 0x0050,
345
c0013f6f
SS		 346 [ECMR] = 0x0160,
347 [ECSR] = 0x0164,
348 [ECSIPR] = 0x0168,
349 [PIR] = 0x016c,
350 [MAHR] = 0x0170,
351 [MALR] = 0x0174,
352 [RFLR] = 0x0178,
353 [PSR] = 0x017c,
354 [TROCR] = 0x0180,
355 [CDCR] = 0x0184,
356 [LCCR] = 0x0188,
357 [CNDCR] = 0x018c,
358 [CEFCR] = 0x0194,
359 [FRECR] = 0x0198,
360 [TSFRCR] = 0x019c,
361 [TLFRCR] = 0x01a0,
362 [RFCR] = 0x01a4,
363 [MAFCR] = 0x01a8,
364 [IPGR] = 0x01b4,
365 [APR] = 0x01b8,
366 [MPR] = 0x01bc,
367 [TPAUSER] = 0x01c4,
368 [BCFR] = 0x01cc,
369
370 [ARSTR] = 0x0000,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
374 [TSU_FCM] = 0x0018,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
386 [TSU_FWSR] = 0x0050,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
389 [TSU_TEN] = 0x0064,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
394
395 [TXNLCR0] = 0x0080,
396 [TXALCR0] = 0x0084,
397 [RXNLCR0] = 0x0088,
398 [RXALCR0] = 0x008c,
399 [FWNLCR0] = 0x0090,
400 [FWALCR0] = 0x0094,
401 [TXNLCR1] = 0x00a0,
402 [TXALCR1] = 0x00a0,
403 [RXNLCR1] = 0x00a8,
404 [RXALCR1] = 0x00ac,
405 [FWNLCR1] = 0x00b0,
406 [FWALCR1] = 0x00b4,
407
408 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 409};
410
740c7f31
BH		 411static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413
2274d375
SS		 414static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415{
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
418
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
420 return;
421
422 iowrite32(data, mdp->addr + offset);
423}
424
425static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426{
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
429
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
431 return ~0U;
432
433 return ioread32(mdp->addr + offset);
434}
435
b2b14d2f
SS		 436static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
437 u32 set)
438{
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
440 enum_index);
441}
442
504c8ca5 443static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 444{
504c8ca5 445 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 446}
447
db893473
SH		 448static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
449{
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
451}
452
8e994402 453static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 454{
5e7a76be 455 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 456 u32 value;
5e7a76be
NI		 457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
f75f14ec
SS		 469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476}
5e7a76be 477
8e994402 478static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 479{
480 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 481
b2b14d2f 482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 483}
484
99f84be6
GU		 485static void sh_eth_chip_reset(struct net_device *ndev)
486{
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
ec65cfce 490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
99f84be6
GU		 491 mdelay(1);
492}
493
a0f48be3
GU		 494static void sh_eth_set_rate_gether(struct net_device *ndev)
495{
496 struct sh_eth_private *mdp = netdev_priv(ndev);
497
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
501 break;
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
504 break;
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
507 break;
a0f48be3
GU		 508 }
509}
510
99f84be6
GU		 511#ifdef CONFIG_OF
512/* R7S72100 */
513static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
516
517 .register_type = SH_ETH_REG_FAST_RZ,
518
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
521 .eesipr_value = 0xff7f009f,
522
523 .tx_check = EESR_TC1 | EESR_FTC,
524 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
525 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
526 EESR_TDE | EESR_ECI,
527 .fdr_value = 0x0000070f,
528
529 .no_psr = 1,
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534 .rpadir = 1,
535 .rpadir_value = 2 << 16,
536 .no_trimd = 1,
537 .no_ade = 1,
538 .hw_crc = 1,
539 .tsu = 1,
540 .shift_rd0 = 1,
541};
a0f48be3
GU		 542
543static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
544{
c66b2581 545 sh_eth_chip_reset(ndev);
a0f48be3
GU		 546
547 sh_eth_select_mii(ndev);
548}
549
550/* R8A7740 */
551static struct sh_eth_cpu_data r8a7740_data = {
552 .chip_reset = sh_eth_chip_reset_r8a7740,
553 .set_duplex = sh_eth_set_duplex,
554 .set_rate = sh_eth_set_rate_gether,
555
556 .register_type = SH_ETH_REG_GIGABIT,
557
558 .ecsr_value = ECSR_ICD | ECSR_MPD,
559 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
560 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
561
562 .tx_check = EESR_TC1 | EESR_FTC,
563 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
564 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
565 EESR_TDE | EESR_ECI,
566 .fdr_value = 0x0000070f,
567
568 .apr = 1,
569 .mpr = 1,
570 .tpauser = 1,
571 .bculr = 1,
572 .hw_swap = 1,
573 .rpadir = 1,
574 .rpadir_value = 2 << 16,
575 .no_trimd = 1,
576 .no_ade = 1,
577 .tsu = 1,
578 .select_mii = 1,
579 .shift_rd0 = 1,
580};
99f84be6 581
04b0ed2a 582/* There is CPU dependent code */
589ebdef 583static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 584{
585 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 586
a3f109bd
SS		 587 switch (mdp->speed) {
588 case 10: /* 10BASE */
b2b14d2f 589 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 590 break;
591 case 100:/* 100BASE */
b2b14d2f 592 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 593 break;
a3f109bd
SS		 594 }
595}
596
674853b2 597/* R8A7778/9 */
589ebdef 598static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 599 .set_duplex = sh_eth_set_duplex,
589ebdef 600 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 601
a3153d8c
SS		 602 .register_type = SH_ETH_REG_FAST_RCAR,
603
a3f109bd
SS		 604 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
605 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
606 .eesipr_value = 0x01ff009f,
607
608 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 609 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
610 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
611 EESR_ECI,
d407bc02 612 .fdr_value = 0x00000f0f,
a3f109bd
SS		 613
614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618};
a3f109bd 619
94a12b15
SS		 620/* R8A7790/1 */
621static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_r8a777x,
624
a3153d8c
SS		 625 .register_type = SH_ETH_REG_FAST_RCAR,
626
e18dbf7e
SH		 627 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
628 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
629 .eesipr_value = 0x01ff009f,
630
631 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 632 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
633 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
634 EESR_ECI,
d407bc02 635 .fdr_value = 0x00000f0f,
e18dbf7e 636
01fbd3f5
GU		 637 .trscer_err_mask = DESC_I_RINT8,
638
e18dbf7e
SH		 639 .apr = 1,
640 .mpr = 1,
641 .tpauser = 1,
642 .hw_swap = 1,
643 .rmiimode = 1,
644};
c74a2248 645#endif /* CONFIG_OF */
e18dbf7e 646
9c3beaab 647static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 648{
649 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 650
651 switch (mdp->speed) {
652 case 10: /* 10BASE */
b2b14d2f 653 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 654 break;
655 case 100:/* 100BASE */
b2b14d2f 656 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 657 break;
65ac8851
YS		 658 }
659}
660
661/* SH7724 */
9c3beaab 662static struct sh_eth_cpu_data sh7724_data = {
65ac8851 663 .set_duplex = sh_eth_set_duplex,
9c3beaab 664 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 665
a3153d8c
SS		 666 .register_type = SH_ETH_REG_FAST_SH4,
667
65ac8851
YS		 668 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
669 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 670 .eesipr_value = 0x01ff009f,
65ac8851
YS		 671
672 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 673 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
674 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
675 EESR_ECI,
65ac8851
YS		 676
677 .apr = 1,
678 .mpr = 1,
679 .tpauser = 1,
680 .hw_swap = 1,
503914cf
MD		 681 .rpadir = 1,
682 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 683};
5cee1d37 684
24549e2a 685static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 686{
687 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 688
689 switch (mdp->speed) {
690 case 10: /* 10BASE */
4a55530f 691 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 692 break;
693 case 100:/* 100BASE */
4a55530f 694 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 695 break;
f29a3d04
YS		 696 }
697}
698
699/* SH7757 */
24549e2a
SS		 700static struct sh_eth_cpu_data sh7757_data = {
701 .set_duplex = sh_eth_set_duplex,
702 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 703
a3153d8c
SS		 704 .register_type = SH_ETH_REG_FAST_SH4,
705
f29a3d04 706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 707
708 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 709 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
710 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
711 EESR_ECI,
f29a3d04 712
5b3dfd13 713 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 714 .apr = 1,
715 .mpr = 1,
716 .tpauser = 1,
717 .hw_swap = 1,
718 .no_ade = 1,
2e98e797
YS		 719 .rpadir = 1,
720 .rpadir_value = 2 << 16,
6b4b4fea 721 .rtrate = 1,
f29a3d04 722};
65ac8851 723
e403d295 724#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 725#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
726#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
727static void sh_eth_chip_reset_giga(struct net_device *ndev)
728{
0799c2d6 729 u32 mahr[2], malr[2];
79270922 730 int i;
8fcd4961
YS		 731
732 /* save MAHR and MALR */
733 for (i = 0; i < 2; i++) {
ae70644d
YS		 734 malr[i] = ioread32((void *)GIGA_MALR(i));
735 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 736 }
737
c66b2581 738 sh_eth_chip_reset(ndev);
8fcd4961
YS		 739
740 /* restore MAHR and MALR */
741 for (i = 0; i < 2; i++) {
ae70644d
YS		 742 iowrite32(malr[i], (void *)GIGA_MALR(i));
743 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 744 }
745}
746
8fcd4961
YS		 747static void sh_eth_set_rate_giga(struct net_device *ndev)
748{
749 struct sh_eth_private *mdp = netdev_priv(ndev);
750
751 switch (mdp->speed) {
752 case 10: /* 10BASE */
753 sh_eth_write(ndev, 0x00000000, GECMR);
754 break;
755 case 100:/* 100BASE */
756 sh_eth_write(ndev, 0x00000010, GECMR);
757 break;
758 case 1000: /* 1000BASE */
759 sh_eth_write(ndev, 0x00000020, GECMR);
760 break;
8fcd4961
YS		 761 }
762}
763
764/* SH7757(GETHERC) */
24549e2a 765static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 766 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 767 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 768 .set_rate = sh_eth_set_rate_giga,
769
a3153d8c
SS		 770 .register_type = SH_ETH_REG_GIGABIT,
771
8fcd4961
YS		 772 .ecsr_value = ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
774 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
775
776 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 777 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
778 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
779 EESR_TDE | EESR_ECI,
8fcd4961 780 .fdr_value = 0x0000072f,
8fcd4961 781
5b3dfd13 782 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 783 .apr = 1,
784 .mpr = 1,
785 .tpauser = 1,
786 .bculr = 1,
787 .hw_swap = 1,
788 .rpadir = 1,
789 .rpadir_value = 2 << 16,
790 .no_trimd = 1,
791 .no_ade = 1,
3acbc971 792 .tsu = 1,
8fcd4961
YS		 793};
794
f5d12767
SS		 795/* SH7734 */
796static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 797 .chip_reset = sh_eth_chip_reset,
798 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 799 .set_rate = sh_eth_set_rate_gether,
800
a3153d8c
SS		 801 .register_type = SH_ETH_REG_GIGABIT,
802
f5d12767
SS		 803 .ecsr_value = ECSR_ICD | ECSR_MPD,
804 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
805 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
806
807 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 808 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
809 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
810 EESR_TDE | EESR_ECI,
f5d12767
SS		 811
812 .apr = 1,
813 .mpr = 1,
814 .tpauser = 1,
815 .bculr = 1,
816 .hw_swap = 1,
817 .no_trimd = 1,
818 .no_ade = 1,
819 .tsu = 1,
820 .hw_crc = 1,
821 .select_mii = 1,
822};
823
824/* SH7763 */
825static struct sh_eth_cpu_data sh7763_data = {
826 .chip_reset = sh_eth_chip_reset,
827 .set_duplex = sh_eth_set_duplex,
828 .set_rate = sh_eth_set_rate_gether,
380af9e3 829
a3153d8c
SS		 830 .register_type = SH_ETH_REG_GIGABIT,
831
380af9e3
YS		 832 .ecsr_value = ECSR_ICD | ECSR_MPD,
833 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
834 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
835
836 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 837 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
838 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 839 EESR_ECI,
380af9e3
YS		 840
841 .apr = 1,
842 .mpr = 1,
843 .tpauser = 1,
844 .bculr = 1,
845 .hw_swap = 1,
380af9e3
YS		 846 .no_trimd = 1,
847 .no_ade = 1,
4986b996 848 .tsu = 1,
5b3dfd13 849 .irq_flags = IRQF_SHARED,
380af9e3
YS		 850};
851
c18a79ab 852static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 853 .register_type = SH_ETH_REG_FAST_SH3_SH2,
854
380af9e3
YS		 855 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
856
857 .apr = 1,
858 .mpr = 1,
859 .tpauser = 1,
860 .hw_swap = 1,
861};
7bbe150d
SS		 862
863static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 864 .register_type = SH_ETH_REG_FAST_SH3_SH2,
865
380af9e3 866 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 867 .tsu = 1,
380af9e3 868};
380af9e3
YS		 869
870static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
871{
872 if (!cd->ecsr_value)
873 cd->ecsr_value = DEFAULT_ECSR_INIT;
874
875 if (!cd->ecsipr_value)
876 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
877
878 if (!cd->fcftr_value)
128296fc 879 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 880 DEFAULT_FIFO_F_D_RFD;
881
882 if (!cd->fdr_value)
883 cd->fdr_value = DEFAULT_FDR_INIT;
884
380af9e3
YS		 885 if (!cd->tx_check)
886 cd->tx_check = DEFAULT_TX_CHECK;
887
888 if (!cd->eesr_err_check)
889 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 890
891 if (!cd->trscer_err_mask)
892 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 893}
894
5cee1d37
NI		 895static int sh_eth_check_reset(struct net_device *ndev)
896{
897 int ret = 0;
898 int cnt = 100;
899
900 while (cnt > 0) {
97717edc 901 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
5cee1d37
NI		 902 break;
903 mdelay(1);
904 cnt--;
905 }
9f8c4265 906 if (cnt <= 0) {
f75f14ec 907 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 908 ret = -ETIMEDOUT;
909 }
910 return ret;
380af9e3 911}
dabdde9e
NI		 912
913static int sh_eth_reset(struct net_device *ndev)
914{
915 struct sh_eth_private *mdp = netdev_priv(ndev);
916 int ret = 0;
917
db893473 918 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e 919 sh_eth_write(ndev, EDSR_ENALL, EDSR);
b2b14d2f 920 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
dabdde9e
NI		 921
922 ret = sh_eth_check_reset(ndev);
923 if (ret)
f738a13d 924 return ret;
dabdde9e
NI		 925
926 /* Table Init */
927 sh_eth_write(ndev, 0x0, TDLAR);
928 sh_eth_write(ndev, 0x0, TDFAR);
929 sh_eth_write(ndev, 0x0, TDFXR);
930 sh_eth_write(ndev, 0x0, TDFFR);
931 sh_eth_write(ndev, 0x0, RDLAR);
932 sh_eth_write(ndev, 0x0, RDFAR);
933 sh_eth_write(ndev, 0x0, RDFXR);
934 sh_eth_write(ndev, 0x0, RDFFR);
935
936 /* Reset HW CRC register */
937 if (mdp->cd->hw_crc)
938 sh_eth_write(ndev, 0x0, CSMR);
939
940 /* Select MII mode */
941 if (mdp->cd->select_mii)
942 sh_eth_select_mii(ndev);
943 } else {
b2b14d2f 944 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
dabdde9e 945 mdelay(3);
b2b14d2f 946 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
dabdde9e
NI		 947 }
948
dabdde9e
NI		 949 return ret;
950}
380af9e3 951
380af9e3
YS		 952static void sh_eth_set_receive_align(struct sk_buff *skb)
953{
4d6a949c 954 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 955
380af9e3 956 if (reserve)
4d6a949c 957 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 958}
380af9e3 959
128296fc 960/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 961static void update_mac_address(struct net_device *ndev)
962{
4a55530f 963 sh_eth_write(ndev,
128296fc
SS		 964 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
965 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 966 sh_eth_write(ndev,
128296fc 967 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 968}
969
128296fc 970/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 971 *
972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
974 * When you want use this device, you must set MAC address in bootloader.
975 *
976 */
748031f9 977static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 978{
748031f9 979 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 980 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 981 } else {
37742f02
SS		 982 u32 mahr = sh_eth_read(ndev, MAHR);
983 u32 malr = sh_eth_read(ndev, MALR);
984
985 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
986 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
987 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
988 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
989 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
990 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 991 }
86a74ff2
NI		 992}
993
0799c2d6 994static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 995{
db893473 996 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 997 return EDTRR_TRNS_GETHER;
998 else
999 return EDTRR_TRNS_ETHER;
1000}
1001
86a74ff2 1002struct bb_info {
ae70644d 1003 void (*set_gate)(void *addr);
86a74ff2 1004 struct mdiobb_ctrl ctrl;
ae70644d 1005 void *addr;
86a74ff2
NI		 1006};
1007
39b4b06b 1008static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1009{
1010 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1011 u32 pir;
b3017e6a
YS		 1012
1013 if (bitbang->set_gate)
1014 bitbang->set_gate(bitbang->addr);
1015
78fa3c5c 1016 pir = ioread32(bitbang->addr);
39b4b06b 1017 if (set)
78fa3c5c 1018 pir |= mask;
86a74ff2 1019 else
78fa3c5c
SS		 1020 pir &= ~mask;
1021 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1022}
1023
1024/* Data I/O pin control */
1025static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1026{
1027 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1028}
1029
1030/* Set bit data*/
1031static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1032{
39b4b06b 1033 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1034}
1035
1036/* Get bit data*/
1037static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1038{
1039 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1040
1041 if (bitbang->set_gate)
1042 bitbang->set_gate(bitbang->addr);
1043
78fa3c5c 1044 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1045}
1046
1047/* MDC pin control */
1048static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1049{
39b4b06b 1050 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1051}
1052
1053/* mdio bus control struct */
1054static struct mdiobb_ops bb_ops = {
1055 .owner = THIS_MODULE,
1056 .set_mdc = sh_mdc_ctrl,
1057 .set_mdio_dir = sh_mmd_ctrl,
1058 .set_mdio_data = sh_set_mdio,
1059 .get_mdio_data = sh_get_mdio,
1060};
1061
86a74ff2
NI		 1062/* free skb and descriptor buffer */
1063static void sh_eth_ring_free(struct net_device *ndev)
1064{
1065 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1066 int ringsize, i;
86a74ff2
NI		 1067
1068 /* Free Rx skb ringbuffer */
1069 if (mdp->rx_skbuff) {
179d80af
SS		 1070 for (i = 0; i < mdp->num_rx_ring; i++)
1071 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1072 }
1073 kfree(mdp->rx_skbuff);
91c77550 1074 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1075
1076 /* Free Tx skb ringbuffer */
1077 if (mdp->tx_skbuff) {
179d80af
SS		 1078 for (i = 0; i < mdp->num_tx_ring; i++)
1079 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1080 }
1081 kfree(mdp->tx_skbuff);
91c77550 1082 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1083
1084 if (mdp->rx_ring) {
1085 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1086 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1087 mdp->rx_desc_dma);
1088 mdp->rx_ring = NULL;
1089 }
1090
1091 if (mdp->tx_ring) {
1092 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1093 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1094 mdp->tx_desc_dma);
1095 mdp->tx_ring = NULL;
1096 }
86a74ff2
NI		 1097}
1098
1099/* format skb and descriptor buffer */
1100static void sh_eth_ring_format(struct net_device *ndev)
1101{
1102 struct sh_eth_private *mdp = netdev_priv(ndev);
1103 int i;
1104 struct sk_buff *skb;
1105 struct sh_eth_rxdesc *rxdesc = NULL;
1106 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1107 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1108 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1109 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1110 dma_addr_t dma_addr;
5cbf20c7 1111 u32 buf_len;
86a74ff2 1112
128296fc
SS		 1113 mdp->cur_rx = 0;
1114 mdp->cur_tx = 0;
1115 mdp->dirty_rx = 0;
1116 mdp->dirty_tx = 0;
86a74ff2
NI		 1117
1118 memset(mdp->rx_ring, 0, rx_ringsize);
1119
1120 /* build Rx ring buffer */
525b8075 1121 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1122 /* skb */
1123 mdp->rx_skbuff[i] = NULL;
4d6a949c 1124 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1125 if (skb == NULL)
1126 break;
380af9e3
YS		 1127 sh_eth_set_receive_align(skb);
1128
ab857916 1129 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1130 buf_len = ALIGN(mdp->rx_buf_sz, 32);
5cbf20c7 1131 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
52b9fa36
BH		 1132 DMA_FROM_DEVICE);
1133 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1134 kfree_skb(skb);
1135 break;
1136 }
1137 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1138
1139 /* RX descriptor */
1140 rxdesc = &mdp->rx_ring[i];
1141 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1142 rxdesc->addr = cpu_to_le32(dma_addr);
1143 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1144
b0ca2a21
NI		 1145 /* Rx descriptor address set */
1146 if (i == 0) {
4a55530f 1147 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1148 if (sh_eth_is_gether(mdp) ||
1149 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1150 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1151 }
86a74ff2
NI		 1152 }
1153
525b8075 1154 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1155
1156 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1157 if (rxdesc)
1158 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1159
1160 memset(mdp->tx_ring, 0, tx_ringsize);
1161
1162 /* build Tx ring buffer */
525b8075 1163 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1164 mdp->tx_skbuff[i] = NULL;
1165 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1166 txdesc->status = cpu_to_le32(TD_TFP);
1167 txdesc->len = cpu_to_le32(0);
b0ca2a21 1168 if (i == 0) {
71557a37 1169 /* Tx descriptor address set */
4a55530f 1170 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1171 if (sh_eth_is_gether(mdp) ||
1172 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1173 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1174 }
86a74ff2
NI		 1175 }
1176
7cf72477 1177 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1178}
1179
1180/* Get skb and descriptor buffer */
1181static int sh_eth_ring_init(struct net_device *ndev)
1182{
1183 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1184 int rx_ringsize, tx_ringsize;
86a74ff2 1185
128296fc 1186 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1187 * card needs room to do 8 byte alignment, +2 so we can reserve
1188 * the first 2 bytes, and +16 gets room for the status word from the
1189 * card.
1190 */
1191 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1192 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1193 if (mdp->cd->rpadir)
1194 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1195
1196 /* Allocate RX and TX skb rings */
2c94e856
SS		 1197 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1198 GFP_KERNEL);
91d80683
SS		 1199 if (!mdp->rx_skbuff)
1200 return -ENOMEM;
86a74ff2 1201
2c94e856
SS		 1202 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1203 GFP_KERNEL);
91d80683 1204 if (!mdp->tx_skbuff)
8e03a5e7 1205 goto ring_free;
86a74ff2
NI		 1206
1207 /* Allocate all Rx descriptors. */
525b8075 1208 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1209 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1210 GFP_KERNEL);
91d80683 1211 if (!mdp->rx_ring)
8e03a5e7 1212 goto ring_free;
86a74ff2
NI		 1213
1214 mdp->dirty_rx = 0;
1215
1216 /* Allocate all Tx descriptors. */
525b8075 1217 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1218 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1219 GFP_KERNEL);
91d80683 1220 if (!mdp->tx_ring)
8e03a5e7 1221 goto ring_free;
91d80683 1222 return 0;
86a74ff2 1223
8e03a5e7
SS		 1224ring_free:
1225 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1226 sh_eth_ring_free(ndev);
1227
91d80683 1228 return -ENOMEM;
86a74ff2
NI		 1229}
1230
f7967210 1231static int sh_eth_dev_init(struct net_device *ndev)
86a74ff2 1232{
86a74ff2 1233 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1234 int ret;
86a74ff2
NI		 1235
1236 /* Soft Reset */
5cee1d37
NI		 1237 ret = sh_eth_reset(ndev);
1238 if (ret)
f738a13d 1239 return ret;
86a74ff2 1240
55754f19
SH		 1241 if (mdp->cd->rmiimode)
1242 sh_eth_write(ndev, 0x1, RMIIMODE);
1243
b0ca2a21
NI		 1244 /* Descriptor format */
1245 sh_eth_ring_format(ndev);
380af9e3 1246 if (mdp->cd->rpadir)
4a55530f 1247 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1248
1249 /* all sh_eth int mask */
4a55530f 1250 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1251
10b9194f 1252#if defined(__LITTLE_ENDIAN)
380af9e3 1253 if (mdp->cd->hw_swap)
4a55530f 1254 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1255 else
b0ca2a21 1256#endif
4a55530f 1257 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1258
b0ca2a21 1259 /* FIFO size set */
4a55530f
YS		 1260 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1261 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1262
530aa2d0
BD		 1263 /* Frame recv control (enable multiple-packets per rx irq) */
1264 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1265
b284fbe3 1266 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1267
380af9e3 1268 if (mdp->cd->bculr)
4a55530f 1269 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1270
4a55530f 1271 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1272
380af9e3 1273 if (!mdp->cd->no_trimd)
4a55530f 1274 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1275
b0ca2a21 1276 /* Recv frame limit set register */
fdb37a7f
YS		 1277 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1278 RFLR);
86a74ff2 1279
b2b14d2f 1280 sh_eth_modify(ndev, EESR, 0, 0);
f7967210
SS		 1281 mdp->irq_enabled = true;
1282 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1283
1284 /* PAUSE Prohibition */
bffa731f
SS		 1285 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1286 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1287
380af9e3
YS		 1288 if (mdp->cd->set_rate)
1289 mdp->cd->set_rate(ndev);
1290
b0ca2a21 1291 /* E-MAC Status Register clear */
4a55530f 1292 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1293
1294 /* E-MAC Interrupt Enable register */
f7967210 1295 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1296
1297 /* Set MAC address */
1298 update_mac_address(ndev);
1299
1300 /* mask reset */
380af9e3 1301 if (mdp->cd->apr)
4a55530f 1302 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1303 if (mdp->cd->mpr)
4a55530f 1304 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1305 if (mdp->cd->tpauser)
4a55530f 1306 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1307
f7967210
SS		 1308 /* Setting the Rx mode will start the Rx process. */
1309 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 1310
1311 return ret;
1312}
1313
740c7f31
BH		 1314static void sh_eth_dev_exit(struct net_device *ndev)
1315{
1316 struct sh_eth_private *mdp = netdev_priv(ndev);
1317 int i;
1318
1319 /* Deactivate all TX descriptors, so DMA should stop at next
1320 * packet boundary if it's currently running
1321 */
1322 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1323 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1324
1325 /* Disable TX FIFO egress to MAC */
1326 sh_eth_rcv_snd_disable(ndev);
1327
1328 /* Stop RX DMA at next packet boundary */
1329 sh_eth_write(ndev, 0, EDRRR);
1330
1331 /* Aside from TX DMA, we can't tell when the hardware is
1332 * really stopped, so we need to reset to make sure.
1333 * Before doing that, wait for long enough to *probably*
1334 * finish transmitting the last packet and poll stats.
1335 */
1336 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1337 sh_eth_get_stats(ndev);
1338 sh_eth_reset(ndev);
a14c7d15
GU		 1339
1340 /* Set MAC address again */
1341 update_mac_address(ndev);
740c7f31
BH		 1342}
1343
86a74ff2
NI		 1344/* free Tx skb function */
1345static int sh_eth_txfree(struct net_device *ndev)
1346{
1347 struct sh_eth_private *mdp = netdev_priv(ndev);
1348 struct sh_eth_txdesc *txdesc;
128296fc 1349 int free_num = 0;
4fa8c3cc 1350 int entry;
86a74ff2
NI		 1351
1352 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1353 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1354 txdesc = &mdp->tx_ring[entry];
7cf72477 1355 if (txdesc->status & cpu_to_le32(TD_TACT))
86a74ff2 1356 break;
7d7355f5 1357 /* TACT bit must be checked before all the following reads */
f32bfb9a 1358 dma_rmb();
e5fd13f4
BH		 1359 netif_info(mdp, tx_done, ndev,
1360 "tx entry %d status 0x%08x\n",
7cf72477 1361 entry, le32_to_cpu(txdesc->status));
86a74ff2
NI		 1362 /* Free the original skb. */
1363 if (mdp->tx_skbuff[entry]) {
7cf72477
SS		 1364 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1365 le32_to_cpu(txdesc->len) >> 16,
5cbf20c7 1366 DMA_TO_DEVICE);
86a74ff2
NI		 1367 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1368 mdp->tx_skbuff[entry] = NULL;
128296fc 1369 free_num++;
86a74ff2 1370 }
7cf72477 1371 txdesc->status = cpu_to_le32(TD_TFP);
525b8075 1372 if (entry >= mdp->num_tx_ring - 1)
7cf72477 1373 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2 1374
bb7d92e3 1375 ndev->stats.tx_packets++;
7cf72477 1376 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
86a74ff2 1377 }
128296fc 1378 return free_num;
86a74ff2
NI		 1379}
1380
1381/* Packet receive function */
3719109d 1382static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1383{
1384 struct sh_eth_private *mdp = netdev_priv(ndev);
1385 struct sh_eth_rxdesc *rxdesc;
1386
525b8075
YS		 1387 int entry = mdp->cur_rx % mdp->num_rx_ring;
1388 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1389 int limit;
86a74ff2 1390 struct sk_buff *skb;
380af9e3 1391 u32 desc_status;
cb368595 1392 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1393 dma_addr_t dma_addr;
4fa8c3cc 1394 u16 pkt_len;
5cbf20c7 1395 u32 buf_len;
86a74ff2 1396
319cd520
MK		 1397 boguscnt = min(boguscnt, *quota);
1398 limit = boguscnt;
86a74ff2 1399 rxdesc = &mdp->rx_ring[entry];
7cf72477 1400 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1401 /* RACT bit must be checked before all the following reads */
f32bfb9a 1402 dma_rmb();
7cf72477
SS		 1403 desc_status = le32_to_cpu(rxdesc->status);
1404 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1405
1406 if (--boguscnt < 0)
1407 break;
1408
e5fd13f4
BH		 1409 netif_info(mdp, rx_status, ndev,
1410 "rx entry %d status 0x%08x len %d\n",
1411 entry, desc_status, pkt_len);
1412
86a74ff2 1413 if (!(desc_status & RDFEND))
bb7d92e3 1414 ndev->stats.rx_length_errors++;
86a74ff2 1415
128296fc 1416 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1417 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1418 * bit 0. However, in case of the R8A7740 and R7S72100
1419 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1420 * driver needs right shifting by 16.
dd019897 1421 */
ac8025a6
SS		 1422 if (mdp->cd->shift_rd0)
1423 desc_status >>= 16;
dd019897 1424
248be83d 1425 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1426 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1427 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1428 ndev->stats.rx_errors++;
86a74ff2 1429 if (desc_status & RD_RFS1)
bb7d92e3 1430 ndev->stats.rx_crc_errors++;
86a74ff2 1431 if (desc_status & RD_RFS2)
bb7d92e3 1432 ndev->stats.rx_frame_errors++;
86a74ff2 1433 if (desc_status & RD_RFS3)
bb7d92e3 1434 ndev->stats.rx_length_errors++;
86a74ff2 1435 if (desc_status & RD_RFS4)
bb7d92e3 1436 ndev->stats.rx_length_errors++;
86a74ff2 1437 if (desc_status & RD_RFS6)
bb7d92e3 1438 ndev->stats.rx_missed_errors++;
86a74ff2 1439 if (desc_status & RD_RFS10)
bb7d92e3 1440 ndev->stats.rx_over_errors++;
248be83d 1441 } else if (skb) {
7cf72477 1442 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1443 if (!mdp->cd->hw_swap)
1444 sh_eth_soft_swap(
1299653a 1445 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1446 pkt_len + 2);
86a74ff2 1447 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1448 if (mdp->cd->rpadir)
1449 skb_reserve(skb, NET_IP_ALIGN);
1299653a 1450 dma_unmap_single(&ndev->dev, dma_addr,
ab857916 1451 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1452 DMA_FROM_DEVICE);
86a74ff2
NI		 1453 skb_put(skb, pkt_len);
1454 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1455 netif_receive_skb(skb);
bb7d92e3
ED		 1456 ndev->stats.rx_packets++;
1457 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1458 if (desc_status & RD_RFS8)
1459 ndev->stats.multicast++;
86a74ff2 1460 }
525b8075 1461 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1462 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1463 }
1464
1465 /* Refill the Rx ring buffers. */
1466 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1467 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1468 rxdesc = &mdp->rx_ring[entry];
ab857916 1469 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1470 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1471 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1472
86a74ff2 1473 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1474 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1475 if (skb == NULL)
1476 break; /* Better luck next round. */
380af9e3 1477 sh_eth_set_receive_align(skb);
52b9fa36 1478 dma_addr = dma_map_single(&ndev->dev, skb->data,
5cbf20c7 1479 buf_len, DMA_FROM_DEVICE);
52b9fa36
BH		 1480 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1481 kfree_skb(skb);
1482 break;
1483 }
1484 mdp->rx_skbuff[entry] = skb;
380af9e3 1485
bc8acf2c 1486 skb_checksum_none_assert(skb);
7cf72477 1487 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1488 }
f32bfb9a 1489 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1490 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1491 rxdesc->status |=
7cf72477 1492 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1493 else
7cf72477 1494 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1495 }
1496
1497 /* Restart Rx engine if stopped. */
1498 /* If we don't need to check status, don't. -KDU */
79fba9f5 1499 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1500 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1501 if (intr_status & EESR_RDE &&
1502 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1503 u32 count = (sh_eth_read(ndev, RDFAR) -
1504 sh_eth_read(ndev, RDLAR)) >> 4;
1505
1506 mdp->cur_rx = count;
1507 mdp->dirty_rx = count;
1508 }
4a55530f 1509 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1510 }
86a74ff2 1511
319cd520
MK		 1512 *quota -= limit - boguscnt - 1;
1513
4f809cea 1514 return *quota <= 0;
86a74ff2
NI		 1515}
1516
4a55530f 1517static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1518{
1519 /* disable tx and rx */
b2b14d2f 1520 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1521}
1522
4a55530f 1523static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1524{
1525 /* enable tx and rx */
b2b14d2f 1526 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1527}
1528
86a74ff2 1529/* error control function */
0799c2d6 1530static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1531{
1532 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1533 u32 felic_stat;
380af9e3
YS		 1534 u32 link_stat;
1535 u32 mask;
86a74ff2
NI		 1536
1537 if (intr_status & EESR_ECI) {
4a55530f
YS		 1538 felic_stat = sh_eth_read(ndev, ECSR);
1539 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1540 if (felic_stat & ECSR_ICD)
bb7d92e3 1541 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1542 if (felic_stat & ECSR_LCHNG) {
1543 /* Link Changed */
4923576b 1544 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1545 goto ignore_link;
380af9e3 1546 } else {
4a55530f 1547 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1548 if (mdp->ether_link_active_low)
1549 link_stat = ~link_stat;
380af9e3 1550 }
128296fc 1551 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1552 sh_eth_rcv_snd_disable(ndev);
128296fc 1553 } else {
86a74ff2 1554 /* Link Up */
b2b14d2f 1555 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
128296fc 1556 /* clear int */
b2b14d2f
SS		 1557 sh_eth_modify(ndev, ECSR, 0, 0);
1558 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1559 DMAC_M_ECI);
86a74ff2 1560 /* enable tx and rx */
4a55530f 1561 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1562 }
1563 }
1564 }
1565
1e1b812b 1566ignore_link:
86a74ff2 1567 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1568 /* Unused write back interrupt */
1569 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1570 ndev->stats.tx_aborted_errors++;
8d5009f6 1571 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1572 }
86a74ff2
NI		 1573 }
1574
1575 if (intr_status & EESR_RABT) {
1576 /* Receive Abort int */
1577 if (intr_status & EESR_RFRMER) {
1578 /* Receive Frame Overflow int */
bb7d92e3 1579 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1580 }
1581 }
380af9e3 1582
dc19e4e5
NI		 1583 if (intr_status & EESR_TDE) {
1584 /* Transmit Descriptor Empty int */
bb7d92e3 1585 ndev->stats.tx_fifo_errors++;
8d5009f6 1586 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1587 }
1588
1589 if (intr_status & EESR_TFE) {
1590 /* FIFO under flow */
bb7d92e3 1591 ndev->stats.tx_fifo_errors++;
8d5009f6 1592 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1593 }
1594
1595 if (intr_status & EESR_RDE) {
1596 /* Receive Descriptor Empty int */
bb7d92e3 1597 ndev->stats.rx_over_errors++;
86a74ff2 1598 }
dc19e4e5 1599
86a74ff2
NI		 1600 if (intr_status & EESR_RFE) {
1601 /* Receive FIFO Overflow int */
bb7d92e3 1602 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1603 }
1604
1605 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1606 /* Address Error */
bb7d92e3 1607 ndev->stats.tx_fifo_errors++;
8d5009f6 1608 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1609 }
380af9e3
YS		 1610
1611 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1612 if (mdp->cd->no_ade)
1613 mask &= ~EESR_ADE;
1614 if (intr_status & mask) {
86a74ff2 1615 /* Tx error */
4a55530f 1616 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1617
86a74ff2 1618 /* dmesg */
da246855
SS		 1619 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1620 intr_status, mdp->cur_tx, mdp->dirty_tx,
1621 (u32)ndev->state, edtrr);
86a74ff2
NI		 1622 /* dirty buffer free */
1623 sh_eth_txfree(ndev);
1624
1625 /* SH7712 BUG */
c5ed5368 1626 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1627 /* tx dma start */
c5ed5368 1628 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1629 }
1630 /* wakeup */
1631 netif_wake_queue(ndev);
1632 }
1633}
1634
1635static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1636{
1637 struct net_device *ndev = netdev;
1638 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1639 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1640 irqreturn_t ret = IRQ_NONE;
0799c2d6 1641 u32 intr_status, intr_enable;
86a74ff2 1642
86a74ff2
NI		 1643 spin_lock(&mdp->lock);
1644
3893b273 1645 /* Get interrupt status */
4a55530f 1646 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1647 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1648 * enabled since it's the one that comes thru regardless of the mask,
1649 * and we need to fully handle it in sh_eth_error() in order to quench
1650 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1651 */
3719109d
SS		 1652 intr_enable = sh_eth_read(ndev, EESIPR);
1653 intr_status &= intr_enable | DMAC_M_ECI;
1654 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1655 ret = IRQ_HANDLED;
3719109d 1656 else
283e38db
BH		 1657 goto out;
1658
1659 if (!likely(mdp->irq_enabled)) {
1660 sh_eth_write(ndev, 0, EESIPR);
1661 goto out;
1662 }
86a74ff2 1663
3719109d
SS		 1664 if (intr_status & EESR_RX_CHECK) {
1665 if (napi_schedule_prep(&mdp->napi)) {
1666 /* Mask Rx interrupts */
1667 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1668 EESIPR);
1669 __napi_schedule(&mdp->napi);
1670 } else {
da246855 1671 netdev_warn(ndev,
0799c2d6 1672 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1673 intr_status, intr_enable);
3719109d
SS		 1674 }
1675 }
86a74ff2 1676
b0ca2a21 1677 /* Tx Check */
380af9e3 1678 if (intr_status & cd->tx_check) {
3719109d
SS		 1679 /* Clear Tx interrupts */
1680 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1681
86a74ff2
NI		 1682 sh_eth_txfree(ndev);
1683 netif_wake_queue(ndev);
1684 }
1685
3719109d
SS		 1686 if (intr_status & cd->eesr_err_check) {
1687 /* Clear error interrupts */
1688 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1689
86a74ff2 1690 sh_eth_error(ndev, intr_status);
3719109d 1691 }
86a74ff2 1692
283e38db 1693out:
86a74ff2
NI		 1694 spin_unlock(&mdp->lock);
1695
0e0fde3c 1696 return ret;
86a74ff2
NI		 1697}
1698
3719109d
SS		 1699static int sh_eth_poll(struct napi_struct *napi, int budget)
1700{
1701 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1702 napi);
1703 struct net_device *ndev = napi->dev;
1704 int quota = budget;
0799c2d6 1705 u32 intr_status;
3719109d
SS		 1706
1707 for (;;) {
1708 intr_status = sh_eth_read(ndev, EESR);
1709 if (!(intr_status & EESR_RX_CHECK))
1710 break;
1711 /* Clear Rx interrupts */
1712 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1713
1714 if (sh_eth_rx(ndev, intr_status, &quota))
1715 goto out;
1716 }
1717
1718 napi_complete(napi);
1719
1720 /* Reenable Rx interrupts */
283e38db
BH		 1721 if (mdp->irq_enabled)
1722 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1723out:
1724 return budget - quota;
1725}
1726
86a74ff2
NI		 1727/* PHY state control function */
1728static void sh_eth_adjust_link(struct net_device *ndev)
1729{
1730 struct sh_eth_private *mdp = netdev_priv(ndev);
9fd0375a 1731 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 1732 int new_state = 0;
1733
3340d2aa 1734 if (phydev->link) {
86a74ff2
NI		 1735 if (phydev->duplex != mdp->duplex) {
1736 new_state = 1;
1737 mdp->duplex = phydev->duplex;
380af9e3
YS		 1738 if (mdp->cd->set_duplex)
1739 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1740 }
1741
1742 if (phydev->speed != mdp->speed) {
1743 new_state = 1;
1744 mdp->speed = phydev->speed;
380af9e3
YS		 1745 if (mdp->cd->set_rate)
1746 mdp->cd->set_rate(ndev);
86a74ff2 1747 }
3340d2aa 1748 if (!mdp->link) {
b2b14d2f 1749 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1750 new_state = 1;
1751 mdp->link = phydev->link;
1e1b812b
SS		 1752 if (mdp->cd->no_psr || mdp->no_ether_link)
1753 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1754 }
1755 } else if (mdp->link) {
1756 new_state = 1;
3340d2aa 1757 mdp->link = 0;
86a74ff2
NI		 1758 mdp->speed = 0;
1759 mdp->duplex = -1;
1e1b812b
SS		 1760 if (mdp->cd->no_psr || mdp->no_ether_link)
1761 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1762 }
1763
dc19e4e5 1764 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1765 phy_print_status(phydev);
1766}
1767
1768/* PHY init function */
1769static int sh_eth_phy_init(struct net_device *ndev)
1770{
702eca02 1771 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1772 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1773 struct phy_device *phydev;
86a74ff2 1774
3340d2aa 1775 mdp->link = 0;
86a74ff2
NI		 1776 mdp->speed = 0;
1777 mdp->duplex = -1;
1778
1779 /* Try connect to PHY */
702eca02
BD		 1780 if (np) {
1781 struct device_node *pn;
1782
1783 pn = of_parse_phandle(np, "phy-handle", 0);
1784 phydev = of_phy_connect(ndev, pn,
1785 sh_eth_adjust_link, 0,
1786 mdp->phy_interface);
1787
8da703dc 1788 of_node_put(pn);
702eca02
BD		 1789 if (!phydev)
1790 phydev = ERR_PTR(-ENOENT);
1791 } else {
1792 char phy_id[MII_BUS_ID_SIZE + 3];
1793
1794 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1795 mdp->mii_bus->id, mdp->phy_id);
1796
1797 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1798 mdp->phy_interface);
1799 }
1800
86a74ff2 1801 if (IS_ERR(phydev)) {
da246855 1802 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1803 return PTR_ERR(phydev);
1804 }
380af9e3 1805
2220943a 1806 phy_attached_info(phydev);
86a74ff2 1807
86a74ff2
NI		 1808 return 0;
1809}
1810
1811/* PHY control start function */
1812static int sh_eth_phy_start(struct net_device *ndev)
1813{
86a74ff2
NI		 1814 int ret;
1815
1816 ret = sh_eth_phy_init(ndev);
1817 if (ret)
1818 return ret;
1819
9fd0375a 1820 phy_start(ndev->phydev);
86a74ff2
NI		 1821
1822 return 0;
1823}
1824
f08aff44
PR		 1825static int sh_eth_get_link_ksettings(struct net_device *ndev,
1826 struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1827{
1828 struct sh_eth_private *mdp = netdev_priv(ndev);
1829 unsigned long flags;
1830 int ret;
1831
9fd0375a 1832 if (!ndev->phydev)
4f9dce23
BH		 1833 return -ENODEV;
1834
dc19e4e5 1835 spin_lock_irqsave(&mdp->lock, flags);
f08aff44 1836 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
dc19e4e5
NI		 1837 spin_unlock_irqrestore(&mdp->lock, flags);
1838
1839 return ret;
1840}
1841
f08aff44
PR		 1842static int sh_eth_set_link_ksettings(struct net_device *ndev,
1843 const struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1844{
1845 struct sh_eth_private *mdp = netdev_priv(ndev);
1846 unsigned long flags;
1847 int ret;
dc19e4e5 1848
9fd0375a 1849 if (!ndev->phydev)
4f9dce23
BH		 1850 return -ENODEV;
1851
dc19e4e5
NI		 1852 spin_lock_irqsave(&mdp->lock, flags);
1853
1854 /* disable tx and rx */
4a55530f 1855 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1856
f08aff44 1857 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
dc19e4e5
NI		 1858 if (ret)
1859 goto error_exit;
1860
f08aff44 1861 if (cmd->base.duplex == DUPLEX_FULL)
dc19e4e5
NI		 1862 mdp->duplex = 1;
1863 else
1864 mdp->duplex = 0;
1865
1866 if (mdp->cd->set_duplex)
1867 mdp->cd->set_duplex(ndev);
1868
1869error_exit:
1870 mdelay(1);
1871
1872 /* enable tx and rx */
4a55530f 1873 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1874
1875 spin_unlock_irqrestore(&mdp->lock, flags);
1876
1877 return ret;
1878}
1879
6b4b4fea
BH		 1880/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1881 * version must be bumped as well. Just adding registers up to that
1882 * limit is fine, as long as the existing register indices don't
1883 * change.
1884 */
1885#define SH_ETH_REG_DUMP_VERSION 1
1886#define SH_ETH_REG_DUMP_MAX_REGS 256
1887
1888static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1889{
1890 struct sh_eth_private *mdp = netdev_priv(ndev);
1891 struct sh_eth_cpu_data *cd = mdp->cd;
1892 u32 *valid_map;
1893 size_t len;
1894
1895 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1896
1897 /* Dump starts with a bitmap that tells ethtool which
1898 * registers are defined for this chip.
1899 */
1900 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1901 if (buf) {
1902 valid_map = buf;
1903 buf += len;
1904 } else {
1905 valid_map = NULL;
1906 }
1907
1908 /* Add a register to the dump, if it has a defined offset.
1909 * This automatically skips most undefined registers, but for
1910 * some it is also necessary to check a capability flag in
1911 * struct sh_eth_cpu_data.
1912 */
1913#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1914#define add_reg_from(reg, read_expr) do { \
1915 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1916 if (buf) { \
1917 mark_reg_valid(reg); \
1918 *buf++ = read_expr; \
1919 } \
1920 ++len; \
1921 } \
1922 } while (0)
1923#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1924#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1925
1926 add_reg(EDSR);
1927 add_reg(EDMR);
1928 add_reg(EDTRR);
1929 add_reg(EDRRR);
1930 add_reg(EESR);
1931 add_reg(EESIPR);
1932 add_reg(TDLAR);
1933 add_reg(TDFAR);
1934 add_reg(TDFXR);
1935 add_reg(TDFFR);
1936 add_reg(RDLAR);
1937 add_reg(RDFAR);
1938 add_reg(RDFXR);
1939 add_reg(RDFFR);
1940 add_reg(TRSCER);
1941 add_reg(RMFCR);
1942 add_reg(TFTR);
1943 add_reg(FDR);
1944 add_reg(RMCR);
1945 add_reg(TFUCR);
1946 add_reg(RFOCR);
1947 if (cd->rmiimode)
1948 add_reg(RMIIMODE);
1949 add_reg(FCFTR);
1950 if (cd->rpadir)
1951 add_reg(RPADIR);
1952 if (!cd->no_trimd)
1953 add_reg(TRIMD);
1954 add_reg(ECMR);
1955 add_reg(ECSR);
1956 add_reg(ECSIPR);
1957 add_reg(PIR);
1958 if (!cd->no_psr)
1959 add_reg(PSR);
1960 add_reg(RDMLR);
1961 add_reg(RFLR);
1962 add_reg(IPGR);
1963 if (cd->apr)
1964 add_reg(APR);
1965 if (cd->mpr)
1966 add_reg(MPR);
1967 add_reg(RFCR);
1968 add_reg(RFCF);
1969 if (cd->tpauser)
1970 add_reg(TPAUSER);
1971 add_reg(TPAUSECR);
1972 add_reg(GECMR);
1973 if (cd->bculr)
1974 add_reg(BCULR);
1975 add_reg(MAHR);
1976 add_reg(MALR);
1977 add_reg(TROCR);
1978 add_reg(CDCR);
1979 add_reg(LCCR);
1980 add_reg(CNDCR);
1981 add_reg(CEFCR);
1982 add_reg(FRECR);
1983 add_reg(TSFRCR);
1984 add_reg(TLFRCR);
1985 add_reg(CERCR);
1986 add_reg(CEECR);
1987 add_reg(MAFCR);
1988 if (cd->rtrate)
1989 add_reg(RTRATE);
1990 if (cd->hw_crc)
1991 add_reg(CSMR);
1992 if (cd->select_mii)
1993 add_reg(RMII_MII);
1994 add_reg(ARSTR);
1995 if (cd->tsu) {
1996 add_tsu_reg(TSU_CTRST);
1997 add_tsu_reg(TSU_FWEN0);
1998 add_tsu_reg(TSU_FWEN1);
1999 add_tsu_reg(TSU_FCM);
2000 add_tsu_reg(TSU_BSYSL0);
2001 add_tsu_reg(TSU_BSYSL1);
2002 add_tsu_reg(TSU_PRISL0);
2003 add_tsu_reg(TSU_PRISL1);
2004 add_tsu_reg(TSU_FWSL0);
2005 add_tsu_reg(TSU_FWSL1);
2006 add_tsu_reg(TSU_FWSLC);
2007 add_tsu_reg(TSU_QTAG0);
2008 add_tsu_reg(TSU_QTAG1);
2009 add_tsu_reg(TSU_QTAGM0);
2010 add_tsu_reg(TSU_QTAGM1);
2011 add_tsu_reg(TSU_FWSR);
2012 add_tsu_reg(TSU_FWINMK);
2013 add_tsu_reg(TSU_ADQT0);
2014 add_tsu_reg(TSU_ADQT1);
2015 add_tsu_reg(TSU_VTAG0);
2016 add_tsu_reg(TSU_VTAG1);
2017 add_tsu_reg(TSU_ADSBSY);
2018 add_tsu_reg(TSU_TEN);
2019 add_tsu_reg(TSU_POST1);
2020 add_tsu_reg(TSU_POST2);
2021 add_tsu_reg(TSU_POST3);
2022 add_tsu_reg(TSU_POST4);
2023 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2024 /* This is the start of a table, not just a single
2025 * register.
2026 */
2027 if (buf) {
2028 unsigned int i;
2029
2030 mark_reg_valid(TSU_ADRH0);
2031 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2032 *buf++ = ioread32(
2033 mdp->tsu_addr +
2034 mdp->reg_offset[TSU_ADRH0] +
2035 i * 4);
2036 }
2037 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2038 }
2039 }
2040
2041#undef mark_reg_valid
2042#undef add_reg_from
2043#undef add_reg
2044#undef add_tsu_reg
2045
2046 return len * 4;
2047}
2048
2049static int sh_eth_get_regs_len(struct net_device *ndev)
2050{
2051 return __sh_eth_get_regs(ndev, NULL);
2052}
2053
2054static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2055 void *buf)
2056{
2057 struct sh_eth_private *mdp = netdev_priv(ndev);
2058
2059 regs->version = SH_ETH_REG_DUMP_VERSION;
2060
2061 pm_runtime_get_sync(&mdp->pdev->dev);
2062 __sh_eth_get_regs(ndev, buf);
2063 pm_runtime_put_sync(&mdp->pdev->dev);
2064}
2065
dc19e4e5
NI		 2066static int sh_eth_nway_reset(struct net_device *ndev)
2067{
2068 struct sh_eth_private *mdp = netdev_priv(ndev);
2069 unsigned long flags;
2070 int ret;
2071
9fd0375a 2072 if (!ndev->phydev)
4f9dce23
BH		 2073 return -ENODEV;
2074
dc19e4e5 2075 spin_lock_irqsave(&mdp->lock, flags);
9fd0375a 2076 ret = phy_start_aneg(ndev->phydev);
dc19e4e5
NI		 2077 spin_unlock_irqrestore(&mdp->lock, flags);
2078
2079 return ret;
2080}
2081
2082static u32 sh_eth_get_msglevel(struct net_device *ndev)
2083{
2084 struct sh_eth_private *mdp = netdev_priv(ndev);
2085 return mdp->msg_enable;
2086}
2087
2088static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2089{
2090 struct sh_eth_private *mdp = netdev_priv(ndev);
2091 mdp->msg_enable = value;
2092}
2093
2094static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2095 "rx_current", "tx_current",
2096 "rx_dirty", "tx_dirty",
2097};
2098#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2099
2100static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2101{
2102 switch (sset) {
2103 case ETH_SS_STATS:
2104 return SH_ETH_STATS_LEN;
2105 default:
2106 return -EOPNOTSUPP;
2107 }
2108}
2109
2110static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2111 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2112{
2113 struct sh_eth_private *mdp = netdev_priv(ndev);
2114 int i = 0;
2115
2116 /* device-specific stats */
2117 data[i++] = mdp->cur_rx;
2118 data[i++] = mdp->cur_tx;
2119 data[i++] = mdp->dirty_rx;
2120 data[i++] = mdp->dirty_tx;
2121}
2122
2123static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2124{
2125 switch (stringset) {
2126 case ETH_SS_STATS:
2127 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2128 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2129 break;
2130 }
2131}
2132
525b8075
YS		 2133static void sh_eth_get_ringparam(struct net_device *ndev,
2134 struct ethtool_ringparam *ring)
2135{
2136 struct sh_eth_private *mdp = netdev_priv(ndev);
2137
2138 ring->rx_max_pending = RX_RING_MAX;
2139 ring->tx_max_pending = TX_RING_MAX;
2140 ring->rx_pending = mdp->num_rx_ring;
2141 ring->tx_pending = mdp->num_tx_ring;
2142}
2143
2144static int sh_eth_set_ringparam(struct net_device *ndev,
2145 struct ethtool_ringparam *ring)
2146{
2147 struct sh_eth_private *mdp = netdev_priv(ndev);
2148 int ret;
2149
2150 if (ring->tx_pending > TX_RING_MAX ||
2151 ring->rx_pending > RX_RING_MAX ||
2152 ring->tx_pending < TX_RING_MIN ||
2153 ring->rx_pending < RX_RING_MIN)
2154 return -EINVAL;
2155 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2156 return -EINVAL;
2157
2158 if (netif_running(ndev)) {
bd888916 2159 netif_device_detach(ndev);
525b8075 2160 netif_tx_disable(ndev);
283e38db
BH		 2161
2162 /* Serialise with the interrupt handler and NAPI, then
2163 * disable interrupts. We have to clear the
2164 * irq_enabled flag first to ensure that interrupts
2165 * won't be re-enabled.
2166 */
2167 mdp->irq_enabled = false;
525b8075 2168 synchronize_irq(ndev->irq);
283e38db 2169 napi_synchronize(&mdp->napi);
525b8075 2170 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2171
740c7f31 2172 sh_eth_dev_exit(ndev);
525b8075 2173
8e03a5e7 2174 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2175 sh_eth_ring_free(ndev);
084236d8 2176 }
525b8075
YS		 2177
2178 /* Set new parameters */
2179 mdp->num_rx_ring = ring->rx_pending;
2180 mdp->num_tx_ring = ring->tx_pending;
2181
525b8075 2182 if (netif_running(ndev)) {
084236d8
BH		 2183 ret = sh_eth_ring_init(ndev);
2184 if (ret < 0) {
2185 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2186 __func__);
2187 return ret;
2188 }
f7967210 2189 ret = sh_eth_dev_init(ndev);
084236d8
BH		 2190 if (ret < 0) {
2191 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2192 __func__);
2193 return ret;
2194 }
2195
bd888916 2196 netif_device_attach(ndev);
525b8075
YS		 2197 }
2198
2199 return 0;
2200}
2201
9b07be4b 2202static const struct ethtool_ops sh_eth_ethtool_ops = {
6b4b4fea
BH		 2203 .get_regs_len = sh_eth_get_regs_len,
2204 .get_regs = sh_eth_get_regs,
9b07be4b 2205 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2206 .get_msglevel = sh_eth_get_msglevel,
2207 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2208 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2209 .get_strings = sh_eth_get_strings,
2210 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2211 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2212 .get_ringparam = sh_eth_get_ringparam,
2213 .set_ringparam = sh_eth_set_ringparam,
f08aff44
PR		 2214 .get_link_ksettings = sh_eth_get_link_ksettings,
2215 .set_link_ksettings = sh_eth_set_link_ksettings,
dc19e4e5
NI		 2216};
2217
86a74ff2
NI		 2218/* network device open function */
2219static int sh_eth_open(struct net_device *ndev)
2220{
86a74ff2 2221 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2222 int ret;
86a74ff2 2223
bcd5149d
MD		 2224 pm_runtime_get_sync(&mdp->pdev->dev);
2225
d2779e99
SS		 2226 napi_enable(&mdp->napi);
2227
a0607fd3 2228 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2229 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2230 if (ret) {
da246855 2231 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2232 goto out_napi_off;
86a74ff2
NI		 2233 }
2234
2235 /* Descriptor set */
2236 ret = sh_eth_ring_init(ndev);
2237 if (ret)
2238 goto out_free_irq;
2239
2240 /* device init */
f7967210 2241 ret = sh_eth_dev_init(ndev);
86a74ff2
NI		 2242 if (ret)
2243 goto out_free_irq;
2244
2245 /* PHY control start*/
2246 ret = sh_eth_phy_start(ndev);
2247 if (ret)
2248 goto out_free_irq;
2249
ad846aa5
SS		 2250 netif_start_queue(ndev);
2251
7fa2955f
MK		 2252 mdp->is_opened = 1;
2253
86a74ff2
NI		 2254 return ret;
2255
2256out_free_irq:
2257 free_irq(ndev->irq, ndev);
d2779e99
SS		 2258out_napi_off:
2259 napi_disable(&mdp->napi);
bcd5149d 2260 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2261 return ret;
2262}
2263
2264/* Timeout function */
2265static void sh_eth_tx_timeout(struct net_device *ndev)
2266{
2267 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2268 struct sh_eth_rxdesc *rxdesc;
2269 int i;
2270
2271 netif_stop_queue(ndev);
2272
8d5009f6
SS		 2273 netif_err(mdp, timer, ndev,
2274 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2275 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2276
2277 /* tx_errors count up */
bb7d92e3 2278 ndev->stats.tx_errors++;
86a74ff2 2279
86a74ff2 2280 /* Free all the skbuffs in the Rx queue. */
525b8075 2281 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2282 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2283 rxdesc->status = cpu_to_le32(0);
2284 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2285 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2286 mdp->rx_skbuff[i] = NULL;
2287 }
525b8075 2288 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2289 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2290 mdp->tx_skbuff[i] = NULL;
2291 }
2292
2293 /* device init */
f7967210 2294 sh_eth_dev_init(ndev);
ad846aa5
SS		 2295
2296 netif_start_queue(ndev);
86a74ff2
NI		 2297}
2298
2299/* Packet transmit function */
2300static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2301{
2302 struct sh_eth_private *mdp = netdev_priv(ndev);
2303 struct sh_eth_txdesc *txdesc;
1299653a 2304 dma_addr_t dma_addr;
86a74ff2 2305 u32 entry;
fb5e2f9b 2306 unsigned long flags;
86a74ff2
NI		 2307
2308 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2309 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2310 if (!sh_eth_txfree(ndev)) {
8d5009f6 2311 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2312 netif_stop_queue(ndev);
2313 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2314 return NETDEV_TX_BUSY;
86a74ff2
NI		 2315 }
2316 }
2317 spin_unlock_irqrestore(&mdp->lock, flags);
2318
dacc73e0 2319 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2320 return NETDEV_TX_OK;
2321
525b8075 2322 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2323 mdp->tx_skbuff[entry] = skb;
2324 txdesc = &mdp->tx_ring[entry];
86a74ff2 2325 /* soft swap. */
380af9e3 2326 if (!mdp->cd->hw_swap)
3e230993 2327 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
1299653a
SS		 2328 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2329 DMA_TO_DEVICE);
2330 if (dma_mapping_error(&ndev->dev, dma_addr)) {
aa3933b8
BH		 2331 kfree_skb(skb);
2332 return NETDEV_TX_OK;
2333 }
7cf72477
SS		 2334 txdesc->addr = cpu_to_le32(dma_addr);
2335 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2336
f32bfb9a 2337 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2338 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2339 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2340 else
7cf72477 2341 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2342
2343 mdp->cur_tx++;
2344
c5ed5368
YS		 2345 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2346 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2347
6ed10654 2348 return NETDEV_TX_OK;
86a74ff2
NI		 2349}
2350
4398f9c8
BH		 2351/* The statistics registers have write-clear behaviour, which means we
2352 * will lose any increment between the read and write. We mitigate
2353 * this by only clearing when we read a non-zero value, so we will
2354 * never falsely report a total of zero.
2355 */
2356static void
2357sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2358{
2359 u32 delta = sh_eth_read(ndev, reg);
2360
2361 if (delta) {
2362 *stat += delta;
2363 sh_eth_write(ndev, 0, reg);
2364 }
2365}
2366
7fa2955f
MK		 2367static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2368{
2369 struct sh_eth_private *mdp = netdev_priv(ndev);
2370
2371 if (sh_eth_is_rz_fast_ether(mdp))
2372 return &ndev->stats;
2373
2374 if (!mdp->is_opened)
2375 return &ndev->stats;
2376
4398f9c8
BH		 2377 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2378 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2379 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2380
2381 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2382 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2383 CERCR);
2384 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2385 CEECR);
7fa2955f 2386 } else {
4398f9c8
BH		 2387 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2388 CNDCR);
7fa2955f
MK		 2389 }
2390
2391 return &ndev->stats;
2392}
2393
86a74ff2
NI		 2394/* device close function */
2395static int sh_eth_close(struct net_device *ndev)
2396{
2397 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2398
2399 netif_stop_queue(ndev);
2400
283e38db
BH		 2401 /* Serialise with the interrupt handler and NAPI, then disable
2402 * interrupts. We have to clear the irq_enabled flag first to
2403 * ensure that interrupts won't be re-enabled.
2404 */
2405 mdp->irq_enabled = false;
2406 synchronize_irq(ndev->irq);
2407 napi_disable(&mdp->napi);
4a55530f 2408 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2409
740c7f31 2410 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2411
2412 /* PHY Disconnect */
9fd0375a
PR		 2413 if (ndev->phydev) {
2414 phy_stop(ndev->phydev);
2415 phy_disconnect(ndev->phydev);
86a74ff2
NI		 2416 }
2417
2418 free_irq(ndev->irq, ndev);
2419
8e03a5e7 2420 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2421 sh_eth_ring_free(ndev);
2422
bcd5149d
MD		 2423 pm_runtime_put_sync(&mdp->pdev->dev);
2424
7fa2955f 2425 mdp->is_opened = 0;
bcd5149d 2426
7fa2955f 2427 return 0;
86a74ff2
NI		 2428}
2429
bb7d92e3 2430/* ioctl to device function */
128296fc 2431static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2 2432{
9fd0375a 2433 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 2434
2435 if (!netif_running(ndev))
2436 return -EINVAL;
2437
2438 if (!phydev)
2439 return -ENODEV;
2440
28b04113 2441 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2442}
2443
6743fe6d
YS		 2444/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2445static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2446 int entry)
2447{
2448 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2449}
2450
2451static u32 sh_eth_tsu_get_post_mask(int entry)
2452{
2453 return 0x0f << (28 - ((entry % 8) * 4));
2454}
2455
2456static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2457{
2458 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2459}
2460
2461static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2462 int entry)
2463{
2464 struct sh_eth_private *mdp = netdev_priv(ndev);
2465 u32 tmp;
2466 void *reg_offset;
2467
2468 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2469 tmp = ioread32(reg_offset);
2470 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2471}
2472
2473static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2474 int entry)
2475{
2476 struct sh_eth_private *mdp = netdev_priv(ndev);
2477 u32 post_mask, ref_mask, tmp;
2478 void *reg_offset;
2479
2480 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2481 post_mask = sh_eth_tsu_get_post_mask(entry);
2482 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2483
2484 tmp = ioread32(reg_offset);
2485 iowrite32(tmp & ~post_mask, reg_offset);
2486
2487 /* If other port enables, the function returns "true" */
2488 return tmp & ref_mask;
2489}
2490
2491static int sh_eth_tsu_busy(struct net_device *ndev)
2492{
2493 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2494 struct sh_eth_private *mdp = netdev_priv(ndev);
2495
2496 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2497 udelay(10);
2498 timeout--;
2499 if (timeout <= 0) {
da246855 2500 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2501 return -ETIMEDOUT;
2502 }
2503 }
2504
2505 return 0;
2506}
2507
2508static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2509 const u8 *addr)
2510{
2511 u32 val;
2512
2513 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2514 iowrite32(val, reg);
2515 if (sh_eth_tsu_busy(ndev) < 0)
2516 return -EBUSY;
2517
2518 val = addr[4] << 8 | addr[5];
2519 iowrite32(val, reg + 4);
2520 if (sh_eth_tsu_busy(ndev) < 0)
2521 return -EBUSY;
2522
2523 return 0;
2524}
2525
2526static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2527{
2528 u32 val;
2529
2530 val = ioread32(reg);
2531 addr[0] = (val >> 24) & 0xff;
2532 addr[1] = (val >> 16) & 0xff;
2533 addr[2] = (val >> 8) & 0xff;
2534 addr[3] = val & 0xff;
2535 val = ioread32(reg + 4);
2536 addr[4] = (val >> 8) & 0xff;
2537 addr[5] = val & 0xff;
2538}
2539
2540
2541static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2542{
2543 struct sh_eth_private *mdp = netdev_priv(ndev);
2544 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2545 int i;
2546 u8 c_addr[ETH_ALEN];
2547
2548 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2549 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2550 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2551 return i;
2552 }
2553
2554 return -ENOENT;
2555}
2556
2557static int sh_eth_tsu_find_empty(struct net_device *ndev)
2558{
2559 u8 blank[ETH_ALEN];
2560 int entry;
2561
2562 memset(blank, 0, sizeof(blank));
2563 entry = sh_eth_tsu_find_entry(ndev, blank);
2564 return (entry < 0) ? -ENOMEM : entry;
2565}
2566
2567static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2568 int entry)
2569{
2570 struct sh_eth_private *mdp = netdev_priv(ndev);
2571 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2572 int ret;
2573 u8 blank[ETH_ALEN];
2574
2575 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2576 ~(1 << (31 - entry)), TSU_TEN);
2577
2578 memset(blank, 0, sizeof(blank));
2579 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2580 if (ret < 0)
2581 return ret;
2582 return 0;
2583}
2584
2585static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2586{
2587 struct sh_eth_private *mdp = netdev_priv(ndev);
2588 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2589 int i, ret;
2590
2591 if (!mdp->cd->tsu)
2592 return 0;
2593
2594 i = sh_eth_tsu_find_entry(ndev, addr);
2595 if (i < 0) {
2596 /* No entry found, create one */
2597 i = sh_eth_tsu_find_empty(ndev);
2598 if (i < 0)
2599 return -ENOMEM;
2600 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2601 if (ret < 0)
2602 return ret;
2603
2604 /* Enable the entry */
2605 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2606 (1 << (31 - i)), TSU_TEN);
2607 }
2608
2609 /* Entry found or created, enable POST */
2610 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2611
2612 return 0;
2613}
2614
2615static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2616{
2617 struct sh_eth_private *mdp = netdev_priv(ndev);
2618 int i, ret;
2619
2620 if (!mdp->cd->tsu)
2621 return 0;
2622
2623 i = sh_eth_tsu_find_entry(ndev, addr);
2624 if (i) {
2625 /* Entry found */
2626 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2627 goto done;
2628
2629 /* Disable the entry if both ports was disabled */
2630 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2631 if (ret < 0)
2632 return ret;
2633 }
2634done:
2635 return 0;
2636}
2637
2638static int sh_eth_tsu_purge_all(struct net_device *ndev)
2639{
2640 struct sh_eth_private *mdp = netdev_priv(ndev);
2641 int i, ret;
2642
b37feed7 2643 if (!mdp->cd->tsu)
6743fe6d
YS		 2644 return 0;
2645
2646 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2647 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2648 continue;
2649
2650 /* Disable the entry if both ports was disabled */
2651 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2652 if (ret < 0)
2653 return ret;
2654 }
2655
2656 return 0;
2657}
2658
2659static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2660{
2661 struct sh_eth_private *mdp = netdev_priv(ndev);
2662 u8 addr[ETH_ALEN];
2663 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2664 int i;
2665
b37feed7 2666 if (!mdp->cd->tsu)
6743fe6d
YS		 2667 return;
2668
2669 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2670 sh_eth_tsu_read_entry(reg_offset, addr);
2671 if (is_multicast_ether_addr(addr))
2672 sh_eth_tsu_del_entry(ndev, addr);
2673 }
2674}
2675
b37feed7
BH		 2676/* Update promiscuous flag and multicast filter */
2677static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2678{
6743fe6d
YS		 2679 struct sh_eth_private *mdp = netdev_priv(ndev);
2680 u32 ecmr_bits;
2681 int mcast_all = 0;
2682 unsigned long flags;
2683
2684 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2685 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2686 * Depending on ndev->flags, set PRM or clear MCT
2687 */
b37feed7
BH		 2688 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2689 if (mdp->cd->tsu)
2690 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2691
2692 if (!(ndev->flags & IFF_MULTICAST)) {
2693 sh_eth_tsu_purge_mcast(ndev);
2694 mcast_all = 1;
2695 }
2696 if (ndev->flags & IFF_ALLMULTI) {
2697 sh_eth_tsu_purge_mcast(ndev);
2698 ecmr_bits &= ~ECMR_MCT;
2699 mcast_all = 1;
2700 }
2701
86a74ff2 2702 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2703 sh_eth_tsu_purge_all(ndev);
2704 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2705 } else if (mdp->cd->tsu) {
2706 struct netdev_hw_addr *ha;
2707 netdev_for_each_mc_addr(ha, ndev) {
2708 if (mcast_all && is_multicast_ether_addr(ha->addr))
2709 continue;
2710
2711 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2712 if (!mcast_all) {
2713 sh_eth_tsu_purge_mcast(ndev);
2714 ecmr_bits &= ~ECMR_MCT;
2715 mcast_all = 1;
2716 }
2717 }
2718 }
86a74ff2 2719 }
6743fe6d
YS		 2720
2721 /* update the ethernet mode */
2722 sh_eth_write(ndev, ecmr_bits, ECMR);
2723
2724 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2725}
71cc7c37
YS		 2726
2727static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2728{
2729 if (!mdp->port)
2730 return TSU_VTAG0;
2731 else
2732 return TSU_VTAG1;
2733}
2734
80d5c368
PM		 2735static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2736 __be16 proto, u16 vid)
71cc7c37
YS		 2737{
2738 struct sh_eth_private *mdp = netdev_priv(ndev);
2739 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2740
2741 if (unlikely(!mdp->cd->tsu))
2742 return -EPERM;
2743
2744 /* No filtering if vid = 0 */
2745 if (!vid)
2746 return 0;
2747
2748 mdp->vlan_num_ids++;
2749
128296fc 2750 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2751 * already enabled, the driver disables it and the filte
2752 */
2753 if (mdp->vlan_num_ids > 1) {
2754 /* disable VLAN filter */
2755 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2756 return 0;
2757 }
2758
2759 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2760 vtag_reg_index);
2761
2762 return 0;
2763}
2764
80d5c368
PM		 2765static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2766 __be16 proto, u16 vid)
71cc7c37
YS		 2767{
2768 struct sh_eth_private *mdp = netdev_priv(ndev);
2769 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2770
2771 if (unlikely(!mdp->cd->tsu))
2772 return -EPERM;
2773
2774 /* No filtering if vid = 0 */
2775 if (!vid)
2776 return 0;
2777
2778 mdp->vlan_num_ids--;
2779 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2780
2781 return 0;
2782}
86a74ff2
NI		 2783
2784/* SuperH's TSU register init function */
4a55530f 2785static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2786{
db893473
SH		 2787 if (sh_eth_is_rz_fast_ether(mdp)) {
2788 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
e1487888
CB		 2789 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2790 TSU_FWSLC); /* Enable POST registers */
db893473
SH		 2791 return;
2792 }
2793
4a55530f
YS		 2794 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2795 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2796 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2797 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2798 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2799 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2800 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2801 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2802 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2803 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2804 if (sh_eth_is_gether(mdp)) {
2805 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2806 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2807 } else {
2808 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2809 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2810 }
4a55530f
YS		 2811 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2812 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2813 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2814 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2815 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2816 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2817 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2818}
2819
2820/* MDIO bus release function */
bd920ff5 2821static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2822{
86a74ff2 2823 /* unregister mdio bus */
bd920ff5 2824 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2825
2826 /* free bitbang info */
bd920ff5 2827 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2828
2829 return 0;
2830}
2831
2832/* MDIO bus init function */
bd920ff5 2833static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2834 struct sh_eth_plat_data *pd)
86a74ff2 2835{
e7f4dc35 2836 int ret;
86a74ff2 2837 struct bb_info *bitbang;
bd920ff5 2838 struct platform_device *pdev = mdp->pdev;
aa8d4225 2839 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2840
2841 /* create bit control struct for PHY */
aa8d4225 2842 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2843 if (!bitbang)
2844 return -ENOMEM;
86a74ff2
NI		 2845
2846 /* bitbang init */
ae70644d 2847 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2848 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2849 bitbang->ctrl.ops = &bb_ops;
2850
c2e07b3a 2851 /* MII controller setting */
86a74ff2 2852 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2853 if (!mdp->mii_bus)
2854 return -ENOMEM;
86a74ff2
NI		 2855
2856 /* Hook up MII support for ethtool */
2857 mdp->mii_bus->name = "sh_mii";
a5bd6060 2858 mdp->mii_bus->parent = dev;
5278fb54 2859 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2860 pdev->name, pdev->id);
86a74ff2 2861
bd920ff5
LP		 2862 /* register MDIO bus */
2863 if (dev->of_node) {
2864 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02 2865 } else {
702eca02
BD		 2866 if (pd->phy_irq > 0)
2867 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2868
2869 ret = mdiobus_register(mdp->mii_bus);
2870 }
2871
86a74ff2 2872 if (ret)
d5e07e69 2873 goto out_free_bus;
86a74ff2 2874
86a74ff2
NI		 2875 return 0;
2876
86a74ff2 2877out_free_bus:
298cf9be 2878 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2879 return ret;
2880}
2881
4a55530f
YS		 2882static const u16 *sh_eth_get_register_offset(int register_type)
2883{
2884 const u16 *reg_offset = NULL;
2885
2886 switch (register_type) {
2887 case SH_ETH_REG_GIGABIT:
2888 reg_offset = sh_eth_offset_gigabit;
2889 break;
db893473
SH		 2890 case SH_ETH_REG_FAST_RZ:
2891 reg_offset = sh_eth_offset_fast_rz;
2892 break;
a3f109bd
SS		 2893 case SH_ETH_REG_FAST_RCAR:
2894 reg_offset = sh_eth_offset_fast_rcar;
2895 break;
4a55530f
YS		 2896 case SH_ETH_REG_FAST_SH4:
2897 reg_offset = sh_eth_offset_fast_sh4;
2898 break;
2899 case SH_ETH_REG_FAST_SH3_SH2:
2900 reg_offset = sh_eth_offset_fast_sh3_sh2;
2901 break;
4a55530f
YS		 2902 }
2903
2904 return reg_offset;
2905}
2906
8f728d79 2907static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2908 .ndo_open = sh_eth_open,
2909 .ndo_stop = sh_eth_close,
2910 .ndo_start_xmit = sh_eth_start_xmit,
2911 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2912 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2913 .ndo_tx_timeout = sh_eth_tx_timeout,
2914 .ndo_do_ioctl = sh_eth_do_ioctl,
2915 .ndo_validate_addr = eth_validate_addr,
2916 .ndo_set_mac_address = eth_mac_addr,
2917 .ndo_change_mtu = eth_change_mtu,
2918};
2919
8f728d79
SS		 2920static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2921 .ndo_open = sh_eth_open,
2922 .ndo_stop = sh_eth_close,
2923 .ndo_start_xmit = sh_eth_start_xmit,
2924 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2925 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2926 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2927 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2928 .ndo_tx_timeout = sh_eth_tx_timeout,
2929 .ndo_do_ioctl = sh_eth_do_ioctl,
2930 .ndo_validate_addr = eth_validate_addr,
2931 .ndo_set_mac_address = eth_mac_addr,
2932 .ndo_change_mtu = eth_change_mtu,
2933};
2934
b356e978
SS		 2935#ifdef CONFIG_OF
2936static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2937{
2938 struct device_node *np = dev->of_node;
2939 struct sh_eth_plat_data *pdata;
b356e978
SS		 2940 const char *mac_addr;
2941
2942 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2943 if (!pdata)
2944 return NULL;
2945
2946 pdata->phy_interface = of_get_phy_mode(np);
2947
b356e978
SS		 2948 mac_addr = of_get_mac_address(np);
2949 if (mac_addr)
2950 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2951
2952 pdata->no_ether_link =
2953 of_property_read_bool(np, "renesas,no-ether-link");
2954 pdata->ether_link_active_low =
2955 of_property_read_bool(np, "renesas,ether-link-active-low");
2956
2957 return pdata;
2958}
2959
2960static const struct of_device_id sh_eth_match_table[] = {
2961 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2962 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2963 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2964 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2965 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2966 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2967 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2968 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2969 { }
2970};
2971MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2972#else
2973static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2974{
2975 return NULL;
2976}
2977#endif
2978
86a74ff2
NI		 2979static int sh_eth_drv_probe(struct platform_device *pdev)
2980{
86a74ff2 2981 struct resource *res;
0b76b862 2982 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2983 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 2984 struct sh_eth_private *mdp;
2985 struct net_device *ndev;
2986 int ret, devno;
86a74ff2
NI		 2987
2988 /* get base addr */
2989 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 2990
2991 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 2992 if (!ndev)
2993 return -ENOMEM;
86a74ff2 2994
b5893a08
BD		 2995 pm_runtime_enable(&pdev->dev);
2996 pm_runtime_get_sync(&pdev->dev);
2997
86a74ff2
NI		 2998 devno = pdev->id;
2999 if (devno < 0)
3000 devno = 0;
3001
cc3c080d 3002 ret = platform_get_irq(pdev, 0);
7a468ac6 3003 if (ret < 0)
86a74ff2 3004 goto out_release;
cc3c080d 3005 ndev->irq = ret;
86a74ff2
NI		 3006
3007 SET_NETDEV_DEV(ndev, &pdev->dev);
3008
86a74ff2 3009 mdp = netdev_priv(ndev);
525b8075
YS		 3010 mdp->num_tx_ring = TX_RING_SIZE;
3011 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3012 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3013 if (IS_ERR(mdp->addr)) {
3014 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3015 goto out_release;
3016 }
3017
c960804f
VB		 3018 ndev->base_addr = res->start;
3019
86a74ff2 3020 spin_lock_init(&mdp->lock);
bcd5149d 3021 mdp->pdev = pdev;
86a74ff2 3022
b356e978
SS		 3023 if (pdev->dev.of_node)
3024 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3025 if (!pd) {
3026 dev_err(&pdev->dev, "no platform data\n");
3027 ret = -EINVAL;
3028 goto out_release;
3029 }
3030
86a74ff2 3031 /* get PHY ID */
71557a37 3032 mdp->phy_id = pd->phy;
e47c9052 3033 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3034 mdp->no_ether_link = pd->no_ether_link;
3035 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3036
380af9e3 3037 /* set cpu data */
42a67c9b 3038 if (id)
b356e978 3039 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3040 else
3041 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3042
a3153d8c 3043 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3044 if (!mdp->reg_offset) {
3045 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3046 mdp->cd->register_type);
3047 ret = -EINVAL;
3048 goto out_release;
3049 }
380af9e3
YS		 3050 sh_eth_set_default_cpu_data(mdp->cd);
3051
86a74ff2 3052 /* set function */
8f728d79
SS		 3053 if (mdp->cd->tsu)
3054 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3055 else
3056 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3057 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3058 ndev->watchdog_timeo = TX_TIMEOUT;
3059
dc19e4e5
NI		 3060 /* debug message level */
3061 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3062
3063 /* read and set MAC address */
748031f9 3064 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3065 if (!is_valid_ether_addr(ndev->dev_addr)) {
3066 dev_warn(&pdev->dev,
3067 "no valid MAC address supplied, using a random one.\n");
3068 eth_hw_addr_random(ndev);
3069 }
86a74ff2 3070
6ba88021
YS		 3071 /* ioremap the TSU registers */
3072 if (mdp->cd->tsu) {
3073 struct resource *rtsu;
3074 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3075 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3076 if (IS_ERR(mdp->tsu_addr)) {
3077 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3078 goto out_release;
3079 }
6743fe6d 3080 mdp->port = devno % 2;
f646968f 3081 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3082 }
3083
150647fb
YS		 3084 /* initialize first or needed device */
3085 if (!devno || pd->needs_init) {
380af9e3
YS		 3086 if (mdp->cd->chip_reset)
3087 mdp->cd->chip_reset(ndev);
86a74ff2 3088
4986b996
YS		 3089 if (mdp->cd->tsu) {
3090 /* TSU init (Init only)*/
3091 sh_eth_tsu_init(mdp);
3092 }
86a74ff2
NI		 3093 }
3094
966d6dbb
HN		 3095 if (mdp->cd->rmiimode)
3096 sh_eth_write(ndev, 0x1, RMIIMODE);
3097
daacf03f
LP		 3098 /* MDIO bus init */
3099 ret = sh_mdio_init(mdp, pd);
3100 if (ret) {
3101 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3102 goto out_release;
3103 }
3104
3719109d
SS		 3105 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3106
86a74ff2
NI		 3107 /* network device register */
3108 ret = register_netdev(ndev);
3109 if (ret)
3719109d 3110 goto out_napi_del;
86a74ff2 3111
25985edc 3112 /* print device information */
f75f14ec
SS		 3113 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3114 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3115
b5893a08 3116 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3117 platform_set_drvdata(pdev, ndev);
3118
3119 return ret;
3120
3719109d
SS		 3121out_napi_del:
3122 netif_napi_del(&mdp->napi);
daacf03f 3123 sh_mdio_release(mdp);
3719109d 3124
86a74ff2
NI		 3125out_release:
3126 /* net_dev free */
3127 if (ndev)
3128 free_netdev(ndev);
3129
b5893a08
BD		 3130 pm_runtime_put(&pdev->dev);
3131 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3132 return ret;
3133}
3134
3135static int sh_eth_drv_remove(struct platform_device *pdev)
3136{
3137 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3138 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3139
86a74ff2 3140 unregister_netdev(ndev);
3719109d 3141 netif_napi_del(&mdp->napi);
daacf03f 3142 sh_mdio_release(mdp);
bcd5149d 3143 pm_runtime_disable(&pdev->dev);
86a74ff2 3144 free_netdev(ndev);
86a74ff2
NI		 3145
3146 return 0;
3147}
3148
540ad1b8 3149#ifdef CONFIG_PM
b71af046
MU		 3150#ifdef CONFIG_PM_SLEEP
3151static int sh_eth_suspend(struct device *dev)
3152{
3153 struct net_device *ndev = dev_get_drvdata(dev);
3154 int ret = 0;
3155
3156 if (netif_running(ndev)) {
3157 netif_device_detach(ndev);
3158 ret = sh_eth_close(ndev);
3159 }
3160
3161 return ret;
3162}
3163
3164static int sh_eth_resume(struct device *dev)
3165{
3166 struct net_device *ndev = dev_get_drvdata(dev);
3167 int ret = 0;
3168
3169 if (netif_running(ndev)) {
3170 ret = sh_eth_open(ndev);
3171 if (ret < 0)
3172 return ret;
3173 netif_device_attach(ndev);
3174 }
3175
3176 return ret;
3177}
3178#endif
3179
bcd5149d
MD		 3180static int sh_eth_runtime_nop(struct device *dev)
3181{
128296fc 3182 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3183 * and ->runtime_resume(). Simply returns success.
3184 *
3185 * This driver re-initializes all registers after
3186 * pm_runtime_get_sync() anyway so there is no need
3187 * to save and restore registers here.
3188 */
3189 return 0;
3190}
3191
540ad1b8 3192static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3193 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3194 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3195};
540ad1b8
NI		 3196#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3197#else
3198#define SH_ETH_PM_OPS NULL
3199#endif
bcd5149d 3200
afe391ad 3201static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3202 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3203 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3204 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3205 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3206 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3207 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3208 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3209 { }
3210};
3211MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3212
86a74ff2
NI		 3213static struct platform_driver sh_eth_driver = {
3214 .probe = sh_eth_drv_probe,
3215 .remove = sh_eth_drv_remove,
afe391ad 3216 .id_table = sh_eth_id_table,
86a74ff2
NI		 3217 .driver = {
3218 .name = CARDNAME,
540ad1b8 3219 .pm = SH_ETH_PM_OPS,
b356e978 3220 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3221 },
3222};
3223
db62f684 3224module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3225
3226MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3227MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3228MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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