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sfc: set the port-id when calling MC_CMD_MAC_STATS
[deliverable/linux.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
52struct efx_ef10_filter_table {
53/* The RX match field masks supported by this fw & hw, in order of priority */
54 enum efx_filter_match_flags rx_match_flags[
55 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
56 unsigned int rx_match_count;
57
58 struct {
59 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 60/* BUSY flag indicates that an update is in progress. AUTO_OLD is
61 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 62 */
63#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 64#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 65#define EFX_EF10_FILTER_FLAGS 3UL
66 u64 handle; /* firmware handle */
67 } *entry;
68 wait_queue_head_t waitq;
69/* Shadow of net_device address lists, guarded by mac_lock */
b59e6ef8
BH		 70#define EFX_EF10_FILTER_DEV_UC_MAX 32
71#define EFX_EF10_FILTER_DEV_MC_MAX 256
8127d661
BH		 72 struct {
73 u8 addr[ETH_ALEN];
74 u16 id;
b59e6ef8
BH		 75 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
76 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
77 int dev_uc_count; /* negative for PROMISC */
78 int dev_mc_count; /* negative for PROMISC/ALLMULTI */
8127d661
BH		 79};
80
81/* An arbitrary search limit for the software hash table */
82#define EFX_EF10_FILTER_SEARCH_LIMIT 200
83
8127d661
BH		 84static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
85static void efx_ef10_filter_table_remove(struct efx_nic *efx);
86
87static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
88{
89 efx_dword_t reg;
90
91 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
92 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
93 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
94}
95
96static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
97{
02246a7f
SS		 98 int bar;
99
100 bar = efx->type->mem_bar;
101 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 102}
103
1cd9ecbb
DP		 104static int efx_ef10_get_pf_index(struct efx_nic *efx)
105{
106 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
107 struct efx_ef10_nic_data *nic_data = efx->nic_data;
108 size_t outlen;
109 int rc;
110
111 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
112 sizeof(outbuf), &outlen);
113 if (rc)
114 return rc;
115 if (outlen < sizeof(outbuf))
116 return -EIO;
117
118 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
119 return 0;
120}
121
88a37de6
SS		 122#ifdef CONFIG_SFC_SRIOV
123static int efx_ef10_get_vf_index(struct efx_nic *efx)
124{
125 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
126 struct efx_ef10_nic_data *nic_data = efx->nic_data;
127 size_t outlen;
128 int rc;
129
130 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
131 sizeof(outbuf), &outlen);
132 if (rc)
133 return rc;
134 if (outlen < sizeof(outbuf))
135 return -EIO;
136
137 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
138 return 0;
139}
140#endif
141
e5a2538a 142static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 143{
144 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
145 struct efx_ef10_nic_data *nic_data = efx->nic_data;
146 size_t outlen;
147 int rc;
148
149 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
150
151 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
152 outbuf, sizeof(outbuf), &outlen);
153 if (rc)
154 return rc;
e5a2538a
BH		 155 if (outlen < sizeof(outbuf)) {
156 netif_err(efx, drv, efx->net_dev,
157 "unable to read datapath firmware capabilities\n");
158 return -EIO;
159 }
160
161 nic_data->datapath_caps =
162 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 163
8d9f9dd4
DP		 164 /* record the DPCPU firmware IDs to determine VEB vswitching support.
165 */
166 nic_data->rx_dpcpu_fw_id =
167 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
168 nic_data->tx_dpcpu_fw_id =
169 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
170
e5a2538a
BH		 171 if (!(nic_data->datapath_caps &
172 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
173 netif_err(efx, drv, efx->net_dev,
174 "current firmware does not support TSO\n");
175 return -ENODEV;
176 }
177
178 if (!(nic_data->datapath_caps &
179 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
180 netif_err(efx, probe, efx->net_dev,
181 "current firmware does not support an RX prefix\n");
182 return -ENODEV;
8127d661
BH		 183 }
184
185 return 0;
186}
187
188static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
189{
190 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
191 int rc;
192
193 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
194 outbuf, sizeof(outbuf), NULL);
195 if (rc)
196 return rc;
197 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
198 return rc > 0 ? rc : -ERANGE;
199}
200
0d5e0fbb 201static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 202{
203 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
204 size_t outlen;
205 int rc;
206
207 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
208
209 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
210 outbuf, sizeof(outbuf), &outlen);
211 if (rc)
212 return rc;
213 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
214 return -EIO;
215
cd84ff4d
EC		 216 ether_addr_copy(mac_address,
217 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 218 return 0;
219}
220
0d5e0fbb
DP		 221static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
222{
223 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
224 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
225 size_t outlen;
226 int num_addrs, rc;
227
228 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
229 EVB_PORT_ID_ASSIGNED);
230 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
231 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
232
233 if (rc)
234 return rc;
235 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
236 return -EIO;
237
238 num_addrs = MCDI_DWORD(outbuf,
239 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
240
241 WARN_ON(num_addrs != 1);
242
243 ether_addr_copy(mac_address,
244 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
245
246 return 0;
247}
248
0f5c0845
SS		 249static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
250 struct device_attribute *attr,
251 char *buf)
252{
253 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
254
255 return sprintf(buf, "%d\n",
256 ((efx->mcdi->fn_flags) &
257 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
258 ? 1 : 0);
259}
260
261static ssize_t efx_ef10_show_primary_flag(struct device *dev,
262 struct device_attribute *attr,
263 char *buf)
264{
265 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
266
267 return sprintf(buf, "%d\n",
268 ((efx->mcdi->fn_flags) &
269 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
270 ? 1 : 0);
271}
272
273static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
274 NULL);
275static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
276
8127d661
BH		 277static int efx_ef10_probe(struct efx_nic *efx)
278{
279 struct efx_ef10_nic_data *nic_data;
8be41320 280 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 281 int i, rc;
282
aa3930ee
BH		 283 /* We can have one VI for each 8K region. However, until we
284 * use TX option descriptors we need two TX queues per channel.
8127d661
BH		 285 */
286 efx->max_channels =
287 min_t(unsigned int,
288 EFX_MAX_CHANNELS,
02246a7f 289 efx_ef10_mem_map_size(efx) /
8127d661 290 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
9fd3d3a4
EC		 291 if (WARN_ON(efx->max_channels == 0))
292 return -EIO;
8127d661
BH		 293
294 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
295 if (!nic_data)
296 return -ENOMEM;
297 efx->nic_data = nic_data;
298
75aba2a5
EC		 299 /* we assume later that we can copy from this buffer in dwords */
300 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
301
8127d661
BH		 302 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
303 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
304 if (rc)
305 goto fail1;
306
307 /* Get the MC's warm boot count. In case it's rebooting right
308 * now, be prepared to retry.
309 */
310 i = 0;
311 for (;;) {
312 rc = efx_ef10_get_warm_boot_count(efx);
313 if (rc >= 0)
314 break;
315 if (++i == 5)
316 goto fail2;
317 ssleep(1);
318 }
319 nic_data->warm_boot_count = rc;
320
321 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
322
45b2449e
DP		 323 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
324
8127d661
BH		 325 /* In case we're recovering from a crash (kexec), we want to
326 * cancel any outstanding request by the previous user of this
327 * function. We send a special message using the least
328 * significant bits of the 'high' (doorbell) register.
329 */
330 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
331
332 rc = efx_mcdi_init(efx);
333 if (rc)
334 goto fail2;
335
336 /* Reset (most) configuration for this function */
337 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
338 if (rc)
339 goto fail3;
340
341 /* Enable event logging */
342 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
343 if (rc)
344 goto fail3;
345
0f5c0845
SS		 346 rc = device_create_file(&efx->pci_dev->dev,
347 &dev_attr_link_control_flag);
1cd9ecbb
DP		 348 if (rc)
349 goto fail3;
350
0f5c0845
SS		 351 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
352 if (rc)
353 goto fail4;
354
355 rc = efx_ef10_get_pf_index(efx);
356 if (rc)
357 goto fail5;
358
e5a2538a 359 rc = efx_ef10_init_datapath_caps(efx);
8127d661 360 if (rc < 0)
0f5c0845 361 goto fail5;
8127d661
BH		 362
363 efx->rx_packet_len_offset =
364 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
365
8127d661
BH		 366 rc = efx_mcdi_port_get_number(efx);
367 if (rc < 0)
0f5c0845 368 goto fail5;
8127d661 369 efx->port_num = rc;
8be41320 370 net_dev->dev_port = rc;
8127d661 371
0d5e0fbb 372 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 373 if (rc)
0f5c0845 374 goto fail5;
8127d661
BH		 375
376 rc = efx_ef10_get_sysclk_freq(efx);
377 if (rc < 0)
0f5c0845 378 goto fail5;
8127d661
BH		 379 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
380
267d9d73
EC		 381 /* Check whether firmware supports bug 35388 workaround.
382 * First try to enable it, then if we get EPERM, just
383 * ask if it's already enabled
384 */
8127d661 385 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
c9012e00 386 if (rc == 0) {
8127d661 387 nic_data->workaround_35388 = true;
c9012e00 388 } else if (rc == -EPERM) {
267d9d73
EC		 389 unsigned int enabled;
390
391 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
392 if (rc)
393 goto fail3;
394 nic_data->workaround_35388 = enabled &
395 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
c9012e00 396 } else if (rc != -ENOSYS && rc != -ENOENT) {
0f5c0845 397 goto fail5;
c9012e00 398 }
8127d661
BH		 399 netif_dbg(efx, probe, efx->net_dev,
400 "workaround for bug 35388 is %sabled\n",
401 nic_data->workaround_35388 ? "en" : "dis");
402
403 rc = efx_mcdi_mon_probe(efx);
267d9d73 404 if (rc && rc != -EPERM)
0f5c0845 405 goto fail5;
8127d661 406
9aecda95
BH		 407 efx_ptp_probe(efx, NULL);
408
1d051e00
SS		 409#ifdef CONFIG_SFC_SRIOV
410 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
411 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
412 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
413
414 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
415 } else
416#endif
417 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
418
8127d661
BH		 419 return 0;
420
0f5c0845
SS		 421fail5:
422 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
423fail4:
424 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 425fail3:
426 efx_mcdi_fini(efx);
427fail2:
428 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
429fail1:
430 kfree(nic_data);
431 efx->nic_data = NULL;
432 return rc;
433}
434
435static int efx_ef10_free_vis(struct efx_nic *efx)
436{
aa09a3da 437 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 438 size_t outlen;
439 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
440 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 441
442 /* -EALREADY means nothing to free, so ignore */
443 if (rc == -EALREADY)
444 rc = 0;
1e0b8120
EC		 445 if (rc)
446 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
447 rc);
8127d661
BH		 448 return rc;
449}
450
183233be
BH		 451#ifdef EFX_USE_PIO
452
453static void efx_ef10_free_piobufs(struct efx_nic *efx)
454{
455 struct efx_ef10_nic_data *nic_data = efx->nic_data;
456 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
457 unsigned int i;
458 int rc;
459
460 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
461
462 for (i = 0; i < nic_data->n_piobufs; i++) {
463 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
464 nic_data->piobuf_handle[i]);
465 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
466 NULL, 0, NULL);
467 WARN_ON(rc);
468 }
469
470 nic_data->n_piobufs = 0;
471}
472
473static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
474{
475 struct efx_ef10_nic_data *nic_data = efx->nic_data;
476 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
477 unsigned int i;
478 size_t outlen;
479 int rc = 0;
480
481 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
482
483 for (i = 0; i < n; i++) {
484 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
485 outbuf, sizeof(outbuf), &outlen);
486 if (rc)
487 break;
488 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
489 rc = -EIO;
490 break;
491 }
492 nic_data->piobuf_handle[i] =
493 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
494 netif_dbg(efx, probe, efx->net_dev,
495 "allocated PIO buffer %u handle %x\n", i,
496 nic_data->piobuf_handle[i]);
497 }
498
499 nic_data->n_piobufs = i;
500 if (rc)
501 efx_ef10_free_piobufs(efx);
502 return rc;
503}
504
505static int efx_ef10_link_piobufs(struct efx_nic *efx)
506{
507 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 508 _MCDI_DECLARE_BUF(inbuf,
509 max(MC_CMD_LINK_PIOBUF_IN_LEN,
510 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 511 struct efx_channel *channel;
512 struct efx_tx_queue *tx_queue;
513 unsigned int offset, index;
514 int rc;
515
516 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
517 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
518
aa09a3da
JC		 519 memset(inbuf, 0, sizeof(inbuf));
520
183233be
BH		 521 /* Link a buffer to each VI in the write-combining mapping */
522 for (index = 0; index < nic_data->n_piobufs; ++index) {
523 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
524 nic_data->piobuf_handle[index]);
525 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
526 nic_data->pio_write_vi_base + index);
527 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
528 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
529 NULL, 0, NULL);
530 if (rc) {
531 netif_err(efx, drv, efx->net_dev,
532 "failed to link VI %u to PIO buffer %u (%d)\n",
533 nic_data->pio_write_vi_base + index, index,
534 rc);
535 goto fail;
536 }
537 netif_dbg(efx, probe, efx->net_dev,
538 "linked VI %u to PIO buffer %u\n",
539 nic_data->pio_write_vi_base + index, index);
540 }
541
542 /* Link a buffer to each TX queue */
543 efx_for_each_channel(channel, efx) {
544 efx_for_each_channel_tx_queue(tx_queue, channel) {
545 /* We assign the PIO buffers to queues in
546 * reverse order to allow for the following
547 * special case.
548 */
549 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
550 tx_queue->channel->channel - 1) *
551 efx_piobuf_size);
552 index = offset / ER_DZ_TX_PIOBUF_SIZE;
553 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
554
555 /* When the host page size is 4K, the first
556 * host page in the WC mapping may be within
557 * the same VI page as the last TX queue. We
558 * can only link one buffer to each VI.
559 */
560 if (tx_queue->queue == nic_data->pio_write_vi_base) {
561 BUG_ON(index != 0);
562 rc = 0;
563 } else {
564 MCDI_SET_DWORD(inbuf,
565 LINK_PIOBUF_IN_PIOBUF_HANDLE,
566 nic_data->piobuf_handle[index]);
567 MCDI_SET_DWORD(inbuf,
568 LINK_PIOBUF_IN_TXQ_INSTANCE,
569 tx_queue->queue);
570 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
571 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
572 NULL, 0, NULL);
573 }
574
575 if (rc) {
576 /* This is non-fatal; the TX path just
577 * won't use PIO for this queue
578 */
579 netif_err(efx, drv, efx->net_dev,
580 "failed to link VI %u to PIO buffer %u (%d)\n",
581 tx_queue->queue, index, rc);
582 tx_queue->piobuf = NULL;
583 } else {
584 tx_queue->piobuf =
585 nic_data->pio_write_base +
586 index * EFX_VI_PAGE_SIZE + offset;
587 tx_queue->piobuf_offset = offset;
588 netif_dbg(efx, probe, efx->net_dev,
589 "linked VI %u to PIO buffer %u offset %x addr %p\n",
590 tx_queue->queue, index,
591 tx_queue->piobuf_offset,
592 tx_queue->piobuf);
593 }
594 }
595 }
596
597 return 0;
598
599fail:
600 while (index--) {
601 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
602 nic_data->pio_write_vi_base + index);
603 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
604 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
605 NULL, 0, NULL);
606 }
607 return rc;
608}
609
610#else /* !EFX_USE_PIO */
611
612static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
613{
614 return n == 0 ? 0 : -ENOBUFS;
615}
616
617static int efx_ef10_link_piobufs(struct efx_nic *efx)
618{
619 return 0;
620}
621
622static void efx_ef10_free_piobufs(struct efx_nic *efx)
623{
624}
625
626#endif /* EFX_USE_PIO */
627
8127d661
BH		 628static void efx_ef10_remove(struct efx_nic *efx)
629{
630 struct efx_ef10_nic_data *nic_data = efx->nic_data;
631 int rc;
632
f1122a34
SS		 633#ifdef CONFIG_SFC_SRIOV
634 struct efx_ef10_nic_data *nic_data_pf;
635 struct pci_dev *pci_dev_pf;
636 struct efx_nic *efx_pf;
637 struct ef10_vf *vf;
638
639 if (efx->pci_dev->is_virtfn) {
640 pci_dev_pf = efx->pci_dev->physfn;
641 if (pci_dev_pf) {
642 efx_pf = pci_get_drvdata(pci_dev_pf);
643 nic_data_pf = efx_pf->nic_data;
644 vf = nic_data_pf->vf + nic_data->vf_index;
645 vf->efx = NULL;
646 } else
647 netif_info(efx, drv, efx->net_dev,
648 "Could not get the PF id from VF\n");
649 }
650#endif
651
9aecda95
BH		 652 efx_ptp_remove(efx);
653
8127d661
BH		 654 efx_mcdi_mon_remove(efx);
655
8127d661
BH		 656 efx_ef10_rx_free_indir_table(efx);
657
183233be
BH		 658 if (nic_data->wc_membase)
659 iounmap(nic_data->wc_membase);
660
8127d661
BH		 661 rc = efx_ef10_free_vis(efx);
662 WARN_ON(rc != 0);
663
183233be
BH		 664 if (!nic_data->must_restore_piobufs)
665 efx_ef10_free_piobufs(efx);
666
0f5c0845
SS		 667 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
668 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
669
8127d661
BH		 670 efx_mcdi_fini(efx);
671 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
672 kfree(nic_data);
673}
674
88a37de6
SS		 675static int efx_ef10_probe_pf(struct efx_nic *efx)
676{
677 return efx_ef10_probe(efx);
678}
679
680#ifdef CONFIG_SFC_SRIOV
681static int efx_ef10_probe_vf(struct efx_nic *efx)
682{
683 int rc;
684
685 rc = efx_ef10_probe(efx);
686 if (rc)
687 return rc;
688
689 rc = efx_ef10_get_vf_index(efx);
690 if (rc)
691 goto fail;
692
f1122a34
SS		 693 if (efx->pci_dev->is_virtfn) {
694 if (efx->pci_dev->physfn) {
695 struct efx_nic *efx_pf =
696 pci_get_drvdata(efx->pci_dev->physfn);
697 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
698 struct efx_ef10_nic_data *nic_data = efx->nic_data;
699
700 nic_data_p->vf[nic_data->vf_index].efx = efx;
701 } else
702 netif_info(efx, drv, efx->net_dev,
703 "Could not get the PF id from VF\n");
704 }
705
88a37de6
SS		 706 return 0;
707
708fail:
709 efx_ef10_remove(efx);
710 return rc;
711}
712#else
713static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
714{
715 return 0;
716}
717#endif
718
8127d661
BH		 719static int efx_ef10_alloc_vis(struct efx_nic *efx,
720 unsigned int min_vis, unsigned int max_vis)
721{
722 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
723 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
724 struct efx_ef10_nic_data *nic_data = efx->nic_data;
725 size_t outlen;
726 int rc;
727
728 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
729 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
730 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
731 outbuf, sizeof(outbuf), &outlen);
732 if (rc != 0)
733 return rc;
734
735 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
736 return -EIO;
737
738 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
739 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
740
741 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
742 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
743 return 0;
744}
745
183233be
BH		 746/* Note that the failure path of this function does not free
747 * resources, as this will be done by efx_ef10_remove().
748 */
8127d661
BH		 749static int efx_ef10_dimension_resources(struct efx_nic *efx)
750{
183233be
BH		 751 struct efx_ef10_nic_data *nic_data = efx->nic_data;
752 unsigned int uc_mem_map_size, wc_mem_map_size;
753 unsigned int min_vis, pio_write_vi_base, max_vis;
754 void __iomem *membase;
755 int rc;
756
757 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 758
183233be
BH		 759#ifdef EFX_USE_PIO
760 /* Try to allocate PIO buffers if wanted and if the full
761 * number of PIO buffers would be sufficient to allocate one
762 * copy-buffer per TX channel. Failure is non-fatal, as there
763 * are only a small number of PIO buffers shared between all
764 * functions of the controller.
765 */
766 if (efx_piobuf_size != 0 &&
767 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
768 efx->n_tx_channels) {
769 unsigned int n_piobufs =
770 DIV_ROUND_UP(efx->n_tx_channels,
771 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
772
773 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
774 if (rc)
775 netif_err(efx, probe, efx->net_dev,
776 "failed to allocate PIO buffers (%d)\n", rc);
777 else
778 netif_dbg(efx, probe, efx->net_dev,
779 "allocated %u PIO buffers\n", n_piobufs);
780 }
781#else
782 nic_data->n_piobufs = 0;
783#endif
784
785 /* PIO buffers should be mapped with write-combining enabled,
786 * and we want to make single UC and WC mappings rather than
787 * several of each (in fact that's the only option if host
788 * page size is >4K). So we may allocate some extra VIs just
789 * for writing PIO buffers through.
52ad762b
DP		 790 *
791 * The UC mapping contains (min_vis - 1) complete VIs and the
792 * first half of the next VI. Then the WC mapping begins with
793 * the second half of this last VI.
183233be
BH		 794 */
795 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
796 ER_DZ_TX_PIOBUF);
797 if (nic_data->n_piobufs) {
52ad762b
DP		 798 /* pio_write_vi_base rounds down to give the number of complete
799 * VIs inside the UC mapping.
800 */
183233be
BH		 801 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
802 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
803 nic_data->n_piobufs) *
804 EFX_VI_PAGE_SIZE) -
805 uc_mem_map_size);
806 max_vis = pio_write_vi_base + nic_data->n_piobufs;
807 } else {
808 pio_write_vi_base = 0;
809 wc_mem_map_size = 0;
810 max_vis = min_vis;
811 }
812
813 /* In case the last attached driver failed to free VIs, do it now */
814 rc = efx_ef10_free_vis(efx);
815 if (rc != 0)
816 return rc;
817
818 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
819 if (rc != 0)
820 return rc;
821
822 /* If we didn't get enough VIs to map all the PIO buffers, free the
823 * PIO buffers
824 */
825 if (nic_data->n_piobufs &&
826 nic_data->n_allocated_vis <
827 pio_write_vi_base + nic_data->n_piobufs) {
828 netif_dbg(efx, probe, efx->net_dev,
829 "%u VIs are not sufficient to map %u PIO buffers\n",
830 nic_data->n_allocated_vis, nic_data->n_piobufs);
831 efx_ef10_free_piobufs(efx);
832 }
833
834 /* Shrink the original UC mapping of the memory BAR */
835 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
836 if (!membase) {
837 netif_err(efx, probe, efx->net_dev,
838 "could not shrink memory BAR to %x\n",
839 uc_mem_map_size);
840 return -ENOMEM;
841 }
842 iounmap(efx->membase);
843 efx->membase = membase;
844
845 /* Set up the WC mapping if needed */
846 if (wc_mem_map_size) {
847 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
848 uc_mem_map_size,
849 wc_mem_map_size);
850 if (!nic_data->wc_membase) {
851 netif_err(efx, probe, efx->net_dev,
852 "could not allocate WC mapping of size %x\n",
853 wc_mem_map_size);
854 return -ENOMEM;
855 }
856 nic_data->pio_write_vi_base = pio_write_vi_base;
857 nic_data->pio_write_base =
858 nic_data->wc_membase +
859 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
860 uc_mem_map_size);
861
862 rc = efx_ef10_link_piobufs(efx);
863 if (rc)
864 efx_ef10_free_piobufs(efx);
865 }
866
867 netif_dbg(efx, probe, efx->net_dev,
868 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
869 &efx->membase_phys, efx->membase, uc_mem_map_size,
870 nic_data->wc_membase, wc_mem_map_size);
871
872 return 0;
8127d661
BH		 873}
874
875static int efx_ef10_init_nic(struct efx_nic *efx)
876{
877 struct efx_ef10_nic_data *nic_data = efx->nic_data;
878 int rc;
879
a915ccc9
BH		 880 if (nic_data->must_check_datapath_caps) {
881 rc = efx_ef10_init_datapath_caps(efx);
882 if (rc)
883 return rc;
884 nic_data->must_check_datapath_caps = false;
885 }
886
8127d661
BH		 887 if (nic_data->must_realloc_vis) {
888 /* We cannot let the number of VIs change now */
889 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
890 nic_data->n_allocated_vis);
891 if (rc)
892 return rc;
893 nic_data->must_realloc_vis = false;
894 }
895
183233be
BH		 896 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
897 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
898 if (rc == 0) {
899 rc = efx_ef10_link_piobufs(efx);
900 if (rc)
901 efx_ef10_free_piobufs(efx);
902 }
903
904 /* Log an error on failure, but this is non-fatal */
905 if (rc)
906 netif_err(efx, drv, efx->net_dev,
907 "failed to restore PIO buffers (%d)\n", rc);
908 nic_data->must_restore_piobufs = false;
909 }
910
267c0157
JC		 911 /* don't fail init if RSS setup doesn't work */
912 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
913
8127d661
BH		 914 return 0;
915}
916
3e336261
JC		 917static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
918{
919 struct efx_ef10_nic_data *nic_data = efx->nic_data;
920
921 /* All our allocations have been reset */
922 nic_data->must_realloc_vis = true;
923 nic_data->must_restore_filters = true;
924 nic_data->must_restore_piobufs = true;
925 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
926}
927
087e9025
JC		 928static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
929{
930 if (reason == RESET_TYPE_MC_FAILURE)
931 return RESET_TYPE_DATAPATH;
932
933 return efx_mcdi_map_reset_reason(reason);
934}
935
8127d661
BH		 936static int efx_ef10_map_reset_flags(u32 *flags)
937{
938 enum {
939 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
940 ETH_RESET_SHARED_SHIFT),
941 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
942 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
943 ETH_RESET_PHY | ETH_RESET_MGMT) <<
944 ETH_RESET_SHARED_SHIFT)
945 };
946
947 /* We assume for now that our PCI function is permitted to
948 * reset everything.
949 */
950
951 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
952 *flags &= ~EF10_RESET_MC;
953 return RESET_TYPE_WORLD;
954 }
955
956 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
957 *flags &= ~EF10_RESET_PORT;
958 return RESET_TYPE_ALL;
959 }
960
961 /* no invisible reset implemented */
962
963 return -EINVAL;
964}
965
3e336261
JC		 966static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
967{
968 int rc = efx_mcdi_reset(efx, reset_type);
969
970 /* If it was a port reset, trigger reallocation of MC resources.
971 * Note that on an MC reset nothing needs to be done now because we'll
972 * detect the MC reset later and handle it then.
e283546c
EC		 973 * For an FLR, we never get an MC reset event, but the MC has reset all
974 * resources assigned to us, so we have to trigger reallocation now.
3e336261 975 */
e283546c
EC		 976 if ((reset_type == RESET_TYPE_ALL ||
977 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 978 efx_ef10_reset_mc_allocations(efx);
979 return rc;
980}
981
8127d661
BH		 982#define EF10_DMA_STAT(ext_name, mcdi_name) \
983 [EF10_STAT_ ## ext_name] = \
984 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
985#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
986 [EF10_STAT_ ## int_name] = \
987 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
988#define EF10_OTHER_STAT(ext_name) \
989 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 990#define GENERIC_SW_STAT(ext_name) \
991 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 992
993static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 994 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
995 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
996 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
997 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
998 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
999 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1000 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1001 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1002 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1003 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1004 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1005 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1006 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1007 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1008 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1009 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1010 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1011 EF10_OTHER_STAT(port_rx_good_bytes),
1012 EF10_OTHER_STAT(port_rx_bad_bytes),
1013 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1014 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1015 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1016 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1017 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1018 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1019 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1020 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1021 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1022 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1023 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1024 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1025 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1026 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1027 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1028 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1029 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1030 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1031 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1032 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1033 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1034 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1035 GENERIC_SW_STAT(rx_nodesc_trunc),
1036 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1037 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1038 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1039 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1040 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1041 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1042 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1043 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1044 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1045 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1046 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1047 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1048 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
8127d661
BH		 1049};
1050
e80ca013
DP		 1051#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1052 (1ULL << EF10_STAT_port_tx_packets) | \
1053 (1ULL << EF10_STAT_port_tx_pause) | \
1054 (1ULL << EF10_STAT_port_tx_unicast) | \
1055 (1ULL << EF10_STAT_port_tx_multicast) | \
1056 (1ULL << EF10_STAT_port_tx_broadcast) | \
1057 (1ULL << EF10_STAT_port_rx_bytes) | \
1058 (1ULL << \
1059 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1060 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1061 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1062 (1ULL << EF10_STAT_port_rx_packets) | \
1063 (1ULL << EF10_STAT_port_rx_good) | \
1064 (1ULL << EF10_STAT_port_rx_bad) | \
1065 (1ULL << EF10_STAT_port_rx_pause) | \
1066 (1ULL << EF10_STAT_port_rx_control) | \
1067 (1ULL << EF10_STAT_port_rx_unicast) | \
1068 (1ULL << EF10_STAT_port_rx_multicast) | \
1069 (1ULL << EF10_STAT_port_rx_broadcast) | \
1070 (1ULL << EF10_STAT_port_rx_lt64) | \
1071 (1ULL << EF10_STAT_port_rx_64) | \
1072 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1073 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1074 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1075 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1076 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1077 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1078 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1079 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1080 (1ULL << EF10_STAT_port_rx_overflow) | \
1081 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1082 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1083 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661
BH		 1084
1085/* These statistics are only provided by the 10G MAC. For a 10G/40G
1086 * switchable port we do not expose these because they might not
1087 * include all the packets they should.
1088 */
e80ca013
DP		 1089#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1090 (1ULL << EF10_STAT_port_tx_lt64) | \
1091 (1ULL << EF10_STAT_port_tx_64) | \
1092 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1093 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1094 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1095 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1096 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1097 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1098
1099/* These statistics are only provided by the 40G MAC. For a 10G/40G
1100 * switchable port we do expose these because the errors will otherwise
1101 * be silent.
1102 */
e80ca013
DP		 1103#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1104 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1105
568d7a00
EC		 1106/* These statistics are only provided if the firmware supports the
1107 * capability PM_AND_RXDP_COUNTERS.
1108 */
1109#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1110 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1111 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1112 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1113 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1114 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1115 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1116 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1117 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1118 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1119 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1120 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1121 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1122
4bae913b 1123static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1124{
4bae913b 1125 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1126 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1127 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 1128
1129 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 1130 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 1131 else
4bae913b 1132 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 1133
1134 if (nic_data->datapath_caps &
1135 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1136 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1137
4bae913b
EC		 1138 return raw_mask;
1139}
1140
1141static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1142{
1143 u64 raw_mask = efx_ef10_raw_stat_mask(efx);
1144
1145#if BITS_PER_LONG == 64
1146 mask[0] = raw_mask;
1147#else
1148 mask[0] = raw_mask & 0xffffffff;
1149 mask[1] = raw_mask >> 32;
1150#endif
8127d661
BH		 1151}
1152
1153static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1154{
4bae913b
EC		 1155 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1156
1157 efx_ef10_get_stat_mask(efx, mask);
8127d661 1158 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1159 mask, names);
8127d661
BH		 1160}
1161
1162static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
1163{
1164 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1165 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1166 __le64 generation_start, generation_end;
1167 u64 *stats = nic_data->stats;
1168 __le64 *dma_stats;
1169
4bae913b
EC		 1170 efx_ef10_get_stat_mask(efx, mask);
1171
8127d661
BH		 1172 dma_stats = efx->stats_buffer.addr;
1173 nic_data = efx->nic_data;
1174
1175 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1176 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1177 return 0;
1178 rmb();
4bae913b 1179 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1180 stats, efx->stats_buffer.addr, false);
d546a893 1181 rmb();
8127d661
BH		 1182 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1183 if (generation_end != generation_start)
1184 return -EAGAIN;
1185
1186 /* Update derived statistics */
e80ca013
DP		 1187 efx_nic_fix_nodesc_drop_stat(efx,
1188 &stats[EF10_STAT_port_rx_nodesc_drops]);
1189 stats[EF10_STAT_port_rx_good_bytes] =
1190 stats[EF10_STAT_port_rx_bytes] -
1191 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1192 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1193 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1194 efx_update_sw_stats(efx, stats);
8127d661
BH		 1195 return 0;
1196}
1197
1198
1199static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
1200 struct rtnl_link_stats64 *core_stats)
1201{
4bae913b 1202 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1203 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1204 u64 *stats = nic_data->stats;
1205 size_t stats_count = 0, index;
1206 int retry;
1207
4bae913b
EC		 1208 efx_ef10_get_stat_mask(efx, mask);
1209
8127d661
BH		 1210 /* If we're unlucky enough to read statistics during the DMA, wait
1211 * up to 10ms for it to finish (typically takes <500us)
1212 */
1213 for (retry = 0; retry < 100; ++retry) {
1214 if (efx_ef10_try_update_nic_stats(efx) == 0)
1215 break;
1216 udelay(100);
1217 }
1218
1219 if (full_stats) {
1220 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1221 if (efx_ef10_stat_desc[index].name) {
1222 *full_stats++ = stats[index];
1223 ++stats_count;
1224 }
1225 }
1226 }
1227
1228 if (core_stats) {
e80ca013
DP		 1229 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1230 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1231 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1232 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1233 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
e4d112e4
EC		 1234 stats[GENERIC_STAT_rx_nodesc_trunc] +
1235 stats[GENERIC_STAT_rx_noskb_drops];
e80ca013 1236 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
8127d661 1237 core_stats->rx_length_errors =
e80ca013
DP		 1238 stats[EF10_STAT_port_rx_gtjumbo] +
1239 stats[EF10_STAT_port_rx_length_error];
1240 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1241 core_stats->rx_frame_errors =
1242 stats[EF10_STAT_port_rx_align_error];
1243 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
8127d661
BH		 1244 core_stats->rx_errors = (core_stats->rx_length_errors +
1245 core_stats->rx_crc_errors +
1246 core_stats->rx_frame_errors);
1247 }
1248
1249 return stats_count;
1250}
1251
1252static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1253{
1254 struct efx_nic *efx = channel->efx;
1255 unsigned int mode, value;
1256 efx_dword_t timer_cmd;
1257
1258 if (channel->irq_moderation) {
1259 mode = 3;
1260 value = channel->irq_moderation - 1;
1261 } else {
1262 mode = 0;
1263 value = 0;
1264 }
1265
1266 if (EFX_EF10_WORKAROUND_35388(efx)) {
1267 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1268 EFE_DD_EVQ_IND_TIMER_FLAGS,
1269 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1270 ERF_DD_EVQ_IND_TIMER_VAL, value);
1271 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1272 channel->channel);
1273 } else {
1274 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1275 ERF_DZ_TC_TIMER_VAL, value);
1276 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1277 channel->channel);
1278 }
1279}
1280
02246a7f
SS		 1281static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1282 struct ethtool_wolinfo *wol) {}
1283
1284static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1285{
1286 return -EOPNOTSUPP;
1287}
1288
8127d661
BH		 1289static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1290{
1291 wol->supported = 0;
1292 wol->wolopts = 0;
1293 memset(&wol->sopass, 0, sizeof(wol->sopass));
1294}
1295
1296static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1297{
1298 if (type != 0)
1299 return -EINVAL;
1300 return 0;
1301}
1302
1303static void efx_ef10_mcdi_request(struct efx_nic *efx,
1304 const efx_dword_t *hdr, size_t hdr_len,
1305 const efx_dword_t *sdu, size_t sdu_len)
1306{
1307 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1308 u8 *pdu = nic_data->mcdi_buf.addr;
1309
1310 memcpy(pdu, hdr, hdr_len);
1311 memcpy(pdu + hdr_len, sdu, sdu_len);
1312 wmb();
1313
1314 /* The hardware provides 'low' and 'high' (doorbell) registers
1315 * for passing the 64-bit address of an MCDI request to
1316 * firmware. However the dwords are swapped by firmware. The
1317 * least significant bits of the doorbell are then 0 for all
1318 * MCDI requests due to alignment.
1319 */
1320 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1321 ER_DZ_MC_DB_LWRD);
1322 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1323 ER_DZ_MC_DB_HWRD);
1324}
1325
1326static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1327{
1328 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1329 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1330
1331 rmb();
1332 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1333}
1334
1335static void
1336efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1337 size_t offset, size_t outlen)
1338{
1339 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1340 const u8 *pdu = nic_data->mcdi_buf.addr;
1341
1342 memcpy(outbuf, pdu + offset, outlen);
1343}
1344
1345static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1346{
1347 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1348 int rc;
1349
1350 rc = efx_ef10_get_warm_boot_count(efx);
1351 if (rc < 0) {
1352 /* The firmware is presumably in the process of
1353 * rebooting. However, we are supposed to report each
1354 * reboot just once, so we must only do that once we
1355 * can read and store the updated warm boot count.
1356 */
1357 return 0;
1358 }
1359
1360 if (rc == nic_data->warm_boot_count)
1361 return 0;
1362
1363 nic_data->warm_boot_count = rc;
1364
1365 /* All our allocations have been reset */
3e336261 1366 efx_ef10_reset_mc_allocations(efx);
8127d661 1367
6d8aaaf6
DP		 1368 /* Driver-created vswitches and vports must be re-created */
1369 nic_data->must_probe_vswitching = true;
1370 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1371
a915ccc9
BH		 1372 /* The datapath firmware might have been changed */
1373 nic_data->must_check_datapath_caps = true;
1374
869070c5
BH		 1375 /* MAC statistics have been cleared on the NIC; clear the local
1376 * statistic that we update with efx_update_diff_stat().
1377 */
e80ca013 1378 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
869070c5 1379
8127d661
BH		 1380 return -EIO;
1381}
1382
1383/* Handle an MSI interrupt
1384 *
1385 * Handle an MSI hardware interrupt. This routine schedules event
1386 * queue processing. No interrupt acknowledgement cycle is necessary.
1387 * Also, we never need to check that the interrupt is for us, since
1388 * MSI interrupts cannot be shared.
1389 */
1390static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1391{
1392 struct efx_msi_context *context = dev_id;
1393 struct efx_nic *efx = context->efx;
1394
1395 netif_vdbg(efx, intr, efx->net_dev,
1396 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1397
1398 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1399 /* Note test interrupts */
1400 if (context->index == efx->irq_level)
1401 efx->last_irq_cpu = raw_smp_processor_id();
1402
1403 /* Schedule processing of the channel */
1404 efx_schedule_channel_irq(efx->channel[context->index]);
1405 }
1406
1407 return IRQ_HANDLED;
1408}
1409
1410static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1411{
1412 struct efx_nic *efx = dev_id;
1413 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1414 struct efx_channel *channel;
1415 efx_dword_t reg;
1416 u32 queues;
1417
1418 /* Read the ISR which also ACKs the interrupts */
1419 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1420 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1421
1422 if (queues == 0)
1423 return IRQ_NONE;
1424
1425 if (likely(soft_enabled)) {
1426 /* Note test interrupts */
1427 if (queues & (1U << efx->irq_level))
1428 efx->last_irq_cpu = raw_smp_processor_id();
1429
1430 efx_for_each_channel(channel, efx) {
1431 if (queues & 1)
1432 efx_schedule_channel_irq(channel);
1433 queues >>= 1;
1434 }
1435 }
1436
1437 netif_vdbg(efx, intr, efx->net_dev,
1438 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1439 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1440
1441 return IRQ_HANDLED;
1442}
1443
1444static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1445{
1446 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1447
1448 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1449
1450 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1451 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1452 inbuf, sizeof(inbuf), NULL, 0, NULL);
1453}
1454
1455static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1456{
1457 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1458 (tx_queue->ptr_mask + 1) *
1459 sizeof(efx_qword_t),
1460 GFP_KERNEL);
1461}
1462
1463/* This writes to the TX_DESC_WPTR and also pushes data */
1464static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1465 const efx_qword_t *txd)
1466{
1467 unsigned int write_ptr;
1468 efx_oword_t reg;
1469
1470 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1471 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1472 reg.qword[0] = *txd;
1473 efx_writeo_page(tx_queue->efx, &reg,
1474 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1475}
1476
1477static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1478{
1479 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1480 EFX_BUF_SIZE));
8127d661
BH		 1481 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1482 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1483 struct efx_channel *channel = tx_queue->channel;
1484 struct efx_nic *efx = tx_queue->efx;
45b2449e 1485 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1486 size_t inlen;
8127d661
BH		 1487 dma_addr_t dma_addr;
1488 efx_qword_t *txd;
1489 int rc;
1490 int i;
aa09a3da 1491 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661
BH		 1492
1493 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1494 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1495 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1496 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1497 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1498 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1499 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1500 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 1501 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 1502
1503 dma_addr = tx_queue->txd.buf.dma_addr;
1504
1505 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1506 tx_queue->queue, entries, (u64)dma_addr);
1507
1508 for (i = 0; i < entries; ++i) {
1509 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1510 dma_addr += EFX_BUF_SIZE;
1511 }
1512
1513 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1514
1515 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
aa09a3da 1516 NULL, 0, NULL);
8127d661
BH		 1517 if (rc)
1518 goto fail;
1519
1520 /* A previous user of this TX queue might have set us up the
1521 * bomb by writing a descriptor to the TX push collector but
1522 * not the doorbell. (Each collector belongs to a port, not a
1523 * queue or function, so cannot easily be reset.) We must
1524 * attempt to push a no-op descriptor in its place.
1525 */
1526 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1527 tx_queue->insert_count = 1;
1528 txd = efx_tx_desc(tx_queue, 0);
1529 EFX_POPULATE_QWORD_4(*txd,
1530 ESF_DZ_TX_DESC_IS_OPT, true,
1531 ESF_DZ_TX_OPTION_TYPE,
1532 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1533 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1534 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1535 tx_queue->write_count = 1;
1536 wmb();
1537 efx_ef10_push_tx_desc(tx_queue, txd);
1538
1539 return;
1540
1541fail:
48ce5634
BH		 1542 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1543 tx_queue->queue);
8127d661
BH		 1544}
1545
1546static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1547{
1548 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 1549 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 1550 struct efx_nic *efx = tx_queue->efx;
1551 size_t outlen;
1552 int rc;
1553
1554 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1555 tx_queue->queue);
1556
1e0b8120 1557 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1558 outbuf, sizeof(outbuf), &outlen);
1559
1560 if (rc && rc != -EALREADY)
1561 goto fail;
1562
1563 return;
1564
1565fail:
1e0b8120
EC		 1566 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1567 outbuf, outlen, rc);
8127d661
BH		 1568}
1569
1570static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1571{
1572 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1573}
1574
1575/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1576static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1577{
1578 unsigned int write_ptr;
1579 efx_dword_t reg;
1580
1581 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1582 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1583 efx_writed_page(tx_queue->efx, &reg,
1584 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1585}
1586
1587static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1588{
1589 unsigned int old_write_count = tx_queue->write_count;
1590 struct efx_tx_buffer *buffer;
1591 unsigned int write_ptr;
1592 efx_qword_t *txd;
1593
1594 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1595
1596 do {
1597 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1598 buffer = &tx_queue->buffer[write_ptr];
1599 txd = efx_tx_desc(tx_queue, write_ptr);
1600 ++tx_queue->write_count;
1601
1602 /* Create TX descriptor ring entry */
1603 if (buffer->flags & EFX_TX_BUF_OPTION) {
1604 *txd = buffer->option;
1605 } else {
1606 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1607 EFX_POPULATE_QWORD_3(
1608 *txd,
1609 ESF_DZ_TX_KER_CONT,
1610 buffer->flags & EFX_TX_BUF_CONT,
1611 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1612 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1613 }
1614 } while (tx_queue->write_count != tx_queue->insert_count);
1615
1616 wmb(); /* Ensure descriptors are written before they are fetched */
1617
1618 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1619 txd = efx_tx_desc(tx_queue,
1620 old_write_count & tx_queue->ptr_mask);
1621 efx_ef10_push_tx_desc(tx_queue, txd);
1622 ++tx_queue->pushes;
1623 } else {
1624 efx_ef10_notify_tx_desc(tx_queue);
1625 }
1626}
1627
267c0157
JC		 1628static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1629 bool exclusive, unsigned *context_size)
8127d661
BH		 1630{
1631 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1632 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 1633 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 1634 size_t outlen;
1635 int rc;
267c0157
JC		 1636 u32 alloc_type = exclusive ?
1637 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1638 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1639 unsigned rss_spread = exclusive ?
1640 efx->rss_spread :
1641 min(rounddown_pow_of_two(efx->rss_spread),
1642 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1643
1644 if (!exclusive && rss_spread == 1) {
1645 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1646 if (context_size)
1647 *context_size = 1;
1648 return 0;
1649 }
8127d661
BH		 1650
1651 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 1652 nic_data->vport_id);
267c0157
JC		 1653 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1654 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 1655
1656 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1657 outbuf, sizeof(outbuf), &outlen);
1658 if (rc != 0)
1659 return rc;
1660
1661 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1662 return -EIO;
1663
1664 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1665
267c0157
JC		 1666 if (context_size)
1667 *context_size = rss_spread;
1668
8127d661
BH		 1669 return 0;
1670}
1671
1672static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1673{
1674 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1675 int rc;
1676
1677 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1678 context);
1679
1680 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1681 NULL, 0, NULL);
1682 WARN_ON(rc != 0);
1683}
1684
267c0157
JC		 1685static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1686 const u32 *rx_indir_table)
8127d661
BH		 1687{
1688 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1689 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1690 int i, rc;
1691
1692 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1693 context);
1694 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1695 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1696
1697 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1698 MCDI_PTR(tablebuf,
1699 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 1700 (u8) rx_indir_table[i];
8127d661
BH		 1701
1702 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1703 sizeof(tablebuf), NULL, 0, NULL);
1704 if (rc != 0)
1705 return rc;
1706
1707 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1708 context);
1709 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1710 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1711 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1712 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1713 efx->rx_hash_key[i];
1714
1715 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1716 sizeof(keybuf), NULL, 0, NULL);
1717}
1718
1719static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1720{
1721 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1722
1723 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1724 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1725 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1726}
1727
267c0157
JC		 1728static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1729 unsigned *context_size)
8127d661 1730{
267c0157 1731 u32 new_rx_rss_context;
8127d661 1732 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 1733 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1734 false, context_size);
1735
1736 if (rc != 0)
1737 return rc;
8127d661 1738
267c0157
JC		 1739 nic_data->rx_rss_context = new_rx_rss_context;
1740 nic_data->rx_rss_context_exclusive = false;
1741 efx_set_default_rx_indir_table(efx);
1742 return 0;
1743}
8127d661 1744
267c0157
JC		 1745static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
1746 const u32 *rx_indir_table)
1747{
1748 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1749 int rc;
1750 u32 new_rx_rss_context;
1751
1752 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
1753 !nic_data->rx_rss_context_exclusive) {
1754 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1755 true, NULL);
1756 if (rc == -EOPNOTSUPP)
1757 return rc;
1758 else if (rc != 0)
1759 goto fail1;
1760 } else {
1761 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 1762 }
1763
267c0157
JC		 1764 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
1765 rx_indir_table);
8127d661 1766 if (rc != 0)
267c0157 1767 goto fail2;
8127d661 1768
267c0157
JC		 1769 if (nic_data->rx_rss_context != new_rx_rss_context)
1770 efx_ef10_rx_free_indir_table(efx);
1771 nic_data->rx_rss_context = new_rx_rss_context;
1772 nic_data->rx_rss_context_exclusive = true;
1773 if (rx_indir_table != efx->rx_indir_table)
1774 memcpy(efx->rx_indir_table, rx_indir_table,
1775 sizeof(efx->rx_indir_table));
1776 return 0;
8127d661 1777
267c0157
JC		 1778fail2:
1779 if (new_rx_rss_context != nic_data->rx_rss_context)
1780 efx_ef10_free_rss_context(efx, new_rx_rss_context);
1781fail1:
8127d661 1782 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 1783 return rc;
1784}
1785
1786static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
1787 const u32 *rx_indir_table)
1788{
1789 int rc;
1790
1791 if (efx->rss_spread == 1)
1792 return 0;
1793
1794 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
1795
1796 if (rc == -ENOBUFS && !user) {
1797 unsigned context_size;
1798 bool mismatch = false;
1799 size_t i;
1800
1801 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
1802 i++)
1803 mismatch = rx_indir_table[i] !=
1804 ethtool_rxfh_indir_default(i, efx->rss_spread);
1805
1806 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
1807 if (rc == 0) {
1808 if (context_size != efx->rss_spread)
1809 netif_warn(efx, probe, efx->net_dev,
1810 "Could not allocate an exclusive RSS"
1811 " context; allocated a shared one of"
1812 " different size."
1813 " Wanted %u, got %u.\n",
1814 efx->rss_spread, context_size);
1815 else if (mismatch)
1816 netif_warn(efx, probe, efx->net_dev,
1817 "Could not allocate an exclusive RSS"
1818 " context; allocated a shared one but"
1819 " could not apply custom"
1820 " indirection.\n");
1821 else
1822 netif_info(efx, probe, efx->net_dev,
1823 "Could not allocate an exclusive RSS"
1824 " context; allocated a shared one.\n");
1825 }
1826 }
1827 return rc;
1828}
1829
1830static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
1831 const u32 *rx_indir_table
1832 __attribute__ ((unused)))
1833{
1834 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1835
1836 if (user)
1837 return -EOPNOTSUPP;
1838 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1839 return 0;
1840 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 1841}
1842
1843static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1844{
1845 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1846 (rx_queue->ptr_mask + 1) *
1847 sizeof(efx_qword_t),
1848 GFP_KERNEL);
1849}
1850
1851static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1852{
1853 MCDI_DECLARE_BUF(inbuf,
1854 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1855 EFX_BUF_SIZE));
8127d661
BH		 1856 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1857 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1858 struct efx_nic *efx = rx_queue->efx;
45b2449e 1859 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1860 size_t inlen;
8127d661
BH		 1861 dma_addr_t dma_addr;
1862 int rc;
1863 int i;
aa09a3da 1864 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 1865
1866 rx_queue->scatter_n = 0;
1867 rx_queue->scatter_len = 0;
1868
1869 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1870 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1871 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1872 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1873 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 1874 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1875 INIT_RXQ_IN_FLAG_PREFIX, 1,
1876 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 1877 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 1878 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 1879
1880 dma_addr = rx_queue->rxd.buf.dma_addr;
1881
1882 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1883 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1884
1885 for (i = 0; i < entries; ++i) {
1886 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1887 dma_addr += EFX_BUF_SIZE;
1888 }
1889
1890 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1891
1892 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 1893 NULL, 0, NULL);
48ce5634
BH		 1894 if (rc)
1895 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1896 efx_rx_queue_index(rx_queue));
8127d661
BH		 1897}
1898
1899static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1900{
1901 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 1902 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 1903 struct efx_nic *efx = rx_queue->efx;
1904 size_t outlen;
1905 int rc;
1906
1907 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1908 efx_rx_queue_index(rx_queue));
1909
1e0b8120 1910 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1911 outbuf, sizeof(outbuf), &outlen);
1912
1913 if (rc && rc != -EALREADY)
1914 goto fail;
1915
1916 return;
1917
1918fail:
1e0b8120
EC		 1919 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1920 outbuf, outlen, rc);
8127d661
BH		 1921}
1922
1923static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1924{
1925 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1926}
1927
1928/* This creates an entry in the RX descriptor queue */
1929static inline void
1930efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1931{
1932 struct efx_rx_buffer *rx_buf;
1933 efx_qword_t *rxd;
1934
1935 rxd = efx_rx_desc(rx_queue, index);
1936 rx_buf = efx_rx_buffer(rx_queue, index);
1937 EFX_POPULATE_QWORD_2(*rxd,
1938 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1939 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1940}
1941
1942static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1943{
1944 struct efx_nic *efx = rx_queue->efx;
1945 unsigned int write_count;
1946 efx_dword_t reg;
1947
1948 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1949 write_count = rx_queue->added_count & ~7;
1950 if (rx_queue->notified_count == write_count)
1951 return;
1952
1953 do
1954 efx_ef10_build_rx_desc(
1955 rx_queue,
1956 rx_queue->notified_count & rx_queue->ptr_mask);
1957 while (++rx_queue->notified_count != write_count);
1958
1959 wmb();
1960 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1961 write_count & rx_queue->ptr_mask);
1962 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1963 efx_rx_queue_index(rx_queue));
1964}
1965
1966static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1967
1968static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1969{
1970 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1971 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1972 efx_qword_t event;
1973
1974 EFX_POPULATE_QWORD_2(event,
1975 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1976 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1977
1978 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1979
1980 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1981 * already swapped the data to little-endian order.
1982 */
1983 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1984 sizeof(efx_qword_t));
1985
1986 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1987 inbuf, sizeof(inbuf), 0,
1988 efx_ef10_rx_defer_refill_complete, 0);
1989}
1990
1991static void
1992efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1993 int rc, efx_dword_t *outbuf,
1994 size_t outlen_actual)
1995{
1996 /* nothing to do */
1997}
1998
1999static int efx_ef10_ev_probe(struct efx_channel *channel)
2000{
2001 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2002 (channel->eventq_mask + 1) *
2003 sizeof(efx_qword_t),
2004 GFP_KERNEL);
2005}
2006
2007static int efx_ef10_ev_init(struct efx_channel *channel)
2008{
2009 MCDI_DECLARE_BUF(inbuf,
2010 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2011 EFX_BUF_SIZE));
2012 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2013 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2014 struct efx_nic *efx = channel->efx;
2015 struct efx_ef10_nic_data *nic_data;
2016 bool supports_rx_merge;
2017 size_t inlen, outlen;
2018 dma_addr_t dma_addr;
2019 int rc;
2020 int i;
2021
2022 nic_data = efx->nic_data;
2023 supports_rx_merge =
2024 !!(nic_data->datapath_caps &
2025 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2026
2027 /* Fill event queue with all ones (i.e. empty events) */
2028 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2029
2030 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2031 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2032 /* INIT_EVQ expects index in vector table, not absolute */
2033 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2034 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2035 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2036 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2037 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2038 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2039 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2040 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2041 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2042 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2043 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2044 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2045 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2046
2047 dma_addr = channel->eventq.buf.dma_addr;
2048 for (i = 0; i < entries; ++i) {
2049 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2050 dma_addr += EFX_BUF_SIZE;
2051 }
2052
2053 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2054
2055 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2056 outbuf, sizeof(outbuf), &outlen);
8127d661 2057 /* IRQ return is ignored */
8127d661
BH		 2058 return rc;
2059}
2060
2061static void efx_ef10_ev_fini(struct efx_channel *channel)
2062{
2063 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
aa09a3da 2064 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2065 struct efx_nic *efx = channel->efx;
2066 size_t outlen;
2067 int rc;
2068
2069 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2070
1e0b8120 2071 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
8127d661
BH		 2072 outbuf, sizeof(outbuf), &outlen);
2073
2074 if (rc && rc != -EALREADY)
2075 goto fail;
2076
2077 return;
2078
2079fail:
1e0b8120
EC		 2080 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2081 outbuf, outlen, rc);
8127d661
BH		 2082}
2083
2084static void efx_ef10_ev_remove(struct efx_channel *channel)
2085{
2086 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2087}
2088
2089static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2090 unsigned int rx_queue_label)
2091{
2092 struct efx_nic *efx = rx_queue->efx;
2093
2094 netif_info(efx, hw, efx->net_dev,
2095 "rx event arrived on queue %d labeled as queue %u\n",
2096 efx_rx_queue_index(rx_queue), rx_queue_label);
2097
2098 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2099}
2100
2101static void
2102efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2103 unsigned int actual, unsigned int expected)
2104{
2105 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2106 struct efx_nic *efx = rx_queue->efx;
2107
2108 netif_info(efx, hw, efx->net_dev,
2109 "dropped %d events (index=%d expected=%d)\n",
2110 dropped, actual, expected);
2111
2112 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2113}
2114
2115/* partially received RX was aborted. clean up. */
2116static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2117{
2118 unsigned int rx_desc_ptr;
2119
8127d661
BH		 2120 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2121 "scattered RX aborted (dropping %u buffers)\n",
2122 rx_queue->scatter_n);
2123
2124 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2125
2126 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2127 0, EFX_RX_PKT_DISCARD);
2128
2129 rx_queue->removed_count += rx_queue->scatter_n;
2130 rx_queue->scatter_n = 0;
2131 rx_queue->scatter_len = 0;
2132 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2133}
2134
2135static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2136 const efx_qword_t *event)
2137{
2138 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2139 unsigned int n_descs, n_packets, i;
2140 struct efx_nic *efx = channel->efx;
2141 struct efx_rx_queue *rx_queue;
2142 bool rx_cont;
2143 u16 flags = 0;
2144
2145 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2146 return 0;
2147
2148 /* Basic packet information */
2149 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2150 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2151 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2152 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2153 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2154
48ce5634
BH		 2155 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2156 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2157 EFX_QWORD_FMT "\n",
2158 EFX_QWORD_VAL(*event));
8127d661
BH		 2159
2160 rx_queue = efx_channel_get_rx_queue(channel);
2161
2162 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2163 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2164
2165 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2166 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2167
2168 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 2169 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2170
8127d661
BH		 2171 /* detect rx abort */
2172 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2173 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2174 netdev_WARN(efx->net_dev,
2175 "invalid RX abort: scatter_n=%u event="
2176 EFX_QWORD_FMT "\n",
2177 rx_queue->scatter_n,
2178 EFX_QWORD_VAL(*event));
8127d661
BH		 2179 efx_ef10_handle_rx_abort(rx_queue);
2180 return 0;
2181 }
2182
92a04168
BH		 2183 /* Check that RX completion merging is valid, i.e.
2184 * the current firmware supports it and this is a
2185 * non-scattered packet.
2186 */
2187 if (!(nic_data->datapath_caps &
2188 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2189 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2190 efx_ef10_handle_rx_bad_lbits(
2191 rx_queue, next_ptr_lbits,
2192 (rx_queue->removed_count +
2193 rx_queue->scatter_n + 1) &
2194 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2195 return 0;
2196 }
2197
2198 /* Merged completion for multiple non-scattered packets */
2199 rx_queue->scatter_n = 1;
2200 rx_queue->scatter_len = 0;
2201 n_packets = n_descs;
2202 ++channel->n_rx_merge_events;
2203 channel->n_rx_merge_packets += n_packets;
2204 flags |= EFX_RX_PKT_PREFIX_LEN;
2205 } else {
2206 ++rx_queue->scatter_n;
2207 rx_queue->scatter_len += rx_bytes;
2208 if (rx_cont)
2209 return 0;
2210 n_packets = 1;
2211 }
2212
2213 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2214 flags |= EFX_RX_PKT_DISCARD;
2215
2216 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2217 channel->n_rx_ip_hdr_chksum_err += n_packets;
2218 } else if (unlikely(EFX_QWORD_FIELD(*event,
2219 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2220 channel->n_rx_tcp_udp_chksum_err += n_packets;
2221 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2222 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2223 flags |= EFX_RX_PKT_CSUMMED;
2224 }
2225
2226 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2227 flags |= EFX_RX_PKT_TCP;
2228
2229 channel->irq_mod_score += 2 * n_packets;
2230
2231 /* Handle received packet(s) */
2232 for (i = 0; i < n_packets; i++) {
2233 efx_rx_packet(rx_queue,
2234 rx_queue->removed_count & rx_queue->ptr_mask,
2235 rx_queue->scatter_n, rx_queue->scatter_len,
2236 flags);
2237 rx_queue->removed_count += rx_queue->scatter_n;
2238 }
2239
2240 rx_queue->scatter_n = 0;
2241 rx_queue->scatter_len = 0;
2242
2243 return n_packets;
2244}
2245
2246static int
2247efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2248{
2249 struct efx_nic *efx = channel->efx;
2250 struct efx_tx_queue *tx_queue;
2251 unsigned int tx_ev_desc_ptr;
2252 unsigned int tx_ev_q_label;
2253 int tx_descs = 0;
2254
2255 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2256 return 0;
2257
2258 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2259 return 0;
2260
2261 /* Transmit completion */
2262 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2263 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2264 tx_queue = efx_channel_get_tx_queue(channel,
2265 tx_ev_q_label % EFX_TXQ_TYPES);
2266 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2267 tx_queue->ptr_mask);
2268 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2269
2270 return tx_descs;
2271}
2272
2273static void
2274efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2275{
2276 struct efx_nic *efx = channel->efx;
2277 int subcode;
2278
2279 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2280
2281 switch (subcode) {
2282 case ESE_DZ_DRV_TIMER_EV:
2283 case ESE_DZ_DRV_WAKE_UP_EV:
2284 break;
2285 case ESE_DZ_DRV_START_UP_EV:
2286 /* event queue init complete. ok. */
2287 break;
2288 default:
2289 netif_err(efx, hw, efx->net_dev,
2290 "channel %d unknown driver event type %d"
2291 " (data " EFX_QWORD_FMT ")\n",
2292 channel->channel, subcode,
2293 EFX_QWORD_VAL(*event));
2294
2295 }
2296}
2297
2298static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2299 efx_qword_t *event)
2300{
2301 struct efx_nic *efx = channel->efx;
2302 u32 subcode;
2303
2304 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2305
2306 switch (subcode) {
2307 case EFX_EF10_TEST:
2308 channel->event_test_cpu = raw_smp_processor_id();
2309 break;
2310 case EFX_EF10_REFILL:
2311 /* The queue must be empty, so we won't receive any rx
2312 * events, so efx_process_channel() won't refill the
2313 * queue. Refill it here
2314 */
cce28794 2315 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 2316 break;
2317 default:
2318 netif_err(efx, hw, efx->net_dev,
2319 "channel %d unknown driver event type %u"
2320 " (data " EFX_QWORD_FMT ")\n",
2321 channel->channel, (unsigned) subcode,
2322 EFX_QWORD_VAL(*event));
2323 }
2324}
2325
2326static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2327{
2328 struct efx_nic *efx = channel->efx;
2329 efx_qword_t event, *p_event;
2330 unsigned int read_ptr;
2331 int ev_code;
2332 int tx_descs = 0;
2333 int spent = 0;
2334
75363a46
EB		 2335 if (quota <= 0)
2336 return spent;
2337
8127d661
BH		 2338 read_ptr = channel->eventq_read_ptr;
2339
2340 for (;;) {
2341 p_event = efx_event(channel, read_ptr);
2342 event = *p_event;
2343
2344 if (!efx_event_present(&event))
2345 break;
2346
2347 EFX_SET_QWORD(*p_event);
2348
2349 ++read_ptr;
2350
2351 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2352
2353 netif_vdbg(efx, drv, efx->net_dev,
2354 "processing event on %d " EFX_QWORD_FMT "\n",
2355 channel->channel, EFX_QWORD_VAL(event));
2356
2357 switch (ev_code) {
2358 case ESE_DZ_EV_CODE_MCDI_EV:
2359 efx_mcdi_process_event(channel, &event);
2360 break;
2361 case ESE_DZ_EV_CODE_RX_EV:
2362 spent += efx_ef10_handle_rx_event(channel, &event);
2363 if (spent >= quota) {
2364 /* XXX can we split a merged event to
2365 * avoid going over-quota?
2366 */
2367 spent = quota;
2368 goto out;
2369 }
2370 break;
2371 case ESE_DZ_EV_CODE_TX_EV:
2372 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2373 if (tx_descs > efx->txq_entries) {
2374 spent = quota;
2375 goto out;
2376 } else if (++spent == quota) {
2377 goto out;
2378 }
2379 break;
2380 case ESE_DZ_EV_CODE_DRIVER_EV:
2381 efx_ef10_handle_driver_event(channel, &event);
2382 if (++spent == quota)
2383 goto out;
2384 break;
2385 case EFX_EF10_DRVGEN_EV:
2386 efx_ef10_handle_driver_generated_event(channel, &event);
2387 break;
2388 default:
2389 netif_err(efx, hw, efx->net_dev,
2390 "channel %d unknown event type %d"
2391 " (data " EFX_QWORD_FMT ")\n",
2392 channel->channel, ev_code,
2393 EFX_QWORD_VAL(event));
2394 }
2395 }
2396
2397out:
2398 channel->eventq_read_ptr = read_ptr;
2399 return spent;
2400}
2401
2402static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2403{
2404 struct efx_nic *efx = channel->efx;
2405 efx_dword_t rptr;
2406
2407 if (EFX_EF10_WORKAROUND_35388(efx)) {
2408 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2409 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2410 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2411 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2412
2413 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2414 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2415 ERF_DD_EVQ_IND_RPTR,
2416 (channel->eventq_read_ptr &
2417 channel->eventq_mask) >>
2418 ERF_DD_EVQ_IND_RPTR_WIDTH);
2419 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2420 channel->channel);
2421 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2422 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2423 ERF_DD_EVQ_IND_RPTR,
2424 channel->eventq_read_ptr &
2425 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2426 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2427 channel->channel);
2428 } else {
2429 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2430 channel->eventq_read_ptr &
2431 channel->eventq_mask);
2432 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2433 }
2434}
2435
2436static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2437{
2438 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2439 struct efx_nic *efx = channel->efx;
2440 efx_qword_t event;
2441 int rc;
2442
2443 EFX_POPULATE_QWORD_2(event,
2444 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2445 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2446
2447 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2448
2449 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2450 * already swapped the data to little-endian order.
2451 */
2452 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2453 sizeof(efx_qword_t));
2454
2455 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2456 NULL, 0, NULL);
2457 if (rc != 0)
2458 goto fail;
2459
2460 return;
2461
2462fail:
2463 WARN_ON(true);
2464 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2465}
2466
2467void efx_ef10_handle_drain_event(struct efx_nic *efx)
2468{
2469 if (atomic_dec_and_test(&efx->active_queues))
2470 wake_up(&efx->flush_wq);
2471
2472 WARN_ON(atomic_read(&efx->active_queues) < 0);
2473}
2474
2475static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2476{
2477 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2478 struct efx_channel *channel;
2479 struct efx_tx_queue *tx_queue;
2480 struct efx_rx_queue *rx_queue;
2481 int pending;
2482
2483 /* If the MC has just rebooted, the TX/RX queues will have already been
2484 * torn down, but efx->active_queues needs to be set to zero.
2485 */
2486 if (nic_data->must_realloc_vis) {
2487 atomic_set(&efx->active_queues, 0);
2488 return 0;
2489 }
2490
2491 /* Do not attempt to write to the NIC during EEH recovery */
2492 if (efx->state != STATE_RECOVERY) {
2493 efx_for_each_channel(channel, efx) {
2494 efx_for_each_channel_rx_queue(rx_queue, channel)
2495 efx_ef10_rx_fini(rx_queue);
2496 efx_for_each_channel_tx_queue(tx_queue, channel)
2497 efx_ef10_tx_fini(tx_queue);
2498 }
2499
2500 wait_event_timeout(efx->flush_wq,
2501 atomic_read(&efx->active_queues) == 0,
2502 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2503 pending = atomic_read(&efx->active_queues);
2504 if (pending) {
2505 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2506 pending);
2507 return -ETIMEDOUT;
2508 }
2509 }
2510
2511 return 0;
2512}
2513
e283546c
EC		 2514static void efx_ef10_prepare_flr(struct efx_nic *efx)
2515{
2516 atomic_set(&efx->active_queues, 0);
2517}
2518
8127d661
BH		 2519static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2520 const struct efx_filter_spec *right)
2521{
2522 if ((left->match_flags ^ right->match_flags) |
2523 ((left->flags ^ right->flags) &
2524 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2525 return false;
2526
2527 return memcmp(&left->outer_vid, &right->outer_vid,
2528 sizeof(struct efx_filter_spec) -
2529 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2530}
2531
2532static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2533{
2534 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2535 return jhash2((const u32 *)&spec->outer_vid,
2536 (sizeof(struct efx_filter_spec) -
2537 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2538 0);
2539 /* XXX should we randomise the initval? */
2540}
2541
2542/* Decide whether a filter should be exclusive or else should allow
2543 * delivery to additional recipients. Currently we decide that
2544 * filters for specific local unicast MAC and IP addresses are
2545 * exclusive.
2546 */
2547static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2548{
2549 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2550 !is_multicast_ether_addr(spec->loc_mac))
2551 return true;
2552
2553 if ((spec->match_flags &
2554 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2555 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2556 if (spec->ether_type == htons(ETH_P_IP) &&
2557 !ipv4_is_multicast(spec->loc_host[0]))
2558 return true;
2559 if (spec->ether_type == htons(ETH_P_IPV6) &&
2560 ((const u8 *)spec->loc_host)[0] != 0xff)
2561 return true;
2562 }
2563
2564 return false;
2565}
2566
2567static struct efx_filter_spec *
2568efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2569 unsigned int filter_idx)
2570{
2571 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2572 ~EFX_EF10_FILTER_FLAGS);
2573}
2574
2575static unsigned int
2576efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2577 unsigned int filter_idx)
2578{
2579 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2580}
2581
2582static void
2583efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2584 unsigned int filter_idx,
2585 const struct efx_filter_spec *spec,
2586 unsigned int flags)
2587{
2588 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2589}
2590
2591static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2592 const struct efx_filter_spec *spec,
2593 efx_dword_t *inbuf, u64 handle,
2594 bool replacing)
2595{
2596 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2597
2598 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2599
2600 if (replacing) {
2601 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2602 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2603 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2604 } else {
2605 u32 match_fields = 0;
2606
2607 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2608 efx_ef10_filter_is_exclusive(spec) ?
2609 MC_CMD_FILTER_OP_IN_OP_INSERT :
2610 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2611
2612 /* Convert match flags and values. Unlike almost
2613 * everything else in MCDI, these fields are in
2614 * network byte order.
2615 */
2616 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2617 match_fields |=
2618 is_multicast_ether_addr(spec->loc_mac) ?
2619 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2620 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2621#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2622 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2623 match_fields |= \
2624 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2625 mcdi_field ## _LBN; \
2626 BUILD_BUG_ON( \
2627 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2628 sizeof(spec->gen_field)); \
2629 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2630 &spec->gen_field, sizeof(spec->gen_field)); \
2631 }
2632 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2633 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2634 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2635 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2636 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2637 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2638 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2639 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2640 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2641 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2642#undef COPY_FIELD
2643 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2644 match_fields);
2645 }
2646
45b2449e 2647 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2648 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2649 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2650 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2651 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 2652 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 2653 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2654 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 2655 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2656 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2657 0 : spec->dmaq_id);
8127d661
BH		 2658 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2659 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2660 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2661 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2662 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2663 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2664 spec->rss_context !=
2665 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2666 spec->rss_context : nic_data->rx_rss_context);
2667}
2668
2669static int efx_ef10_filter_push(struct efx_nic *efx,
2670 const struct efx_filter_spec *spec,
2671 u64 *handle, bool replacing)
2672{
2673 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2674 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2675 int rc;
2676
2677 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2678 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2679 outbuf, sizeof(outbuf), NULL);
2680 if (rc == 0)
2681 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 2682 if (rc == -ENOSPC)
2683 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 2684 return rc;
2685}
2686
2687static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2688 enum efx_filter_match_flags match_flags)
2689{
2690 unsigned int match_pri;
2691
2692 for (match_pri = 0;
2693 match_pri < table->rx_match_count;
2694 match_pri++)
2695 if (table->rx_match_flags[match_pri] == match_flags)
2696 return match_pri;
2697
2698 return -EPROTONOSUPPORT;
2699}
2700
2701static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2702 struct efx_filter_spec *spec,
2703 bool replace_equal)
2704{
2705 struct efx_ef10_filter_table *table = efx->filter_state;
2706 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2707 struct efx_filter_spec *saved_spec;
2708 unsigned int match_pri, hash;
2709 unsigned int priv_flags;
2710 bool replacing = false;
2711 int ins_index = -1;
2712 DEFINE_WAIT(wait);
2713 bool is_mc_recip;
2714 s32 rc;
2715
2716 /* For now, only support RX filters */
2717 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2718 EFX_FILTER_FLAG_RX)
2719 return -EINVAL;
2720
2721 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2722 if (rc < 0)
2723 return rc;
2724 match_pri = rc;
2725
2726 hash = efx_ef10_filter_hash(spec);
2727 is_mc_recip = efx_filter_is_mc_recipient(spec);
2728 if (is_mc_recip)
2729 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2730
2731 /* Find any existing filters with the same match tuple or
2732 * else a free slot to insert at. If any of them are busy,
2733 * we have to wait and retry.
2734 */
2735 for (;;) {
2736 unsigned int depth = 1;
2737 unsigned int i;
2738
2739 spin_lock_bh(&efx->filter_lock);
2740
2741 for (;;) {
2742 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2743 saved_spec = efx_ef10_filter_entry_spec(table, i);
2744
2745 if (!saved_spec) {
2746 if (ins_index < 0)
2747 ins_index = i;
2748 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2749 if (table->entry[i].spec &
2750 EFX_EF10_FILTER_FLAG_BUSY)
2751 break;
2752 if (spec->priority < saved_spec->priority &&
7665d1ab 2753 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 2754 rc = -EPERM;
2755 goto out_unlock;
2756 }
2757 if (!is_mc_recip) {
2758 /* This is the only one */
2759 if (spec->priority ==
2760 saved_spec->priority &&
2761 !replace_equal) {
2762 rc = -EEXIST;
2763 goto out_unlock;
2764 }
2765 ins_index = i;
2766 goto found;
2767 } else if (spec->priority >
2768 saved_spec->priority ||
2769 (spec->priority ==
2770 saved_spec->priority &&
2771 replace_equal)) {
2772 if (ins_index < 0)
2773 ins_index = i;
2774 else
2775 __set_bit(depth, mc_rem_map);
2776 }
2777 }
2778
2779 /* Once we reach the maximum search depth, use
2780 * the first suitable slot or return -EBUSY if
2781 * there was none
2782 */
2783 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2784 if (ins_index < 0) {
2785 rc = -EBUSY;
2786 goto out_unlock;
2787 }
2788 goto found;
2789 }
2790
2791 ++depth;
2792 }
2793
2794 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2795 spin_unlock_bh(&efx->filter_lock);
2796 schedule();
2797 }
2798
2799found:
2800 /* Create a software table entry if necessary, and mark it
2801 * busy. We might yet fail to insert, but any attempt to
2802 * insert a conflicting filter while we're waiting for the
2803 * firmware must find the busy entry.
2804 */
2805 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2806 if (saved_spec) {
7665d1ab
BH		 2807 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2808 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 2809 /* Just make sure it won't be removed */
7665d1ab
BH		 2810 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2811 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 2812 table->entry[ins_index].spec &=
b59e6ef8 2813 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 2814 rc = ins_index;
2815 goto out_unlock;
2816 }
2817 replacing = true;
2818 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2819 } else {
2820 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2821 if (!saved_spec) {
2822 rc = -ENOMEM;
2823 goto out_unlock;
2824 }
2825 *saved_spec = *spec;
2826 priv_flags = 0;
2827 }
2828 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2829 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2830
2831 /* Mark lower-priority multicast recipients busy prior to removal */
2832 if (is_mc_recip) {
2833 unsigned int depth, i;
2834
2835 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2836 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2837 if (test_bit(depth, mc_rem_map))
2838 table->entry[i].spec |=
2839 EFX_EF10_FILTER_FLAG_BUSY;
2840 }
2841 }
2842
2843 spin_unlock_bh(&efx->filter_lock);
2844
2845 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2846 replacing);
2847
2848 /* Finalise the software table entry */
2849 spin_lock_bh(&efx->filter_lock);
2850 if (rc == 0) {
2851 if (replacing) {
2852 /* Update the fields that may differ */
7665d1ab
BH		 2853 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2854 saved_spec->flags |=
2855 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 2856 saved_spec->priority = spec->priority;
7665d1ab 2857 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 2858 saved_spec->flags |= spec->flags;
2859 saved_spec->rss_context = spec->rss_context;
2860 saved_spec->dmaq_id = spec->dmaq_id;
2861 }
2862 } else if (!replacing) {
2863 kfree(saved_spec);
2864 saved_spec = NULL;
2865 }
2866 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2867
2868 /* Remove and finalise entries for lower-priority multicast
2869 * recipients
2870 */
2871 if (is_mc_recip) {
2872 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2873 unsigned int depth, i;
2874
2875 memset(inbuf, 0, sizeof(inbuf));
2876
2877 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2878 if (!test_bit(depth, mc_rem_map))
2879 continue;
2880
2881 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2882 saved_spec = efx_ef10_filter_entry_spec(table, i);
2883 priv_flags = efx_ef10_filter_entry_flags(table, i);
2884
2885 if (rc == 0) {
2886 spin_unlock_bh(&efx->filter_lock);
2887 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2888 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2889 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2890 table->entry[i].handle);
2891 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2892 inbuf, sizeof(inbuf),
2893 NULL, 0, NULL);
2894 spin_lock_bh(&efx->filter_lock);
2895 }
2896
2897 if (rc == 0) {
2898 kfree(saved_spec);
2899 saved_spec = NULL;
2900 priv_flags = 0;
2901 } else {
2902 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2903 }
2904 efx_ef10_filter_set_entry(table, i, saved_spec,
2905 priv_flags);
2906 }
2907 }
2908
2909 /* If successful, return the inserted filter ID */
2910 if (rc == 0)
2911 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2912
2913 wake_up_all(&table->waitq);
2914out_unlock:
2915 spin_unlock_bh(&efx->filter_lock);
2916 finish_wait(&table->waitq, &wait);
2917 return rc;
2918}
2919
9fd8095d 2920static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 2921{
2922 /* no need to do anything here on EF10 */
2923}
2924
2925/* Remove a filter.
b59e6ef8
BH		 2926 * If !by_index, remove by ID
2927 * If by_index, remove by index
8127d661
BH		 2928 * Filter ID may come from userland and must be range-checked.
2929 */
2930static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 2931 unsigned int priority_mask,
b59e6ef8 2932 u32 filter_id, bool by_index)
8127d661
BH		 2933{
2934 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2935 struct efx_ef10_filter_table *table = efx->filter_state;
2936 MCDI_DECLARE_BUF(inbuf,
2937 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2938 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2939 struct efx_filter_spec *spec;
2940 DEFINE_WAIT(wait);
2941 int rc;
2942
2943 /* Find the software table entry and mark it busy. Don't
2944 * remove it yet; any attempt to update while we're waiting
2945 * for the firmware must find the busy entry.
2946 */
2947 for (;;) {
2948 spin_lock_bh(&efx->filter_lock);
2949 if (!(table->entry[filter_idx].spec &
2950 EFX_EF10_FILTER_FLAG_BUSY))
2951 break;
2952 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2953 spin_unlock_bh(&efx->filter_lock);
2954 schedule();
2955 }
7665d1ab 2956
8127d661 2957 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 2958 if (!spec ||
b59e6ef8 2959 (!by_index &&
8127d661
BH		 2960 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2961 filter_id / HUNT_FILTER_TBL_ROWS)) {
2962 rc = -ENOENT;
2963 goto out_unlock;
2964 }
7665d1ab
BH		 2965
2966 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 2967 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 2968 /* Just remove flags */
2969 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 2970 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 2971 rc = 0;
2972 goto out_unlock;
2973 }
2974
fbd79120 2975 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 2976 rc = -ENOENT;
2977 goto out_unlock;
2978 }
2979
8127d661
BH		 2980 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2981 spin_unlock_bh(&efx->filter_lock);
2982
7665d1ab 2983 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 2984 /* Reset to an automatic filter */
8127d661
BH		 2985
2986 struct efx_filter_spec new_spec = *spec;
2987
7665d1ab 2988 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 2989 new_spec.flags = (EFX_FILTER_FLAG_RX |
7665d1ab 2990 EFX_FILTER_FLAG_RX_RSS);
8127d661
BH		 2991 new_spec.dmaq_id = 0;
2992 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2993 rc = efx_ef10_filter_push(efx, &new_spec,
2994 &table->entry[filter_idx].handle,
2995 true);
2996
2997 spin_lock_bh(&efx->filter_lock);
2998 if (rc == 0)
2999 *spec = new_spec;
3000 } else {
3001 /* Really remove the filter */
3002
3003 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3004 efx_ef10_filter_is_exclusive(spec) ?
3005 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3006 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3007 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3008 table->entry[filter_idx].handle);
3009 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3010 inbuf, sizeof(inbuf), NULL, 0, NULL);
3011
3012 spin_lock_bh(&efx->filter_lock);
3013 if (rc == 0) {
3014 kfree(spec);
3015 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3016 }
3017 }
7665d1ab 3018
8127d661
BH		 3019 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3020 wake_up_all(&table->waitq);
3021out_unlock:
3022 spin_unlock_bh(&efx->filter_lock);
3023 finish_wait(&table->waitq, &wait);
3024 return rc;
3025}
3026
3027static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3028 enum efx_filter_priority priority,
3029 u32 filter_id)
3030{
fbd79120
BH		 3031 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3032 filter_id, false);
8127d661
BH		 3033}
3034
3035static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3036 enum efx_filter_priority priority,
3037 u32 filter_id, struct efx_filter_spec *spec)
3038{
3039 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3040 struct efx_ef10_filter_table *table = efx->filter_state;
3041 const struct efx_filter_spec *saved_spec;
3042 int rc;
3043
3044 spin_lock_bh(&efx->filter_lock);
3045 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3046 if (saved_spec && saved_spec->priority == priority &&
3047 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3048 filter_id / HUNT_FILTER_TBL_ROWS) {
3049 *spec = *saved_spec;
3050 rc = 0;
3051 } else {
3052 rc = -ENOENT;
3053 }
3054 spin_unlock_bh(&efx->filter_lock);
3055 return rc;
3056}
3057
fbd79120 3058static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 3059 enum efx_filter_priority priority)
3060{
fbd79120
BH		 3061 unsigned int priority_mask;
3062 unsigned int i;
3063 int rc;
3064
3065 priority_mask = (((1U << (priority + 1)) - 1) &
3066 ~(1U << EFX_FILTER_PRI_AUTO));
3067
3068 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3069 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3070 i, true);
3071 if (rc && rc != -ENOENT)
3072 return rc;
3073 }
3074
3075 return 0;
8127d661
BH		 3076}
3077
3078static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3079 enum efx_filter_priority priority)
3080{
3081 struct efx_ef10_filter_table *table = efx->filter_state;
3082 unsigned int filter_idx;
3083 s32 count = 0;
3084
3085 spin_lock_bh(&efx->filter_lock);
3086 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3087 if (table->entry[filter_idx].spec &&
3088 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3089 priority)
3090 ++count;
3091 }
3092 spin_unlock_bh(&efx->filter_lock);
3093 return count;
3094}
3095
3096static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3097{
3098 struct efx_ef10_filter_table *table = efx->filter_state;
3099
3100 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3101}
3102
3103static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3104 enum efx_filter_priority priority,
3105 u32 *buf, u32 size)
3106{
3107 struct efx_ef10_filter_table *table = efx->filter_state;
3108 struct efx_filter_spec *spec;
3109 unsigned int filter_idx;
3110 s32 count = 0;
3111
3112 spin_lock_bh(&efx->filter_lock);
3113 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3114 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3115 if (spec && spec->priority == priority) {
3116 if (count == size) {
3117 count = -EMSGSIZE;
3118 break;
3119 }
3120 buf[count++] = (efx_ef10_filter_rx_match_pri(
3121 table, spec->match_flags) *
3122 HUNT_FILTER_TBL_ROWS +
3123 filter_idx);
3124 }
3125 }
3126 spin_unlock_bh(&efx->filter_lock);
3127 return count;
3128}
3129
3130#ifdef CONFIG_RFS_ACCEL
3131
3132static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3133
3134static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3135 struct efx_filter_spec *spec)
3136{
3137 struct efx_ef10_filter_table *table = efx->filter_state;
3138 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3139 struct efx_filter_spec *saved_spec;
3140 unsigned int hash, i, depth = 1;
3141 bool replacing = false;
3142 int ins_index = -1;
3143 u64 cookie;
3144 s32 rc;
3145
3146 /* Must be an RX filter without RSS and not for a multicast
3147 * destination address (RFS only works for connected sockets).
3148 * These restrictions allow us to pass only a tiny amount of
3149 * data through to the completion function.
3150 */
3151 EFX_WARN_ON_PARANOID(spec->flags !=
3152 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3153 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3154 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3155
3156 hash = efx_ef10_filter_hash(spec);
3157
3158 spin_lock_bh(&efx->filter_lock);
3159
3160 /* Find any existing filter with the same match tuple or else
3161 * a free slot to insert at. If an existing filter is busy,
3162 * we have to give up.
3163 */
3164 for (;;) {
3165 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3166 saved_spec = efx_ef10_filter_entry_spec(table, i);
3167
3168 if (!saved_spec) {
3169 if (ins_index < 0)
3170 ins_index = i;
3171 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3172 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3173 rc = -EBUSY;
3174 goto fail_unlock;
3175 }
8127d661
BH		 3176 if (spec->priority < saved_spec->priority) {
3177 rc = -EPERM;
3178 goto fail_unlock;
3179 }
3180 ins_index = i;
3181 break;
3182 }
3183
3184 /* Once we reach the maximum search depth, use the
3185 * first suitable slot or return -EBUSY if there was
3186 * none
3187 */
3188 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3189 if (ins_index < 0) {
3190 rc = -EBUSY;
3191 goto fail_unlock;
3192 }
3193 break;
3194 }
3195
3196 ++depth;
3197 }
3198
3199 /* Create a software table entry if necessary, and mark it
3200 * busy. We might yet fail to insert, but any attempt to
3201 * insert a conflicting filter while we're waiting for the
3202 * firmware must find the busy entry.
3203 */
3204 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3205 if (saved_spec) {
3206 replacing = true;
3207 } else {
3208 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3209 if (!saved_spec) {
3210 rc = -ENOMEM;
3211 goto fail_unlock;
3212 }
3213 *saved_spec = *spec;
3214 }
3215 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3216 EFX_EF10_FILTER_FLAG_BUSY);
3217
3218 spin_unlock_bh(&efx->filter_lock);
3219
3220 /* Pack up the variables needed on completion */
3221 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3222
3223 efx_ef10_filter_push_prep(efx, spec, inbuf,
3224 table->entry[ins_index].handle, replacing);
3225 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3226 MC_CMD_FILTER_OP_OUT_LEN,
3227 efx_ef10_filter_rfs_insert_complete, cookie);
3228
3229 return ins_index;
3230
3231fail_unlock:
3232 spin_unlock_bh(&efx->filter_lock);
3233 return rc;
3234}
3235
3236static void
3237efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3238 int rc, efx_dword_t *outbuf,
3239 size_t outlen_actual)
3240{
3241 struct efx_ef10_filter_table *table = efx->filter_state;
3242 unsigned int ins_index, dmaq_id;
3243 struct efx_filter_spec *spec;
3244 bool replacing;
3245
3246 /* Unpack the cookie */
3247 replacing = cookie >> 31;
3248 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3249 dmaq_id = cookie & 0xffff;
3250
3251 spin_lock_bh(&efx->filter_lock);
3252 spec = efx_ef10_filter_entry_spec(table, ins_index);
3253 if (rc == 0) {
3254 table->entry[ins_index].handle =
3255 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3256 if (replacing)
3257 spec->dmaq_id = dmaq_id;
3258 } else if (!replacing) {
3259 kfree(spec);
3260 spec = NULL;
3261 }
3262 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3263 spin_unlock_bh(&efx->filter_lock);
3264
3265 wake_up_all(&table->waitq);
3266}
3267
3268static void
3269efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3270 unsigned long filter_idx,
3271 int rc, efx_dword_t *outbuf,
3272 size_t outlen_actual);
3273
3274static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3275 unsigned int filter_idx)
3276{
3277 struct efx_ef10_filter_table *table = efx->filter_state;
3278 struct efx_filter_spec *spec =
3279 efx_ef10_filter_entry_spec(table, filter_idx);
3280 MCDI_DECLARE_BUF(inbuf,
3281 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3282 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3283
3284 if (!spec ||
3285 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3286 spec->priority != EFX_FILTER_PRI_HINT ||
3287 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3288 flow_id, filter_idx))
3289 return false;
3290
3291 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3292 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3293 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3294 table->entry[filter_idx].handle);
3295 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3296 efx_ef10_filter_rfs_expire_complete, filter_idx))
3297 return false;
3298
3299 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3300 return true;
3301}
3302
3303static void
3304efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3305 unsigned long filter_idx,
3306 int rc, efx_dword_t *outbuf,
3307 size_t outlen_actual)
3308{
3309 struct efx_ef10_filter_table *table = efx->filter_state;
3310 struct efx_filter_spec *spec =
3311 efx_ef10_filter_entry_spec(table, filter_idx);
3312
3313 spin_lock_bh(&efx->filter_lock);
3314 if (rc == 0) {
3315 kfree(spec);
3316 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3317 }
3318 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3319 wake_up_all(&table->waitq);
3320 spin_unlock_bh(&efx->filter_lock);
3321}
3322
3323#endif /* CONFIG_RFS_ACCEL */
3324
3325static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3326{
3327 int match_flags = 0;
3328
3329#define MAP_FLAG(gen_flag, mcdi_field) { \
3330 u32 old_mcdi_flags = mcdi_flags; \
3331 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3332 mcdi_field ## _LBN); \
3333 if (mcdi_flags != old_mcdi_flags) \
3334 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3335 }
3336 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3337 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3338 MAP_FLAG(REM_HOST, SRC_IP);
3339 MAP_FLAG(LOC_HOST, DST_IP);
3340 MAP_FLAG(REM_MAC, SRC_MAC);
3341 MAP_FLAG(REM_PORT, SRC_PORT);
3342 MAP_FLAG(LOC_MAC, DST_MAC);
3343 MAP_FLAG(LOC_PORT, DST_PORT);
3344 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3345 MAP_FLAG(INNER_VID, INNER_VLAN);
3346 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3347 MAP_FLAG(IP_PROTO, IP_PROTO);
3348#undef MAP_FLAG
3349
3350 /* Did we map them all? */
3351 if (mcdi_flags)
3352 return -EINVAL;
3353
3354 return match_flags;
3355}
3356
3357static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3358{
3359 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3360 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3361 unsigned int pd_match_pri, pd_match_count;
3362 struct efx_ef10_filter_table *table;
3363 size_t outlen;
3364 int rc;
3365
3366 table = kzalloc(sizeof(*table), GFP_KERNEL);
3367 if (!table)
3368 return -ENOMEM;
3369
3370 /* Find out which RX filter types are supported, and their priorities */
3371 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3372 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3373 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3374 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3375 &outlen);
3376 if (rc)
3377 goto fail;
3378 pd_match_count = MCDI_VAR_ARRAY_LEN(
3379 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3380 table->rx_match_count = 0;
3381
3382 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3383 u32 mcdi_flags =
3384 MCDI_ARRAY_DWORD(
3385 outbuf,
3386 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3387 pd_match_pri);
3388 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3389 if (rc < 0) {
3390 netif_dbg(efx, probe, efx->net_dev,
3391 "%s: fw flags %#x pri %u not supported in driver\n",
3392 __func__, mcdi_flags, pd_match_pri);
3393 } else {
3394 netif_dbg(efx, probe, efx->net_dev,
3395 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3396 __func__, mcdi_flags, pd_match_pri,
3397 rc, table->rx_match_count);
3398 table->rx_match_flags[table->rx_match_count++] = rc;
3399 }
3400 }
3401
3402 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3403 if (!table->entry) {
3404 rc = -ENOMEM;
3405 goto fail;
3406 }
3407
3408 efx->filter_state = table;
3409 init_waitqueue_head(&table->waitq);
3410 return 0;
3411
3412fail:
3413 kfree(table);
3414 return rc;
3415}
3416
0d322413
EC		 3417/* Caller must hold efx->filter_sem for read if race against
3418 * efx_ef10_filter_table_remove() is possible
3419 */
8127d661
BH		 3420static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3421{
3422 struct efx_ef10_filter_table *table = efx->filter_state;
3423 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3424 struct efx_filter_spec *spec;
3425 unsigned int filter_idx;
3426 bool failed = false;
3427 int rc;
3428
0d322413
EC		 3429 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3430
8127d661
BH		 3431 if (!nic_data->must_restore_filters)
3432 return;
3433
0d322413
EC		 3434 if (!table)
3435 return;
3436
8127d661
BH		 3437 spin_lock_bh(&efx->filter_lock);
3438
3439 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3440 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3441 if (!spec)
3442 continue;
3443
3444 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3445 spin_unlock_bh(&efx->filter_lock);
3446
3447 rc = efx_ef10_filter_push(efx, spec,
3448 &table->entry[filter_idx].handle,
3449 false);
3450 if (rc)
3451 failed = true;
3452
3453 spin_lock_bh(&efx->filter_lock);
3454 if (rc) {
3455 kfree(spec);
3456 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3457 } else {
3458 table->entry[filter_idx].spec &=
3459 ~EFX_EF10_FILTER_FLAG_BUSY;
3460 }
3461 }
3462
3463 spin_unlock_bh(&efx->filter_lock);
3464
3465 if (failed)
3466 netif_err(efx, hw, efx->net_dev,
3467 "unable to restore all filters\n");
3468 else
3469 nic_data->must_restore_filters = false;
3470}
3471
0d322413 3472/* Caller must hold efx->filter_sem for write */
8127d661
BH		 3473static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3474{
3475 struct efx_ef10_filter_table *table = efx->filter_state;
3476 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3477 struct efx_filter_spec *spec;
3478 unsigned int filter_idx;
3479 int rc;
3480
0d322413
EC		 3481 efx->filter_state = NULL;
3482 if (!table)
3483 return;
3484
8127d661
BH		 3485 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3486 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3487 if (!spec)
3488 continue;
3489
3490 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3491 efx_ef10_filter_is_exclusive(spec) ?
3492 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3493 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3494 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3495 table->entry[filter_idx].handle);
3496 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3497 NULL, 0, NULL);
48ce5634
BH		 3498 if (rc)
3499 netdev_WARN(efx->net_dev,
3500 "filter_idx=%#x handle=%#llx\n",
3501 filter_idx,
3502 table->entry[filter_idx].handle);
8127d661
BH		 3503 kfree(spec);
3504 }
3505
3506 vfree(table->entry);
3507 kfree(table);
3508}
3509
0d322413
EC		 3510/* Caller must hold efx->filter_sem for read if race against
3511 * efx_ef10_filter_table_remove() is possible
3512 */
8127d661
BH		 3513static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3514{
3515 struct efx_ef10_filter_table *table = efx->filter_state;
3516 struct net_device *net_dev = efx->net_dev;
3517 struct efx_filter_spec spec;
3518 bool remove_failed = false;
3519 struct netdev_hw_addr *uc;
3520 struct netdev_hw_addr *mc;
3521 unsigned int filter_idx;
3522 int i, n, rc;
3523
3524 if (!efx_dev_registered(efx))
3525 return;
3526
0d322413
EC		 3527 if (!table)
3528 return;
3529
8127d661
BH		 3530 /* Mark old filters that may need to be removed */
3531 spin_lock_bh(&efx->filter_lock);
b59e6ef8 3532 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
8127d661 3533 for (i = 0; i < n; i++) {
b59e6ef8
BH		 3534 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3535 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661 3536 }
b59e6ef8 3537 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
8127d661 3538 for (i = 0; i < n; i++) {
b59e6ef8
BH		 3539 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3540 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3541 }
3542 spin_unlock_bh(&efx->filter_lock);
3543
3544 /* Copy/convert the address lists; add the primary station
3545 * address and broadcast address
3546 */
3547 netif_addr_lock_bh(net_dev);
3548 if (net_dev->flags & IFF_PROMISC ||
b59e6ef8
BH		 3549 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3550 table->dev_uc_count = -1;
8127d661 3551 } else {
b59e6ef8 3552 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
cd84ff4d 3553 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
8127d661
BH		 3554 i = 1;
3555 netdev_for_each_uc_addr(uc, net_dev) {
cd84ff4d 3556 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
8127d661
BH		 3557 i++;
3558 }
3559 }
3560 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
b59e6ef8
BH		 3561 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3562 table->dev_mc_count = -1;
8127d661 3563 } else {
b59e6ef8
BH		 3564 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3565 eth_broadcast_addr(table->dev_mc_list[0].addr);
8127d661
BH		 3566 i = 1;
3567 netdev_for_each_mc_addr(mc, net_dev) {
cd84ff4d 3568 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
8127d661
BH		 3569 i++;
3570 }
3571 }
3572 netif_addr_unlock_bh(net_dev);
3573
3574 /* Insert/renew unicast filters */
b59e6ef8
BH		 3575 if (table->dev_uc_count >= 0) {
3576 for (i = 0; i < table->dev_uc_count; i++) {
7665d1ab
BH		 3577 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3578 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3579 0);
3580 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
b59e6ef8 3581 table->dev_uc_list[i].addr);
8127d661
BH		 3582 rc = efx_ef10_filter_insert(efx, &spec, true);
3583 if (rc < 0) {
3584 /* Fall back to unicast-promisc */
3585 while (i--)
3586 efx_ef10_filter_remove_safe(
7665d1ab 3587 efx, EFX_FILTER_PRI_AUTO,
b59e6ef8
BH		 3588 table->dev_uc_list[i].id);
3589 table->dev_uc_count = -1;
8127d661
BH		 3590 break;
3591 }
b59e6ef8 3592 table->dev_uc_list[i].id = rc;
8127d661
BH		 3593 }
3594 }
b59e6ef8 3595 if (table->dev_uc_count < 0) {
7665d1ab
BH		 3596 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3597 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3598 0);
3599 efx_filter_set_uc_def(&spec);
3600 rc = efx_ef10_filter_insert(efx, &spec, true);
3601 if (rc < 0) {
3602 WARN_ON(1);
b59e6ef8 3603 table->dev_uc_count = 0;
8127d661 3604 } else {
b59e6ef8 3605 table->dev_uc_list[0].id = rc;
8127d661
BH		 3606 }
3607 }
3608
3609 /* Insert/renew multicast filters */
b59e6ef8
BH		 3610 if (table->dev_mc_count >= 0) {
3611 for (i = 0; i < table->dev_mc_count; i++) {
7665d1ab
BH		 3612 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3613 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3614 0);
3615 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
b59e6ef8 3616 table->dev_mc_list[i].addr);
8127d661
BH		 3617 rc = efx_ef10_filter_insert(efx, &spec, true);
3618 if (rc < 0) {
3619 /* Fall back to multicast-promisc */
3620 while (i--)
3621 efx_ef10_filter_remove_safe(
7665d1ab 3622 efx, EFX_FILTER_PRI_AUTO,
b59e6ef8
BH		 3623 table->dev_mc_list[i].id);
3624 table->dev_mc_count = -1;
8127d661
BH		 3625 break;
3626 }
b59e6ef8 3627 table->dev_mc_list[i].id = rc;
8127d661
BH		 3628 }
3629 }
b59e6ef8 3630 if (table->dev_mc_count < 0) {
7665d1ab
BH		 3631 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3632 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3633 0);
3634 efx_filter_set_mc_def(&spec);
3635 rc = efx_ef10_filter_insert(efx, &spec, true);
3636 if (rc < 0) {
3637 WARN_ON(1);
b59e6ef8 3638 table->dev_mc_count = 0;
8127d661 3639 } else {
b59e6ef8 3640 table->dev_mc_list[0].id = rc;
8127d661
BH		 3641 }
3642 }
3643
3644 /* Remove filters that weren't renewed. Since nothing else
b59e6ef8 3645 * changes the AUTO_OLD flag or removes these filters, we
8127d661
BH		 3646 * don't need to hold the filter_lock while scanning for
3647 * these filters.
3648 */
3649 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3650 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 3651 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
7665d1ab 3652 if (efx_ef10_filter_remove_internal(
fbd79120
BH		 3653 efx, 1U << EFX_FILTER_PRI_AUTO,
3654 i, true) < 0)
8127d661
BH		 3655 remove_failed = true;
3656 }
3657 }
3658 WARN_ON(remove_failed);
3659}
3660
910c8789
SS		 3661static int efx_ef10_set_mac_address(struct efx_nic *efx)
3662{
3663 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
3664 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3665 bool was_enabled = efx->port_enabled;
3666 int rc;
3667
3668 efx_device_detach_sync(efx);
3669 efx_net_stop(efx->net_dev);
3670 down_write(&efx->filter_sem);
3671 efx_ef10_filter_table_remove(efx);
3672
3673 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
3674 efx->net_dev->dev_addr);
3675 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
3676 nic_data->vport_id);
3677 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
3678 sizeof(inbuf), NULL, 0, NULL);
3679
3680 efx_ef10_filter_table_probe(efx);
3681 up_write(&efx->filter_sem);
3682 if (was_enabled)
3683 efx_net_open(efx->net_dev);
3684 netif_device_attach(efx->net_dev);
3685
3686#if !defined(CONFIG_SFC_SRIOV)
3687 if (rc == -EPERM)
3688 netif_err(efx, drv, efx->net_dev,
3689 "Cannot change MAC address; use sfboot to enable mac-spoofing"
3690 " on this interface\n");
3691#else
3692 if (rc == -EPERM) {
3693 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
3694
3695 /* Switch to PF and change MAC address on vport */
3696 if (efx->pci_dev->is_virtfn && pci_dev_pf) {
3697 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
3698
3699 if (!efx_ef10_sriov_set_vf_mac(efx_pf,
3700 nic_data->vf_index,
3701 efx->net_dev->dev_addr))
3702 return 0;
3703 }
3704 netif_err(efx, drv, efx->net_dev,
3705 "Cannot change MAC address; use sfboot to enable mac-spoofing"
3706 " on this interface\n");
3707 } else if (efx->pci_dev->is_virtfn) {
3708 /* Successfully changed by VF (with MAC spoofing), so update the
3709 * parent PF if possible.
3710 */
3711 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
3712
3713 if (pci_dev_pf) {
3714 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
3715 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
3716 unsigned int i;
3717
3718 for (i = 0; i < efx_pf->vf_count; ++i) {
3719 struct ef10_vf *vf = nic_data->vf + i;
3720
3721 if (vf->efx == efx) {
3722 ether_addr_copy(vf->mac,
3723 efx->net_dev->dev_addr);
3724 return 0;
3725 }
3726 }
3727 }
3728 }
3729#endif
3730 return rc;
3731}
3732
8127d661
BH		 3733static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3734{
3735 efx_ef10_filter_sync_rx_mode(efx);
3736
3737 return efx_mcdi_set_mac(efx);
3738}
3739
862f894c
SS		 3740static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
3741{
3742 efx_ef10_filter_sync_rx_mode(efx);
3743
3744 return 0;
3745}
3746
74cd60a4
JC		 3747static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3748{
3749 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3750
3751 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3752 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3753 NULL, 0, NULL);
3754}
3755
3756/* MC BISTs follow a different poll mechanism to phy BISTs.
3757 * The BIST is done in the poll handler on the MC, and the MCDI command
3758 * will block until the BIST is done.
3759 */
3760static int efx_ef10_poll_bist(struct efx_nic *efx)
3761{
3762 int rc;
3763 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3764 size_t outlen;
3765 u32 result;
3766
3767 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3768 outbuf, sizeof(outbuf), &outlen);
3769 if (rc != 0)
3770 return rc;
3771
3772 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3773 return -EIO;
3774
3775 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3776 switch (result) {
3777 case MC_CMD_POLL_BIST_PASSED:
3778 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3779 return 0;
3780 case MC_CMD_POLL_BIST_TIMEOUT:
3781 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3782 return -EIO;
3783 case MC_CMD_POLL_BIST_FAILED:
3784 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3785 return -EIO;
3786 default:
3787 netif_err(efx, hw, efx->net_dev,
3788 "BIST returned unknown result %u", result);
3789 return -EIO;
3790 }
3791}
3792
3793static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3794{
3795 int rc;
3796
3797 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3798
3799 rc = efx_ef10_start_bist(efx, bist_type);
3800 if (rc != 0)
3801 return rc;
3802
3803 return efx_ef10_poll_bist(efx);
3804}
3805
3806static int
3807efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3808{
3809 int rc, rc2;
3810
3811 efx_reset_down(efx, RESET_TYPE_WORLD);
3812
3813 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3814 NULL, 0, NULL, 0, NULL);
3815 if (rc != 0)
3816 goto out;
3817
3818 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3819 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3820
3821 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3822
3823out:
3824 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3825 return rc ? rc : rc2;
3826}
3827
8127d661
BH		 3828#ifdef CONFIG_SFC_MTD
3829
3830struct efx_ef10_nvram_type_info {
3831 u16 type, type_mask;
3832 u8 port;
3833 const char *name;
3834};
3835
3836static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3837 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3838 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3839 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3840 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3841 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3842 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3843 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3844 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3845 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 3846 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 3847 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3848};
3849
3850static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3851 struct efx_mcdi_mtd_partition *part,
3852 unsigned int type)
3853{
3854 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3855 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3856 const struct efx_ef10_nvram_type_info *info;
3857 size_t size, erase_size, outlen;
3858 bool protected;
3859 int rc;
3860
3861 for (info = efx_ef10_nvram_types; ; info++) {
3862 if (info ==
3863 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3864 return -ENODEV;
3865 if ((type & ~info->type_mask) == info->type)
3866 break;
3867 }
3868 if (info->port != efx_port_num(efx))
3869 return -ENODEV;
3870
3871 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3872 if (rc)
3873 return rc;
3874 if (protected)
3875 return -ENODEV; /* hide it */
3876
3877 part->nvram_type = type;
3878
3879 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3880 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3881 outbuf, sizeof(outbuf), &outlen);
3882 if (rc)
3883 return rc;
3884 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3885 return -EIO;
3886 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3887 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3888 part->fw_subtype = MCDI_DWORD(outbuf,
3889 NVRAM_METADATA_OUT_SUBTYPE);
3890
3891 part->common.dev_type_name = "EF10 NVRAM manager";
3892 part->common.type_name = info->name;
3893
3894 part->common.mtd.type = MTD_NORFLASH;
3895 part->common.mtd.flags = MTD_CAP_NORFLASH;
3896 part->common.mtd.size = size;
3897 part->common.mtd.erasesize = erase_size;
3898
3899 return 0;
3900}
3901
3902static int efx_ef10_mtd_probe(struct efx_nic *efx)
3903{
3904 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3905 struct efx_mcdi_mtd_partition *parts;
3906 size_t outlen, n_parts_total, i, n_parts;
3907 unsigned int type;
3908 int rc;
3909
3910 ASSERT_RTNL();
3911
3912 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3913 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3914 outbuf, sizeof(outbuf), &outlen);
3915 if (rc)
3916 return rc;
3917 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3918 return -EIO;
3919
3920 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3921 if (n_parts_total >
3922 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3923 return -EIO;
3924
3925 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3926 if (!parts)
3927 return -ENOMEM;
3928
3929 n_parts = 0;
3930 for (i = 0; i < n_parts_total; i++) {
3931 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3932 i);
3933 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3934 if (rc == 0)
3935 n_parts++;
3936 else if (rc != -ENODEV)
3937 goto fail;
3938 }
3939
3940 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3941fail:
3942 if (rc)
3943 kfree(parts);
3944 return rc;
3945}
3946
3947#endif /* CONFIG_SFC_MTD */
3948
3949static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3950{
3951 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3952}
3953
02246a7f
SS		 3954static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
3955 u32 host_time) {}
3956
bd9a265d
JC		 3957static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3958 bool temp)
3959{
3960 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3961 int rc;
3962
3963 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3964 channel->sync_events_state == SYNC_EVENTS_VALID ||
3965 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3966 return 0;
3967 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3968
3969 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3970 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3971 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3972 channel->channel);
3973
3974 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3975 inbuf, sizeof(inbuf), NULL, 0, NULL);
3976
3977 if (rc != 0)
3978 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3979 SYNC_EVENTS_DISABLED;
3980
3981 return rc;
3982}
3983
3984static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3985 bool temp)
3986{
3987 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3988 int rc;
3989
3990 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3991 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3992 return 0;
3993 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3994 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3995 return 0;
3996 }
3997 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3998 SYNC_EVENTS_DISABLED;
3999
4000 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4001 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4002 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4003 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4004 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4005 channel->channel);
4006
4007 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4008 inbuf, sizeof(inbuf), NULL, 0, NULL);
4009
4010 return rc;
4011}
4012
4013static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4014 bool temp)
4015{
4016 int (*set)(struct efx_channel *channel, bool temp);
4017 struct efx_channel *channel;
4018
4019 set = en ?
4020 efx_ef10_rx_enable_timestamping :
4021 efx_ef10_rx_disable_timestamping;
4022
4023 efx_for_each_channel(channel, efx) {
4024 int rc = set(channel, temp);
4025 if (en && rc != 0) {
4026 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4027 return rc;
4028 }
4029 }
4030
4031 return 0;
4032}
4033
02246a7f
SS		 4034static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4035 struct hwtstamp_config *init)
4036{
4037 return -EOPNOTSUPP;
4038}
4039
bd9a265d
JC		 4040static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4041 struct hwtstamp_config *init)
4042{
4043 int rc;
4044
4045 switch (init->rx_filter) {
4046 case HWTSTAMP_FILTER_NONE:
4047 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4048 /* if TX timestamping is still requested then leave PTP on */
4049 return efx_ptp_change_mode(efx,
4050 init->tx_type != HWTSTAMP_TX_OFF, 0);
4051 case HWTSTAMP_FILTER_ALL:
4052 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4053 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4054 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4055 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4056 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4057 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4058 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4059 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4060 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4061 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4062 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4063 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4064 init->rx_filter = HWTSTAMP_FILTER_ALL;
4065 rc = efx_ptp_change_mode(efx, true, 0);
4066 if (!rc)
4067 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4068 if (rc)
4069 efx_ptp_change_mode(efx, false, 0);
4070 return rc;
4071 default:
4072 return -ERANGE;
4073 }
4074}
4075
02246a7f 4076const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 4077 .is_vf = true,
02246a7f
SS		 4078 .mem_bar = EFX_MEM_VF_BAR,
4079 .mem_map_size = efx_ef10_mem_map_size,
4080 .probe = efx_ef10_probe_vf,
4081 .remove = efx_ef10_remove,
4082 .dimension_resources = efx_ef10_dimension_resources,
4083 .init = efx_ef10_init_nic,
4084 .fini = efx_port_dummy_op_void,
087e9025 4085 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 4086 .map_reset_flags = efx_ef10_map_reset_flags,
4087 .reset = efx_ef10_reset,
4088 .probe_port = efx_mcdi_port_probe,
4089 .remove_port = efx_mcdi_port_remove,
4090 .fini_dmaq = efx_ef10_fini_dmaq,
4091 .prepare_flr = efx_ef10_prepare_flr,
4092 .finish_flr = efx_port_dummy_op_void,
4093 .describe_stats = efx_ef10_describe_stats,
4094 .update_stats = efx_ef10_update_stats,
4095 .start_stats = efx_port_dummy_op_void,
4096 .pull_stats = efx_port_dummy_op_void,
4097 .stop_stats = efx_port_dummy_op_void,
4098 .set_id_led = efx_mcdi_set_id_led,
4099 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 4100 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 4101 .check_mac_fault = efx_mcdi_mac_check_fault,
4102 .reconfigure_port = efx_mcdi_port_reconfigure,
4103 .get_wol = efx_ef10_get_wol_vf,
4104 .set_wol = efx_ef10_set_wol_vf,
4105 .resume_wol = efx_port_dummy_op_void,
4106 .mcdi_request = efx_ef10_mcdi_request,
4107 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4108 .mcdi_read_response = efx_ef10_mcdi_read_response,
4109 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4110 .irq_enable_master = efx_port_dummy_op_void,
4111 .irq_test_generate = efx_ef10_irq_test_generate,
4112 .irq_disable_non_ev = efx_port_dummy_op_void,
4113 .irq_handle_msi = efx_ef10_msi_interrupt,
4114 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4115 .tx_probe = efx_ef10_tx_probe,
4116 .tx_init = efx_ef10_tx_init,
4117 .tx_remove = efx_ef10_tx_remove,
4118 .tx_write = efx_ef10_tx_write,
267c0157 4119 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 4120 .rx_probe = efx_ef10_rx_probe,
4121 .rx_init = efx_ef10_rx_init,
4122 .rx_remove = efx_ef10_rx_remove,
4123 .rx_write = efx_ef10_rx_write,
4124 .rx_defer_refill = efx_ef10_rx_defer_refill,
4125 .ev_probe = efx_ef10_ev_probe,
4126 .ev_init = efx_ef10_ev_init,
4127 .ev_fini = efx_ef10_ev_fini,
4128 .ev_remove = efx_ef10_ev_remove,
4129 .ev_process = efx_ef10_ev_process,
4130 .ev_read_ack = efx_ef10_ev_read_ack,
4131 .ev_test_generate = efx_ef10_ev_test_generate,
4132 .filter_table_probe = efx_ef10_filter_table_probe,
4133 .filter_table_restore = efx_ef10_filter_table_restore,
4134 .filter_table_remove = efx_ef10_filter_table_remove,
4135 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4136 .filter_insert = efx_ef10_filter_insert,
4137 .filter_remove_safe = efx_ef10_filter_remove_safe,
4138 .filter_get_safe = efx_ef10_filter_get_safe,
4139 .filter_clear_rx = efx_ef10_filter_clear_rx,
4140 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4141 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4142 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4143#ifdef CONFIG_RFS_ACCEL
4144 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4145 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4146#endif
4147#ifdef CONFIG_SFC_MTD
4148 .mtd_probe = efx_port_dummy_op_int,
4149#endif
4150 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4151 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4152#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 4153 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4154 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4155 .vswitching_remove = efx_ef10_vswitching_remove_vf,
1d051e00 4156 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
02246a7f 4157#endif
0d5e0fbb 4158 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 4159 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 4160
02246a7f
SS		 4161 .revision = EFX_REV_HUNT_A0,
4162 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4163 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4164 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4165 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4166 .can_rx_scatter = true,
4167 .always_rx_scatter = true,
4168 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4169 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4170 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4171 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4172 .mcdi_max_ver = 2,
4173 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4174 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4175 1 << HWTSTAMP_FILTER_ALL,
4176};
4177
8127d661 4178const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 4179 .is_vf = false,
02246a7f 4180 .mem_bar = EFX_MEM_BAR,
8127d661 4181 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 4182 .probe = efx_ef10_probe_pf,
8127d661
BH		 4183 .remove = efx_ef10_remove,
4184 .dimension_resources = efx_ef10_dimension_resources,
4185 .init = efx_ef10_init_nic,
4186 .fini = efx_port_dummy_op_void,
087e9025 4187 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 4188 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 4189 .reset = efx_ef10_reset,
8127d661
BH		 4190 .probe_port = efx_mcdi_port_probe,
4191 .remove_port = efx_mcdi_port_remove,
4192 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 4193 .prepare_flr = efx_ef10_prepare_flr,
4194 .finish_flr = efx_port_dummy_op_void,
8127d661
BH		 4195 .describe_stats = efx_ef10_describe_stats,
4196 .update_stats = efx_ef10_update_stats,
4197 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 4198 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 4199 .stop_stats = efx_mcdi_mac_stop_stats,
4200 .set_id_led = efx_mcdi_set_id_led,
4201 .push_irq_moderation = efx_ef10_push_irq_moderation,
4202 .reconfigure_mac = efx_ef10_mac_reconfigure,
4203 .check_mac_fault = efx_mcdi_mac_check_fault,
4204 .reconfigure_port = efx_mcdi_port_reconfigure,
4205 .get_wol = efx_ef10_get_wol,
4206 .set_wol = efx_ef10_set_wol,
4207 .resume_wol = efx_port_dummy_op_void,
74cd60a4 4208 .test_chip = efx_ef10_test_chip,
8127d661
BH		 4209 .test_nvram = efx_mcdi_nvram_test_all,
4210 .mcdi_request = efx_ef10_mcdi_request,
4211 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4212 .mcdi_read_response = efx_ef10_mcdi_read_response,
4213 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4214 .irq_enable_master = efx_port_dummy_op_void,
4215 .irq_test_generate = efx_ef10_irq_test_generate,
4216 .irq_disable_non_ev = efx_port_dummy_op_void,
4217 .irq_handle_msi = efx_ef10_msi_interrupt,
4218 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4219 .tx_probe = efx_ef10_tx_probe,
4220 .tx_init = efx_ef10_tx_init,
4221 .tx_remove = efx_ef10_tx_remove,
4222 .tx_write = efx_ef10_tx_write,
267c0157 4223 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 4224 .rx_probe = efx_ef10_rx_probe,
4225 .rx_init = efx_ef10_rx_init,
4226 .rx_remove = efx_ef10_rx_remove,
4227 .rx_write = efx_ef10_rx_write,
4228 .rx_defer_refill = efx_ef10_rx_defer_refill,
4229 .ev_probe = efx_ef10_ev_probe,
4230 .ev_init = efx_ef10_ev_init,
4231 .ev_fini = efx_ef10_ev_fini,
4232 .ev_remove = efx_ef10_ev_remove,
4233 .ev_process = efx_ef10_ev_process,
4234 .ev_read_ack = efx_ef10_ev_read_ack,
4235 .ev_test_generate = efx_ef10_ev_test_generate,
4236 .filter_table_probe = efx_ef10_filter_table_probe,
4237 .filter_table_restore = efx_ef10_filter_table_restore,
4238 .filter_table_remove = efx_ef10_filter_table_remove,
4239 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4240 .filter_insert = efx_ef10_filter_insert,
4241 .filter_remove_safe = efx_ef10_filter_remove_safe,
4242 .filter_get_safe = efx_ef10_filter_get_safe,
4243 .filter_clear_rx = efx_ef10_filter_clear_rx,
4244 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4245 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4246 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4247#ifdef CONFIG_RFS_ACCEL
4248 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4249 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4250#endif
4251#ifdef CONFIG_SFC_MTD
4252 .mtd_probe = efx_ef10_mtd_probe,
4253 .mtd_rename = efx_mcdi_mtd_rename,
4254 .mtd_read = efx_mcdi_mtd_read,
4255 .mtd_erase = efx_mcdi_mtd_erase,
4256 .mtd_write = efx_mcdi_mtd_write,
4257 .mtd_sync = efx_mcdi_mtd_sync,
4258#endif
4259 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 4260 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4261 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
7fa8d547 4262#ifdef CONFIG_SFC_SRIOV
834e23dd 4263 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 4264 .sriov_init = efx_ef10_sriov_init,
4265 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 4266 .sriov_wanted = efx_ef10_sriov_wanted,
4267 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 4268 .sriov_flr = efx_ef10_sriov_flr,
4269 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4270 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4271 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4272 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 4273 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 4274 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4275 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4276 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 4277#endif
0d5e0fbb 4278 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 4279 .set_mac_address = efx_ef10_set_mac_address,
8127d661
BH		 4280
4281 .revision = EFX_REV_HUNT_A0,
4282 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4283 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4284 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 4285 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 4286 .can_rx_scatter = true,
4287 .always_rx_scatter = true,
4288 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4289 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4290 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4291 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4292 .mcdi_max_ver = 2,
4293 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 4294 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4295 1 << HWTSTAMP_FILTER_ALL,
8127d661 4296};
Linux kernel - Deliverables
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