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Merge branch 'thunderx-next'
[deliverable/linux.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
52struct efx_ef10_filter_table {
53/* The RX match field masks supported by this fw & hw, in order of priority */
54 enum efx_filter_match_flags rx_match_flags[
55 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
56 unsigned int rx_match_count;
57
58 struct {
59 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 60/* BUSY flag indicates that an update is in progress. AUTO_OLD is
61 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 62 */
63#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 64#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 65#define EFX_EF10_FILTER_FLAGS 3UL
66 u64 handle; /* firmware handle */
67 } *entry;
68 wait_queue_head_t waitq;
69/* Shadow of net_device address lists, guarded by mac_lock */
b59e6ef8
BH		 70#define EFX_EF10_FILTER_DEV_UC_MAX 32
71#define EFX_EF10_FILTER_DEV_MC_MAX 256
8127d661
BH		 72 struct {
73 u8 addr[ETH_ALEN];
74 u16 id;
b59e6ef8
BH		 75 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
76 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
77 int dev_uc_count; /* negative for PROMISC */
78 int dev_mc_count; /* negative for PROMISC/ALLMULTI */
8127d661
BH		 79};
80
81/* An arbitrary search limit for the software hash table */
82#define EFX_EF10_FILTER_SEARCH_LIMIT 200
83
8127d661
BH		 84static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
85static void efx_ef10_filter_table_remove(struct efx_nic *efx);
86
87static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
88{
89 efx_dword_t reg;
90
91 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
92 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
93 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
94}
95
96static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
97{
02246a7f
SS		 98 int bar;
99
100 bar = efx->type->mem_bar;
101 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 102}
103
1cd9ecbb
DP		 104static int efx_ef10_get_pf_index(struct efx_nic *efx)
105{
106 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
107 struct efx_ef10_nic_data *nic_data = efx->nic_data;
108 size_t outlen;
109 int rc;
110
111 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
112 sizeof(outbuf), &outlen);
113 if (rc)
114 return rc;
115 if (outlen < sizeof(outbuf))
116 return -EIO;
117
118 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
119 return 0;
120}
121
88a37de6
SS		 122#ifdef CONFIG_SFC_SRIOV
123static int efx_ef10_get_vf_index(struct efx_nic *efx)
124{
125 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
126 struct efx_ef10_nic_data *nic_data = efx->nic_data;
127 size_t outlen;
128 int rc;
129
130 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
131 sizeof(outbuf), &outlen);
132 if (rc)
133 return rc;
134 if (outlen < sizeof(outbuf))
135 return -EIO;
136
137 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
138 return 0;
139}
140#endif
141
e5a2538a 142static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 143{
144 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
145 struct efx_ef10_nic_data *nic_data = efx->nic_data;
146 size_t outlen;
147 int rc;
148
149 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
150
151 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
152 outbuf, sizeof(outbuf), &outlen);
153 if (rc)
154 return rc;
e5a2538a
BH		 155 if (outlen < sizeof(outbuf)) {
156 netif_err(efx, drv, efx->net_dev,
157 "unable to read datapath firmware capabilities\n");
158 return -EIO;
159 }
160
161 nic_data->datapath_caps =
162 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 163
8d9f9dd4
DP		 164 /* record the DPCPU firmware IDs to determine VEB vswitching support.
165 */
166 nic_data->rx_dpcpu_fw_id =
167 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
168 nic_data->tx_dpcpu_fw_id =
169 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
170
e5a2538a
BH		 171 if (!(nic_data->datapath_caps &
172 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
173 netif_err(efx, drv, efx->net_dev,
174 "current firmware does not support TSO\n");
175 return -ENODEV;
176 }
177
178 if (!(nic_data->datapath_caps &
179 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
180 netif_err(efx, probe, efx->net_dev,
181 "current firmware does not support an RX prefix\n");
182 return -ENODEV;
8127d661
BH		 183 }
184
185 return 0;
186}
187
188static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
189{
190 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
191 int rc;
192
193 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
194 outbuf, sizeof(outbuf), NULL);
195 if (rc)
196 return rc;
197 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
198 return rc > 0 ? rc : -ERANGE;
199}
200
0d5e0fbb 201static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 202{
203 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
204 size_t outlen;
205 int rc;
206
207 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
208
209 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
210 outbuf, sizeof(outbuf), &outlen);
211 if (rc)
212 return rc;
213 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
214 return -EIO;
215
cd84ff4d
EC		 216 ether_addr_copy(mac_address,
217 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 218 return 0;
219}
220
0d5e0fbb
DP		 221static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
222{
223 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
224 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
225 size_t outlen;
226 int num_addrs, rc;
227
228 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
229 EVB_PORT_ID_ASSIGNED);
230 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
231 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
232
233 if (rc)
234 return rc;
235 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
236 return -EIO;
237
238 num_addrs = MCDI_DWORD(outbuf,
239 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
240
241 WARN_ON(num_addrs != 1);
242
243 ether_addr_copy(mac_address,
244 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
245
246 return 0;
247}
248
8127d661
BH		 249static int efx_ef10_probe(struct efx_nic *efx)
250{
251 struct efx_ef10_nic_data *nic_data;
252 int i, rc;
253
aa3930ee
BH		 254 /* We can have one VI for each 8K region. However, until we
255 * use TX option descriptors we need two TX queues per channel.
8127d661
BH		 256 */
257 efx->max_channels =
258 min_t(unsigned int,
259 EFX_MAX_CHANNELS,
02246a7f 260 efx_ef10_mem_map_size(efx) /
8127d661 261 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
9fd3d3a4
EC		 262 if (WARN_ON(efx->max_channels == 0))
263 return -EIO;
8127d661
BH		 264
265 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
266 if (!nic_data)
267 return -ENOMEM;
268 efx->nic_data = nic_data;
269
75aba2a5
EC		 270 /* we assume later that we can copy from this buffer in dwords */
271 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
272
8127d661
BH		 273 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
274 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
275 if (rc)
276 goto fail1;
277
278 /* Get the MC's warm boot count. In case it's rebooting right
279 * now, be prepared to retry.
280 */
281 i = 0;
282 for (;;) {
283 rc = efx_ef10_get_warm_boot_count(efx);
284 if (rc >= 0)
285 break;
286 if (++i == 5)
287 goto fail2;
288 ssleep(1);
289 }
290 nic_data->warm_boot_count = rc;
291
292 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
293
45b2449e
DP		 294 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
295
8127d661
BH		 296 /* In case we're recovering from a crash (kexec), we want to
297 * cancel any outstanding request by the previous user of this
298 * function. We send a special message using the least
299 * significant bits of the 'high' (doorbell) register.
300 */
301 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
302
303 rc = efx_mcdi_init(efx);
304 if (rc)
305 goto fail2;
306
307 /* Reset (most) configuration for this function */
308 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
309 if (rc)
310 goto fail3;
311
312 /* Enable event logging */
313 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
314 if (rc)
315 goto fail3;
316
1cd9ecbb
DP		 317 rc = efx_ef10_get_pf_index(efx);
318 if (rc)
319 goto fail3;
320
e5a2538a 321 rc = efx_ef10_init_datapath_caps(efx);
8127d661
BH		 322 if (rc < 0)
323 goto fail3;
324
325 efx->rx_packet_len_offset =
326 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
327
8127d661
BH		 328 rc = efx_mcdi_port_get_number(efx);
329 if (rc < 0)
330 goto fail3;
331 efx->port_num = rc;
332
0d5e0fbb 333 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661
BH		 334 if (rc)
335 goto fail3;
336
337 rc = efx_ef10_get_sysclk_freq(efx);
338 if (rc < 0)
339 goto fail3;
340 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
341
267d9d73
EC		 342 /* Check whether firmware supports bug 35388 workaround.
343 * First try to enable it, then if we get EPERM, just
344 * ask if it's already enabled
345 */
8127d661
BH		 346 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
347 if (rc == 0)
348 nic_data->workaround_35388 = true;
267d9d73
EC		 349 else if (rc == -EPERM) {
350 unsigned int enabled;
351
352 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
353 if (rc)
354 goto fail3;
355 nic_data->workaround_35388 = enabled &
356 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
357 }
8127d661
BH		 358 else if (rc != -ENOSYS && rc != -ENOENT)
359 goto fail3;
360 netif_dbg(efx, probe, efx->net_dev,
361 "workaround for bug 35388 is %sabled\n",
362 nic_data->workaround_35388 ? "en" : "dis");
363
364 rc = efx_mcdi_mon_probe(efx);
267d9d73 365 if (rc && rc != -EPERM)
8127d661
BH		 366 goto fail3;
367
9aecda95
BH		 368 efx_ptp_probe(efx, NULL);
369
8127d661
BH		 370 return 0;
371
372fail3:
373 efx_mcdi_fini(efx);
374fail2:
375 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
376fail1:
377 kfree(nic_data);
378 efx->nic_data = NULL;
379 return rc;
380}
381
382static int efx_ef10_free_vis(struct efx_nic *efx)
383{
aa09a3da 384 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 385 size_t outlen;
386 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
387 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 388
389 /* -EALREADY means nothing to free, so ignore */
390 if (rc == -EALREADY)
391 rc = 0;
1e0b8120
EC		 392 if (rc)
393 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
394 rc);
8127d661
BH		 395 return rc;
396}
397
183233be
BH		 398#ifdef EFX_USE_PIO
399
400static void efx_ef10_free_piobufs(struct efx_nic *efx)
401{
402 struct efx_ef10_nic_data *nic_data = efx->nic_data;
403 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
404 unsigned int i;
405 int rc;
406
407 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
408
409 for (i = 0; i < nic_data->n_piobufs; i++) {
410 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
411 nic_data->piobuf_handle[i]);
412 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
413 NULL, 0, NULL);
414 WARN_ON(rc);
415 }
416
417 nic_data->n_piobufs = 0;
418}
419
420static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
421{
422 struct efx_ef10_nic_data *nic_data = efx->nic_data;
423 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
424 unsigned int i;
425 size_t outlen;
426 int rc = 0;
427
428 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
429
430 for (i = 0; i < n; i++) {
431 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
432 outbuf, sizeof(outbuf), &outlen);
433 if (rc)
434 break;
435 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
436 rc = -EIO;
437 break;
438 }
439 nic_data->piobuf_handle[i] =
440 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
441 netif_dbg(efx, probe, efx->net_dev,
442 "allocated PIO buffer %u handle %x\n", i,
443 nic_data->piobuf_handle[i]);
444 }
445
446 nic_data->n_piobufs = i;
447 if (rc)
448 efx_ef10_free_piobufs(efx);
449 return rc;
450}
451
452static int efx_ef10_link_piobufs(struct efx_nic *efx)
453{
454 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 455 _MCDI_DECLARE_BUF(inbuf,
456 max(MC_CMD_LINK_PIOBUF_IN_LEN,
457 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 458 struct efx_channel *channel;
459 struct efx_tx_queue *tx_queue;
460 unsigned int offset, index;
461 int rc;
462
463 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
464 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
465
aa09a3da
JC		 466 memset(inbuf, 0, sizeof(inbuf));
467
183233be
BH		 468 /* Link a buffer to each VI in the write-combining mapping */
469 for (index = 0; index < nic_data->n_piobufs; ++index) {
470 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
471 nic_data->piobuf_handle[index]);
472 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
473 nic_data->pio_write_vi_base + index);
474 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
475 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
476 NULL, 0, NULL);
477 if (rc) {
478 netif_err(efx, drv, efx->net_dev,
479 "failed to link VI %u to PIO buffer %u (%d)\n",
480 nic_data->pio_write_vi_base + index, index,
481 rc);
482 goto fail;
483 }
484 netif_dbg(efx, probe, efx->net_dev,
485 "linked VI %u to PIO buffer %u\n",
486 nic_data->pio_write_vi_base + index, index);
487 }
488
489 /* Link a buffer to each TX queue */
490 efx_for_each_channel(channel, efx) {
491 efx_for_each_channel_tx_queue(tx_queue, channel) {
492 /* We assign the PIO buffers to queues in
493 * reverse order to allow for the following
494 * special case.
495 */
496 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
497 tx_queue->channel->channel - 1) *
498 efx_piobuf_size);
499 index = offset / ER_DZ_TX_PIOBUF_SIZE;
500 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
501
502 /* When the host page size is 4K, the first
503 * host page in the WC mapping may be within
504 * the same VI page as the last TX queue. We
505 * can only link one buffer to each VI.
506 */
507 if (tx_queue->queue == nic_data->pio_write_vi_base) {
508 BUG_ON(index != 0);
509 rc = 0;
510 } else {
511 MCDI_SET_DWORD(inbuf,
512 LINK_PIOBUF_IN_PIOBUF_HANDLE,
513 nic_data->piobuf_handle[index]);
514 MCDI_SET_DWORD(inbuf,
515 LINK_PIOBUF_IN_TXQ_INSTANCE,
516 tx_queue->queue);
517 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
518 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
519 NULL, 0, NULL);
520 }
521
522 if (rc) {
523 /* This is non-fatal; the TX path just
524 * won't use PIO for this queue
525 */
526 netif_err(efx, drv, efx->net_dev,
527 "failed to link VI %u to PIO buffer %u (%d)\n",
528 tx_queue->queue, index, rc);
529 tx_queue->piobuf = NULL;
530 } else {
531 tx_queue->piobuf =
532 nic_data->pio_write_base +
533 index * EFX_VI_PAGE_SIZE + offset;
534 tx_queue->piobuf_offset = offset;
535 netif_dbg(efx, probe, efx->net_dev,
536 "linked VI %u to PIO buffer %u offset %x addr %p\n",
537 tx_queue->queue, index,
538 tx_queue->piobuf_offset,
539 tx_queue->piobuf);
540 }
541 }
542 }
543
544 return 0;
545
546fail:
547 while (index--) {
548 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
549 nic_data->pio_write_vi_base + index);
550 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
551 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
552 NULL, 0, NULL);
553 }
554 return rc;
555}
556
557#else /* !EFX_USE_PIO */
558
559static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
560{
561 return n == 0 ? 0 : -ENOBUFS;
562}
563
564static int efx_ef10_link_piobufs(struct efx_nic *efx)
565{
566 return 0;
567}
568
569static void efx_ef10_free_piobufs(struct efx_nic *efx)
570{
571}
572
573#endif /* EFX_USE_PIO */
574
8127d661
BH		 575static void efx_ef10_remove(struct efx_nic *efx)
576{
577 struct efx_ef10_nic_data *nic_data = efx->nic_data;
578 int rc;
579
f1122a34
SS		 580#ifdef CONFIG_SFC_SRIOV
581 struct efx_ef10_nic_data *nic_data_pf;
582 struct pci_dev *pci_dev_pf;
583 struct efx_nic *efx_pf;
584 struct ef10_vf *vf;
585
586 if (efx->pci_dev->is_virtfn) {
587 pci_dev_pf = efx->pci_dev->physfn;
588 if (pci_dev_pf) {
589 efx_pf = pci_get_drvdata(pci_dev_pf);
590 nic_data_pf = efx_pf->nic_data;
591 vf = nic_data_pf->vf + nic_data->vf_index;
592 vf->efx = NULL;
593 } else
594 netif_info(efx, drv, efx->net_dev,
595 "Could not get the PF id from VF\n");
596 }
597#endif
598
9aecda95
BH		 599 efx_ptp_remove(efx);
600
8127d661
BH		 601 efx_mcdi_mon_remove(efx);
602
8127d661
BH		 603 efx_ef10_rx_free_indir_table(efx);
604
183233be
BH		 605 if (nic_data->wc_membase)
606 iounmap(nic_data->wc_membase);
607
8127d661
BH		 608 rc = efx_ef10_free_vis(efx);
609 WARN_ON(rc != 0);
610
183233be
BH		 611 if (!nic_data->must_restore_piobufs)
612 efx_ef10_free_piobufs(efx);
613
8127d661
BH		 614 efx_mcdi_fini(efx);
615 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
616 kfree(nic_data);
617}
618
88a37de6
SS		 619static int efx_ef10_probe_pf(struct efx_nic *efx)
620{
621 return efx_ef10_probe(efx);
622}
623
624#ifdef CONFIG_SFC_SRIOV
625static int efx_ef10_probe_vf(struct efx_nic *efx)
626{
627 int rc;
628
629 rc = efx_ef10_probe(efx);
630 if (rc)
631 return rc;
632
633 rc = efx_ef10_get_vf_index(efx);
634 if (rc)
635 goto fail;
636
f1122a34
SS		 637 if (efx->pci_dev->is_virtfn) {
638 if (efx->pci_dev->physfn) {
639 struct efx_nic *efx_pf =
640 pci_get_drvdata(efx->pci_dev->physfn);
641 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
642 struct efx_ef10_nic_data *nic_data = efx->nic_data;
643
644 nic_data_p->vf[nic_data->vf_index].efx = efx;
645 } else
646 netif_info(efx, drv, efx->net_dev,
647 "Could not get the PF id from VF\n");
648 }
649
88a37de6
SS		 650 return 0;
651
652fail:
653 efx_ef10_remove(efx);
654 return rc;
655}
656#else
657static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
658{
659 return 0;
660}
661#endif
662
8127d661
BH		 663static int efx_ef10_alloc_vis(struct efx_nic *efx,
664 unsigned int min_vis, unsigned int max_vis)
665{
666 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
667 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
668 struct efx_ef10_nic_data *nic_data = efx->nic_data;
669 size_t outlen;
670 int rc;
671
672 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
673 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
674 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
675 outbuf, sizeof(outbuf), &outlen);
676 if (rc != 0)
677 return rc;
678
679 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
680 return -EIO;
681
682 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
683 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
684
685 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
686 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
687 return 0;
688}
689
183233be
BH		 690/* Note that the failure path of this function does not free
691 * resources, as this will be done by efx_ef10_remove().
692 */
8127d661
BH		 693static int efx_ef10_dimension_resources(struct efx_nic *efx)
694{
183233be
BH		 695 struct efx_ef10_nic_data *nic_data = efx->nic_data;
696 unsigned int uc_mem_map_size, wc_mem_map_size;
697 unsigned int min_vis, pio_write_vi_base, max_vis;
698 void __iomem *membase;
699 int rc;
700
701 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 702
183233be
BH		 703#ifdef EFX_USE_PIO
704 /* Try to allocate PIO buffers if wanted and if the full
705 * number of PIO buffers would be sufficient to allocate one
706 * copy-buffer per TX channel. Failure is non-fatal, as there
707 * are only a small number of PIO buffers shared between all
708 * functions of the controller.
709 */
710 if (efx_piobuf_size != 0 &&
711 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
712 efx->n_tx_channels) {
713 unsigned int n_piobufs =
714 DIV_ROUND_UP(efx->n_tx_channels,
715 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
716
717 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
718 if (rc)
719 netif_err(efx, probe, efx->net_dev,
720 "failed to allocate PIO buffers (%d)\n", rc);
721 else
722 netif_dbg(efx, probe, efx->net_dev,
723 "allocated %u PIO buffers\n", n_piobufs);
724 }
725#else
726 nic_data->n_piobufs = 0;
727#endif
728
729 /* PIO buffers should be mapped with write-combining enabled,
730 * and we want to make single UC and WC mappings rather than
731 * several of each (in fact that's the only option if host
732 * page size is >4K). So we may allocate some extra VIs just
733 * for writing PIO buffers through.
52ad762b
DP		 734 *
735 * The UC mapping contains (min_vis - 1) complete VIs and the
736 * first half of the next VI. Then the WC mapping begins with
737 * the second half of this last VI.
183233be
BH		 738 */
739 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
740 ER_DZ_TX_PIOBUF);
741 if (nic_data->n_piobufs) {
52ad762b
DP		 742 /* pio_write_vi_base rounds down to give the number of complete
743 * VIs inside the UC mapping.
744 */
183233be
BH		 745 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
746 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
747 nic_data->n_piobufs) *
748 EFX_VI_PAGE_SIZE) -
749 uc_mem_map_size);
750 max_vis = pio_write_vi_base + nic_data->n_piobufs;
751 } else {
752 pio_write_vi_base = 0;
753 wc_mem_map_size = 0;
754 max_vis = min_vis;
755 }
756
757 /* In case the last attached driver failed to free VIs, do it now */
758 rc = efx_ef10_free_vis(efx);
759 if (rc != 0)
760 return rc;
761
762 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
763 if (rc != 0)
764 return rc;
765
766 /* If we didn't get enough VIs to map all the PIO buffers, free the
767 * PIO buffers
768 */
769 if (nic_data->n_piobufs &&
770 nic_data->n_allocated_vis <
771 pio_write_vi_base + nic_data->n_piobufs) {
772 netif_dbg(efx, probe, efx->net_dev,
773 "%u VIs are not sufficient to map %u PIO buffers\n",
774 nic_data->n_allocated_vis, nic_data->n_piobufs);
775 efx_ef10_free_piobufs(efx);
776 }
777
778 /* Shrink the original UC mapping of the memory BAR */
779 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
780 if (!membase) {
781 netif_err(efx, probe, efx->net_dev,
782 "could not shrink memory BAR to %x\n",
783 uc_mem_map_size);
784 return -ENOMEM;
785 }
786 iounmap(efx->membase);
787 efx->membase = membase;
788
789 /* Set up the WC mapping if needed */
790 if (wc_mem_map_size) {
791 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
792 uc_mem_map_size,
793 wc_mem_map_size);
794 if (!nic_data->wc_membase) {
795 netif_err(efx, probe, efx->net_dev,
796 "could not allocate WC mapping of size %x\n",
797 wc_mem_map_size);
798 return -ENOMEM;
799 }
800 nic_data->pio_write_vi_base = pio_write_vi_base;
801 nic_data->pio_write_base =
802 nic_data->wc_membase +
803 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
804 uc_mem_map_size);
805
806 rc = efx_ef10_link_piobufs(efx);
807 if (rc)
808 efx_ef10_free_piobufs(efx);
809 }
810
811 netif_dbg(efx, probe, efx->net_dev,
812 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
813 &efx->membase_phys, efx->membase, uc_mem_map_size,
814 nic_data->wc_membase, wc_mem_map_size);
815
816 return 0;
8127d661
BH		 817}
818
819static int efx_ef10_init_nic(struct efx_nic *efx)
820{
821 struct efx_ef10_nic_data *nic_data = efx->nic_data;
822 int rc;
823
a915ccc9
BH		 824 if (nic_data->must_check_datapath_caps) {
825 rc = efx_ef10_init_datapath_caps(efx);
826 if (rc)
827 return rc;
828 nic_data->must_check_datapath_caps = false;
829 }
830
8127d661
BH		 831 if (nic_data->must_realloc_vis) {
832 /* We cannot let the number of VIs change now */
833 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
834 nic_data->n_allocated_vis);
835 if (rc)
836 return rc;
837 nic_data->must_realloc_vis = false;
838 }
839
183233be
BH		 840 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
841 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
842 if (rc == 0) {
843 rc = efx_ef10_link_piobufs(efx);
844 if (rc)
845 efx_ef10_free_piobufs(efx);
846 }
847
848 /* Log an error on failure, but this is non-fatal */
849 if (rc)
850 netif_err(efx, drv, efx->net_dev,
851 "failed to restore PIO buffers (%d)\n", rc);
852 nic_data->must_restore_piobufs = false;
853 }
854
267c0157
JC		 855 /* don't fail init if RSS setup doesn't work */
856 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
857
8127d661
BH		 858 return 0;
859}
860
3e336261
JC		 861static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
862{
863 struct efx_ef10_nic_data *nic_data = efx->nic_data;
864
865 /* All our allocations have been reset */
866 nic_data->must_realloc_vis = true;
867 nic_data->must_restore_filters = true;
868 nic_data->must_restore_piobufs = true;
869 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
870}
871
087e9025
JC		 872static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
873{
874 if (reason == RESET_TYPE_MC_FAILURE)
875 return RESET_TYPE_DATAPATH;
876
877 return efx_mcdi_map_reset_reason(reason);
878}
879
8127d661
BH		 880static int efx_ef10_map_reset_flags(u32 *flags)
881{
882 enum {
883 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
884 ETH_RESET_SHARED_SHIFT),
885 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
886 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
887 ETH_RESET_PHY | ETH_RESET_MGMT) <<
888 ETH_RESET_SHARED_SHIFT)
889 };
890
891 /* We assume for now that our PCI function is permitted to
892 * reset everything.
893 */
894
895 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
896 *flags &= ~EF10_RESET_MC;
897 return RESET_TYPE_WORLD;
898 }
899
900 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
901 *flags &= ~EF10_RESET_PORT;
902 return RESET_TYPE_ALL;
903 }
904
905 /* no invisible reset implemented */
906
907 return -EINVAL;
908}
909
3e336261
JC		 910static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
911{
912 int rc = efx_mcdi_reset(efx, reset_type);
913
914 /* If it was a port reset, trigger reallocation of MC resources.
915 * Note that on an MC reset nothing needs to be done now because we'll
916 * detect the MC reset later and handle it then.
e283546c
EC		 917 * For an FLR, we never get an MC reset event, but the MC has reset all
918 * resources assigned to us, so we have to trigger reallocation now.
3e336261 919 */
e283546c
EC		 920 if ((reset_type == RESET_TYPE_ALL ||
921 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 922 efx_ef10_reset_mc_allocations(efx);
923 return rc;
924}
925
8127d661
BH		 926#define EF10_DMA_STAT(ext_name, mcdi_name) \
927 [EF10_STAT_ ## ext_name] = \
928 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
929#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
930 [EF10_STAT_ ## int_name] = \
931 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
932#define EF10_OTHER_STAT(ext_name) \
933 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 934#define GENERIC_SW_STAT(ext_name) \
935 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 936
937static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
938 EF10_DMA_STAT(tx_bytes, TX_BYTES),
939 EF10_DMA_STAT(tx_packets, TX_PKTS),
940 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
941 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
942 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
943 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
944 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
945 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
946 EF10_DMA_STAT(tx_64, TX_64_PKTS),
947 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
948 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
949 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
950 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
951 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
952 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
953 EF10_DMA_STAT(rx_bytes, RX_BYTES),
954 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
955 EF10_OTHER_STAT(rx_good_bytes),
956 EF10_OTHER_STAT(rx_bad_bytes),
957 EF10_DMA_STAT(rx_packets, RX_PKTS),
958 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
959 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
960 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
961 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
962 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
963 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
964 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
965 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
966 EF10_DMA_STAT(rx_64, RX_64_PKTS),
967 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
968 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
969 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
970 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
971 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
972 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
973 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
974 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
975 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
976 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
977 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
978 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 979 GENERIC_SW_STAT(rx_nodesc_trunc),
980 GENERIC_SW_STAT(rx_noskb_drops),
568d7a00
EC		 981 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
982 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
983 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
984 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
985 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
986 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
987 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
988 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
989 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
990 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
79ac47ae
SS		 991 EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
992 EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
8127d661
BH		 993};
994
995#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
996 (1ULL << EF10_STAT_tx_packets) | \
997 (1ULL << EF10_STAT_tx_pause) | \
998 (1ULL << EF10_STAT_tx_unicast) | \
999 (1ULL << EF10_STAT_tx_multicast) | \
1000 (1ULL << EF10_STAT_tx_broadcast) | \
1001 (1ULL << EF10_STAT_rx_bytes) | \
1002 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
1003 (1ULL << EF10_STAT_rx_good_bytes) | \
1004 (1ULL << EF10_STAT_rx_bad_bytes) | \
1005 (1ULL << EF10_STAT_rx_packets) | \
1006 (1ULL << EF10_STAT_rx_good) | \
1007 (1ULL << EF10_STAT_rx_bad) | \
1008 (1ULL << EF10_STAT_rx_pause) | \
1009 (1ULL << EF10_STAT_rx_control) | \
1010 (1ULL << EF10_STAT_rx_unicast) | \
1011 (1ULL << EF10_STAT_rx_multicast) | \
1012 (1ULL << EF10_STAT_rx_broadcast) | \
1013 (1ULL << EF10_STAT_rx_lt64) | \
1014 (1ULL << EF10_STAT_rx_64) | \
1015 (1ULL << EF10_STAT_rx_65_to_127) | \
1016 (1ULL << EF10_STAT_rx_128_to_255) | \
1017 (1ULL << EF10_STAT_rx_256_to_511) | \
1018 (1ULL << EF10_STAT_rx_512_to_1023) | \
1019 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
1020 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
1021 (1ULL << EF10_STAT_rx_gtjumbo) | \
1022 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
1023 (1ULL << EF10_STAT_rx_overflow) | \
e4d112e4
EC		 1024 (1ULL << EF10_STAT_rx_nodesc_drops) | \
1025 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1026 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661
BH		 1027
1028/* These statistics are only provided by the 10G MAC. For a 10G/40G
1029 * switchable port we do not expose these because they might not
1030 * include all the packets they should.
1031 */
1032#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
1033 (1ULL << EF10_STAT_tx_lt64) | \
1034 (1ULL << EF10_STAT_tx_64) | \
1035 (1ULL << EF10_STAT_tx_65_to_127) | \
1036 (1ULL << EF10_STAT_tx_128_to_255) | \
1037 (1ULL << EF10_STAT_tx_256_to_511) | \
1038 (1ULL << EF10_STAT_tx_512_to_1023) | \
1039 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
1040 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
1041
1042/* These statistics are only provided by the 40G MAC. For a 10G/40G
1043 * switchable port we do expose these because the errors will otherwise
1044 * be silent.
1045 */
1046#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
1047 (1ULL << EF10_STAT_rx_length_error))
1048
568d7a00
EC		 1049/* These statistics are only provided if the firmware supports the
1050 * capability PM_AND_RXDP_COUNTERS.
1051 */
1052#define HUNT_PM_AND_RXDP_STAT_MASK ( \
1053 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
1054 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
1055 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
1056 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
1057 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
1058 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
1059 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
1060 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
1061 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
1062 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
79ac47ae
SS		 1063 (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \
1064 (1ULL << EF10_STAT_rx_dp_hlb_wait))
568d7a00 1065
4bae913b 1066static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1067{
4bae913b 1068 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1069 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1070 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 1071
1072 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 1073 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 1074 else
4bae913b 1075 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 1076
1077 if (nic_data->datapath_caps &
1078 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1079 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1080
4bae913b
EC		 1081 return raw_mask;
1082}
1083
1084static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1085{
1086 u64 raw_mask = efx_ef10_raw_stat_mask(efx);
1087
1088#if BITS_PER_LONG == 64
1089 mask[0] = raw_mask;
1090#else
1091 mask[0] = raw_mask & 0xffffffff;
1092 mask[1] = raw_mask >> 32;
1093#endif
8127d661
BH		 1094}
1095
1096static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1097{
4bae913b
EC		 1098 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1099
1100 efx_ef10_get_stat_mask(efx, mask);
8127d661 1101 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1102 mask, names);
8127d661
BH		 1103}
1104
1105static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
1106{
1107 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1108 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1109 __le64 generation_start, generation_end;
1110 u64 *stats = nic_data->stats;
1111 __le64 *dma_stats;
1112
4bae913b
EC		 1113 efx_ef10_get_stat_mask(efx, mask);
1114
8127d661
BH		 1115 dma_stats = efx->stats_buffer.addr;
1116 nic_data = efx->nic_data;
1117
1118 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1119 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1120 return 0;
1121 rmb();
4bae913b 1122 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1123 stats, efx->stats_buffer.addr, false);
d546a893 1124 rmb();
8127d661
BH		 1125 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1126 if (generation_end != generation_start)
1127 return -EAGAIN;
1128
1129 /* Update derived statistics */
f8f3b5ae 1130 efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
8127d661
BH		 1131 stats[EF10_STAT_rx_good_bytes] =
1132 stats[EF10_STAT_rx_bytes] -
1133 stats[EF10_STAT_rx_bytes_minus_good_bytes];
1134 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
1135 stats[EF10_STAT_rx_bytes_minus_good_bytes]);
e4d112e4 1136 efx_update_sw_stats(efx, stats);
8127d661
BH		 1137 return 0;
1138}
1139
1140
1141static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
1142 struct rtnl_link_stats64 *core_stats)
1143{
4bae913b 1144 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1145 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1146 u64 *stats = nic_data->stats;
1147 size_t stats_count = 0, index;
1148 int retry;
1149
4bae913b
EC		 1150 efx_ef10_get_stat_mask(efx, mask);
1151
8127d661
BH		 1152 /* If we're unlucky enough to read statistics during the DMA, wait
1153 * up to 10ms for it to finish (typically takes <500us)
1154 */
1155 for (retry = 0; retry < 100; ++retry) {
1156 if (efx_ef10_try_update_nic_stats(efx) == 0)
1157 break;
1158 udelay(100);
1159 }
1160
1161 if (full_stats) {
1162 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1163 if (efx_ef10_stat_desc[index].name) {
1164 *full_stats++ = stats[index];
1165 ++stats_count;
1166 }
1167 }
1168 }
1169
1170 if (core_stats) {
1171 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
1172 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
1173 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
1174 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
e4d112e4
EC		 1175 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] +
1176 stats[GENERIC_STAT_rx_nodesc_trunc] +
1177 stats[GENERIC_STAT_rx_noskb_drops];
8127d661
BH		 1178 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1179 core_stats->rx_length_errors =
1180 stats[EF10_STAT_rx_gtjumbo] +
1181 stats[EF10_STAT_rx_length_error];
1182 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1183 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1184 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1185 core_stats->rx_errors = (core_stats->rx_length_errors +
1186 core_stats->rx_crc_errors +
1187 core_stats->rx_frame_errors);
1188 }
1189
1190 return stats_count;
1191}
1192
1193static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1194{
1195 struct efx_nic *efx = channel->efx;
1196 unsigned int mode, value;
1197 efx_dword_t timer_cmd;
1198
1199 if (channel->irq_moderation) {
1200 mode = 3;
1201 value = channel->irq_moderation - 1;
1202 } else {
1203 mode = 0;
1204 value = 0;
1205 }
1206
1207 if (EFX_EF10_WORKAROUND_35388(efx)) {
1208 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1209 EFE_DD_EVQ_IND_TIMER_FLAGS,
1210 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1211 ERF_DD_EVQ_IND_TIMER_VAL, value);
1212 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1213 channel->channel);
1214 } else {
1215 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1216 ERF_DZ_TC_TIMER_VAL, value);
1217 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1218 channel->channel);
1219 }
1220}
1221
02246a7f
SS		 1222static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1223 struct ethtool_wolinfo *wol) {}
1224
1225static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1226{
1227 return -EOPNOTSUPP;
1228}
1229
8127d661
BH		 1230static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1231{
1232 wol->supported = 0;
1233 wol->wolopts = 0;
1234 memset(&wol->sopass, 0, sizeof(wol->sopass));
1235}
1236
1237static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1238{
1239 if (type != 0)
1240 return -EINVAL;
1241 return 0;
1242}
1243
1244static void efx_ef10_mcdi_request(struct efx_nic *efx,
1245 const efx_dword_t *hdr, size_t hdr_len,
1246 const efx_dword_t *sdu, size_t sdu_len)
1247{
1248 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1249 u8 *pdu = nic_data->mcdi_buf.addr;
1250
1251 memcpy(pdu, hdr, hdr_len);
1252 memcpy(pdu + hdr_len, sdu, sdu_len);
1253 wmb();
1254
1255 /* The hardware provides 'low' and 'high' (doorbell) registers
1256 * for passing the 64-bit address of an MCDI request to
1257 * firmware. However the dwords are swapped by firmware. The
1258 * least significant bits of the doorbell are then 0 for all
1259 * MCDI requests due to alignment.
1260 */
1261 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1262 ER_DZ_MC_DB_LWRD);
1263 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1264 ER_DZ_MC_DB_HWRD);
1265}
1266
1267static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1268{
1269 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1270 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1271
1272 rmb();
1273 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1274}
1275
1276static void
1277efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1278 size_t offset, size_t outlen)
1279{
1280 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1281 const u8 *pdu = nic_data->mcdi_buf.addr;
1282
1283 memcpy(outbuf, pdu + offset, outlen);
1284}
1285
1286static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1287{
1288 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1289 int rc;
1290
1291 rc = efx_ef10_get_warm_boot_count(efx);
1292 if (rc < 0) {
1293 /* The firmware is presumably in the process of
1294 * rebooting. However, we are supposed to report each
1295 * reboot just once, so we must only do that once we
1296 * can read and store the updated warm boot count.
1297 */
1298 return 0;
1299 }
1300
1301 if (rc == nic_data->warm_boot_count)
1302 return 0;
1303
1304 nic_data->warm_boot_count = rc;
1305
1306 /* All our allocations have been reset */
3e336261 1307 efx_ef10_reset_mc_allocations(efx);
8127d661 1308
6d8aaaf6
DP		 1309 /* Driver-created vswitches and vports must be re-created */
1310 nic_data->must_probe_vswitching = true;
1311 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1312
a915ccc9
BH		 1313 /* The datapath firmware might have been changed */
1314 nic_data->must_check_datapath_caps = true;
1315
869070c5
BH		 1316 /* MAC statistics have been cleared on the NIC; clear the local
1317 * statistic that we update with efx_update_diff_stat().
1318 */
1319 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1320
8127d661
BH		 1321 return -EIO;
1322}
1323
1324/* Handle an MSI interrupt
1325 *
1326 * Handle an MSI hardware interrupt. This routine schedules event
1327 * queue processing. No interrupt acknowledgement cycle is necessary.
1328 * Also, we never need to check that the interrupt is for us, since
1329 * MSI interrupts cannot be shared.
1330 */
1331static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1332{
1333 struct efx_msi_context *context = dev_id;
1334 struct efx_nic *efx = context->efx;
1335
1336 netif_vdbg(efx, intr, efx->net_dev,
1337 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1338
1339 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1340 /* Note test interrupts */
1341 if (context->index == efx->irq_level)
1342 efx->last_irq_cpu = raw_smp_processor_id();
1343
1344 /* Schedule processing of the channel */
1345 efx_schedule_channel_irq(efx->channel[context->index]);
1346 }
1347
1348 return IRQ_HANDLED;
1349}
1350
1351static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1352{
1353 struct efx_nic *efx = dev_id;
1354 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1355 struct efx_channel *channel;
1356 efx_dword_t reg;
1357 u32 queues;
1358
1359 /* Read the ISR which also ACKs the interrupts */
1360 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1361 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1362
1363 if (queues == 0)
1364 return IRQ_NONE;
1365
1366 if (likely(soft_enabled)) {
1367 /* Note test interrupts */
1368 if (queues & (1U << efx->irq_level))
1369 efx->last_irq_cpu = raw_smp_processor_id();
1370
1371 efx_for_each_channel(channel, efx) {
1372 if (queues & 1)
1373 efx_schedule_channel_irq(channel);
1374 queues >>= 1;
1375 }
1376 }
1377
1378 netif_vdbg(efx, intr, efx->net_dev,
1379 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1380 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1381
1382 return IRQ_HANDLED;
1383}
1384
1385static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1386{
1387 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1388
1389 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1390
1391 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1392 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1393 inbuf, sizeof(inbuf), NULL, 0, NULL);
1394}
1395
1396static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1397{
1398 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1399 (tx_queue->ptr_mask + 1) *
1400 sizeof(efx_qword_t),
1401 GFP_KERNEL);
1402}
1403
1404/* This writes to the TX_DESC_WPTR and also pushes data */
1405static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1406 const efx_qword_t *txd)
1407{
1408 unsigned int write_ptr;
1409 efx_oword_t reg;
1410
1411 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1412 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1413 reg.qword[0] = *txd;
1414 efx_writeo_page(tx_queue->efx, &reg,
1415 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1416}
1417
1418static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1419{
1420 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1421 EFX_BUF_SIZE));
8127d661
BH		 1422 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1423 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1424 struct efx_channel *channel = tx_queue->channel;
1425 struct efx_nic *efx = tx_queue->efx;
45b2449e 1426 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1427 size_t inlen;
8127d661
BH		 1428 dma_addr_t dma_addr;
1429 efx_qword_t *txd;
1430 int rc;
1431 int i;
aa09a3da 1432 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661
BH		 1433
1434 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1435 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1436 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1437 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1438 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1439 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1440 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1441 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 1442 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 1443
1444 dma_addr = tx_queue->txd.buf.dma_addr;
1445
1446 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1447 tx_queue->queue, entries, (u64)dma_addr);
1448
1449 for (i = 0; i < entries; ++i) {
1450 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1451 dma_addr += EFX_BUF_SIZE;
1452 }
1453
1454 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1455
1456 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
aa09a3da 1457 NULL, 0, NULL);
8127d661
BH		 1458 if (rc)
1459 goto fail;
1460
1461 /* A previous user of this TX queue might have set us up the
1462 * bomb by writing a descriptor to the TX push collector but
1463 * not the doorbell. (Each collector belongs to a port, not a
1464 * queue or function, so cannot easily be reset.) We must
1465 * attempt to push a no-op descriptor in its place.
1466 */
1467 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1468 tx_queue->insert_count = 1;
1469 txd = efx_tx_desc(tx_queue, 0);
1470 EFX_POPULATE_QWORD_4(*txd,
1471 ESF_DZ_TX_DESC_IS_OPT, true,
1472 ESF_DZ_TX_OPTION_TYPE,
1473 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1474 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1475 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1476 tx_queue->write_count = 1;
1477 wmb();
1478 efx_ef10_push_tx_desc(tx_queue, txd);
1479
1480 return;
1481
1482fail:
48ce5634
BH		 1483 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1484 tx_queue->queue);
8127d661
BH		 1485}
1486
1487static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1488{
1489 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 1490 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 1491 struct efx_nic *efx = tx_queue->efx;
1492 size_t outlen;
1493 int rc;
1494
1495 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1496 tx_queue->queue);
1497
1e0b8120 1498 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1499 outbuf, sizeof(outbuf), &outlen);
1500
1501 if (rc && rc != -EALREADY)
1502 goto fail;
1503
1504 return;
1505
1506fail:
1e0b8120
EC		 1507 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1508 outbuf, outlen, rc);
8127d661
BH		 1509}
1510
1511static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1512{
1513 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1514}
1515
1516/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1517static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1518{
1519 unsigned int write_ptr;
1520 efx_dword_t reg;
1521
1522 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1523 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1524 efx_writed_page(tx_queue->efx, &reg,
1525 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1526}
1527
1528static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1529{
1530 unsigned int old_write_count = tx_queue->write_count;
1531 struct efx_tx_buffer *buffer;
1532 unsigned int write_ptr;
1533 efx_qword_t *txd;
1534
1535 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1536
1537 do {
1538 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1539 buffer = &tx_queue->buffer[write_ptr];
1540 txd = efx_tx_desc(tx_queue, write_ptr);
1541 ++tx_queue->write_count;
1542
1543 /* Create TX descriptor ring entry */
1544 if (buffer->flags & EFX_TX_BUF_OPTION) {
1545 *txd = buffer->option;
1546 } else {
1547 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1548 EFX_POPULATE_QWORD_3(
1549 *txd,
1550 ESF_DZ_TX_KER_CONT,
1551 buffer->flags & EFX_TX_BUF_CONT,
1552 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1553 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1554 }
1555 } while (tx_queue->write_count != tx_queue->insert_count);
1556
1557 wmb(); /* Ensure descriptors are written before they are fetched */
1558
1559 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1560 txd = efx_tx_desc(tx_queue,
1561 old_write_count & tx_queue->ptr_mask);
1562 efx_ef10_push_tx_desc(tx_queue, txd);
1563 ++tx_queue->pushes;
1564 } else {
1565 efx_ef10_notify_tx_desc(tx_queue);
1566 }
1567}
1568
267c0157
JC		 1569static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1570 bool exclusive, unsigned *context_size)
8127d661
BH		 1571{
1572 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1573 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 1574 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 1575 size_t outlen;
1576 int rc;
267c0157
JC		 1577 u32 alloc_type = exclusive ?
1578 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1579 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1580 unsigned rss_spread = exclusive ?
1581 efx->rss_spread :
1582 min(rounddown_pow_of_two(efx->rss_spread),
1583 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1584
1585 if (!exclusive && rss_spread == 1) {
1586 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1587 if (context_size)
1588 *context_size = 1;
1589 return 0;
1590 }
8127d661
BH		 1591
1592 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 1593 nic_data->vport_id);
267c0157
JC		 1594 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1595 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 1596
1597 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1598 outbuf, sizeof(outbuf), &outlen);
1599 if (rc != 0)
1600 return rc;
1601
1602 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1603 return -EIO;
1604
1605 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1606
267c0157
JC		 1607 if (context_size)
1608 *context_size = rss_spread;
1609
8127d661
BH		 1610 return 0;
1611}
1612
1613static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1614{
1615 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1616 int rc;
1617
1618 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1619 context);
1620
1621 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1622 NULL, 0, NULL);
1623 WARN_ON(rc != 0);
1624}
1625
267c0157
JC		 1626static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1627 const u32 *rx_indir_table)
8127d661
BH		 1628{
1629 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1630 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1631 int i, rc;
1632
1633 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1634 context);
1635 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1636 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1637
1638 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1639 MCDI_PTR(tablebuf,
1640 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 1641 (u8) rx_indir_table[i];
8127d661
BH		 1642
1643 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1644 sizeof(tablebuf), NULL, 0, NULL);
1645 if (rc != 0)
1646 return rc;
1647
1648 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1649 context);
1650 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1651 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1652 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1653 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1654 efx->rx_hash_key[i];
1655
1656 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1657 sizeof(keybuf), NULL, 0, NULL);
1658}
1659
1660static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1661{
1662 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1663
1664 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1665 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1666 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1667}
1668
267c0157
JC		 1669static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1670 unsigned *context_size)
8127d661 1671{
267c0157 1672 u32 new_rx_rss_context;
8127d661 1673 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 1674 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1675 false, context_size);
1676
1677 if (rc != 0)
1678 return rc;
8127d661 1679
267c0157
JC		 1680 nic_data->rx_rss_context = new_rx_rss_context;
1681 nic_data->rx_rss_context_exclusive = false;
1682 efx_set_default_rx_indir_table(efx);
1683 return 0;
1684}
8127d661 1685
267c0157
JC		 1686static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
1687 const u32 *rx_indir_table)
1688{
1689 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1690 int rc;
1691 u32 new_rx_rss_context;
1692
1693 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
1694 !nic_data->rx_rss_context_exclusive) {
1695 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1696 true, NULL);
1697 if (rc == -EOPNOTSUPP)
1698 return rc;
1699 else if (rc != 0)
1700 goto fail1;
1701 } else {
1702 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 1703 }
1704
267c0157
JC		 1705 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
1706 rx_indir_table);
8127d661 1707 if (rc != 0)
267c0157 1708 goto fail2;
8127d661 1709
267c0157
JC		 1710 if (nic_data->rx_rss_context != new_rx_rss_context)
1711 efx_ef10_rx_free_indir_table(efx);
1712 nic_data->rx_rss_context = new_rx_rss_context;
1713 nic_data->rx_rss_context_exclusive = true;
1714 if (rx_indir_table != efx->rx_indir_table)
1715 memcpy(efx->rx_indir_table, rx_indir_table,
1716 sizeof(efx->rx_indir_table));
1717 return 0;
8127d661 1718
267c0157
JC		 1719fail2:
1720 if (new_rx_rss_context != nic_data->rx_rss_context)
1721 efx_ef10_free_rss_context(efx, new_rx_rss_context);
1722fail1:
8127d661 1723 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 1724 return rc;
1725}
1726
1727static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
1728 const u32 *rx_indir_table)
1729{
1730 int rc;
1731
1732 if (efx->rss_spread == 1)
1733 return 0;
1734
1735 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
1736
1737 if (rc == -ENOBUFS && !user) {
1738 unsigned context_size;
1739 bool mismatch = false;
1740 size_t i;
1741
1742 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
1743 i++)
1744 mismatch = rx_indir_table[i] !=
1745 ethtool_rxfh_indir_default(i, efx->rss_spread);
1746
1747 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
1748 if (rc == 0) {
1749 if (context_size != efx->rss_spread)
1750 netif_warn(efx, probe, efx->net_dev,
1751 "Could not allocate an exclusive RSS"
1752 " context; allocated a shared one of"
1753 " different size."
1754 " Wanted %u, got %u.\n",
1755 efx->rss_spread, context_size);
1756 else if (mismatch)
1757 netif_warn(efx, probe, efx->net_dev,
1758 "Could not allocate an exclusive RSS"
1759 " context; allocated a shared one but"
1760 " could not apply custom"
1761 " indirection.\n");
1762 else
1763 netif_info(efx, probe, efx->net_dev,
1764 "Could not allocate an exclusive RSS"
1765 " context; allocated a shared one.\n");
1766 }
1767 }
1768 return rc;
1769}
1770
1771static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
1772 const u32 *rx_indir_table
1773 __attribute__ ((unused)))
1774{
1775 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1776
1777 if (user)
1778 return -EOPNOTSUPP;
1779 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1780 return 0;
1781 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 1782}
1783
1784static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1785{
1786 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1787 (rx_queue->ptr_mask + 1) *
1788 sizeof(efx_qword_t),
1789 GFP_KERNEL);
1790}
1791
1792static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1793{
1794 MCDI_DECLARE_BUF(inbuf,
1795 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1796 EFX_BUF_SIZE));
8127d661
BH		 1797 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1798 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1799 struct efx_nic *efx = rx_queue->efx;
45b2449e 1800 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1801 size_t inlen;
8127d661
BH		 1802 dma_addr_t dma_addr;
1803 int rc;
1804 int i;
aa09a3da 1805 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 1806
1807 rx_queue->scatter_n = 0;
1808 rx_queue->scatter_len = 0;
1809
1810 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1811 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1812 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1813 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1814 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 1815 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1816 INIT_RXQ_IN_FLAG_PREFIX, 1,
1817 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 1818 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 1819 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 1820
1821 dma_addr = rx_queue->rxd.buf.dma_addr;
1822
1823 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1824 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1825
1826 for (i = 0; i < entries; ++i) {
1827 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1828 dma_addr += EFX_BUF_SIZE;
1829 }
1830
1831 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1832
1833 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 1834 NULL, 0, NULL);
48ce5634
BH		 1835 if (rc)
1836 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1837 efx_rx_queue_index(rx_queue));
8127d661
BH		 1838}
1839
1840static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1841{
1842 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 1843 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 1844 struct efx_nic *efx = rx_queue->efx;
1845 size_t outlen;
1846 int rc;
1847
1848 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1849 efx_rx_queue_index(rx_queue));
1850
1e0b8120 1851 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1852 outbuf, sizeof(outbuf), &outlen);
1853
1854 if (rc && rc != -EALREADY)
1855 goto fail;
1856
1857 return;
1858
1859fail:
1e0b8120
EC		 1860 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1861 outbuf, outlen, rc);
8127d661
BH		 1862}
1863
1864static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1865{
1866 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1867}
1868
1869/* This creates an entry in the RX descriptor queue */
1870static inline void
1871efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1872{
1873 struct efx_rx_buffer *rx_buf;
1874 efx_qword_t *rxd;
1875
1876 rxd = efx_rx_desc(rx_queue, index);
1877 rx_buf = efx_rx_buffer(rx_queue, index);
1878 EFX_POPULATE_QWORD_2(*rxd,
1879 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1880 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1881}
1882
1883static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1884{
1885 struct efx_nic *efx = rx_queue->efx;
1886 unsigned int write_count;
1887 efx_dword_t reg;
1888
1889 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1890 write_count = rx_queue->added_count & ~7;
1891 if (rx_queue->notified_count == write_count)
1892 return;
1893
1894 do
1895 efx_ef10_build_rx_desc(
1896 rx_queue,
1897 rx_queue->notified_count & rx_queue->ptr_mask);
1898 while (++rx_queue->notified_count != write_count);
1899
1900 wmb();
1901 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1902 write_count & rx_queue->ptr_mask);
1903 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1904 efx_rx_queue_index(rx_queue));
1905}
1906
1907static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1908
1909static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1910{
1911 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1912 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1913 efx_qword_t event;
1914
1915 EFX_POPULATE_QWORD_2(event,
1916 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1917 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1918
1919 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1920
1921 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1922 * already swapped the data to little-endian order.
1923 */
1924 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1925 sizeof(efx_qword_t));
1926
1927 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1928 inbuf, sizeof(inbuf), 0,
1929 efx_ef10_rx_defer_refill_complete, 0);
1930}
1931
1932static void
1933efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1934 int rc, efx_dword_t *outbuf,
1935 size_t outlen_actual)
1936{
1937 /* nothing to do */
1938}
1939
1940static int efx_ef10_ev_probe(struct efx_channel *channel)
1941{
1942 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1943 (channel->eventq_mask + 1) *
1944 sizeof(efx_qword_t),
1945 GFP_KERNEL);
1946}
1947
1948static int efx_ef10_ev_init(struct efx_channel *channel)
1949{
1950 MCDI_DECLARE_BUF(inbuf,
1951 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1952 EFX_BUF_SIZE));
1953 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1954 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1955 struct efx_nic *efx = channel->efx;
1956 struct efx_ef10_nic_data *nic_data;
1957 bool supports_rx_merge;
1958 size_t inlen, outlen;
1959 dma_addr_t dma_addr;
1960 int rc;
1961 int i;
1962
1963 nic_data = efx->nic_data;
1964 supports_rx_merge =
1965 !!(nic_data->datapath_caps &
1966 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1967
1968 /* Fill event queue with all ones (i.e. empty events) */
1969 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1970
1971 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1972 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1973 /* INIT_EVQ expects index in vector table, not absolute */
1974 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1975 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1976 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1977 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1978 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1979 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1980 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1981 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1982 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1983 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1984 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1985 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1986 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1987
1988 dma_addr = channel->eventq.buf.dma_addr;
1989 for (i = 0; i < entries; ++i) {
1990 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1991 dma_addr += EFX_BUF_SIZE;
1992 }
1993
1994 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1995
1996 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1997 outbuf, sizeof(outbuf), &outlen);
8127d661 1998 /* IRQ return is ignored */
8127d661
BH		 1999 return rc;
2000}
2001
2002static void efx_ef10_ev_fini(struct efx_channel *channel)
2003{
2004 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
aa09a3da 2005 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2006 struct efx_nic *efx = channel->efx;
2007 size_t outlen;
2008 int rc;
2009
2010 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2011
1e0b8120 2012 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
8127d661
BH		 2013 outbuf, sizeof(outbuf), &outlen);
2014
2015 if (rc && rc != -EALREADY)
2016 goto fail;
2017
2018 return;
2019
2020fail:
1e0b8120
EC		 2021 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2022 outbuf, outlen, rc);
8127d661
BH		 2023}
2024
2025static void efx_ef10_ev_remove(struct efx_channel *channel)
2026{
2027 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2028}
2029
2030static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2031 unsigned int rx_queue_label)
2032{
2033 struct efx_nic *efx = rx_queue->efx;
2034
2035 netif_info(efx, hw, efx->net_dev,
2036 "rx event arrived on queue %d labeled as queue %u\n",
2037 efx_rx_queue_index(rx_queue), rx_queue_label);
2038
2039 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2040}
2041
2042static void
2043efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2044 unsigned int actual, unsigned int expected)
2045{
2046 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2047 struct efx_nic *efx = rx_queue->efx;
2048
2049 netif_info(efx, hw, efx->net_dev,
2050 "dropped %d events (index=%d expected=%d)\n",
2051 dropped, actual, expected);
2052
2053 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2054}
2055
2056/* partially received RX was aborted. clean up. */
2057static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2058{
2059 unsigned int rx_desc_ptr;
2060
8127d661
BH		 2061 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2062 "scattered RX aborted (dropping %u buffers)\n",
2063 rx_queue->scatter_n);
2064
2065 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2066
2067 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2068 0, EFX_RX_PKT_DISCARD);
2069
2070 rx_queue->removed_count += rx_queue->scatter_n;
2071 rx_queue->scatter_n = 0;
2072 rx_queue->scatter_len = 0;
2073 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2074}
2075
2076static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2077 const efx_qword_t *event)
2078{
2079 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2080 unsigned int n_descs, n_packets, i;
2081 struct efx_nic *efx = channel->efx;
2082 struct efx_rx_queue *rx_queue;
2083 bool rx_cont;
2084 u16 flags = 0;
2085
2086 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2087 return 0;
2088
2089 /* Basic packet information */
2090 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2091 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2092 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2093 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2094 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2095
48ce5634
BH		 2096 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2097 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2098 EFX_QWORD_FMT "\n",
2099 EFX_QWORD_VAL(*event));
8127d661
BH		 2100
2101 rx_queue = efx_channel_get_rx_queue(channel);
2102
2103 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2104 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2105
2106 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2107 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2108
2109 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 2110 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2111
8127d661
BH		 2112 /* detect rx abort */
2113 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2114 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2115 netdev_WARN(efx->net_dev,
2116 "invalid RX abort: scatter_n=%u event="
2117 EFX_QWORD_FMT "\n",
2118 rx_queue->scatter_n,
2119 EFX_QWORD_VAL(*event));
8127d661
BH		 2120 efx_ef10_handle_rx_abort(rx_queue);
2121 return 0;
2122 }
2123
92a04168
BH		 2124 /* Check that RX completion merging is valid, i.e.
2125 * the current firmware supports it and this is a
2126 * non-scattered packet.
2127 */
2128 if (!(nic_data->datapath_caps &
2129 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2130 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2131 efx_ef10_handle_rx_bad_lbits(
2132 rx_queue, next_ptr_lbits,
2133 (rx_queue->removed_count +
2134 rx_queue->scatter_n + 1) &
2135 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2136 return 0;
2137 }
2138
2139 /* Merged completion for multiple non-scattered packets */
2140 rx_queue->scatter_n = 1;
2141 rx_queue->scatter_len = 0;
2142 n_packets = n_descs;
2143 ++channel->n_rx_merge_events;
2144 channel->n_rx_merge_packets += n_packets;
2145 flags |= EFX_RX_PKT_PREFIX_LEN;
2146 } else {
2147 ++rx_queue->scatter_n;
2148 rx_queue->scatter_len += rx_bytes;
2149 if (rx_cont)
2150 return 0;
2151 n_packets = 1;
2152 }
2153
2154 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2155 flags |= EFX_RX_PKT_DISCARD;
2156
2157 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2158 channel->n_rx_ip_hdr_chksum_err += n_packets;
2159 } else if (unlikely(EFX_QWORD_FIELD(*event,
2160 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2161 channel->n_rx_tcp_udp_chksum_err += n_packets;
2162 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2163 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2164 flags |= EFX_RX_PKT_CSUMMED;
2165 }
2166
2167 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2168 flags |= EFX_RX_PKT_TCP;
2169
2170 channel->irq_mod_score += 2 * n_packets;
2171
2172 /* Handle received packet(s) */
2173 for (i = 0; i < n_packets; i++) {
2174 efx_rx_packet(rx_queue,
2175 rx_queue->removed_count & rx_queue->ptr_mask,
2176 rx_queue->scatter_n, rx_queue->scatter_len,
2177 flags);
2178 rx_queue->removed_count += rx_queue->scatter_n;
2179 }
2180
2181 rx_queue->scatter_n = 0;
2182 rx_queue->scatter_len = 0;
2183
2184 return n_packets;
2185}
2186
2187static int
2188efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2189{
2190 struct efx_nic *efx = channel->efx;
2191 struct efx_tx_queue *tx_queue;
2192 unsigned int tx_ev_desc_ptr;
2193 unsigned int tx_ev_q_label;
2194 int tx_descs = 0;
2195
2196 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2197 return 0;
2198
2199 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2200 return 0;
2201
2202 /* Transmit completion */
2203 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2204 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2205 tx_queue = efx_channel_get_tx_queue(channel,
2206 tx_ev_q_label % EFX_TXQ_TYPES);
2207 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2208 tx_queue->ptr_mask);
2209 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2210
2211 return tx_descs;
2212}
2213
2214static void
2215efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2216{
2217 struct efx_nic *efx = channel->efx;
2218 int subcode;
2219
2220 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2221
2222 switch (subcode) {
2223 case ESE_DZ_DRV_TIMER_EV:
2224 case ESE_DZ_DRV_WAKE_UP_EV:
2225 break;
2226 case ESE_DZ_DRV_START_UP_EV:
2227 /* event queue init complete. ok. */
2228 break;
2229 default:
2230 netif_err(efx, hw, efx->net_dev,
2231 "channel %d unknown driver event type %d"
2232 " (data " EFX_QWORD_FMT ")\n",
2233 channel->channel, subcode,
2234 EFX_QWORD_VAL(*event));
2235
2236 }
2237}
2238
2239static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2240 efx_qword_t *event)
2241{
2242 struct efx_nic *efx = channel->efx;
2243 u32 subcode;
2244
2245 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2246
2247 switch (subcode) {
2248 case EFX_EF10_TEST:
2249 channel->event_test_cpu = raw_smp_processor_id();
2250 break;
2251 case EFX_EF10_REFILL:
2252 /* The queue must be empty, so we won't receive any rx
2253 * events, so efx_process_channel() won't refill the
2254 * queue. Refill it here
2255 */
cce28794 2256 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 2257 break;
2258 default:
2259 netif_err(efx, hw, efx->net_dev,
2260 "channel %d unknown driver event type %u"
2261 " (data " EFX_QWORD_FMT ")\n",
2262 channel->channel, (unsigned) subcode,
2263 EFX_QWORD_VAL(*event));
2264 }
2265}
2266
2267static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2268{
2269 struct efx_nic *efx = channel->efx;
2270 efx_qword_t event, *p_event;
2271 unsigned int read_ptr;
2272 int ev_code;
2273 int tx_descs = 0;
2274 int spent = 0;
2275
75363a46
EB		 2276 if (quota <= 0)
2277 return spent;
2278
8127d661
BH		 2279 read_ptr = channel->eventq_read_ptr;
2280
2281 for (;;) {
2282 p_event = efx_event(channel, read_ptr);
2283 event = *p_event;
2284
2285 if (!efx_event_present(&event))
2286 break;
2287
2288 EFX_SET_QWORD(*p_event);
2289
2290 ++read_ptr;
2291
2292 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2293
2294 netif_vdbg(efx, drv, efx->net_dev,
2295 "processing event on %d " EFX_QWORD_FMT "\n",
2296 channel->channel, EFX_QWORD_VAL(event));
2297
2298 switch (ev_code) {
2299 case ESE_DZ_EV_CODE_MCDI_EV:
2300 efx_mcdi_process_event(channel, &event);
2301 break;
2302 case ESE_DZ_EV_CODE_RX_EV:
2303 spent += efx_ef10_handle_rx_event(channel, &event);
2304 if (spent >= quota) {
2305 /* XXX can we split a merged event to
2306 * avoid going over-quota?
2307 */
2308 spent = quota;
2309 goto out;
2310 }
2311 break;
2312 case ESE_DZ_EV_CODE_TX_EV:
2313 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2314 if (tx_descs > efx->txq_entries) {
2315 spent = quota;
2316 goto out;
2317 } else if (++spent == quota) {
2318 goto out;
2319 }
2320 break;
2321 case ESE_DZ_EV_CODE_DRIVER_EV:
2322 efx_ef10_handle_driver_event(channel, &event);
2323 if (++spent == quota)
2324 goto out;
2325 break;
2326 case EFX_EF10_DRVGEN_EV:
2327 efx_ef10_handle_driver_generated_event(channel, &event);
2328 break;
2329 default:
2330 netif_err(efx, hw, efx->net_dev,
2331 "channel %d unknown event type %d"
2332 " (data " EFX_QWORD_FMT ")\n",
2333 channel->channel, ev_code,
2334 EFX_QWORD_VAL(event));
2335 }
2336 }
2337
2338out:
2339 channel->eventq_read_ptr = read_ptr;
2340 return spent;
2341}
2342
2343static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2344{
2345 struct efx_nic *efx = channel->efx;
2346 efx_dword_t rptr;
2347
2348 if (EFX_EF10_WORKAROUND_35388(efx)) {
2349 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2350 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2351 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2352 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2353
2354 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2355 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2356 ERF_DD_EVQ_IND_RPTR,
2357 (channel->eventq_read_ptr &
2358 channel->eventq_mask) >>
2359 ERF_DD_EVQ_IND_RPTR_WIDTH);
2360 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2361 channel->channel);
2362 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2363 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2364 ERF_DD_EVQ_IND_RPTR,
2365 channel->eventq_read_ptr &
2366 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2367 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2368 channel->channel);
2369 } else {
2370 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2371 channel->eventq_read_ptr &
2372 channel->eventq_mask);
2373 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2374 }
2375}
2376
2377static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2378{
2379 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2380 struct efx_nic *efx = channel->efx;
2381 efx_qword_t event;
2382 int rc;
2383
2384 EFX_POPULATE_QWORD_2(event,
2385 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2386 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2387
2388 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2389
2390 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2391 * already swapped the data to little-endian order.
2392 */
2393 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2394 sizeof(efx_qword_t));
2395
2396 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2397 NULL, 0, NULL);
2398 if (rc != 0)
2399 goto fail;
2400
2401 return;
2402
2403fail:
2404 WARN_ON(true);
2405 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2406}
2407
2408void efx_ef10_handle_drain_event(struct efx_nic *efx)
2409{
2410 if (atomic_dec_and_test(&efx->active_queues))
2411 wake_up(&efx->flush_wq);
2412
2413 WARN_ON(atomic_read(&efx->active_queues) < 0);
2414}
2415
2416static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2417{
2418 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2419 struct efx_channel *channel;
2420 struct efx_tx_queue *tx_queue;
2421 struct efx_rx_queue *rx_queue;
2422 int pending;
2423
2424 /* If the MC has just rebooted, the TX/RX queues will have already been
2425 * torn down, but efx->active_queues needs to be set to zero.
2426 */
2427 if (nic_data->must_realloc_vis) {
2428 atomic_set(&efx->active_queues, 0);
2429 return 0;
2430 }
2431
2432 /* Do not attempt to write to the NIC during EEH recovery */
2433 if (efx->state != STATE_RECOVERY) {
2434 efx_for_each_channel(channel, efx) {
2435 efx_for_each_channel_rx_queue(rx_queue, channel)
2436 efx_ef10_rx_fini(rx_queue);
2437 efx_for_each_channel_tx_queue(tx_queue, channel)
2438 efx_ef10_tx_fini(tx_queue);
2439 }
2440
2441 wait_event_timeout(efx->flush_wq,
2442 atomic_read(&efx->active_queues) == 0,
2443 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2444 pending = atomic_read(&efx->active_queues);
2445 if (pending) {
2446 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2447 pending);
2448 return -ETIMEDOUT;
2449 }
2450 }
2451
2452 return 0;
2453}
2454
e283546c
EC		 2455static void efx_ef10_prepare_flr(struct efx_nic *efx)
2456{
2457 atomic_set(&efx->active_queues, 0);
2458}
2459
8127d661
BH		 2460static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2461 const struct efx_filter_spec *right)
2462{
2463 if ((left->match_flags ^ right->match_flags) |
2464 ((left->flags ^ right->flags) &
2465 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2466 return false;
2467
2468 return memcmp(&left->outer_vid, &right->outer_vid,
2469 sizeof(struct efx_filter_spec) -
2470 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2471}
2472
2473static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2474{
2475 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2476 return jhash2((const u32 *)&spec->outer_vid,
2477 (sizeof(struct efx_filter_spec) -
2478 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2479 0);
2480 /* XXX should we randomise the initval? */
2481}
2482
2483/* Decide whether a filter should be exclusive or else should allow
2484 * delivery to additional recipients. Currently we decide that
2485 * filters for specific local unicast MAC and IP addresses are
2486 * exclusive.
2487 */
2488static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2489{
2490 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2491 !is_multicast_ether_addr(spec->loc_mac))
2492 return true;
2493
2494 if ((spec->match_flags &
2495 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2496 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2497 if (spec->ether_type == htons(ETH_P_IP) &&
2498 !ipv4_is_multicast(spec->loc_host[0]))
2499 return true;
2500 if (spec->ether_type == htons(ETH_P_IPV6) &&
2501 ((const u8 *)spec->loc_host)[0] != 0xff)
2502 return true;
2503 }
2504
2505 return false;
2506}
2507
2508static struct efx_filter_spec *
2509efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2510 unsigned int filter_idx)
2511{
2512 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2513 ~EFX_EF10_FILTER_FLAGS);
2514}
2515
2516static unsigned int
2517efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2518 unsigned int filter_idx)
2519{
2520 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2521}
2522
2523static void
2524efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2525 unsigned int filter_idx,
2526 const struct efx_filter_spec *spec,
2527 unsigned int flags)
2528{
2529 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2530}
2531
2532static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2533 const struct efx_filter_spec *spec,
2534 efx_dword_t *inbuf, u64 handle,
2535 bool replacing)
2536{
2537 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2538
2539 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2540
2541 if (replacing) {
2542 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2543 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2544 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2545 } else {
2546 u32 match_fields = 0;
2547
2548 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2549 efx_ef10_filter_is_exclusive(spec) ?
2550 MC_CMD_FILTER_OP_IN_OP_INSERT :
2551 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2552
2553 /* Convert match flags and values. Unlike almost
2554 * everything else in MCDI, these fields are in
2555 * network byte order.
2556 */
2557 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2558 match_fields |=
2559 is_multicast_ether_addr(spec->loc_mac) ?
2560 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2561 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2562#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2563 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2564 match_fields |= \
2565 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2566 mcdi_field ## _LBN; \
2567 BUILD_BUG_ON( \
2568 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2569 sizeof(spec->gen_field)); \
2570 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2571 &spec->gen_field, sizeof(spec->gen_field)); \
2572 }
2573 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2574 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2575 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2576 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2577 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2578 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2579 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2580 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2581 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2582 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2583#undef COPY_FIELD
2584 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2585 match_fields);
2586 }
2587
45b2449e 2588 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2589 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2590 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2591 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2592 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 2593 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 2594 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2595 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 2596 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2597 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2598 0 : spec->dmaq_id);
8127d661
BH		 2599 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2600 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2601 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2602 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2603 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2604 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2605 spec->rss_context !=
2606 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2607 spec->rss_context : nic_data->rx_rss_context);
2608}
2609
2610static int efx_ef10_filter_push(struct efx_nic *efx,
2611 const struct efx_filter_spec *spec,
2612 u64 *handle, bool replacing)
2613{
2614 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2615 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2616 int rc;
2617
2618 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2619 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2620 outbuf, sizeof(outbuf), NULL);
2621 if (rc == 0)
2622 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 2623 if (rc == -ENOSPC)
2624 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 2625 return rc;
2626}
2627
2628static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2629 enum efx_filter_match_flags match_flags)
2630{
2631 unsigned int match_pri;
2632
2633 for (match_pri = 0;
2634 match_pri < table->rx_match_count;
2635 match_pri++)
2636 if (table->rx_match_flags[match_pri] == match_flags)
2637 return match_pri;
2638
2639 return -EPROTONOSUPPORT;
2640}
2641
2642static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2643 struct efx_filter_spec *spec,
2644 bool replace_equal)
2645{
2646 struct efx_ef10_filter_table *table = efx->filter_state;
2647 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2648 struct efx_filter_spec *saved_spec;
2649 unsigned int match_pri, hash;
2650 unsigned int priv_flags;
2651 bool replacing = false;
2652 int ins_index = -1;
2653 DEFINE_WAIT(wait);
2654 bool is_mc_recip;
2655 s32 rc;
2656
2657 /* For now, only support RX filters */
2658 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2659 EFX_FILTER_FLAG_RX)
2660 return -EINVAL;
2661
2662 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2663 if (rc < 0)
2664 return rc;
2665 match_pri = rc;
2666
2667 hash = efx_ef10_filter_hash(spec);
2668 is_mc_recip = efx_filter_is_mc_recipient(spec);
2669 if (is_mc_recip)
2670 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2671
2672 /* Find any existing filters with the same match tuple or
2673 * else a free slot to insert at. If any of them are busy,
2674 * we have to wait and retry.
2675 */
2676 for (;;) {
2677 unsigned int depth = 1;
2678 unsigned int i;
2679
2680 spin_lock_bh(&efx->filter_lock);
2681
2682 for (;;) {
2683 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2684 saved_spec = efx_ef10_filter_entry_spec(table, i);
2685
2686 if (!saved_spec) {
2687 if (ins_index < 0)
2688 ins_index = i;
2689 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2690 if (table->entry[i].spec &
2691 EFX_EF10_FILTER_FLAG_BUSY)
2692 break;
2693 if (spec->priority < saved_spec->priority &&
7665d1ab 2694 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 2695 rc = -EPERM;
2696 goto out_unlock;
2697 }
2698 if (!is_mc_recip) {
2699 /* This is the only one */
2700 if (spec->priority ==
2701 saved_spec->priority &&
2702 !replace_equal) {
2703 rc = -EEXIST;
2704 goto out_unlock;
2705 }
2706 ins_index = i;
2707 goto found;
2708 } else if (spec->priority >
2709 saved_spec->priority ||
2710 (spec->priority ==
2711 saved_spec->priority &&
2712 replace_equal)) {
2713 if (ins_index < 0)
2714 ins_index = i;
2715 else
2716 __set_bit(depth, mc_rem_map);
2717 }
2718 }
2719
2720 /* Once we reach the maximum search depth, use
2721 * the first suitable slot or return -EBUSY if
2722 * there was none
2723 */
2724 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2725 if (ins_index < 0) {
2726 rc = -EBUSY;
2727 goto out_unlock;
2728 }
2729 goto found;
2730 }
2731
2732 ++depth;
2733 }
2734
2735 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2736 spin_unlock_bh(&efx->filter_lock);
2737 schedule();
2738 }
2739
2740found:
2741 /* Create a software table entry if necessary, and mark it
2742 * busy. We might yet fail to insert, but any attempt to
2743 * insert a conflicting filter while we're waiting for the
2744 * firmware must find the busy entry.
2745 */
2746 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2747 if (saved_spec) {
7665d1ab
BH		 2748 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2749 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 2750 /* Just make sure it won't be removed */
7665d1ab
BH		 2751 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2752 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 2753 table->entry[ins_index].spec &=
b59e6ef8 2754 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 2755 rc = ins_index;
2756 goto out_unlock;
2757 }
2758 replacing = true;
2759 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2760 } else {
2761 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2762 if (!saved_spec) {
2763 rc = -ENOMEM;
2764 goto out_unlock;
2765 }
2766 *saved_spec = *spec;
2767 priv_flags = 0;
2768 }
2769 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2770 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2771
2772 /* Mark lower-priority multicast recipients busy prior to removal */
2773 if (is_mc_recip) {
2774 unsigned int depth, i;
2775
2776 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2777 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2778 if (test_bit(depth, mc_rem_map))
2779 table->entry[i].spec |=
2780 EFX_EF10_FILTER_FLAG_BUSY;
2781 }
2782 }
2783
2784 spin_unlock_bh(&efx->filter_lock);
2785
2786 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2787 replacing);
2788
2789 /* Finalise the software table entry */
2790 spin_lock_bh(&efx->filter_lock);
2791 if (rc == 0) {
2792 if (replacing) {
2793 /* Update the fields that may differ */
7665d1ab
BH		 2794 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2795 saved_spec->flags |=
2796 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 2797 saved_spec->priority = spec->priority;
7665d1ab 2798 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 2799 saved_spec->flags |= spec->flags;
2800 saved_spec->rss_context = spec->rss_context;
2801 saved_spec->dmaq_id = spec->dmaq_id;
2802 }
2803 } else if (!replacing) {
2804 kfree(saved_spec);
2805 saved_spec = NULL;
2806 }
2807 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2808
2809 /* Remove and finalise entries for lower-priority multicast
2810 * recipients
2811 */
2812 if (is_mc_recip) {
2813 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2814 unsigned int depth, i;
2815
2816 memset(inbuf, 0, sizeof(inbuf));
2817
2818 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2819 if (!test_bit(depth, mc_rem_map))
2820 continue;
2821
2822 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2823 saved_spec = efx_ef10_filter_entry_spec(table, i);
2824 priv_flags = efx_ef10_filter_entry_flags(table, i);
2825
2826 if (rc == 0) {
2827 spin_unlock_bh(&efx->filter_lock);
2828 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2829 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2830 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2831 table->entry[i].handle);
2832 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2833 inbuf, sizeof(inbuf),
2834 NULL, 0, NULL);
2835 spin_lock_bh(&efx->filter_lock);
2836 }
2837
2838 if (rc == 0) {
2839 kfree(saved_spec);
2840 saved_spec = NULL;
2841 priv_flags = 0;
2842 } else {
2843 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2844 }
2845 efx_ef10_filter_set_entry(table, i, saved_spec,
2846 priv_flags);
2847 }
2848 }
2849
2850 /* If successful, return the inserted filter ID */
2851 if (rc == 0)
2852 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2853
2854 wake_up_all(&table->waitq);
2855out_unlock:
2856 spin_unlock_bh(&efx->filter_lock);
2857 finish_wait(&table->waitq, &wait);
2858 return rc;
2859}
2860
9fd8095d 2861static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 2862{
2863 /* no need to do anything here on EF10 */
2864}
2865
2866/* Remove a filter.
b59e6ef8
BH		 2867 * If !by_index, remove by ID
2868 * If by_index, remove by index
8127d661
BH		 2869 * Filter ID may come from userland and must be range-checked.
2870 */
2871static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 2872 unsigned int priority_mask,
b59e6ef8 2873 u32 filter_id, bool by_index)
8127d661
BH		 2874{
2875 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2876 struct efx_ef10_filter_table *table = efx->filter_state;
2877 MCDI_DECLARE_BUF(inbuf,
2878 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2879 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2880 struct efx_filter_spec *spec;
2881 DEFINE_WAIT(wait);
2882 int rc;
2883
2884 /* Find the software table entry and mark it busy. Don't
2885 * remove it yet; any attempt to update while we're waiting
2886 * for the firmware must find the busy entry.
2887 */
2888 for (;;) {
2889 spin_lock_bh(&efx->filter_lock);
2890 if (!(table->entry[filter_idx].spec &
2891 EFX_EF10_FILTER_FLAG_BUSY))
2892 break;
2893 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2894 spin_unlock_bh(&efx->filter_lock);
2895 schedule();
2896 }
7665d1ab 2897
8127d661 2898 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 2899 if (!spec ||
b59e6ef8 2900 (!by_index &&
8127d661
BH		 2901 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2902 filter_id / HUNT_FILTER_TBL_ROWS)) {
2903 rc = -ENOENT;
2904 goto out_unlock;
2905 }
7665d1ab
BH		 2906
2907 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 2908 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 2909 /* Just remove flags */
2910 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 2911 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 2912 rc = 0;
2913 goto out_unlock;
2914 }
2915
fbd79120 2916 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 2917 rc = -ENOENT;
2918 goto out_unlock;
2919 }
2920
8127d661
BH		 2921 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2922 spin_unlock_bh(&efx->filter_lock);
2923
7665d1ab 2924 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 2925 /* Reset to an automatic filter */
8127d661
BH		 2926
2927 struct efx_filter_spec new_spec = *spec;
2928
7665d1ab 2929 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 2930 new_spec.flags = (EFX_FILTER_FLAG_RX |
7665d1ab 2931 EFX_FILTER_FLAG_RX_RSS);
8127d661
BH		 2932 new_spec.dmaq_id = 0;
2933 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2934 rc = efx_ef10_filter_push(efx, &new_spec,
2935 &table->entry[filter_idx].handle,
2936 true);
2937
2938 spin_lock_bh(&efx->filter_lock);
2939 if (rc == 0)
2940 *spec = new_spec;
2941 } else {
2942 /* Really remove the filter */
2943
2944 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2945 efx_ef10_filter_is_exclusive(spec) ?
2946 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2947 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2948 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2949 table->entry[filter_idx].handle);
2950 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2951 inbuf, sizeof(inbuf), NULL, 0, NULL);
2952
2953 spin_lock_bh(&efx->filter_lock);
2954 if (rc == 0) {
2955 kfree(spec);
2956 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2957 }
2958 }
7665d1ab 2959
8127d661
BH		 2960 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2961 wake_up_all(&table->waitq);
2962out_unlock:
2963 spin_unlock_bh(&efx->filter_lock);
2964 finish_wait(&table->waitq, &wait);
2965 return rc;
2966}
2967
2968static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2969 enum efx_filter_priority priority,
2970 u32 filter_id)
2971{
fbd79120
BH		 2972 return efx_ef10_filter_remove_internal(efx, 1U << priority,
2973 filter_id, false);
8127d661
BH		 2974}
2975
2976static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2977 enum efx_filter_priority priority,
2978 u32 filter_id, struct efx_filter_spec *spec)
2979{
2980 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2981 struct efx_ef10_filter_table *table = efx->filter_state;
2982 const struct efx_filter_spec *saved_spec;
2983 int rc;
2984
2985 spin_lock_bh(&efx->filter_lock);
2986 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2987 if (saved_spec && saved_spec->priority == priority &&
2988 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2989 filter_id / HUNT_FILTER_TBL_ROWS) {
2990 *spec = *saved_spec;
2991 rc = 0;
2992 } else {
2993 rc = -ENOENT;
2994 }
2995 spin_unlock_bh(&efx->filter_lock);
2996 return rc;
2997}
2998
fbd79120 2999static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 3000 enum efx_filter_priority priority)
3001{
fbd79120
BH		 3002 unsigned int priority_mask;
3003 unsigned int i;
3004 int rc;
3005
3006 priority_mask = (((1U << (priority + 1)) - 1) &
3007 ~(1U << EFX_FILTER_PRI_AUTO));
3008
3009 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3010 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3011 i, true);
3012 if (rc && rc != -ENOENT)
3013 return rc;
3014 }
3015
3016 return 0;
8127d661
BH		 3017}
3018
3019static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3020 enum efx_filter_priority priority)
3021{
3022 struct efx_ef10_filter_table *table = efx->filter_state;
3023 unsigned int filter_idx;
3024 s32 count = 0;
3025
3026 spin_lock_bh(&efx->filter_lock);
3027 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3028 if (table->entry[filter_idx].spec &&
3029 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3030 priority)
3031 ++count;
3032 }
3033 spin_unlock_bh(&efx->filter_lock);
3034 return count;
3035}
3036
3037static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3038{
3039 struct efx_ef10_filter_table *table = efx->filter_state;
3040
3041 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3042}
3043
3044static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3045 enum efx_filter_priority priority,
3046 u32 *buf, u32 size)
3047{
3048 struct efx_ef10_filter_table *table = efx->filter_state;
3049 struct efx_filter_spec *spec;
3050 unsigned int filter_idx;
3051 s32 count = 0;
3052
3053 spin_lock_bh(&efx->filter_lock);
3054 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3055 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3056 if (spec && spec->priority == priority) {
3057 if (count == size) {
3058 count = -EMSGSIZE;
3059 break;
3060 }
3061 buf[count++] = (efx_ef10_filter_rx_match_pri(
3062 table, spec->match_flags) *
3063 HUNT_FILTER_TBL_ROWS +
3064 filter_idx);
3065 }
3066 }
3067 spin_unlock_bh(&efx->filter_lock);
3068 return count;
3069}
3070
3071#ifdef CONFIG_RFS_ACCEL
3072
3073static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3074
3075static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3076 struct efx_filter_spec *spec)
3077{
3078 struct efx_ef10_filter_table *table = efx->filter_state;
3079 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3080 struct efx_filter_spec *saved_spec;
3081 unsigned int hash, i, depth = 1;
3082 bool replacing = false;
3083 int ins_index = -1;
3084 u64 cookie;
3085 s32 rc;
3086
3087 /* Must be an RX filter without RSS and not for a multicast
3088 * destination address (RFS only works for connected sockets).
3089 * These restrictions allow us to pass only a tiny amount of
3090 * data through to the completion function.
3091 */
3092 EFX_WARN_ON_PARANOID(spec->flags !=
3093 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3094 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3095 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3096
3097 hash = efx_ef10_filter_hash(spec);
3098
3099 spin_lock_bh(&efx->filter_lock);
3100
3101 /* Find any existing filter with the same match tuple or else
3102 * a free slot to insert at. If an existing filter is busy,
3103 * we have to give up.
3104 */
3105 for (;;) {
3106 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3107 saved_spec = efx_ef10_filter_entry_spec(table, i);
3108
3109 if (!saved_spec) {
3110 if (ins_index < 0)
3111 ins_index = i;
3112 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3113 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3114 rc = -EBUSY;
3115 goto fail_unlock;
3116 }
8127d661
BH		 3117 if (spec->priority < saved_spec->priority) {
3118 rc = -EPERM;
3119 goto fail_unlock;
3120 }
3121 ins_index = i;
3122 break;
3123 }
3124
3125 /* Once we reach the maximum search depth, use the
3126 * first suitable slot or return -EBUSY if there was
3127 * none
3128 */
3129 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3130 if (ins_index < 0) {
3131 rc = -EBUSY;
3132 goto fail_unlock;
3133 }
3134 break;
3135 }
3136
3137 ++depth;
3138 }
3139
3140 /* Create a software table entry if necessary, and mark it
3141 * busy. We might yet fail to insert, but any attempt to
3142 * insert a conflicting filter while we're waiting for the
3143 * firmware must find the busy entry.
3144 */
3145 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3146 if (saved_spec) {
3147 replacing = true;
3148 } else {
3149 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3150 if (!saved_spec) {
3151 rc = -ENOMEM;
3152 goto fail_unlock;
3153 }
3154 *saved_spec = *spec;
3155 }
3156 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3157 EFX_EF10_FILTER_FLAG_BUSY);
3158
3159 spin_unlock_bh(&efx->filter_lock);
3160
3161 /* Pack up the variables needed on completion */
3162 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3163
3164 efx_ef10_filter_push_prep(efx, spec, inbuf,
3165 table->entry[ins_index].handle, replacing);
3166 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3167 MC_CMD_FILTER_OP_OUT_LEN,
3168 efx_ef10_filter_rfs_insert_complete, cookie);
3169
3170 return ins_index;
3171
3172fail_unlock:
3173 spin_unlock_bh(&efx->filter_lock);
3174 return rc;
3175}
3176
3177static void
3178efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3179 int rc, efx_dword_t *outbuf,
3180 size_t outlen_actual)
3181{
3182 struct efx_ef10_filter_table *table = efx->filter_state;
3183 unsigned int ins_index, dmaq_id;
3184 struct efx_filter_spec *spec;
3185 bool replacing;
3186
3187 /* Unpack the cookie */
3188 replacing = cookie >> 31;
3189 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3190 dmaq_id = cookie & 0xffff;
3191
3192 spin_lock_bh(&efx->filter_lock);
3193 spec = efx_ef10_filter_entry_spec(table, ins_index);
3194 if (rc == 0) {
3195 table->entry[ins_index].handle =
3196 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3197 if (replacing)
3198 spec->dmaq_id = dmaq_id;
3199 } else if (!replacing) {
3200 kfree(spec);
3201 spec = NULL;
3202 }
3203 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3204 spin_unlock_bh(&efx->filter_lock);
3205
3206 wake_up_all(&table->waitq);
3207}
3208
3209static void
3210efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3211 unsigned long filter_idx,
3212 int rc, efx_dword_t *outbuf,
3213 size_t outlen_actual);
3214
3215static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3216 unsigned int filter_idx)
3217{
3218 struct efx_ef10_filter_table *table = efx->filter_state;
3219 struct efx_filter_spec *spec =
3220 efx_ef10_filter_entry_spec(table, filter_idx);
3221 MCDI_DECLARE_BUF(inbuf,
3222 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3223 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3224
3225 if (!spec ||
3226 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3227 spec->priority != EFX_FILTER_PRI_HINT ||
3228 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3229 flow_id, filter_idx))
3230 return false;
3231
3232 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3233 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3234 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3235 table->entry[filter_idx].handle);
3236 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3237 efx_ef10_filter_rfs_expire_complete, filter_idx))
3238 return false;
3239
3240 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3241 return true;
3242}
3243
3244static void
3245efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3246 unsigned long filter_idx,
3247 int rc, efx_dword_t *outbuf,
3248 size_t outlen_actual)
3249{
3250 struct efx_ef10_filter_table *table = efx->filter_state;
3251 struct efx_filter_spec *spec =
3252 efx_ef10_filter_entry_spec(table, filter_idx);
3253
3254 spin_lock_bh(&efx->filter_lock);
3255 if (rc == 0) {
3256 kfree(spec);
3257 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3258 }
3259 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3260 wake_up_all(&table->waitq);
3261 spin_unlock_bh(&efx->filter_lock);
3262}
3263
3264#endif /* CONFIG_RFS_ACCEL */
3265
3266static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3267{
3268 int match_flags = 0;
3269
3270#define MAP_FLAG(gen_flag, mcdi_field) { \
3271 u32 old_mcdi_flags = mcdi_flags; \
3272 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3273 mcdi_field ## _LBN); \
3274 if (mcdi_flags != old_mcdi_flags) \
3275 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3276 }
3277 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3278 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3279 MAP_FLAG(REM_HOST, SRC_IP);
3280 MAP_FLAG(LOC_HOST, DST_IP);
3281 MAP_FLAG(REM_MAC, SRC_MAC);
3282 MAP_FLAG(REM_PORT, SRC_PORT);
3283 MAP_FLAG(LOC_MAC, DST_MAC);
3284 MAP_FLAG(LOC_PORT, DST_PORT);
3285 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3286 MAP_FLAG(INNER_VID, INNER_VLAN);
3287 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3288 MAP_FLAG(IP_PROTO, IP_PROTO);
3289#undef MAP_FLAG
3290
3291 /* Did we map them all? */
3292 if (mcdi_flags)
3293 return -EINVAL;
3294
3295 return match_flags;
3296}
3297
3298static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3299{
3300 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3301 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3302 unsigned int pd_match_pri, pd_match_count;
3303 struct efx_ef10_filter_table *table;
3304 size_t outlen;
3305 int rc;
3306
3307 table = kzalloc(sizeof(*table), GFP_KERNEL);
3308 if (!table)
3309 return -ENOMEM;
3310
3311 /* Find out which RX filter types are supported, and their priorities */
3312 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3313 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3314 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3315 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3316 &outlen);
3317 if (rc)
3318 goto fail;
3319 pd_match_count = MCDI_VAR_ARRAY_LEN(
3320 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3321 table->rx_match_count = 0;
3322
3323 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3324 u32 mcdi_flags =
3325 MCDI_ARRAY_DWORD(
3326 outbuf,
3327 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3328 pd_match_pri);
3329 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3330 if (rc < 0) {
3331 netif_dbg(efx, probe, efx->net_dev,
3332 "%s: fw flags %#x pri %u not supported in driver\n",
3333 __func__, mcdi_flags, pd_match_pri);
3334 } else {
3335 netif_dbg(efx, probe, efx->net_dev,
3336 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3337 __func__, mcdi_flags, pd_match_pri,
3338 rc, table->rx_match_count);
3339 table->rx_match_flags[table->rx_match_count++] = rc;
3340 }
3341 }
3342
3343 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3344 if (!table->entry) {
3345 rc = -ENOMEM;
3346 goto fail;
3347 }
3348
3349 efx->filter_state = table;
3350 init_waitqueue_head(&table->waitq);
3351 return 0;
3352
3353fail:
3354 kfree(table);
3355 return rc;
3356}
3357
0d322413
EC		 3358/* Caller must hold efx->filter_sem for read if race against
3359 * efx_ef10_filter_table_remove() is possible
3360 */
8127d661
BH		 3361static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3362{
3363 struct efx_ef10_filter_table *table = efx->filter_state;
3364 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3365 struct efx_filter_spec *spec;
3366 unsigned int filter_idx;
3367 bool failed = false;
3368 int rc;
3369
0d322413
EC		 3370 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3371
8127d661
BH		 3372 if (!nic_data->must_restore_filters)
3373 return;
3374
0d322413
EC		 3375 if (!table)
3376 return;
3377
8127d661
BH		 3378 spin_lock_bh(&efx->filter_lock);
3379
3380 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3381 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3382 if (!spec)
3383 continue;
3384
3385 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3386 spin_unlock_bh(&efx->filter_lock);
3387
3388 rc = efx_ef10_filter_push(efx, spec,
3389 &table->entry[filter_idx].handle,
3390 false);
3391 if (rc)
3392 failed = true;
3393
3394 spin_lock_bh(&efx->filter_lock);
3395 if (rc) {
3396 kfree(spec);
3397 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3398 } else {
3399 table->entry[filter_idx].spec &=
3400 ~EFX_EF10_FILTER_FLAG_BUSY;
3401 }
3402 }
3403
3404 spin_unlock_bh(&efx->filter_lock);
3405
3406 if (failed)
3407 netif_err(efx, hw, efx->net_dev,
3408 "unable to restore all filters\n");
3409 else
3410 nic_data->must_restore_filters = false;
3411}
3412
0d322413 3413/* Caller must hold efx->filter_sem for write */
8127d661
BH		 3414static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3415{
3416 struct efx_ef10_filter_table *table = efx->filter_state;
3417 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3418 struct efx_filter_spec *spec;
3419 unsigned int filter_idx;
3420 int rc;
3421
0d322413
EC		 3422 efx->filter_state = NULL;
3423 if (!table)
3424 return;
3425
8127d661
BH		 3426 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3427 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3428 if (!spec)
3429 continue;
3430
3431 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3432 efx_ef10_filter_is_exclusive(spec) ?
3433 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3434 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3435 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3436 table->entry[filter_idx].handle);
3437 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3438 NULL, 0, NULL);
48ce5634
BH		 3439 if (rc)
3440 netdev_WARN(efx->net_dev,
3441 "filter_idx=%#x handle=%#llx\n",
3442 filter_idx,
3443 table->entry[filter_idx].handle);
8127d661
BH		 3444 kfree(spec);
3445 }
3446
3447 vfree(table->entry);
3448 kfree(table);
3449}
3450
0d322413
EC		 3451/* Caller must hold efx->filter_sem for read if race against
3452 * efx_ef10_filter_table_remove() is possible
3453 */
8127d661
BH		 3454static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3455{
3456 struct efx_ef10_filter_table *table = efx->filter_state;
3457 struct net_device *net_dev = efx->net_dev;
3458 struct efx_filter_spec spec;
3459 bool remove_failed = false;
3460 struct netdev_hw_addr *uc;
3461 struct netdev_hw_addr *mc;
3462 unsigned int filter_idx;
3463 int i, n, rc;
3464
3465 if (!efx_dev_registered(efx))
3466 return;
3467
0d322413
EC		 3468 if (!table)
3469 return;
3470
8127d661
BH		 3471 /* Mark old filters that may need to be removed */
3472 spin_lock_bh(&efx->filter_lock);
b59e6ef8 3473 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
8127d661 3474 for (i = 0; i < n; i++) {
b59e6ef8
BH		 3475 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3476 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661 3477 }
b59e6ef8 3478 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
8127d661 3479 for (i = 0; i < n; i++) {
b59e6ef8
BH		 3480 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3481 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3482 }
3483 spin_unlock_bh(&efx->filter_lock);
3484
3485 /* Copy/convert the address lists; add the primary station
3486 * address and broadcast address
3487 */
3488 netif_addr_lock_bh(net_dev);
3489 if (net_dev->flags & IFF_PROMISC ||
b59e6ef8
BH		 3490 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3491 table->dev_uc_count = -1;
8127d661 3492 } else {
b59e6ef8 3493 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
cd84ff4d 3494 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
8127d661
BH		 3495 i = 1;
3496 netdev_for_each_uc_addr(uc, net_dev) {
cd84ff4d 3497 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
8127d661
BH		 3498 i++;
3499 }
3500 }
3501 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
b59e6ef8
BH		 3502 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3503 table->dev_mc_count = -1;
8127d661 3504 } else {
b59e6ef8
BH		 3505 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3506 eth_broadcast_addr(table->dev_mc_list[0].addr);
8127d661
BH		 3507 i = 1;
3508 netdev_for_each_mc_addr(mc, net_dev) {
cd84ff4d 3509 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
8127d661
BH		 3510 i++;
3511 }
3512 }
3513 netif_addr_unlock_bh(net_dev);
3514
3515 /* Insert/renew unicast filters */
b59e6ef8
BH		 3516 if (table->dev_uc_count >= 0) {
3517 for (i = 0; i < table->dev_uc_count; i++) {
7665d1ab
BH		 3518 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3519 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3520 0);
3521 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
b59e6ef8 3522 table->dev_uc_list[i].addr);
8127d661
BH		 3523 rc = efx_ef10_filter_insert(efx, &spec, true);
3524 if (rc < 0) {
3525 /* Fall back to unicast-promisc */
3526 while (i--)
3527 efx_ef10_filter_remove_safe(
7665d1ab 3528 efx, EFX_FILTER_PRI_AUTO,
b59e6ef8
BH		 3529 table->dev_uc_list[i].id);
3530 table->dev_uc_count = -1;
8127d661
BH		 3531 break;
3532 }
b59e6ef8 3533 table->dev_uc_list[i].id = rc;
8127d661
BH		 3534 }
3535 }
b59e6ef8 3536 if (table->dev_uc_count < 0) {
7665d1ab
BH		 3537 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3538 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3539 0);
3540 efx_filter_set_uc_def(&spec);
3541 rc = efx_ef10_filter_insert(efx, &spec, true);
3542 if (rc < 0) {
3543 WARN_ON(1);
b59e6ef8 3544 table->dev_uc_count = 0;
8127d661 3545 } else {
b59e6ef8 3546 table->dev_uc_list[0].id = rc;
8127d661
BH		 3547 }
3548 }
3549
3550 /* Insert/renew multicast filters */
b59e6ef8
BH		 3551 if (table->dev_mc_count >= 0) {
3552 for (i = 0; i < table->dev_mc_count; i++) {
7665d1ab
BH		 3553 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3554 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3555 0);
3556 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
b59e6ef8 3557 table->dev_mc_list[i].addr);
8127d661
BH		 3558 rc = efx_ef10_filter_insert(efx, &spec, true);
3559 if (rc < 0) {
3560 /* Fall back to multicast-promisc */
3561 while (i--)
3562 efx_ef10_filter_remove_safe(
7665d1ab 3563 efx, EFX_FILTER_PRI_AUTO,
b59e6ef8
BH		 3564 table->dev_mc_list[i].id);
3565 table->dev_mc_count = -1;
8127d661
BH		 3566 break;
3567 }
b59e6ef8 3568 table->dev_mc_list[i].id = rc;
8127d661
BH		 3569 }
3570 }
b59e6ef8 3571 if (table->dev_mc_count < 0) {
7665d1ab
BH		 3572 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3573 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3574 0);
3575 efx_filter_set_mc_def(&spec);
3576 rc = efx_ef10_filter_insert(efx, &spec, true);
3577 if (rc < 0) {
3578 WARN_ON(1);
b59e6ef8 3579 table->dev_mc_count = 0;
8127d661 3580 } else {
b59e6ef8 3581 table->dev_mc_list[0].id = rc;
8127d661
BH		 3582 }
3583 }
3584
3585 /* Remove filters that weren't renewed. Since nothing else
b59e6ef8 3586 * changes the AUTO_OLD flag or removes these filters, we
8127d661
BH		 3587 * don't need to hold the filter_lock while scanning for
3588 * these filters.
3589 */
3590 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3591 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 3592 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
7665d1ab 3593 if (efx_ef10_filter_remove_internal(
fbd79120
BH		 3594 efx, 1U << EFX_FILTER_PRI_AUTO,
3595 i, true) < 0)
8127d661
BH		 3596 remove_failed = true;
3597 }
3598 }
3599 WARN_ON(remove_failed);
3600}
3601
910c8789
SS		 3602static int efx_ef10_set_mac_address(struct efx_nic *efx)
3603{
3604 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
3605 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3606 bool was_enabled = efx->port_enabled;
3607 int rc;
3608
3609 efx_device_detach_sync(efx);
3610 efx_net_stop(efx->net_dev);
3611 down_write(&efx->filter_sem);
3612 efx_ef10_filter_table_remove(efx);
3613
3614 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
3615 efx->net_dev->dev_addr);
3616 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
3617 nic_data->vport_id);
3618 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
3619 sizeof(inbuf), NULL, 0, NULL);
3620
3621 efx_ef10_filter_table_probe(efx);
3622 up_write(&efx->filter_sem);
3623 if (was_enabled)
3624 efx_net_open(efx->net_dev);
3625 netif_device_attach(efx->net_dev);
3626
3627#if !defined(CONFIG_SFC_SRIOV)
3628 if (rc == -EPERM)
3629 netif_err(efx, drv, efx->net_dev,
3630 "Cannot change MAC address; use sfboot to enable mac-spoofing"
3631 " on this interface\n");
3632#else
3633 if (rc == -EPERM) {
3634 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
3635
3636 /* Switch to PF and change MAC address on vport */
3637 if (efx->pci_dev->is_virtfn && pci_dev_pf) {
3638 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
3639
3640 if (!efx_ef10_sriov_set_vf_mac(efx_pf,
3641 nic_data->vf_index,
3642 efx->net_dev->dev_addr))
3643 return 0;
3644 }
3645 netif_err(efx, drv, efx->net_dev,
3646 "Cannot change MAC address; use sfboot to enable mac-spoofing"
3647 " on this interface\n");
3648 } else if (efx->pci_dev->is_virtfn) {
3649 /* Successfully changed by VF (with MAC spoofing), so update the
3650 * parent PF if possible.
3651 */
3652 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
3653
3654 if (pci_dev_pf) {
3655 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
3656 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
3657 unsigned int i;
3658
3659 for (i = 0; i < efx_pf->vf_count; ++i) {
3660 struct ef10_vf *vf = nic_data->vf + i;
3661
3662 if (vf->efx == efx) {
3663 ether_addr_copy(vf->mac,
3664 efx->net_dev->dev_addr);
3665 return 0;
3666 }
3667 }
3668 }
3669 }
3670#endif
3671 return rc;
3672}
3673
8127d661
BH		 3674static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3675{
3676 efx_ef10_filter_sync_rx_mode(efx);
3677
3678 return efx_mcdi_set_mac(efx);
3679}
3680
862f894c
SS		 3681static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
3682{
3683 efx_ef10_filter_sync_rx_mode(efx);
3684
3685 return 0;
3686}
3687
74cd60a4
JC		 3688static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3689{
3690 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3691
3692 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3693 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3694 NULL, 0, NULL);
3695}
3696
3697/* MC BISTs follow a different poll mechanism to phy BISTs.
3698 * The BIST is done in the poll handler on the MC, and the MCDI command
3699 * will block until the BIST is done.
3700 */
3701static int efx_ef10_poll_bist(struct efx_nic *efx)
3702{
3703 int rc;
3704 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3705 size_t outlen;
3706 u32 result;
3707
3708 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3709 outbuf, sizeof(outbuf), &outlen);
3710 if (rc != 0)
3711 return rc;
3712
3713 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3714 return -EIO;
3715
3716 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3717 switch (result) {
3718 case MC_CMD_POLL_BIST_PASSED:
3719 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3720 return 0;
3721 case MC_CMD_POLL_BIST_TIMEOUT:
3722 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3723 return -EIO;
3724 case MC_CMD_POLL_BIST_FAILED:
3725 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3726 return -EIO;
3727 default:
3728 netif_err(efx, hw, efx->net_dev,
3729 "BIST returned unknown result %u", result);
3730 return -EIO;
3731 }
3732}
3733
3734static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3735{
3736 int rc;
3737
3738 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3739
3740 rc = efx_ef10_start_bist(efx, bist_type);
3741 if (rc != 0)
3742 return rc;
3743
3744 return efx_ef10_poll_bist(efx);
3745}
3746
3747static int
3748efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3749{
3750 int rc, rc2;
3751
3752 efx_reset_down(efx, RESET_TYPE_WORLD);
3753
3754 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3755 NULL, 0, NULL, 0, NULL);
3756 if (rc != 0)
3757 goto out;
3758
3759 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3760 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3761
3762 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3763
3764out:
3765 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3766 return rc ? rc : rc2;
3767}
3768
8127d661
BH		 3769#ifdef CONFIG_SFC_MTD
3770
3771struct efx_ef10_nvram_type_info {
3772 u16 type, type_mask;
3773 u8 port;
3774 const char *name;
3775};
3776
3777static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3778 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3779 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3780 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3781 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3782 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3783 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3784 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3785 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3786 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 3787 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 3788 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3789};
3790
3791static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3792 struct efx_mcdi_mtd_partition *part,
3793 unsigned int type)
3794{
3795 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3796 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3797 const struct efx_ef10_nvram_type_info *info;
3798 size_t size, erase_size, outlen;
3799 bool protected;
3800 int rc;
3801
3802 for (info = efx_ef10_nvram_types; ; info++) {
3803 if (info ==
3804 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3805 return -ENODEV;
3806 if ((type & ~info->type_mask) == info->type)
3807 break;
3808 }
3809 if (info->port != efx_port_num(efx))
3810 return -ENODEV;
3811
3812 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3813 if (rc)
3814 return rc;
3815 if (protected)
3816 return -ENODEV; /* hide it */
3817
3818 part->nvram_type = type;
3819
3820 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3821 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3822 outbuf, sizeof(outbuf), &outlen);
3823 if (rc)
3824 return rc;
3825 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3826 return -EIO;
3827 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3828 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3829 part->fw_subtype = MCDI_DWORD(outbuf,
3830 NVRAM_METADATA_OUT_SUBTYPE);
3831
3832 part->common.dev_type_name = "EF10 NVRAM manager";
3833 part->common.type_name = info->name;
3834
3835 part->common.mtd.type = MTD_NORFLASH;
3836 part->common.mtd.flags = MTD_CAP_NORFLASH;
3837 part->common.mtd.size = size;
3838 part->common.mtd.erasesize = erase_size;
3839
3840 return 0;
3841}
3842
3843static int efx_ef10_mtd_probe(struct efx_nic *efx)
3844{
3845 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3846 struct efx_mcdi_mtd_partition *parts;
3847 size_t outlen, n_parts_total, i, n_parts;
3848 unsigned int type;
3849 int rc;
3850
3851 ASSERT_RTNL();
3852
3853 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3854 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3855 outbuf, sizeof(outbuf), &outlen);
3856 if (rc)
3857 return rc;
3858 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3859 return -EIO;
3860
3861 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3862 if (n_parts_total >
3863 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3864 return -EIO;
3865
3866 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3867 if (!parts)
3868 return -ENOMEM;
3869
3870 n_parts = 0;
3871 for (i = 0; i < n_parts_total; i++) {
3872 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3873 i);
3874 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3875 if (rc == 0)
3876 n_parts++;
3877 else if (rc != -ENODEV)
3878 goto fail;
3879 }
3880
3881 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3882fail:
3883 if (rc)
3884 kfree(parts);
3885 return rc;
3886}
3887
3888#endif /* CONFIG_SFC_MTD */
3889
3890static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3891{
3892 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3893}
3894
02246a7f
SS		 3895static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
3896 u32 host_time) {}
3897
bd9a265d
JC		 3898static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3899 bool temp)
3900{
3901 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3902 int rc;
3903
3904 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3905 channel->sync_events_state == SYNC_EVENTS_VALID ||
3906 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3907 return 0;
3908 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3909
3910 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3911 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3912 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3913 channel->channel);
3914
3915 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3916 inbuf, sizeof(inbuf), NULL, 0, NULL);
3917
3918 if (rc != 0)
3919 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3920 SYNC_EVENTS_DISABLED;
3921
3922 return rc;
3923}
3924
3925static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3926 bool temp)
3927{
3928 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3929 int rc;
3930
3931 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3932 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3933 return 0;
3934 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3935 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3936 return 0;
3937 }
3938 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3939 SYNC_EVENTS_DISABLED;
3940
3941 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3942 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3943 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3944 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3945 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3946 channel->channel);
3947
3948 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3949 inbuf, sizeof(inbuf), NULL, 0, NULL);
3950
3951 return rc;
3952}
3953
3954static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3955 bool temp)
3956{
3957 int (*set)(struct efx_channel *channel, bool temp);
3958 struct efx_channel *channel;
3959
3960 set = en ?
3961 efx_ef10_rx_enable_timestamping :
3962 efx_ef10_rx_disable_timestamping;
3963
3964 efx_for_each_channel(channel, efx) {
3965 int rc = set(channel, temp);
3966 if (en && rc != 0) {
3967 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3968 return rc;
3969 }
3970 }
3971
3972 return 0;
3973}
3974
02246a7f
SS		 3975static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
3976 struct hwtstamp_config *init)
3977{
3978 return -EOPNOTSUPP;
3979}
3980
bd9a265d
JC		 3981static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3982 struct hwtstamp_config *init)
3983{
3984 int rc;
3985
3986 switch (init->rx_filter) {
3987 case HWTSTAMP_FILTER_NONE:
3988 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3989 /* if TX timestamping is still requested then leave PTP on */
3990 return efx_ptp_change_mode(efx,
3991 init->tx_type != HWTSTAMP_TX_OFF, 0);
3992 case HWTSTAMP_FILTER_ALL:
3993 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3994 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3995 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3996 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3997 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3998 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3999 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4000 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4001 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4002 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4003 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4004 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4005 init->rx_filter = HWTSTAMP_FILTER_ALL;
4006 rc = efx_ptp_change_mode(efx, true, 0);
4007 if (!rc)
4008 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4009 if (rc)
4010 efx_ptp_change_mode(efx, false, 0);
4011 return rc;
4012 default:
4013 return -ERANGE;
4014 }
4015}
4016
02246a7f 4017const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 4018 .is_vf = true,
02246a7f
SS		 4019 .mem_bar = EFX_MEM_VF_BAR,
4020 .mem_map_size = efx_ef10_mem_map_size,
4021 .probe = efx_ef10_probe_vf,
4022 .remove = efx_ef10_remove,
4023 .dimension_resources = efx_ef10_dimension_resources,
4024 .init = efx_ef10_init_nic,
4025 .fini = efx_port_dummy_op_void,
087e9025 4026 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 4027 .map_reset_flags = efx_ef10_map_reset_flags,
4028 .reset = efx_ef10_reset,
4029 .probe_port = efx_mcdi_port_probe,
4030 .remove_port = efx_mcdi_port_remove,
4031 .fini_dmaq = efx_ef10_fini_dmaq,
4032 .prepare_flr = efx_ef10_prepare_flr,
4033 .finish_flr = efx_port_dummy_op_void,
4034 .describe_stats = efx_ef10_describe_stats,
4035 .update_stats = efx_ef10_update_stats,
4036 .start_stats = efx_port_dummy_op_void,
4037 .pull_stats = efx_port_dummy_op_void,
4038 .stop_stats = efx_port_dummy_op_void,
4039 .set_id_led = efx_mcdi_set_id_led,
4040 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 4041 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 4042 .check_mac_fault = efx_mcdi_mac_check_fault,
4043 .reconfigure_port = efx_mcdi_port_reconfigure,
4044 .get_wol = efx_ef10_get_wol_vf,
4045 .set_wol = efx_ef10_set_wol_vf,
4046 .resume_wol = efx_port_dummy_op_void,
4047 .mcdi_request = efx_ef10_mcdi_request,
4048 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4049 .mcdi_read_response = efx_ef10_mcdi_read_response,
4050 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4051 .irq_enable_master = efx_port_dummy_op_void,
4052 .irq_test_generate = efx_ef10_irq_test_generate,
4053 .irq_disable_non_ev = efx_port_dummy_op_void,
4054 .irq_handle_msi = efx_ef10_msi_interrupt,
4055 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4056 .tx_probe = efx_ef10_tx_probe,
4057 .tx_init = efx_ef10_tx_init,
4058 .tx_remove = efx_ef10_tx_remove,
4059 .tx_write = efx_ef10_tx_write,
267c0157 4060 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 4061 .rx_probe = efx_ef10_rx_probe,
4062 .rx_init = efx_ef10_rx_init,
4063 .rx_remove = efx_ef10_rx_remove,
4064 .rx_write = efx_ef10_rx_write,
4065 .rx_defer_refill = efx_ef10_rx_defer_refill,
4066 .ev_probe = efx_ef10_ev_probe,
4067 .ev_init = efx_ef10_ev_init,
4068 .ev_fini = efx_ef10_ev_fini,
4069 .ev_remove = efx_ef10_ev_remove,
4070 .ev_process = efx_ef10_ev_process,
4071 .ev_read_ack = efx_ef10_ev_read_ack,
4072 .ev_test_generate = efx_ef10_ev_test_generate,
4073 .filter_table_probe = efx_ef10_filter_table_probe,
4074 .filter_table_restore = efx_ef10_filter_table_restore,
4075 .filter_table_remove = efx_ef10_filter_table_remove,
4076 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4077 .filter_insert = efx_ef10_filter_insert,
4078 .filter_remove_safe = efx_ef10_filter_remove_safe,
4079 .filter_get_safe = efx_ef10_filter_get_safe,
4080 .filter_clear_rx = efx_ef10_filter_clear_rx,
4081 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4082 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4083 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4084#ifdef CONFIG_RFS_ACCEL
4085 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4086 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4087#endif
4088#ifdef CONFIG_SFC_MTD
4089 .mtd_probe = efx_port_dummy_op_int,
4090#endif
4091 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4092 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4093#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 4094 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4095 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4096 .vswitching_remove = efx_ef10_vswitching_remove_vf,
02246a7f 4097#endif
0d5e0fbb 4098 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 4099 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 4100
02246a7f
SS		 4101 .revision = EFX_REV_HUNT_A0,
4102 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4103 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4104 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4105 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4106 .can_rx_scatter = true,
4107 .always_rx_scatter = true,
4108 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4109 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4110 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4111 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4112 .mcdi_max_ver = 2,
4113 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4114 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4115 1 << HWTSTAMP_FILTER_ALL,
4116};
4117
8127d661 4118const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 4119 .is_vf = false,
02246a7f 4120 .mem_bar = EFX_MEM_BAR,
8127d661 4121 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 4122 .probe = efx_ef10_probe_pf,
8127d661
BH		 4123 .remove = efx_ef10_remove,
4124 .dimension_resources = efx_ef10_dimension_resources,
4125 .init = efx_ef10_init_nic,
4126 .fini = efx_port_dummy_op_void,
087e9025 4127 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 4128 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 4129 .reset = efx_ef10_reset,
8127d661
BH		 4130 .probe_port = efx_mcdi_port_probe,
4131 .remove_port = efx_mcdi_port_remove,
4132 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 4133 .prepare_flr = efx_ef10_prepare_flr,
4134 .finish_flr = efx_port_dummy_op_void,
8127d661
BH		 4135 .describe_stats = efx_ef10_describe_stats,
4136 .update_stats = efx_ef10_update_stats,
4137 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 4138 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 4139 .stop_stats = efx_mcdi_mac_stop_stats,
4140 .set_id_led = efx_mcdi_set_id_led,
4141 .push_irq_moderation = efx_ef10_push_irq_moderation,
4142 .reconfigure_mac = efx_ef10_mac_reconfigure,
4143 .check_mac_fault = efx_mcdi_mac_check_fault,
4144 .reconfigure_port = efx_mcdi_port_reconfigure,
4145 .get_wol = efx_ef10_get_wol,
4146 .set_wol = efx_ef10_set_wol,
4147 .resume_wol = efx_port_dummy_op_void,
74cd60a4 4148 .test_chip = efx_ef10_test_chip,
8127d661
BH		 4149 .test_nvram = efx_mcdi_nvram_test_all,
4150 .mcdi_request = efx_ef10_mcdi_request,
4151 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4152 .mcdi_read_response = efx_ef10_mcdi_read_response,
4153 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4154 .irq_enable_master = efx_port_dummy_op_void,
4155 .irq_test_generate = efx_ef10_irq_test_generate,
4156 .irq_disable_non_ev = efx_port_dummy_op_void,
4157 .irq_handle_msi = efx_ef10_msi_interrupt,
4158 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4159 .tx_probe = efx_ef10_tx_probe,
4160 .tx_init = efx_ef10_tx_init,
4161 .tx_remove = efx_ef10_tx_remove,
4162 .tx_write = efx_ef10_tx_write,
267c0157 4163 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 4164 .rx_probe = efx_ef10_rx_probe,
4165 .rx_init = efx_ef10_rx_init,
4166 .rx_remove = efx_ef10_rx_remove,
4167 .rx_write = efx_ef10_rx_write,
4168 .rx_defer_refill = efx_ef10_rx_defer_refill,
4169 .ev_probe = efx_ef10_ev_probe,
4170 .ev_init = efx_ef10_ev_init,
4171 .ev_fini = efx_ef10_ev_fini,
4172 .ev_remove = efx_ef10_ev_remove,
4173 .ev_process = efx_ef10_ev_process,
4174 .ev_read_ack = efx_ef10_ev_read_ack,
4175 .ev_test_generate = efx_ef10_ev_test_generate,
4176 .filter_table_probe = efx_ef10_filter_table_probe,
4177 .filter_table_restore = efx_ef10_filter_table_restore,
4178 .filter_table_remove = efx_ef10_filter_table_remove,
4179 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4180 .filter_insert = efx_ef10_filter_insert,
4181 .filter_remove_safe = efx_ef10_filter_remove_safe,
4182 .filter_get_safe = efx_ef10_filter_get_safe,
4183 .filter_clear_rx = efx_ef10_filter_clear_rx,
4184 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4185 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4186 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4187#ifdef CONFIG_RFS_ACCEL
4188 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4189 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4190#endif
4191#ifdef CONFIG_SFC_MTD
4192 .mtd_probe = efx_ef10_mtd_probe,
4193 .mtd_rename = efx_mcdi_mtd_rename,
4194 .mtd_read = efx_mcdi_mtd_read,
4195 .mtd_erase = efx_mcdi_mtd_erase,
4196 .mtd_write = efx_mcdi_mtd_write,
4197 .mtd_sync = efx_mcdi_mtd_sync,
4198#endif
4199 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 4200 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4201 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
7fa8d547 4202#ifdef CONFIG_SFC_SRIOV
834e23dd 4203 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 4204 .sriov_init = efx_ef10_sriov_init,
4205 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 4206 .sriov_wanted = efx_ef10_sriov_wanted,
4207 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 4208 .sriov_flr = efx_ef10_sriov_flr,
4209 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4210 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4211 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4212 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 4213 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 4214 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4215 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4216 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 4217#endif
0d5e0fbb 4218 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 4219 .set_mac_address = efx_ef10_set_mac_address,
8127d661
BH		 4220
4221 .revision = EFX_REV_HUNT_A0,
4222 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4223 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4224 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 4225 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 4226 .can_rx_scatter = true,
4227 .always_rx_scatter = true,
4228 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4229 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4230 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4231 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4232 .mcdi_max_ver = 2,
4233 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 4234 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4235 1 << HWTSTAMP_FILTER_ALL,
8127d661 4236};
Linux kernel - Deliverables
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