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f0d37f42 | 1 | /**************************************************************************** |
f2b0befd BH |
2 | * Driver for Solarflare network controllers and boards |
3 | * Copyright 2009-2013 Solarflare Communications Inc. | |
f0d37f42 SH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | ||
11 | #ifndef MCDI_PCOL_H | |
12 | #define MCDI_PCOL_H | |
13 | ||
14 | /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ | |
15 | /* Power-on reset state */ | |
16 | #define MC_FW_STATE_POR (1) | |
17 | /* If this is set in MC_RESET_STATE_REG then it should be | |
18 | * possible to jump into IMEM without loading code from flash. */ | |
19 | #define MC_FW_WARM_BOOT_OK (2) | |
20 | /* The MC main image has started to boot. */ | |
21 | #define MC_FW_STATE_BOOTING (4) | |
22 | /* The Scheduler has started. */ | |
23 | #define MC_FW_STATE_SCHED (8) | |
f2b0befd BH |
24 | /* If this is set in MC_RESET_STATE_REG then it should be |
25 | * possible to jump into IMEM without loading code from flash. | |
26 | * Unlike a warm boot, assume DMEM has been reloaded, so that | |
27 | * the MC persistent data must be reinitialised. */ | |
28 | #define MC_FW_TEPID_BOOT_OK (16) | |
a9196bb0 EC |
29 | /* We have entered the main firmware via recovery mode. This |
30 | * means that MC persistent data must be reinitialised, but that | |
31 | * we shouldn't touch PCIe config. */ | |
32 | #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) | |
f2b0befd BH |
33 | /* BIST state has been initialized */ |
34 | #define MC_FW_BIST_INIT_OK (128) | |
f0d37f42 | 35 | |
05a9320f BH |
36 | /* Siena MC shared memmory offsets */ |
37 | /* The 'doorbell' addresses are hard-wired to alert the MC when written */ | |
38 | #define MC_SMEM_P0_DOORBELL_OFST 0x000 | |
39 | #define MC_SMEM_P1_DOORBELL_OFST 0x004 | |
40 | /* The rest of these are firmware-defined */ | |
41 | #define MC_SMEM_P0_PDU_OFST 0x008 | |
42 | #define MC_SMEM_P1_PDU_OFST 0x108 | |
43 | #define MC_SMEM_PDU_LEN 0x100 | |
44 | #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 | |
45 | #define MC_SMEM_P0_STATUS_OFST 0x7f8 | |
46 | #define MC_SMEM_P1_STATUS_OFST 0x7fc | |
47 | ||
f0d37f42 SH |
48 | /* Values to be written to the per-port status dword in shared |
49 | * memory on reboot and assert */ | |
50 | #define MC_STATUS_DWORD_REBOOT (0xb007b007) | |
51 | #define MC_STATUS_DWORD_ASSERT (0xdeaddead) | |
52 | ||
f2b0befd BH |
53 | /* Check whether an mcfw version (in host order) belongs to a bootloader */ |
54 | #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) | |
55 | ||
f0d37f42 SH |
56 | /* The current version of the MCDI protocol. |
57 | * | |
58 | * Note that the ROM burnt into the card only talks V0, so at the very | |
59 | * least every driver must support version 0 and MCDI_PCOL_VERSION | |
60 | */ | |
f2b0befd | 61 | #define MCDI_PCOL_VERSION 2 |
f0d37f42 | 62 | |
05a9320f BH |
63 | /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ |
64 | ||
1aa8b471 | 65 | /* MCDI version 1 |
f0d37f42 | 66 | * |
f2b0befd | 67 | * Each MCDI request starts with an MCDI_HEADER, which is a 32bit |
f0d37f42 SH |
68 | * structure, filled in by the client. |
69 | * | |
70 | * 0 7 8 16 20 22 23 24 31 | |
71 | * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | | |
72 | * | | | | |
73 | * | | \--- Response | |
74 | * | \------- Error | |
75 | * \------------------------------ Resync (always set) | |
76 | * | |
77 | * The client writes it's request into MC shared memory, and rings the | |
78 | * doorbell. Each request is completed by either by the MC writting | |
79 | * back into shared memory, or by writting out an event. | |
80 | * | |
81 | * All MCDI commands support completion by shared memory response. Each | |
82 | * request may also contain additional data (accounted for by HEADER.LEN), | |
83 | * and some response's may also contain additional data (again, accounted | |
84 | * for by HEADER.LEN). | |
85 | * | |
86 | * Some MCDI commands support completion by event, in which any associated | |
87 | * response data is included in the event. | |
88 | * | |
89 | * The protocol requires one response to be delivered for every request, a | |
90 | * request should not be sent unless the response for the previous request | |
91 | * has been received (either by polling shared memory, or by receiving | |
92 | * an event). | |
93 | */ | |
94 | ||
95 | /** Request/Response structure */ | |
96 | #define MCDI_HEADER_OFST 0 | |
97 | #define MCDI_HEADER_CODE_LBN 0 | |
98 | #define MCDI_HEADER_CODE_WIDTH 7 | |
99 | #define MCDI_HEADER_RESYNC_LBN 7 | |
100 | #define MCDI_HEADER_RESYNC_WIDTH 1 | |
101 | #define MCDI_HEADER_DATALEN_LBN 8 | |
102 | #define MCDI_HEADER_DATALEN_WIDTH 8 | |
103 | #define MCDI_HEADER_SEQ_LBN 16 | |
f0d37f42 | 104 | #define MCDI_HEADER_SEQ_WIDTH 4 |
f2b0befd BH |
105 | #define MCDI_HEADER_RSVD_LBN 20 |
106 | #define MCDI_HEADER_RSVD_WIDTH 1 | |
107 | #define MCDI_HEADER_NOT_EPOCH_LBN 21 | |
108 | #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 | |
f0d37f42 SH |
109 | #define MCDI_HEADER_ERROR_LBN 22 |
110 | #define MCDI_HEADER_ERROR_WIDTH 1 | |
111 | #define MCDI_HEADER_RESPONSE_LBN 23 | |
112 | #define MCDI_HEADER_RESPONSE_WIDTH 1 | |
113 | #define MCDI_HEADER_XFLAGS_LBN 24 | |
114 | #define MCDI_HEADER_XFLAGS_WIDTH 8 | |
115 | /* Request response using event */ | |
116 | #define MCDI_HEADER_XFLAGS_EVREQ 0x01 | |
117 | ||
118 | /* Maximum number of payload bytes */ | |
d0c2ee99 | 119 | #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc |
f2b0befd BH |
120 | #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 |
121 | ||
122 | #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 | |
d0c2ee99 | 123 | |
f0d37f42 SH |
124 | |
125 | /* The MC can generate events for two reasons: | |
126 | * - To complete a shared memory request if XFLAGS_EVREQ was set | |
127 | * - As a notification (link state, i2c event), controlled | |
128 | * via MC_CMD_LOG_CTRL | |
129 | * | |
130 | * Both events share a common structure: | |
131 | * | |
132 | * 0 32 33 36 44 52 60 | |
133 | * | Data | Cont | Level | Src | Code | Rsvd | | |
134 | * | | |
135 | * \ There is another event pending in this notification | |
136 | * | |
137 | * If Code==CMDDONE, then the fields are further interpreted as: | |
138 | * | |
25985edc | 139 | * - LEVEL==INFO Command succeeded |
f0d37f42 SH |
140 | * - LEVEL==ERR Command failed |
141 | * | |
142 | * 0 8 16 24 32 | |
143 | * | Seq | Datalen | Errno | Rsvd | | |
144 | * | |
145 | * These fields are taken directly out of the standard MCDI header, i.e., | |
146 | * LEVEL==ERR, Datalen == 0 => Reboot | |
147 | * | |
148 | * Events can be squirted out of the UART (using LOG_CTRL) without a | |
149 | * MCDI header. An event can be distinguished from a MCDI response by | |
150 | * examining the first byte which is 0xc0. This corresponds to the | |
151 | * non-existent MCDI command MC_CMD_DEBUG_LOG. | |
152 | * | |
153 | * 0 7 8 | |
154 | * | command | Resync | = 0xc0 | |
155 | * | |
156 | * Since the event is written in big-endian byte order, this works | |
157 | * providing bits 56-63 of the event are 0xc0. | |
158 | * | |
159 | * 56 60 63 | |
160 | * | Rsvd | Code | = 0xc0 | |
161 | * | |
162 | * Which means for convenience the event code is 0xc for all MC | |
163 | * generated events. | |
164 | */ | |
165 | #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc | |
166 | ||
f0d37f42 | 167 | |
f2b0befd BH |
168 | /* Operation not permitted. */ |
169 | #define MC_CMD_ERR_EPERM 1 | |
f0d37f42 SH |
170 | /* Non-existent command target */ |
171 | #define MC_CMD_ERR_ENOENT 2 | |
172 | /* assert() has killed the MC */ | |
173 | #define MC_CMD_ERR_EINTR 4 | |
f2b0befd BH |
174 | /* I/O failure */ |
175 | #define MC_CMD_ERR_EIO 5 | |
a9196bb0 EC |
176 | /* Already exists */ |
177 | #define MC_CMD_ERR_EEXIST 6 | |
f2b0befd BH |
178 | /* Try again */ |
179 | #define MC_CMD_ERR_EAGAIN 11 | |
180 | /* Out of memory */ | |
181 | #define MC_CMD_ERR_ENOMEM 12 | |
f0d37f42 SH |
182 | /* Caller does not hold required locks */ |
183 | #define MC_CMD_ERR_EACCES 13 | |
184 | /* Resource is currently unavailable (e.g. lock contention) */ | |
185 | #define MC_CMD_ERR_EBUSY 16 | |
f2b0befd BH |
186 | /* No such device */ |
187 | #define MC_CMD_ERR_ENODEV 19 | |
f0d37f42 SH |
188 | /* Invalid argument to target */ |
189 | #define MC_CMD_ERR_EINVAL 22 | |
a9196bb0 EC |
190 | /* Broken pipe */ |
191 | #define MC_CMD_ERR_EPIPE 32 | |
192 | /* Read-only */ | |
193 | #define MC_CMD_ERR_EROFS 30 | |
f2b0befd BH |
194 | /* Out of range */ |
195 | #define MC_CMD_ERR_ERANGE 34 | |
f0d37f42 SH |
196 | /* Non-recursive resource is already acquired */ |
197 | #define MC_CMD_ERR_EDEADLK 35 | |
198 | /* Operation not implemented */ | |
199 | #define MC_CMD_ERR_ENOSYS 38 | |
200 | /* Operation timed out */ | |
201 | #define MC_CMD_ERR_ETIME 62 | |
f2b0befd BH |
202 | /* Link has been severed */ |
203 | #define MC_CMD_ERR_ENOLINK 67 | |
204 | /* Protocol error */ | |
205 | #define MC_CMD_ERR_EPROTO 71 | |
206 | /* Operation not supported */ | |
207 | #define MC_CMD_ERR_ENOTSUP 95 | |
208 | /* Address not available */ | |
209 | #define MC_CMD_ERR_EADDRNOTAVAIL 99 | |
210 | /* Not connected */ | |
211 | #define MC_CMD_ERR_ENOTCONN 107 | |
212 | /* Operation already in progress */ | |
213 | #define MC_CMD_ERR_EALREADY 114 | |
214 | ||
215 | /* Resource allocation failed. */ | |
216 | #define MC_CMD_ERR_ALLOC_FAIL 0x1000 | |
217 | /* V-adaptor not found. */ | |
218 | #define MC_CMD_ERR_NO_VADAPTOR 0x1001 | |
219 | /* EVB port not found. */ | |
220 | #define MC_CMD_ERR_NO_EVB_PORT 0x1002 | |
221 | /* V-switch not found. */ | |
222 | #define MC_CMD_ERR_NO_VSWITCH 0x1003 | |
223 | /* Too many VLAN tags. */ | |
224 | #define MC_CMD_ERR_VLAN_LIMIT 0x1004 | |
225 | /* Bad PCI function number. */ | |
226 | #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 | |
227 | /* Invalid VLAN mode. */ | |
228 | #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 | |
229 | /* Invalid v-switch type. */ | |
230 | #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 | |
231 | /* Invalid v-port type. */ | |
232 | #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 | |
233 | /* MAC address exists. */ | |
234 | #define MC_CMD_ERR_MAC_EXIST 0x1009 | |
235 | /* Slave core not present */ | |
236 | #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a | |
512bb06c BH |
237 | /* The datapath is disabled. */ |
238 | #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b | |
a9196bb0 EC |
239 | /* The requesting client is not a function */ |
240 | #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c | |
241 | /* The requested operation might require the | |
242 | command to be passed between MCs, and the | |
243 | transport doesn't support that. Should | |
244 | only ever been seen over the UART. */ | |
245 | #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d | |
246 | /* VLAN tag(s) exists */ | |
247 | #define MC_CMD_ERR_VLAN_EXIST 0x100e | |
248 | /* No MAC address assigned to an EVB port */ | |
249 | #define MC_CMD_ERR_NO_MAC_ADDR 0x100f | |
250 | /* Notifies the driver that the request has been relayed | |
251 | * to an admin function for authorization. The driver should | |
252 | * wait for a PROXY_RESPONSE event and then resend its request. | |
253 | * This error code is followed by a 32-bit handle that | |
254 | * helps matching it with the respective PROXY_RESPONSE event. */ | |
255 | #define MC_CMD_ERR_PROXY_PENDING 0x1010 | |
256 | #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 | |
257 | /* The request cannot be passed for authorization because | |
258 | * another request from the same function is currently being | |
259 | * authorized. The drvier should try again later. */ | |
260 | #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 | |
261 | /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function | |
262 | * that has enabled proxying or BLOCK_INDEX points to a function that | |
263 | * doesn't await an authorization. */ | |
264 | #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 | |
265 | /* This code is currently only used internally in FW. Its meaning is that | |
266 | * an operation failed due to lack of SR-IOV privilege. | |
267 | * Normally it is translated to EPERM by send_cmd_err(), | |
268 | * but it may also be used to trigger some special mechanism | |
269 | * for handling such case, e.g. to relay the failed request | |
270 | * to a designated admin function for authorization. */ | |
271 | #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 | |
272 | /* Workaround 26807 could not be turned on/off because some functions | |
273 | * have already installed filters. See the comment at | |
274 | * MC_CMD_WORKAROUND_BUG26807. */ | |
275 | #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 | |
23e202b4 EC |
276 | /* The clock whose frequency you've attempted to set set |
277 | * doesn't exist on this NIC */ | |
278 | #define MC_CMD_ERR_NO_CLOCK 0x1015 | |
f0d37f42 SH |
279 | |
280 | #define MC_CMD_ERR_CODE_OFST 0 | |
281 | ||
05a9320f BH |
282 | /* We define 8 "escape" commands to allow |
283 | for command number space extension */ | |
284 | ||
285 | #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 | |
286 | #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 | |
287 | #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A | |
288 | #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B | |
289 | #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C | |
290 | #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D | |
291 | #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E | |
292 | #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F | |
293 | ||
294 | /* Vectors in the boot ROM */ | |
295 | /* Point to the copycode entry point. */ | |
f2b0befd BH |
296 | #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) |
297 | #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) | |
23e202b4 | 298 | #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) |
05a9320f | 299 | /* Points to the recovery mode entry point. */ |
f2b0befd BH |
300 | #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) |
301 | #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) | |
23e202b4 | 302 | #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) |
f0d37f42 | 303 | |
f0d37f42 SH |
304 | /* The command set exported by the boot ROM (MCDI v0) */ |
305 | #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ | |
306 | (1 << MC_CMD_READ32) | \ | |
307 | (1 << MC_CMD_WRITE32) | \ | |
308 | (1 << MC_CMD_COPYCODE) | \ | |
309 | (1 << MC_CMD_GET_VERSION), \ | |
310 | 0, 0, 0 } | |
f0d37f42 | 311 | |
05a9320f BH |
312 | #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ |
313 | (MC_CMD_SENSOR_ENTRY_OFST + (_x)) | |
314 | ||
315 | #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ | |
316 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
317 | MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ | |
318 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
319 | ||
320 | #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ | |
321 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
322 | MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ | |
323 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
324 | ||
325 | #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ | |
326 | (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ | |
327 | MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ | |
328 | (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) | |
329 | ||
a9196bb0 EC |
330 | /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default |
331 | * stack ID (which must be in the range 1-255) along with an EVB port ID. | |
332 | */ | |
333 | #define EVB_STACK_ID(n) (((n) & 0xff) << 16) | |
334 | ||
05a9320f | 335 | |
f2b0befd BH |
336 | /* Version 2 adds an optional argument to error returns: the errno value |
337 | * may be followed by the (0-based) number of the first argument that | |
338 | * could not be processed. | |
339 | */ | |
340 | #define MC_CMD_ERR_ARG_OFST 4 | |
341 | ||
342 | /* No space */ | |
343 | #define MC_CMD_ERR_ENOSPC 28 | |
344 | ||
05a9320f BH |
345 | /* MCDI_EVENT structuredef */ |
346 | #define MCDI_EVENT_LEN 8 | |
347 | #define MCDI_EVENT_CONT_LBN 32 | |
348 | #define MCDI_EVENT_CONT_WIDTH 1 | |
349 | #define MCDI_EVENT_LEVEL_LBN 33 | |
350 | #define MCDI_EVENT_LEVEL_WIDTH 3 | |
f2b0befd BH |
351 | /* enum: Info. */ |
352 | #define MCDI_EVENT_LEVEL_INFO 0x0 | |
353 | /* enum: Warning. */ | |
354 | #define MCDI_EVENT_LEVEL_WARN 0x1 | |
355 | /* enum: Error. */ | |
356 | #define MCDI_EVENT_LEVEL_ERR 0x2 | |
357 | /* enum: Fatal. */ | |
358 | #define MCDI_EVENT_LEVEL_FATAL 0x3 | |
05a9320f BH |
359 | #define MCDI_EVENT_DATA_OFST 0 |
360 | #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 | |
361 | #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 | |
362 | #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 | |
363 | #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 | |
364 | #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 | |
365 | #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 | |
366 | #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 | |
367 | #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 | |
368 | #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 | |
369 | #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 | |
f2b0befd BH |
370 | /* enum: 100Mbs */ |
371 | #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 | |
372 | /* enum: 1Gbs */ | |
373 | #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 | |
374 | /* enum: 10Gbs */ | |
375 | #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 | |
376 | /* enum: 40Gbs */ | |
377 | #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 | |
05a9320f BH |
378 | #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 |
379 | #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 | |
380 | #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 | |
381 | #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 | |
382 | #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 | |
383 | #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 | |
384 | #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 | |
385 | #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 | |
386 | #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 | |
387 | #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 | |
388 | #define MCDI_EVENT_FWALERT_DATA_LBN 8 | |
389 | #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 | |
390 | #define MCDI_EVENT_FWALERT_REASON_LBN 0 | |
391 | #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 | |
f2b0befd BH |
392 | /* enum: SRAM Access. */ |
393 | #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 | |
05a9320f BH |
394 | #define MCDI_EVENT_FLR_VF_LBN 0 |
395 | #define MCDI_EVENT_FLR_VF_WIDTH 8 | |
396 | #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 | |
397 | #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 | |
398 | #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 | |
399 | #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 | |
f2b0befd BH |
400 | /* enum: Descriptor loader reported failure */ |
401 | #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 | |
402 | /* enum: Descriptor ring empty and no EOP seen for packet */ | |
403 | #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 | |
404 | /* enum: Overlength packet */ | |
405 | #define MCDI_EVENT_TX_ERR_2BIG 0x3 | |
406 | /* enum: Malformed option descriptor */ | |
407 | #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 | |
408 | /* enum: Option descriptor part way through a packet */ | |
409 | #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 | |
410 | /* enum: DMA or PIO data access error */ | |
411 | #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 | |
05a9320f BH |
412 | #define MCDI_EVENT_TX_ERR_INFO_LBN 16 |
413 | #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 | |
f2b0befd BH |
414 | #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 |
415 | #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 | |
05a9320f BH |
416 | #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 |
417 | #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 | |
418 | #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 | |
419 | #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 | |
f2b0befd BH |
420 | /* enum: PLL lost lock */ |
421 | #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 | |
422 | /* enum: Filter overflow (PDMA) */ | |
423 | #define MCDI_EVENT_PTP_ERR_FILTER 0x2 | |
424 | /* enum: FIFO overflow (FPGA) */ | |
425 | #define MCDI_EVENT_PTP_ERR_FIFO 0x3 | |
426 | /* enum: Merge queue overflow */ | |
427 | #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 | |
428 | #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 | |
429 | #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 | |
430 | /* enum: AOE failed to load - no valid image? */ | |
431 | #define MCDI_EVENT_AOE_NO_LOAD 0x1 | |
432 | /* enum: AOE FC reported an exception */ | |
433 | #define MCDI_EVENT_AOE_FC_ASSERT 0x2 | |
434 | /* enum: AOE FC watchdogged */ | |
435 | #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 | |
436 | /* enum: AOE FC failed to start */ | |
437 | #define MCDI_EVENT_AOE_FC_NO_START 0x4 | |
438 | /* enum: Generic AOE fault - likely to have been reported via other means too | |
439 | * but intended for use by aoex driver. | |
440 | */ | |
441 | #define MCDI_EVENT_AOE_FAULT 0x5 | |
442 | /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ | |
443 | #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 | |
444 | /* enum: AOE loaded successfully */ | |
445 | #define MCDI_EVENT_AOE_LOAD 0x7 | |
446 | /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ | |
447 | #define MCDI_EVENT_AOE_DMA 0x8 | |
448 | /* enum: AOE byteblaster connected/disconnected (Connection status in | |
449 | * AOE_ERR_DATA) | |
450 | */ | |
451 | #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 | |
512bb06c BH |
452 | /* enum: DDR ECC status update */ |
453 | #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa | |
a9196bb0 EC |
454 | /* enum: PTP status update */ |
455 | #define MCDI_EVENT_AOE_PTP_STATUS 0xb | |
f2b0befd BH |
456 | #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 |
457 | #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 | |
458 | #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 | |
459 | #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 | |
460 | #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 | |
461 | #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 | |
462 | #define MCDI_EVENT_RX_ERR_INFO_LBN 16 | |
463 | #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 | |
464 | #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 | |
465 | #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 | |
466 | #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 | |
467 | #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 | |
468 | #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 | |
469 | #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 | |
a9196bb0 EC |
470 | #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 |
471 | #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 | |
472 | /* enum: MUM failed to load - no valid image? */ | |
473 | #define MCDI_EVENT_MUM_NO_LOAD 0x1 | |
474 | /* enum: MUM f/w reported an exception */ | |
475 | #define MCDI_EVENT_MUM_ASSERT 0x2 | |
476 | /* enum: MUM not kicking watchdog */ | |
477 | #define MCDI_EVENT_MUM_WATCHDOG 0x3 | |
478 | #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 | |
479 | #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 | |
05a9320f BH |
480 | #define MCDI_EVENT_DATA_LBN 0 |
481 | #define MCDI_EVENT_DATA_WIDTH 32 | |
482 | #define MCDI_EVENT_SRC_LBN 36 | |
483 | #define MCDI_EVENT_SRC_WIDTH 8 | |
484 | #define MCDI_EVENT_EV_CODE_LBN 60 | |
485 | #define MCDI_EVENT_EV_CODE_WIDTH 4 | |
486 | #define MCDI_EVENT_CODE_LBN 44 | |
487 | #define MCDI_EVENT_CODE_WIDTH 8 | |
a9196bb0 EC |
488 | /* enum: Event generated by host software */ |
489 | #define MCDI_EVENT_SW_EVENT 0x0 | |
f2b0befd BH |
490 | /* enum: Bad assert. */ |
491 | #define MCDI_EVENT_CODE_BADSSERT 0x1 | |
492 | /* enum: PM Notice. */ | |
493 | #define MCDI_EVENT_CODE_PMNOTICE 0x2 | |
494 | /* enum: Command done. */ | |
495 | #define MCDI_EVENT_CODE_CMDDONE 0x3 | |
496 | /* enum: Link change. */ | |
497 | #define MCDI_EVENT_CODE_LINKCHANGE 0x4 | |
498 | /* enum: Sensor Event. */ | |
499 | #define MCDI_EVENT_CODE_SENSOREVT 0x5 | |
500 | /* enum: Schedule error. */ | |
501 | #define MCDI_EVENT_CODE_SCHEDERR 0x6 | |
502 | /* enum: Reboot. */ | |
503 | #define MCDI_EVENT_CODE_REBOOT 0x7 | |
504 | /* enum: Mac stats DMA. */ | |
505 | #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 | |
506 | /* enum: Firmware alert. */ | |
507 | #define MCDI_EVENT_CODE_FWALERT 0x9 | |
508 | /* enum: Function level reset. */ | |
509 | #define MCDI_EVENT_CODE_FLR 0xa | |
510 | /* enum: Transmit error */ | |
511 | #define MCDI_EVENT_CODE_TX_ERR 0xb | |
512 | /* enum: Tx flush has completed */ | |
513 | #define MCDI_EVENT_CODE_TX_FLUSH 0xc | |
514 | /* enum: PTP packet received timestamp */ | |
515 | #define MCDI_EVENT_CODE_PTP_RX 0xd | |
516 | /* enum: PTP NIC failure */ | |
517 | #define MCDI_EVENT_CODE_PTP_FAULT 0xe | |
518 | /* enum: PTP PPS event */ | |
519 | #define MCDI_EVENT_CODE_PTP_PPS 0xf | |
520 | /* enum: Rx flush has completed */ | |
521 | #define MCDI_EVENT_CODE_RX_FLUSH 0x10 | |
522 | /* enum: Receive error */ | |
523 | #define MCDI_EVENT_CODE_RX_ERR 0x11 | |
524 | /* enum: AOE fault */ | |
525 | #define MCDI_EVENT_CODE_AOE 0x12 | |
526 | /* enum: Network port calibration failed (VCAL). */ | |
527 | #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 | |
528 | /* enum: HW PPS event */ | |
529 | #define MCDI_EVENT_CODE_HW_PPS 0x14 | |
530 | /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and | |
531 | * a different format) | |
532 | */ | |
533 | #define MCDI_EVENT_CODE_MC_REBOOT 0x15 | |
534 | /* enum: the MC has detected a parity error */ | |
535 | #define MCDI_EVENT_CODE_PAR_ERR 0x16 | |
536 | /* enum: the MC has detected a correctable error */ | |
537 | #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 | |
538 | /* enum: the MC has detected an uncorrectable error */ | |
539 | #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 | |
512bb06c BH |
540 | /* enum: The MC has entered offline BIST mode */ |
541 | #define MCDI_EVENT_CODE_MC_BIST 0x19 | |
542 | /* enum: PTP tick event providing current NIC time */ | |
543 | #define MCDI_EVENT_CODE_PTP_TIME 0x1a | |
a9196bb0 EC |
544 | /* enum: MUM fault */ |
545 | #define MCDI_EVENT_CODE_MUM 0x1b | |
546 | /* enum: notify the designated PF of a new authorization request */ | |
547 | #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c | |
548 | /* enum: notify a function that awaits an authorization that its request has | |
549 | * been processed and it may now resend the command | |
550 | */ | |
551 | #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d | |
f2b0befd BH |
552 | /* enum: Artificial event generated by host and posted via MC for test |
553 | * purposes. | |
554 | */ | |
555 | #define MCDI_EVENT_CODE_TESTGEN 0xfa | |
05a9320f BH |
556 | #define MCDI_EVENT_CMDDONE_DATA_OFST 0 |
557 | #define MCDI_EVENT_CMDDONE_DATA_LBN 0 | |
558 | #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 | |
559 | #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 | |
560 | #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 | |
561 | #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 | |
562 | #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 | |
563 | #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 | |
564 | #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 | |
565 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 | |
566 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 | |
567 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 | |
568 | #define MCDI_EVENT_TX_ERR_DATA_OFST 0 | |
569 | #define MCDI_EVENT_TX_ERR_DATA_LBN 0 | |
570 | #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 | |
512bb06c BH |
571 | /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of |
572 | * timestamp | |
573 | */ | |
05a9320f BH |
574 | #define MCDI_EVENT_PTP_SECONDS_OFST 0 |
575 | #define MCDI_EVENT_PTP_SECONDS_LBN 0 | |
576 | #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 | |
512bb06c BH |
577 | /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of |
578 | * timestamp | |
579 | */ | |
580 | #define MCDI_EVENT_PTP_MAJOR_OFST 0 | |
581 | #define MCDI_EVENT_PTP_MAJOR_LBN 0 | |
582 | #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 | |
583 | /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field | |
584 | * of timestamp | |
585 | */ | |
05a9320f BH |
586 | #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 |
587 | #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 | |
588 | #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 | |
512bb06c BH |
589 | /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of |
590 | * timestamp | |
591 | */ | |
592 | #define MCDI_EVENT_PTP_MINOR_OFST 0 | |
593 | #define MCDI_EVENT_PTP_MINOR_LBN 0 | |
594 | #define MCDI_EVENT_PTP_MINOR_WIDTH 32 | |
595 | /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet | |
596 | */ | |
05a9320f BH |
597 | #define MCDI_EVENT_PTP_UUID_OFST 0 |
598 | #define MCDI_EVENT_PTP_UUID_LBN 0 | |
599 | #define MCDI_EVENT_PTP_UUID_WIDTH 32 | |
f2b0befd BH |
600 | #define MCDI_EVENT_RX_ERR_DATA_OFST 0 |
601 | #define MCDI_EVENT_RX_ERR_DATA_LBN 0 | |
602 | #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 | |
603 | #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 | |
604 | #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 | |
605 | #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 | |
606 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 | |
607 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 | |
608 | #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 | |
609 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 | |
610 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 | |
611 | #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 | |
512bb06c BH |
612 | /* For CODE_PTP_TIME events, the major value of the PTP clock */ |
613 | #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 | |
614 | #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 | |
615 | #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 | |
616 | /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ | |
617 | #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 | |
618 | #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 | |
a9196bb0 EC |
619 | /* For CODE_PTP_TIME events where report sync status is enabled, indicates |
620 | * whether the NIC clock has ever been set | |
621 | */ | |
622 | #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 | |
623 | #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 | |
624 | /* For CODE_PTP_TIME events where report sync status is enabled, indicates | |
625 | * whether the NIC and System clocks are in sync | |
626 | */ | |
627 | #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 | |
628 | #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 | |
629 | /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of | |
630 | * the minor value of the PTP clock | |
631 | */ | |
632 | #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 | |
633 | #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 | |
634 | #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 | |
635 | #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 | |
636 | #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 | |
637 | #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 | |
638 | #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 | |
639 | #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 | |
640 | /* Zero means that the request has been completed or authorized, and the driver | |
641 | * should resend it. A non-zero value means that the authorization has been | |
642 | * denied, and gives the reason. Typically it will be EPERM. | |
643 | */ | |
644 | #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 | |
645 | #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 | |
f2b0befd BH |
646 | |
647 | /* FCDI_EVENT structuredef */ | |
648 | #define FCDI_EVENT_LEN 8 | |
649 | #define FCDI_EVENT_CONT_LBN 32 | |
650 | #define FCDI_EVENT_CONT_WIDTH 1 | |
651 | #define FCDI_EVENT_LEVEL_LBN 33 | |
652 | #define FCDI_EVENT_LEVEL_WIDTH 3 | |
653 | /* enum: Info. */ | |
654 | #define FCDI_EVENT_LEVEL_INFO 0x0 | |
655 | /* enum: Warning. */ | |
656 | #define FCDI_EVENT_LEVEL_WARN 0x1 | |
657 | /* enum: Error. */ | |
658 | #define FCDI_EVENT_LEVEL_ERR 0x2 | |
659 | /* enum: Fatal. */ | |
660 | #define FCDI_EVENT_LEVEL_FATAL 0x3 | |
661 | #define FCDI_EVENT_DATA_OFST 0 | |
662 | #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 | |
663 | #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 | |
664 | #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ | |
665 | #define FCDI_EVENT_LINK_UP 0x1 /* enum */ | |
666 | #define FCDI_EVENT_DATA_LBN 0 | |
667 | #define FCDI_EVENT_DATA_WIDTH 32 | |
668 | #define FCDI_EVENT_SRC_LBN 36 | |
669 | #define FCDI_EVENT_SRC_WIDTH 8 | |
670 | #define FCDI_EVENT_EV_CODE_LBN 60 | |
671 | #define FCDI_EVENT_EV_CODE_WIDTH 4 | |
672 | #define FCDI_EVENT_CODE_LBN 44 | |
673 | #define FCDI_EVENT_CODE_WIDTH 8 | |
674 | /* enum: The FC was rebooted. */ | |
675 | #define FCDI_EVENT_CODE_REBOOT 0x1 | |
676 | /* enum: Bad assert. */ | |
677 | #define FCDI_EVENT_CODE_ASSERT 0x2 | |
678 | /* enum: DDR3 test result. */ | |
679 | #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 | |
680 | /* enum: Link status. */ | |
681 | #define FCDI_EVENT_CODE_LINK_STATE 0x4 | |
682 | /* enum: A timed read is ready to be serviced. */ | |
683 | #define FCDI_EVENT_CODE_TIMED_READ 0x5 | |
684 | /* enum: One or more PPS IN events */ | |
685 | #define FCDI_EVENT_CODE_PPS_IN 0x6 | |
512bb06c BH |
686 | /* enum: Tick event from PTP clock */ |
687 | #define FCDI_EVENT_CODE_PTP_TICK 0x7 | |
688 | /* enum: ECC error counters */ | |
689 | #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 | |
a9196bb0 EC |
690 | /* enum: Current status of PTP */ |
691 | #define FCDI_EVENT_CODE_PTP_STATUS 0x9 | |
692 | /* enum: Port id config to map MC-FC port idx */ | |
693 | #define FCDI_EVENT_CODE_PORT_CONFIG 0xa | |
23e202b4 EC |
694 | /* enum: Boot result or error code */ |
695 | #define FCDI_EVENT_CODE_BOOT_RESULT 0xb | |
696 | #define FCDI_EVENT_REBOOT_SRC_LBN 36 | |
697 | #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 | |
698 | #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ | |
699 | #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ | |
f2b0befd BH |
700 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 |
701 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 | |
702 | #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 | |
703 | #define FCDI_EVENT_ASSERT_TYPE_LBN 36 | |
704 | #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 | |
705 | #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 | |
706 | #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 | |
707 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 | |
708 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 | |
709 | #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 | |
710 | #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 | |
711 | #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 | |
712 | #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 | |
a9196bb0 EC |
713 | #define FCDI_EVENT_PTP_STATE_OFST 0 |
714 | #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ | |
715 | #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ | |
716 | #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ | |
717 | #define FCDI_EVENT_PTP_STATE_LBN 0 | |
718 | #define FCDI_EVENT_PTP_STATE_WIDTH 32 | |
512bb06c BH |
719 | #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 |
720 | #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 | |
721 | #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 | |
722 | #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 | |
723 | #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 | |
a9196bb0 EC |
724 | /* Index of MC port being referred to */ |
725 | #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 | |
726 | #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 | |
727 | /* FC Port index that matches the MC port index in SRC */ | |
728 | #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 | |
729 | #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 | |
730 | #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 | |
23e202b4 EC |
731 | #define FCDI_EVENT_BOOT_RESULT_OFST 0 |
732 | /* Enum values, see field(s): */ | |
733 | /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ | |
734 | #define FCDI_EVENT_BOOT_RESULT_LBN 0 | |
735 | #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 | |
512bb06c BH |
736 | |
737 | /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events | |
738 | * to the MC. Note that this structure | is overlayed over a normal FCDI event | |
739 | * such that bits 32-63 containing | event code, level, source etc remain the | |
740 | * same. In this case the data | field of the header is defined to be the | |
741 | * number of timestamps | |
742 | */ | |
743 | #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 | |
744 | #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 | |
745 | #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) | |
f2b0befd BH |
746 | /* Number of timestamps following */ |
747 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 | |
748 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 | |
749 | #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 | |
750 | /* Seconds field of a timestamp record */ | |
751 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 | |
752 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 | |
753 | #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 | |
754 | /* Nanoseconds field of a timestamp record */ | |
755 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 | |
756 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 | |
757 | #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 | |
758 | /* Timestamp records comprising the event */ | |
512bb06c BH |
759 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 |
760 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 | |
761 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 | |
762 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 | |
763 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 | |
764 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 | |
765 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 | |
766 | #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 | |
05a9320f | 767 | |
a9196bb0 EC |
768 | /* MUM_EVENT structuredef */ |
769 | #define MUM_EVENT_LEN 8 | |
770 | #define MUM_EVENT_CONT_LBN 32 | |
771 | #define MUM_EVENT_CONT_WIDTH 1 | |
772 | #define MUM_EVENT_LEVEL_LBN 33 | |
773 | #define MUM_EVENT_LEVEL_WIDTH 3 | |
774 | /* enum: Info. */ | |
775 | #define MUM_EVENT_LEVEL_INFO 0x0 | |
776 | /* enum: Warning. */ | |
777 | #define MUM_EVENT_LEVEL_WARN 0x1 | |
778 | /* enum: Error. */ | |
779 | #define MUM_EVENT_LEVEL_ERR 0x2 | |
780 | /* enum: Fatal. */ | |
781 | #define MUM_EVENT_LEVEL_FATAL 0x3 | |
782 | #define MUM_EVENT_DATA_OFST 0 | |
783 | #define MUM_EVENT_SENSOR_ID_LBN 0 | |
784 | #define MUM_EVENT_SENSOR_ID_WIDTH 8 | |
785 | /* Enum values, see field(s): */ | |
786 | /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ | |
787 | #define MUM_EVENT_SENSOR_STATE_LBN 8 | |
788 | #define MUM_EVENT_SENSOR_STATE_WIDTH 8 | |
789 | #define MUM_EVENT_PORT_PHY_READY_LBN 0 | |
790 | #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 | |
791 | #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 | |
792 | #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 | |
793 | #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 | |
794 | #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 | |
795 | #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 | |
796 | #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 | |
797 | #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 | |
798 | #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 | |
799 | #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 | |
800 | #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 | |
801 | #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 | |
802 | #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 | |
803 | #define MUM_EVENT_DATA_LBN 0 | |
804 | #define MUM_EVENT_DATA_WIDTH 32 | |
805 | #define MUM_EVENT_SRC_LBN 36 | |
806 | #define MUM_EVENT_SRC_WIDTH 8 | |
807 | #define MUM_EVENT_EV_CODE_LBN 60 | |
808 | #define MUM_EVENT_EV_CODE_WIDTH 4 | |
809 | #define MUM_EVENT_CODE_LBN 44 | |
810 | #define MUM_EVENT_CODE_WIDTH 8 | |
811 | /* enum: The MUM was rebooted. */ | |
812 | #define MUM_EVENT_CODE_REBOOT 0x1 | |
813 | /* enum: Bad assert. */ | |
814 | #define MUM_EVENT_CODE_ASSERT 0x2 | |
815 | /* enum: Sensor failure. */ | |
816 | #define MUM_EVENT_CODE_SENSOR 0x3 | |
817 | /* enum: Link fault has been asserted, or has cleared. */ | |
818 | #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 | |
819 | #define MUM_EVENT_SENSOR_DATA_OFST 0 | |
820 | #define MUM_EVENT_SENSOR_DATA_LBN 0 | |
821 | #define MUM_EVENT_SENSOR_DATA_WIDTH 32 | |
822 | #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 | |
823 | #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 | |
824 | #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 | |
825 | #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 | |
826 | #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 | |
827 | #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 | |
828 | #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 | |
829 | #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 | |
830 | #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 | |
831 | #define MUM_EVENT_PORT_PHY_TECH_OFST 0 | |
832 | #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ | |
833 | #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ | |
834 | #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ | |
835 | #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ | |
836 | #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ | |
837 | #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ | |
838 | #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ | |
839 | #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ | |
840 | #define MUM_EVENT_PORT_PHY_TECH_LBN 0 | |
841 | #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 | |
842 | #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 | |
843 | #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 | |
844 | #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ | |
845 | #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ | |
846 | #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ | |
847 | #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ | |
848 | #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ | |
849 | #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 | |
850 | #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 | |
851 | ||
05a9320f BH |
852 | |
853 | /***********************************/ | |
854 | /* MC_CMD_READ32 | |
855 | * Read multiple 32byte words from MC memory. | |
856 | */ | |
857 | #define MC_CMD_READ32 0x1 | |
858 | ||
75122ec8 SS |
859 | #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
860 | ||
05a9320f BH |
861 | /* MC_CMD_READ32_IN msgrequest */ |
862 | #define MC_CMD_READ32_IN_LEN 8 | |
863 | #define MC_CMD_READ32_IN_ADDR_OFST 0 | |
864 | #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 | |
865 | ||
866 | /* MC_CMD_READ32_OUT msgresponse */ | |
867 | #define MC_CMD_READ32_OUT_LENMIN 4 | |
868 | #define MC_CMD_READ32_OUT_LENMAX 252 | |
869 | #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) | |
870 | #define MC_CMD_READ32_OUT_BUFFER_OFST 0 | |
871 | #define MC_CMD_READ32_OUT_BUFFER_LEN 4 | |
872 | #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 | |
873 | #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 | |
874 | ||
875 | ||
876 | /***********************************/ | |
877 | /* MC_CMD_WRITE32 | |
878 | * Write multiple 32byte words to MC memory. | |
879 | */ | |
880 | #define MC_CMD_WRITE32 0x2 | |
881 | ||
75122ec8 SS |
882 | #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
883 | ||
05a9320f BH |
884 | /* MC_CMD_WRITE32_IN msgrequest */ |
885 | #define MC_CMD_WRITE32_IN_LENMIN 8 | |
886 | #define MC_CMD_WRITE32_IN_LENMAX 252 | |
887 | #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) | |
888 | #define MC_CMD_WRITE32_IN_ADDR_OFST 0 | |
889 | #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 | |
890 | #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 | |
891 | #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 | |
892 | #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 | |
893 | ||
894 | /* MC_CMD_WRITE32_OUT msgresponse */ | |
895 | #define MC_CMD_WRITE32_OUT_LEN 0 | |
896 | ||
897 | ||
898 | /***********************************/ | |
899 | /* MC_CMD_COPYCODE | |
900 | * Copy MC code between two locations and jump. | |
901 | */ | |
902 | #define MC_CMD_COPYCODE 0x3 | |
903 | ||
75122ec8 SS |
904 | #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
905 | ||
05a9320f BH |
906 | /* MC_CMD_COPYCODE_IN msgrequest */ |
907 | #define MC_CMD_COPYCODE_IN_LEN 16 | |
a9196bb0 EC |
908 | /* Source address |
909 | * | |
910 | * The main image should be entered via a copy of a single word from and to a | |
911 | * magic address, which controls various aspects of the boot. The magic address | |
912 | * is a bitfield, with each bit as documented below. | |
512bb06c | 913 | */ |
a9196bb0 EC |
914 | #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 |
915 | /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ | |
512bb06c | 916 | #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 |
a9196bb0 EC |
917 | /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and |
918 | * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) | |
f2b0befd BH |
919 | */ |
920 | #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 | |
a9196bb0 EC |
921 | /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, |
922 | * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see | |
923 | * below) | |
f2b0befd BH |
924 | */ |
925 | #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc | |
a9196bb0 EC |
926 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 |
927 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 | |
928 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 | |
929 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 | |
930 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 | |
931 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 | |
932 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 | |
933 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 | |
934 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 | |
935 | #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 | |
f2b0befd | 936 | /* Destination address */ |
05a9320f BH |
937 | #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 |
938 | #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 | |
f2b0befd | 939 | /* Address of where to jump after copy. */ |
05a9320f | 940 | #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 |
f2b0befd BH |
941 | /* enum: Control should return to the caller rather than jumping */ |
942 | #define MC_CMD_COPYCODE_JUMP_NONE 0x1 | |
05a9320f BH |
943 | |
944 | /* MC_CMD_COPYCODE_OUT msgresponse */ | |
945 | #define MC_CMD_COPYCODE_OUT_LEN 0 | |
946 | ||
947 | ||
948 | /***********************************/ | |
949 | /* MC_CMD_SET_FUNC | |
f2b0befd | 950 | * Select function for function-specific commands. |
05a9320f BH |
951 | */ |
952 | #define MC_CMD_SET_FUNC 0x4 | |
953 | ||
75122ec8 SS |
954 | #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
955 | ||
05a9320f BH |
956 | /* MC_CMD_SET_FUNC_IN msgrequest */ |
957 | #define MC_CMD_SET_FUNC_IN_LEN 4 | |
f2b0befd | 958 | /* Set function */ |
05a9320f BH |
959 | #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 |
960 | ||
961 | /* MC_CMD_SET_FUNC_OUT msgresponse */ | |
962 | #define MC_CMD_SET_FUNC_OUT_LEN 0 | |
963 | ||
964 | ||
965 | /***********************************/ | |
966 | /* MC_CMD_GET_BOOT_STATUS | |
f2b0befd | 967 | * Get the instruction address from which the MC booted. |
05a9320f BH |
968 | */ |
969 | #define MC_CMD_GET_BOOT_STATUS 0x5 | |
970 | ||
75122ec8 SS |
971 | #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
972 | ||
05a9320f BH |
973 | /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ |
974 | #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 | |
975 | ||
976 | /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ | |
977 | #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 | |
f2b0befd | 978 | /* ?? */ |
05a9320f | 979 | #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 |
f2b0befd BH |
980 | /* enum: indicates that the MC wasn't flash booted */ |
981 | #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef | |
05a9320f BH |
982 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 |
983 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 | |
984 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 | |
985 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 | |
986 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 | |
987 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 | |
988 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 | |
f0d37f42 | 989 | |
f0d37f42 | 990 | |
05a9320f BH |
991 | /***********************************/ |
992 | /* MC_CMD_GET_ASSERTS | |
f2b0befd BH |
993 | * Get (and optionally clear) the current assertion status. Only |
994 | * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other | |
995 | * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS | |
f0d37f42 | 996 | */ |
05a9320f | 997 | #define MC_CMD_GET_ASSERTS 0x6 |
f0d37f42 | 998 | |
75122ec8 SS |
999 | #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1000 | ||
05a9320f BH |
1001 | /* MC_CMD_GET_ASSERTS_IN msgrequest */ |
1002 | #define MC_CMD_GET_ASSERTS_IN_LEN 4 | |
f2b0befd | 1003 | /* Set to clear assertion */ |
05a9320f BH |
1004 | #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 |
1005 | ||
1006 | /* MC_CMD_GET_ASSERTS_OUT msgresponse */ | |
1007 | #define MC_CMD_GET_ASSERTS_OUT_LEN 140 | |
f2b0befd | 1008 | /* Assertion status flag. */ |
05a9320f | 1009 | #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 |
f2b0befd BH |
1010 | /* enum: No assertions have failed. */ |
1011 | #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 | |
1012 | /* enum: A system-level assertion has failed. */ | |
1013 | #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 | |
1014 | /* enum: A thread-level assertion has failed. */ | |
1015 | #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 | |
1016 | /* enum: The system was reset by the watchdog. */ | |
1017 | #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 | |
1018 | /* enum: An illegal address trap stopped the system (huntington and later) */ | |
1019 | #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 | |
1020 | /* Failing PC value */ | |
05a9320f | 1021 | #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 |
f2b0befd | 1022 | /* Saved GP regs */ |
05a9320f BH |
1023 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 |
1024 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 | |
1025 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 | |
a9196bb0 EC |
1026 | /* enum: A magic value hinting that the value in this register at the time of |
1027 | * the failure has likely been lost. | |
1028 | */ | |
1029 | #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 | |
f2b0befd | 1030 | /* Failing thread address */ |
05a9320f BH |
1031 | #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 |
1032 | #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 | |
f0d37f42 | 1033 | |
05a9320f BH |
1034 | |
1035 | /***********************************/ | |
1036 | /* MC_CMD_LOG_CTRL | |
a9196bb0 EC |
1037 | * Configure the output stream for log events such as link state changes, |
1038 | * sensor notifications and MCDI completions | |
05a9320f BH |
1039 | */ |
1040 | #define MC_CMD_LOG_CTRL 0x7 | |
1041 | ||
75122ec8 SS |
1042 | #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
1043 | ||
05a9320f BH |
1044 | /* MC_CMD_LOG_CTRL_IN msgrequest */ |
1045 | #define MC_CMD_LOG_CTRL_IN_LEN 8 | |
f2b0befd | 1046 | /* Log destination */ |
05a9320f | 1047 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 |
f2b0befd BH |
1048 | /* enum: UART. */ |
1049 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 | |
1050 | /* enum: Event queue. */ | |
1051 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 | |
a9196bb0 | 1052 | /* Legacy argument. Must be zero. */ |
05a9320f BH |
1053 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 |
1054 | ||
1055 | /* MC_CMD_LOG_CTRL_OUT msgresponse */ | |
1056 | #define MC_CMD_LOG_CTRL_OUT_LEN 0 | |
1057 | ||
1058 | ||
1059 | /***********************************/ | |
1060 | /* MC_CMD_GET_VERSION | |
1061 | * Get version information about the MC firmware. | |
1062 | */ | |
1063 | #define MC_CMD_GET_VERSION 0x8 | |
1064 | ||
75122ec8 SS |
1065 | #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
1066 | ||
05a9320f BH |
1067 | /* MC_CMD_GET_VERSION_IN msgrequest */ |
1068 | #define MC_CMD_GET_VERSION_IN_LEN 0 | |
1069 | ||
f2b0befd BH |
1070 | /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ |
1071 | #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 | |
1072 | /* placeholder, set to 0 */ | |
1073 | #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 | |
1074 | ||
1075 | /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ | |
05a9320f BH |
1076 | #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 |
1077 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 | |
f2b0befd BH |
1078 | /* enum: Reserved version number to indicate "any" version. */ |
1079 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff | |
1080 | /* enum: Bootrom version value for Siena. */ | |
1081 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 | |
1082 | /* enum: Bootrom version value for Huntington. */ | |
1083 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 | |
05a9320f BH |
1084 | |
1085 | /* MC_CMD_GET_VERSION_OUT msgresponse */ | |
1086 | #define MC_CMD_GET_VERSION_OUT_LEN 32 | |
1087 | /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ | |
1088 | /* Enum values, see field(s): */ | |
1089 | /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ | |
1090 | #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 | |
f2b0befd | 1091 | /* 128bit mask of functions supported by the current firmware */ |
05a9320f BH |
1092 | #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 |
1093 | #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 | |
1094 | #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 | |
1095 | #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 | |
1096 | #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 | |
1097 | #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 | |
1098 | ||
f2b0befd BH |
1099 | /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ |
1100 | #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 | |
1101 | /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ | |
1102 | /* Enum values, see field(s): */ | |
1103 | /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ | |
1104 | #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 | |
1105 | /* 128bit mask of functions supported by the current firmware */ | |
1106 | #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 | |
1107 | #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 | |
1108 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 | |
1109 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 | |
1110 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 | |
1111 | #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 | |
1112 | /* extra info */ | |
1113 | #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 | |
1114 | #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 | |
05a9320f BH |
1115 | |
1116 | ||
1117 | /***********************************/ | |
1118 | /* MC_CMD_PTP | |
1119 | * Perform PTP operation | |
1120 | */ | |
1121 | #define MC_CMD_PTP 0xb | |
1122 | ||
75122ec8 SS |
1123 | #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
1124 | ||
05a9320f BH |
1125 | /* MC_CMD_PTP_IN msgrequest */ |
1126 | #define MC_CMD_PTP_IN_LEN 1 | |
f2b0befd | 1127 | /* PTP operation code */ |
05a9320f BH |
1128 | #define MC_CMD_PTP_IN_OP_OFST 0 |
1129 | #define MC_CMD_PTP_IN_OP_LEN 1 | |
f2b0befd BH |
1130 | /* enum: Enable PTP packet timestamping operation. */ |
1131 | #define MC_CMD_PTP_OP_ENABLE 0x1 | |
1132 | /* enum: Disable PTP packet timestamping operation. */ | |
1133 | #define MC_CMD_PTP_OP_DISABLE 0x2 | |
1134 | /* enum: Send a PTP packet. */ | |
1135 | #define MC_CMD_PTP_OP_TRANSMIT 0x3 | |
1136 | /* enum: Read the current NIC time. */ | |
1137 | #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 | |
1138 | /* enum: Get the current PTP status. */ | |
1139 | #define MC_CMD_PTP_OP_STATUS 0x5 | |
1140 | /* enum: Adjust the PTP NIC's time. */ | |
1141 | #define MC_CMD_PTP_OP_ADJUST 0x6 | |
1142 | /* enum: Synchronize host and NIC time. */ | |
1143 | #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 | |
1144 | /* enum: Basic manufacturing tests. */ | |
1145 | #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 | |
1146 | /* enum: Packet based manufacturing tests. */ | |
1147 | #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 | |
1148 | /* enum: Reset some of the PTP related statistics */ | |
1149 | #define MC_CMD_PTP_OP_RESET_STATS 0xa | |
1150 | /* enum: Debug operations to MC. */ | |
1151 | #define MC_CMD_PTP_OP_DEBUG 0xb | |
1152 | /* enum: Read an FPGA register */ | |
1153 | #define MC_CMD_PTP_OP_FPGAREAD 0xc | |
1154 | /* enum: Write an FPGA register */ | |
1155 | #define MC_CMD_PTP_OP_FPGAWRITE 0xd | |
1156 | /* enum: Apply an offset to the NIC clock */ | |
1157 | #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe | |
1158 | /* enum: Change Apply an offset to the NIC clock */ | |
1159 | #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf | |
1160 | /* enum: Set the MC packet filter VLAN tags for received PTP packets */ | |
1161 | #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 | |
1162 | /* enum: Set the MC packet filter UUID for received PTP packets */ | |
1163 | #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 | |
1164 | /* enum: Set the MC packet filter Domain for received PTP packets */ | |
1165 | #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 | |
1166 | /* enum: Set the clock source */ | |
1167 | #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 | |
1168 | /* enum: Reset value of Timer Reg. */ | |
1169 | #define MC_CMD_PTP_OP_RST_CLK 0x14 | |
1170 | /* enum: Enable the forwarding of PPS events to the host */ | |
1171 | #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 | |
512bb06c BH |
1172 | /* enum: Get the time format used by this NIC for PTP operations */ |
1173 | #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 | |
1174 | /* enum: Get the clock attributes. NOTE- extended version of | |
1175 | * MC_CMD_PTP_OP_GET_TIME_FORMAT | |
1176 | */ | |
1177 | #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 | |
1178 | /* enum: Get corrections that should be applied to the various different | |
1179 | * timestamps | |
1180 | */ | |
1181 | #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 | |
1182 | /* enum: Subscribe to receive periodic time events indicating the current NIC | |
1183 | * time | |
1184 | */ | |
1185 | #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 | |
1186 | /* enum: Unsubscribe to stop receiving time events */ | |
1187 | #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 | |
1188 | /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS | |
1189 | * input on the same NIC. | |
1190 | */ | |
1191 | #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a | |
a9196bb0 EC |
1192 | /* enum: Set the PTP sync status. Status is used by firmware to report to event |
1193 | * subscribers. | |
1194 | */ | |
1195 | #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b | |
f2b0befd | 1196 | /* enum: Above this for future use. */ |
a9196bb0 | 1197 | #define MC_CMD_PTP_OP_MAX 0x1c |
05a9320f BH |
1198 | |
1199 | /* MC_CMD_PTP_IN_ENABLE msgrequest */ | |
1200 | #define MC_CMD_PTP_IN_ENABLE_LEN 16 | |
1201 | #define MC_CMD_PTP_IN_CMD_OFST 0 | |
1202 | #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 | |
f2b0befd | 1203 | /* Event queue for PTP events */ |
05a9320f | 1204 | #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 |
f2b0befd | 1205 | /* PTP timestamping mode */ |
05a9320f | 1206 | #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 |
f2b0befd BH |
1207 | /* enum: PTP, version 1 */ |
1208 | #define MC_CMD_PTP_MODE_V1 0x0 | |
1209 | /* enum: PTP, version 1, with VLAN headers - deprecated */ | |
1210 | #define MC_CMD_PTP_MODE_V1_VLAN 0x1 | |
1211 | /* enum: PTP, version 2 */ | |
1212 | #define MC_CMD_PTP_MODE_V2 0x2 | |
1213 | /* enum: PTP, version 2, with VLAN headers - deprecated */ | |
1214 | #define MC_CMD_PTP_MODE_V2_VLAN 0x3 | |
1215 | /* enum: PTP, version 2, with improved UUID filtering */ | |
1216 | #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 | |
1217 | /* enum: FCoE (seconds and microseconds) */ | |
1218 | #define MC_CMD_PTP_MODE_FCOE 0x5 | |
05a9320f BH |
1219 | |
1220 | /* MC_CMD_PTP_IN_DISABLE msgrequest */ | |
1221 | #define MC_CMD_PTP_IN_DISABLE_LEN 8 | |
1222 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1223 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1224 | ||
1225 | /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ | |
1226 | #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 | |
576eda8b | 1227 | #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 |
05a9320f BH |
1228 | #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) |
1229 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1230 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1231 | /* Transmit packet length */ |
05a9320f | 1232 | #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 |
f2b0befd | 1233 | /* Transmit packet data */ |
05a9320f BH |
1234 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 |
1235 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 | |
1236 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 | |
576eda8b | 1237 | #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 |
05a9320f BH |
1238 | |
1239 | /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ | |
1240 | #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 | |
1241 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1242 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1243 | ||
1244 | /* MC_CMD_PTP_IN_STATUS msgrequest */ | |
1245 | #define MC_CMD_PTP_IN_STATUS_LEN 8 | |
1246 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1247 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1248 | ||
1249 | /* MC_CMD_PTP_IN_ADJUST msgrequest */ | |
1250 | #define MC_CMD_PTP_IN_ADJUST_LEN 24 | |
1251 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1252 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1253 | /* Frequency adjustment 40 bit fixed point ns */ |
05a9320f BH |
1254 | #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 |
1255 | #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 | |
1256 | #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 | |
1257 | #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 | |
f2b0befd BH |
1258 | /* enum: Number of fractional bits in frequency adjustment */ |
1259 | #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 | |
1260 | /* Time adjustment in seconds */ | |
05a9320f | 1261 | #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 |
512bb06c BH |
1262 | /* Time adjustment major value */ |
1263 | #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 | |
f2b0befd | 1264 | /* Time adjustment in nanoseconds */ |
05a9320f | 1265 | #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 |
512bb06c BH |
1266 | /* Time adjustment minor value */ |
1267 | #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 | |
05a9320f BH |
1268 | |
1269 | /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ | |
1270 | #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 | |
1271 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1272 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1273 | /* Number of time readings to capture */ |
05a9320f | 1274 | #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 |
f2b0befd BH |
1275 | /* Host address in which to write "synchronization started" indication (64 |
1276 | * bits) | |
1277 | */ | |
05a9320f BH |
1278 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 |
1279 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 | |
1280 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 | |
1281 | #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 | |
1282 | ||
1283 | /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ | |
1284 | #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 | |
1285 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1286 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1287 | ||
1288 | /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ | |
1289 | #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 | |
1290 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1291 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1292 | /* Enable or disable packet testing */ |
05a9320f BH |
1293 | #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 |
1294 | ||
1295 | /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ | |
1296 | #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 | |
1297 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
f2b0befd | 1298 | /* Reset PTP statistics */ |
05a9320f BH |
1299 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
1300 | ||
1301 | /* MC_CMD_PTP_IN_DEBUG msgrequest */ | |
1302 | #define MC_CMD_PTP_IN_DEBUG_LEN 12 | |
1303 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1304 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
f2b0befd | 1305 | /* Debug operations */ |
05a9320f BH |
1306 | #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 |
1307 | ||
f2b0befd BH |
1308 | /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ |
1309 | #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 | |
1310 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1311 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1312 | #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 | |
1313 | #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 | |
1314 | ||
1315 | /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ | |
1316 | #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 | |
1317 | #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 | |
1318 | #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) | |
1319 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1320 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1321 | #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 | |
1322 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 | |
1323 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 | |
1324 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 | |
1325 | #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 | |
1326 | ||
1327 | /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ | |
1328 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 | |
1329 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1330 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1331 | /* Time adjustment in seconds */ | |
1332 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 | |
512bb06c BH |
1333 | /* Time adjustment major value */ |
1334 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 | |
f2b0befd BH |
1335 | /* Time adjustment in nanoseconds */ |
1336 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 | |
512bb06c BH |
1337 | /* Time adjustment minor value */ |
1338 | #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 | |
f2b0befd BH |
1339 | |
1340 | /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ | |
1341 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 | |
1342 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1343 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1344 | /* Frequency adjustment 40 bit fixed point ns */ | |
1345 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 | |
1346 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 | |
1347 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 | |
1348 | #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 | |
1349 | /* enum: Number of fractional bits in frequency adjustment */ | |
1350 | /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ | |
1351 | ||
1352 | /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ | |
1353 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 | |
1354 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1355 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1356 | /* Number of VLAN tags, 0 if not VLAN */ | |
1357 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 | |
1358 | /* Set of VLAN tags to filter against */ | |
1359 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 | |
1360 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 | |
1361 | #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 | |
1362 | ||
1363 | /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ | |
1364 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 | |
1365 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1366 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1367 | /* 1 to enable UUID filtering, 0 to disable */ | |
1368 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 | |
1369 | /* UUID to filter against */ | |
1370 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 | |
1371 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 | |
1372 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 | |
1373 | #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 | |
1374 | ||
1375 | /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ | |
1376 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 | |
1377 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1378 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1379 | /* 1 to enable Domain filtering, 0 to disable */ | |
1380 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 | |
1381 | /* Domain number to filter against */ | |
1382 | #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 | |
1383 | ||
1384 | /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ | |
1385 | #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 | |
1386 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1387 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1388 | /* Set the clock source. */ | |
1389 | #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 | |
1390 | /* enum: Internal. */ | |
1391 | #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 | |
1392 | /* enum: External. */ | |
1393 | #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 | |
1394 | ||
1395 | /* MC_CMD_PTP_IN_RST_CLK msgrequest */ | |
1396 | #define MC_CMD_PTP_IN_RST_CLK_LEN 8 | |
1397 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1398 | /* Reset value of Timer Reg. */ | |
1399 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1400 | ||
1401 | /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ | |
1402 | #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 | |
1403 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1404 | /* Enable or disable */ | |
1405 | #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 | |
1406 | /* enum: Enable */ | |
1407 | #define MC_CMD_PTP_ENABLE_PPS 0x0 | |
1408 | /* enum: Disable */ | |
1409 | #define MC_CMD_PTP_DISABLE_PPS 0x1 | |
512bb06c | 1410 | /* Queue id to send events back */ |
f2b0befd BH |
1411 | #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 |
1412 | ||
512bb06c BH |
1413 | /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ |
1414 | #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 | |
1415 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1416 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1417 | ||
1418 | /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ | |
1419 | #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 | |
1420 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1421 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1422 | ||
1423 | /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ | |
1424 | #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 | |
1425 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1426 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1427 | ||
1428 | /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ | |
1429 | #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 | |
1430 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1431 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
a9196bb0 | 1432 | /* Original field containing queue ID. Now extended to include flags. */ |
512bb06c | 1433 | #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 |
a9196bb0 EC |
1434 | #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 |
1435 | #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 | |
1436 | #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 | |
1437 | #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 | |
512bb06c BH |
1438 | |
1439 | /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ | |
1440 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 | |
1441 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1442 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1443 | /* Unsubscribe options */ | |
1444 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 | |
1445 | /* enum: Unsubscribe a single queue */ | |
1446 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 | |
1447 | /* enum: Unsubscribe all queues */ | |
1448 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 | |
1449 | /* Event queue ID */ | |
1450 | #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 | |
1451 | ||
1452 | /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ | |
1453 | #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 | |
1454 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1455 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1456 | /* 1 to enable PPS test mode, 0 to disable and return result. */ | |
1457 | #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 | |
1458 | ||
a9196bb0 EC |
1459 | /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ |
1460 | #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 | |
1461 | /* MC_CMD_PTP_IN_CMD_OFST 0 */ | |
1462 | /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ | |
1463 | /* NIC - Host System Clock Synchronization status */ | |
1464 | #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 | |
1465 | /* enum: Host System clock and NIC clock are not in sync */ | |
1466 | #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 | |
1467 | /* enum: Host System clock and NIC clock are synchronized */ | |
1468 | #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 | |
1469 | /* If synchronized, number of seconds until clocks should be considered to be | |
1470 | * no longer in sync. | |
1471 | */ | |
1472 | #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 | |
1473 | #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 | |
1474 | #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 | |
1475 | ||
05a9320f BH |
1476 | /* MC_CMD_PTP_OUT msgresponse */ |
1477 | #define MC_CMD_PTP_OUT_LEN 0 | |
1478 | ||
1479 | /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ | |
1480 | #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 | |
f2b0befd | 1481 | /* Value of seconds timestamp */ |
05a9320f | 1482 | #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 |
512bb06c BH |
1483 | /* Timestamp major value */ |
1484 | #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 | |
f2b0befd | 1485 | /* Value of nanoseconds timestamp */ |
05a9320f | 1486 | #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 |
512bb06c BH |
1487 | /* Timestamp minor value */ |
1488 | #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 | |
1489 | ||
1490 | /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ | |
1491 | #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 | |
1492 | ||
1493 | /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ | |
1494 | #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 | |
05a9320f BH |
1495 | |
1496 | /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ | |
1497 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 | |
f2b0befd | 1498 | /* Value of seconds timestamp */ |
05a9320f | 1499 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 |
512bb06c BH |
1500 | /* Timestamp major value */ |
1501 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 | |
f2b0befd | 1502 | /* Value of nanoseconds timestamp */ |
05a9320f | 1503 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 |
512bb06c BH |
1504 | /* Timestamp minor value */ |
1505 | #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 | |
05a9320f BH |
1506 | |
1507 | /* MC_CMD_PTP_OUT_STATUS msgresponse */ | |
1508 | #define MC_CMD_PTP_OUT_STATUS_LEN 64 | |
f2b0befd | 1509 | /* Frequency of NIC's hardware clock */ |
05a9320f | 1510 | #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 |
f2b0befd | 1511 | /* Number of packets transmitted and timestamped */ |
05a9320f | 1512 | #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 |
f2b0befd | 1513 | /* Number of packets received and timestamped */ |
05a9320f | 1514 | #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 |
f2b0befd | 1515 | /* Number of packets timestamped by the FPGA */ |
05a9320f | 1516 | #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 |
f2b0befd | 1517 | /* Number of packets filter matched */ |
05a9320f | 1518 | #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 |
f2b0befd | 1519 | /* Number of packets not filter matched */ |
05a9320f | 1520 | #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 |
f2b0befd | 1521 | /* Number of PPS overflows (noise on input?) */ |
05a9320f | 1522 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 |
f2b0befd | 1523 | /* Number of PPS bad periods */ |
05a9320f | 1524 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 |
512bb06c | 1525 | /* Minimum period of PPS pulse in nanoseconds */ |
05a9320f | 1526 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 |
512bb06c | 1527 | /* Maximum period of PPS pulse in nanoseconds */ |
05a9320f | 1528 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 |
512bb06c | 1529 | /* Last period of PPS pulse in nanoseconds */ |
05a9320f | 1530 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 |
512bb06c | 1531 | /* Mean period of PPS pulse in nanoseconds */ |
05a9320f | 1532 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 |
512bb06c | 1533 | /* Minimum offset of PPS pulse in nanoseconds (signed) */ |
05a9320f | 1534 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 |
512bb06c | 1535 | /* Maximum offset of PPS pulse in nanoseconds (signed) */ |
05a9320f | 1536 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 |
512bb06c | 1537 | /* Last offset of PPS pulse in nanoseconds (signed) */ |
05a9320f | 1538 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 |
512bb06c | 1539 | /* Mean offset of PPS pulse in nanoseconds (signed) */ |
05a9320f BH |
1540 | #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 |
1541 | ||
1542 | /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ | |
1543 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 | |
1544 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 | |
1545 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) | |
f2b0befd | 1546 | /* A set of host and NIC times */ |
05a9320f BH |
1547 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 |
1548 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 | |
1549 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 | |
1550 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 | |
f2b0befd | 1551 | /* Host time immediately before NIC's hardware clock read */ |
05a9320f | 1552 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 |
f2b0befd | 1553 | /* Value of seconds timestamp */ |
05a9320f | 1554 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 |
512bb06c BH |
1555 | /* Timestamp major value */ |
1556 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 | |
f2b0befd | 1557 | /* Value of nanoseconds timestamp */ |
05a9320f | 1558 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 |
512bb06c BH |
1559 | /* Timestamp minor value */ |
1560 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 | |
f2b0befd | 1561 | /* Host time immediately after NIC's hardware clock read */ |
05a9320f | 1562 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 |
f2b0befd | 1563 | /* Number of nanoseconds waited after reading NIC's hardware clock */ |
05a9320f BH |
1564 | #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 |
1565 | ||
1566 | /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ | |
1567 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 | |
f2b0befd | 1568 | /* Results of testing */ |
05a9320f | 1569 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 |
f2b0befd BH |
1570 | /* enum: Successful test */ |
1571 | #define MC_CMD_PTP_MANF_SUCCESS 0x0 | |
1572 | /* enum: FPGA load failed */ | |
1573 | #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 | |
1574 | /* enum: FPGA version invalid */ | |
1575 | #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 | |
1576 | /* enum: FPGA registers incorrect */ | |
1577 | #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 | |
1578 | /* enum: Oscillator possibly not working? */ | |
1579 | #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 | |
1580 | /* enum: Timestamps not increasing */ | |
1581 | #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 | |
1582 | /* enum: Mismatched packet count */ | |
1583 | #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 | |
1584 | /* enum: Mismatched packet count (Siena filter and FPGA) */ | |
1585 | #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 | |
1586 | /* enum: Not enough packets to perform timestamp check */ | |
1587 | #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 | |
1588 | /* enum: Timestamp trigger GPIO not working */ | |
1589 | #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 | |
512bb06c BH |
1590 | /* enum: Insufficient PPS events to perform checks */ |
1591 | #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa | |
1592 | /* enum: PPS time event period not sufficiently close to 1s. */ | |
1593 | #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb | |
1594 | /* enum: PPS time event nS reading not sufficiently close to zero. */ | |
1595 | #define MC_CMD_PTP_MANF_PPS_NS 0xc | |
1596 | /* enum: PTP peripheral registers incorrect */ | |
1597 | #define MC_CMD_PTP_MANF_REGISTERS 0xd | |
1598 | /* enum: Failed to read time from PTP peripheral */ | |
1599 | #define MC_CMD_PTP_MANF_CLOCK_READ 0xe | |
f2b0befd | 1600 | /* Presence of external oscillator */ |
05a9320f BH |
1601 | #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 |
1602 | ||
1603 | /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ | |
1604 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 | |
f2b0befd | 1605 | /* Results of testing */ |
05a9320f | 1606 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 |
f2b0befd | 1607 | /* Number of packets received by FPGA */ |
05a9320f | 1608 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 |
f2b0befd | 1609 | /* Number of packets received by Siena filters */ |
05a9320f BH |
1610 | #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 |
1611 | ||
f2b0befd BH |
1612 | /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ |
1613 | #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 | |
1614 | #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 | |
1615 | #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) | |
1616 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 | |
1617 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 | |
1618 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 | |
1619 | #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 | |
1620 | ||
512bb06c BH |
1621 | /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ |
1622 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 | |
1623 | /* Time format required/used by for this NIC. Applies to all PTP MCDI | |
1624 | * operations that pass times between the host and firmware. If this operation | |
1625 | * is not supported (older firmware) a format of seconds and nanoseconds should | |
1626 | * be assumed. | |
1627 | */ | |
1628 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 | |
1629 | /* enum: Times are in seconds and nanoseconds */ | |
1630 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 | |
1631 | /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ | |
1632 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 | |
1633 | /* enum: Major register has units of seconds, minor 2^-27s per tick */ | |
1634 | #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 | |
1635 | ||
1636 | /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ | |
a9196bb0 | 1637 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 |
512bb06c BH |
1638 | /* Time format required/used by for this NIC. Applies to all PTP MCDI |
1639 | * operations that pass times between the host and firmware. If this operation | |
1640 | * is not supported (older firmware) a format of seconds and nanoseconds should | |
1641 | * be assumed. | |
1642 | */ | |
1643 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 | |
1644 | /* enum: Times are in seconds and nanoseconds */ | |
1645 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 | |
1646 | /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ | |
1647 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 | |
1648 | /* enum: Major register has units of seconds, minor 2^-27s per tick */ | |
1649 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 | |
1650 | /* Minimum acceptable value for a corrected synchronization timeset. When | |
1651 | * comparing host and NIC clock times, the MC returns a set of samples that | |
1652 | * contain the host start and end time, the MC time when the host start was | |
1653 | * detected and the time the MC waited between reading the time and detecting | |
1654 | * the host end. The corrected sync window is the difference between the host | |
1655 | * end and start times minus the time that the MC waited for host end. | |
1656 | */ | |
1657 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 | |
a9196bb0 EC |
1658 | /* Various PTP capabilities */ |
1659 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 | |
1660 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 | |
1661 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 | |
1662 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 | |
1663 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 | |
1664 | #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 | |
512bb06c BH |
1665 | |
1666 | /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ | |
1667 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 | |
23e202b4 | 1668 | /* Uncorrected error on PTP transmit timestamps in NIC clock format */ |
512bb06c | 1669 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 |
23e202b4 | 1670 | /* Uncorrected error on PTP receive timestamps in NIC clock format */ |
512bb06c BH |
1671 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 |
1672 | /* Uncorrected error on PPS output in NIC clock format */ | |
1673 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 | |
1674 | /* Uncorrected error on PPS input in NIC clock format */ | |
1675 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 | |
1676 | ||
23e202b4 EC |
1677 | /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ |
1678 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 | |
1679 | /* Uncorrected error on PTP transmit timestamps in NIC clock format */ | |
1680 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 | |
1681 | /* Uncorrected error on PTP receive timestamps in NIC clock format */ | |
1682 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 | |
1683 | /* Uncorrected error on PPS output in NIC clock format */ | |
1684 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 | |
1685 | /* Uncorrected error on PPS input in NIC clock format */ | |
1686 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 | |
1687 | /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ | |
1688 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 | |
1689 | /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ | |
1690 | #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 | |
1691 | ||
512bb06c BH |
1692 | /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ |
1693 | #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 | |
1694 | /* Results of testing */ | |
1695 | #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 | |
1696 | /* Enum values, see field(s): */ | |
1697 | /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ | |
1698 | ||
a9196bb0 EC |
1699 | /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ |
1700 | #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 | |
1701 | ||
05a9320f BH |
1702 | |
1703 | /***********************************/ | |
1704 | /* MC_CMD_CSR_READ32 | |
1705 | * Read 32bit words from the indirect memory map. | |
1706 | */ | |
1707 | #define MC_CMD_CSR_READ32 0xc | |
1708 | ||
75122ec8 SS |
1709 | #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1710 | ||
05a9320f BH |
1711 | /* MC_CMD_CSR_READ32_IN msgrequest */ |
1712 | #define MC_CMD_CSR_READ32_IN_LEN 12 | |
f2b0befd | 1713 | /* Address */ |
05a9320f BH |
1714 | #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 |
1715 | #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 | |
1716 | #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 | |
1717 | ||
1718 | /* MC_CMD_CSR_READ32_OUT msgresponse */ | |
1719 | #define MC_CMD_CSR_READ32_OUT_LENMIN 4 | |
1720 | #define MC_CMD_CSR_READ32_OUT_LENMAX 252 | |
1721 | #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 1722 | /* The last dword is the status, not a value read */ |
05a9320f BH |
1723 | #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 |
1724 | #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 | |
1725 | #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 | |
1726 | #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 | |
1727 | ||
1728 | ||
1729 | /***********************************/ | |
1730 | /* MC_CMD_CSR_WRITE32 | |
1731 | * Write 32bit dwords to the indirect memory map. | |
1732 | */ | |
1733 | #define MC_CMD_CSR_WRITE32 0xd | |
1734 | ||
75122ec8 SS |
1735 | #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1736 | ||
05a9320f BH |
1737 | /* MC_CMD_CSR_WRITE32_IN msgrequest */ |
1738 | #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 | |
1739 | #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 | |
1740 | #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) | |
f2b0befd | 1741 | /* Address */ |
05a9320f BH |
1742 | #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 |
1743 | #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 | |
1744 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 | |
1745 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 | |
1746 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 | |
1747 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 | |
1748 | ||
1749 | /* MC_CMD_CSR_WRITE32_OUT msgresponse */ | |
1750 | #define MC_CMD_CSR_WRITE32_OUT_LEN 4 | |
1751 | #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 | |
1752 | ||
1753 | ||
f2b0befd BH |
1754 | /***********************************/ |
1755 | /* MC_CMD_HP | |
1756 | * These commands are used for HP related features. They are grouped under one | |
1757 | * MCDI command to avoid creating too many MCDI commands. | |
1758 | */ | |
1759 | #define MC_CMD_HP 0x54 | |
1760 | ||
75122ec8 SS |
1761 | #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1762 | ||
f2b0befd BH |
1763 | /* MC_CMD_HP_IN msgrequest */ |
1764 | #define MC_CMD_HP_IN_LEN 16 | |
1765 | /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at | |
1766 | * the specified address with the specified interval.When address is NULL, | |
1767 | * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current | |
1768 | * state / 2: (debug) Show temperature reported by one of the supported | |
1769 | * sensors. | |
1770 | */ | |
1771 | #define MC_CMD_HP_IN_SUBCMD_OFST 0 | |
1772 | /* enum: OCSD (Option Card Sensor Data) sub-command. */ | |
1773 | #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 | |
1774 | /* enum: Last known valid HP sub-command. */ | |
1775 | #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 | |
1776 | /* The address to the array of sensor fields. (Or NULL to use a sub-command.) | |
1777 | */ | |
1778 | #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 | |
1779 | #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 | |
1780 | #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 | |
1781 | #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 | |
1782 | /* The requested update interval, in seconds. (Or the sub-command if ADDR is | |
1783 | * NULL.) | |
1784 | */ | |
1785 | #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 | |
1786 | ||
1787 | /* MC_CMD_HP_OUT msgresponse */ | |
1788 | #define MC_CMD_HP_OUT_LEN 4 | |
1789 | #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 | |
1790 | /* enum: OCSD stopped for this card. */ | |
1791 | #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 | |
1792 | /* enum: OCSD was successfully started with the address provided. */ | |
1793 | #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 | |
1794 | /* enum: OCSD was already started for this card. */ | |
1795 | #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 | |
1796 | ||
1797 | ||
05a9320f BH |
1798 | /***********************************/ |
1799 | /* MC_CMD_STACKINFO | |
1800 | * Get stack information. | |
1801 | */ | |
1802 | #define MC_CMD_STACKINFO 0xf | |
1803 | ||
75122ec8 SS |
1804 | #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1805 | ||
05a9320f BH |
1806 | /* MC_CMD_STACKINFO_IN msgrequest */ |
1807 | #define MC_CMD_STACKINFO_IN_LEN 0 | |
1808 | ||
1809 | /* MC_CMD_STACKINFO_OUT msgresponse */ | |
1810 | #define MC_CMD_STACKINFO_OUT_LENMIN 12 | |
1811 | #define MC_CMD_STACKINFO_OUT_LENMAX 252 | |
1812 | #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) | |
f2b0befd | 1813 | /* (thread ptr, stack size, free space) for each thread in system */ |
05a9320f BH |
1814 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 |
1815 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 | |
1816 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 | |
1817 | #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 | |
1818 | ||
1819 | ||
1820 | /***********************************/ | |
1821 | /* MC_CMD_MDIO_READ | |
1822 | * MDIO register read. | |
f0d37f42 SH |
1823 | */ |
1824 | #define MC_CMD_MDIO_READ 0x10 | |
f0d37f42 | 1825 | |
75122ec8 SS |
1826 | #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
1827 | ||
05a9320f BH |
1828 | /* MC_CMD_MDIO_READ_IN msgrequest */ |
1829 | #define MC_CMD_MDIO_READ_IN_LEN 16 | |
f2b0befd BH |
1830 | /* Bus number; there are two MDIO buses: one for the internal PHY, and one for |
1831 | * external devices. | |
1832 | */ | |
05a9320f | 1833 | #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 |
f2b0befd BH |
1834 | /* enum: Internal. */ |
1835 | #define MC_CMD_MDIO_BUS_INTERNAL 0x0 | |
1836 | /* enum: External. */ | |
1837 | #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 | |
1838 | /* Port address */ | |
05a9320f | 1839 | #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 |
f2b0befd | 1840 | /* Device Address or clause 22. */ |
05a9320f | 1841 | #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 |
f2b0befd BH |
1842 | /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you |
1843 | * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. | |
1844 | */ | |
1845 | #define MC_CMD_MDIO_CLAUSE22 0x20 | |
1846 | /* Address */ | |
05a9320f | 1847 | #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 |
f0d37f42 | 1848 | |
05a9320f BH |
1849 | /* MC_CMD_MDIO_READ_OUT msgresponse */ |
1850 | #define MC_CMD_MDIO_READ_OUT_LEN 8 | |
f2b0befd | 1851 | /* Value */ |
05a9320f | 1852 | #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 |
f2b0befd BH |
1853 | /* Status the MDIO commands return the raw status bits from the MDIO block. A |
1854 | * "good" transaction should have the DONE bit set and all other bits clear. | |
1855 | */ | |
05a9320f | 1856 | #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 |
f2b0befd BH |
1857 | /* enum: Good. */ |
1858 | #define MC_CMD_MDIO_STATUS_GOOD 0x8 | |
f0d37f42 | 1859 | |
05a9320f BH |
1860 | |
1861 | /***********************************/ | |
1862 | /* MC_CMD_MDIO_WRITE | |
1863 | * MDIO register write. | |
f0d37f42 | 1864 | */ |
05a9320f | 1865 | #define MC_CMD_MDIO_WRITE 0x11 |
f0d37f42 | 1866 | |
75122ec8 SS |
1867 | #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1868 | ||
05a9320f BH |
1869 | /* MC_CMD_MDIO_WRITE_IN msgrequest */ |
1870 | #define MC_CMD_MDIO_WRITE_IN_LEN 20 | |
f2b0befd BH |
1871 | /* Bus number; there are two MDIO buses: one for the internal PHY, and one for |
1872 | * external devices. | |
1873 | */ | |
05a9320f | 1874 | #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 |
f2b0befd | 1875 | /* enum: Internal. */ |
05a9320f | 1876 | /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ |
f2b0befd | 1877 | /* enum: External. */ |
05a9320f | 1878 | /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ |
f2b0befd | 1879 | /* Port address */ |
05a9320f | 1880 | #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 |
f2b0befd | 1881 | /* Device Address or clause 22. */ |
05a9320f | 1882 | #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 |
f2b0befd BH |
1883 | /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you |
1884 | * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. | |
1885 | */ | |
05a9320f | 1886 | /* MC_CMD_MDIO_CLAUSE22 0x20 */ |
f2b0befd | 1887 | /* Address */ |
05a9320f | 1888 | #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 |
f2b0befd | 1889 | /* Value */ |
05a9320f | 1890 | #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 |
f0d37f42 | 1891 | |
05a9320f BH |
1892 | /* MC_CMD_MDIO_WRITE_OUT msgresponse */ |
1893 | #define MC_CMD_MDIO_WRITE_OUT_LEN 4 | |
f2b0befd BH |
1894 | /* Status; the MDIO commands return the raw status bits from the MDIO block. A |
1895 | * "good" transaction should have the DONE bit set and all other bits clear. | |
1896 | */ | |
05a9320f | 1897 | #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 |
f2b0befd | 1898 | /* enum: Good. */ |
05a9320f BH |
1899 | /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ |
1900 | ||
1901 | ||
1902 | /***********************************/ | |
1903 | /* MC_CMD_DBI_WRITE | |
1904 | * Write DBI register(s). | |
f0d37f42 SH |
1905 | */ |
1906 | #define MC_CMD_DBI_WRITE 0x12 | |
05a9320f | 1907 | |
75122ec8 SS |
1908 | #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
1909 | ||
05a9320f BH |
1910 | /* MC_CMD_DBI_WRITE_IN msgrequest */ |
1911 | #define MC_CMD_DBI_WRITE_IN_LENMIN 12 | |
1912 | #define MC_CMD_DBI_WRITE_IN_LENMAX 252 | |
1913 | #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) | |
f2b0befd BH |
1914 | /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset |
1915 | * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. | |
1916 | */ | |
05a9320f BH |
1917 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 |
1918 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 | |
1919 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 | |
1920 | #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 | |
1921 | ||
1922 | /* MC_CMD_DBI_WRITE_OUT msgresponse */ | |
1923 | #define MC_CMD_DBI_WRITE_OUT_LEN 0 | |
1924 | ||
1925 | /* MC_CMD_DBIWROP_TYPEDEF structuredef */ | |
1926 | #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 | |
1927 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 | |
1928 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 | |
1929 | #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 | |
f2b0befd BH |
1930 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 |
1931 | #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 | |
1932 | #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 | |
1933 | #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 | |
1934 | #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 | |
1935 | #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 | |
1936 | #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 | |
1937 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 | |
1938 | #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 | |
05a9320f BH |
1939 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 |
1940 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 | |
1941 | #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 | |
1942 | ||
1943 | ||
1944 | /***********************************/ | |
1945 | /* MC_CMD_PORT_READ32 | |
f2b0befd BH |
1946 | * Read a 32-bit register from the indirect port register map. The port to |
1947 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1948 | */ |
1949 | #define MC_CMD_PORT_READ32 0x14 | |
f0d37f42 | 1950 | |
05a9320f BH |
1951 | /* MC_CMD_PORT_READ32_IN msgrequest */ |
1952 | #define MC_CMD_PORT_READ32_IN_LEN 4 | |
f2b0befd | 1953 | /* Address */ |
05a9320f BH |
1954 | #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 |
1955 | ||
1956 | /* MC_CMD_PORT_READ32_OUT msgresponse */ | |
1957 | #define MC_CMD_PORT_READ32_OUT_LEN 8 | |
f2b0befd | 1958 | /* Value */ |
05a9320f | 1959 | #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 |
f2b0befd | 1960 | /* Status */ |
05a9320f BH |
1961 | #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 |
1962 | ||
1963 | ||
1964 | /***********************************/ | |
1965 | /* MC_CMD_PORT_WRITE32 | |
f2b0befd BH |
1966 | * Write a 32-bit register to the indirect port register map. The port to |
1967 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1968 | */ |
1969 | #define MC_CMD_PORT_WRITE32 0x15 | |
05a9320f BH |
1970 | |
1971 | /* MC_CMD_PORT_WRITE32_IN msgrequest */ | |
1972 | #define MC_CMD_PORT_WRITE32_IN_LEN 8 | |
f2b0befd | 1973 | /* Address */ |
05a9320f | 1974 | #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 |
f2b0befd | 1975 | /* Value */ |
05a9320f BH |
1976 | #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 |
1977 | ||
1978 | /* MC_CMD_PORT_WRITE32_OUT msgresponse */ | |
1979 | #define MC_CMD_PORT_WRITE32_OUT_LEN 4 | |
f2b0befd | 1980 | /* Status */ |
05a9320f BH |
1981 | #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 |
1982 | ||
1983 | ||
1984 | /***********************************/ | |
1985 | /* MC_CMD_PORT_READ128 | |
f2b0befd BH |
1986 | * Read a 128-bit register from the indirect port register map. The port to |
1987 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
1988 | */ |
1989 | #define MC_CMD_PORT_READ128 0x16 | |
05a9320f BH |
1990 | |
1991 | /* MC_CMD_PORT_READ128_IN msgrequest */ | |
1992 | #define MC_CMD_PORT_READ128_IN_LEN 4 | |
f2b0befd | 1993 | /* Address */ |
05a9320f BH |
1994 | #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 |
1995 | ||
1996 | /* MC_CMD_PORT_READ128_OUT msgresponse */ | |
1997 | #define MC_CMD_PORT_READ128_OUT_LEN 20 | |
f2b0befd | 1998 | /* Value */ |
05a9320f BH |
1999 | #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 |
2000 | #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 | |
f2b0befd | 2001 | /* Status */ |
05a9320f BH |
2002 | #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 |
2003 | ||
2004 | ||
2005 | /***********************************/ | |
2006 | /* MC_CMD_PORT_WRITE128 | |
f2b0befd BH |
2007 | * Write a 128-bit register to the indirect port register map. The port to |
2008 | * access is implied by the Shared memory channel used. | |
f0d37f42 SH |
2009 | */ |
2010 | #define MC_CMD_PORT_WRITE128 0x17 | |
05a9320f BH |
2011 | |
2012 | /* MC_CMD_PORT_WRITE128_IN msgrequest */ | |
2013 | #define MC_CMD_PORT_WRITE128_IN_LEN 20 | |
f2b0befd | 2014 | /* Address */ |
05a9320f | 2015 | #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 |
f2b0befd | 2016 | /* Value */ |
05a9320f BH |
2017 | #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 |
2018 | #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 | |
2019 | ||
2020 | /* MC_CMD_PORT_WRITE128_OUT msgresponse */ | |
2021 | #define MC_CMD_PORT_WRITE128_OUT_LEN 4 | |
f2b0befd | 2022 | /* Status */ |
05a9320f BH |
2023 | #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 |
2024 | ||
f2b0befd BH |
2025 | /* MC_CMD_CAPABILITIES structuredef */ |
2026 | #define MC_CMD_CAPABILITIES_LEN 4 | |
2027 | /* Small buf table. */ | |
2028 | #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 | |
2029 | #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 | |
2030 | /* Turbo mode (for Maranello). */ | |
2031 | #define MC_CMD_CAPABILITIES_TURBO_LBN 1 | |
2032 | #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 | |
2033 | /* Turbo mode active (for Maranello). */ | |
2034 | #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 | |
2035 | #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 | |
2036 | /* PTP offload. */ | |
2037 | #define MC_CMD_CAPABILITIES_PTP_LBN 3 | |
2038 | #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 | |
2039 | /* AOE mode. */ | |
2040 | #define MC_CMD_CAPABILITIES_AOE_LBN 4 | |
2041 | #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 | |
2042 | /* AOE mode active. */ | |
2043 | #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 | |
2044 | #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 | |
2045 | /* AOE mode active. */ | |
2046 | #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 | |
2047 | #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 | |
2048 | #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 | |
2049 | #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 | |
2050 | ||
05a9320f BH |
2051 | |
2052 | /***********************************/ | |
2053 | /* MC_CMD_GET_BOARD_CFG | |
2054 | * Returns the MC firmware configuration structure. | |
f0d37f42 SH |
2055 | */ |
2056 | #define MC_CMD_GET_BOARD_CFG 0x18 | |
05a9320f | 2057 | |
75122ec8 SS |
2058 | #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2059 | ||
05a9320f BH |
2060 | /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ |
2061 | #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 | |
2062 | ||
2063 | /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ | |
2064 | #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 | |
2065 | #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 | |
2066 | #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) | |
2067 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 | |
2068 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 | |
2069 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 | |
f2b0befd | 2070 | /* See MC_CMD_CAPABILITIES */ |
05a9320f | 2071 | #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 |
f2b0befd | 2072 | /* See MC_CMD_CAPABILITIES */ |
05a9320f | 2073 | #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 |
05a9320f BH |
2074 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 |
2075 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 | |
2076 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 | |
2077 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 | |
2078 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 | |
2079 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 | |
2080 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 | |
2081 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 | |
f2b0befd BH |
2082 | /* This field contains a 16-bit value for each of the types of NVRAM area. The |
2083 | * values are defined in the firmware/mc/platform/.c file for a specific board | |
2084 | * type, but otherwise have no meaning to the MC; they are used by the driver | |
2085 | * to manage selection of appropriate firmware updates. | |
2086 | */ | |
05a9320f BH |
2087 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 |
2088 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 | |
2089 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 | |
2090 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 | |
2091 | ||
2092 | ||
2093 | /***********************************/ | |
2094 | /* MC_CMD_DBI_READX | |
f2b0befd | 2095 | * Read DBI register(s) -- extended functionality |
f0d37f42 SH |
2096 | */ |
2097 | #define MC_CMD_DBI_READX 0x19 | |
f0d37f42 | 2098 | |
75122ec8 SS |
2099 | #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
2100 | ||
05a9320f BH |
2101 | /* MC_CMD_DBI_READX_IN msgrequest */ |
2102 | #define MC_CMD_DBI_READX_IN_LENMIN 8 | |
2103 | #define MC_CMD_DBI_READX_IN_LENMAX 248 | |
2104 | #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) | |
f2b0befd | 2105 | /* Each Read op consists of an address (offset 0), VF/CS2) */ |
05a9320f BH |
2106 | #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 |
2107 | #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 | |
2108 | #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 | |
2109 | #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 | |
2110 | #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 | |
2111 | #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 | |
2112 | ||
2113 | /* MC_CMD_DBI_READX_OUT msgresponse */ | |
2114 | #define MC_CMD_DBI_READX_OUT_LENMIN 4 | |
2115 | #define MC_CMD_DBI_READX_OUT_LENMAX 252 | |
2116 | #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 2117 | /* Value */ |
05a9320f BH |
2118 | #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 |
2119 | #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 | |
2120 | #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 | |
2121 | #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 | |
2122 | ||
f2b0befd BH |
2123 | /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ |
2124 | #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 | |
2125 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 | |
2126 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 | |
2127 | #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 | |
2128 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 | |
2129 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 | |
2130 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 | |
2131 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 | |
2132 | #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 | |
2133 | #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 | |
2134 | #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 | |
2135 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 | |
2136 | #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 | |
2137 | ||
05a9320f BH |
2138 | |
2139 | /***********************************/ | |
2140 | /* MC_CMD_SET_RAND_SEED | |
2141 | * Set the 16byte seed for the MC pseudo-random generator. | |
f0d37f42 SH |
2142 | */ |
2143 | #define MC_CMD_SET_RAND_SEED 0x1a | |
f0d37f42 | 2144 | |
75122ec8 SS |
2145 | #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
2146 | ||
05a9320f BH |
2147 | /* MC_CMD_SET_RAND_SEED_IN msgrequest */ |
2148 | #define MC_CMD_SET_RAND_SEED_IN_LEN 16 | |
f2b0befd | 2149 | /* Seed value. */ |
05a9320f BH |
2150 | #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 |
2151 | #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 | |
2152 | ||
2153 | /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ | |
2154 | #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 | |
2155 | ||
2156 | ||
2157 | /***********************************/ | |
2158 | /* MC_CMD_LTSSM_HIST | |
f2b0befd | 2159 | * Retrieve the history of the LTSSM, if the build supports it. |
f0d37f42 SH |
2160 | */ |
2161 | #define MC_CMD_LTSSM_HIST 0x1b | |
2162 | ||
05a9320f BH |
2163 | /* MC_CMD_LTSSM_HIST_IN msgrequest */ |
2164 | #define MC_CMD_LTSSM_HIST_IN_LEN 0 | |
2165 | ||
2166 | /* MC_CMD_LTSSM_HIST_OUT msgresponse */ | |
2167 | #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 | |
2168 | #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 | |
2169 | #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) | |
f2b0befd | 2170 | /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ |
05a9320f BH |
2171 | #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 |
2172 | #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 | |
2173 | #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 | |
2174 | #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 | |
2175 | ||
2176 | ||
2177 | /***********************************/ | |
2178 | /* MC_CMD_DRV_ATTACH | |
f2b0befd BH |
2179 | * Inform MCPU that this port is managed on the host (i.e. driver active). For |
2180 | * Huntington, also request the preferred datapath firmware to use if possible | |
2181 | * (it may not be possible for this request to be fulfilled; the driver must | |
2182 | * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which | |
2183 | * features are actually available). The FIRMWARE_ID field is ignored by older | |
2184 | * platforms. | |
f0d37f42 SH |
2185 | */ |
2186 | #define MC_CMD_DRV_ATTACH 0x1c | |
f0d37f42 | 2187 | |
75122ec8 SS |
2188 | #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2189 | ||
05a9320f | 2190 | /* MC_CMD_DRV_ATTACH_IN msgrequest */ |
f2b0befd | 2191 | #define MC_CMD_DRV_ATTACH_IN_LEN 12 |
23e202b4 | 2192 | /* new state to set if UPDATE=1 */ |
05a9320f | 2193 | #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 |
23e202b4 EC |
2194 | #define MC_CMD_DRV_ATTACH_LBN 0 |
2195 | #define MC_CMD_DRV_ATTACH_WIDTH 1 | |
2196 | #define MC_CMD_DRV_PREBOOT_LBN 1 | |
2197 | #define MC_CMD_DRV_PREBOOT_WIDTH 1 | |
f2b0befd | 2198 | /* 1 to set new state, or 0 to just report the existing state */ |
05a9320f | 2199 | #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 |
f2b0befd BH |
2200 | /* preferred datapath firmware (for Huntington; ignored for Siena) */ |
2201 | #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 | |
2202 | /* enum: Prefer to use full featured firmware */ | |
2203 | #define MC_CMD_FW_FULL_FEATURED 0x0 | |
2204 | /* enum: Prefer to use firmware with fewer features but lower latency */ | |
2205 | #define MC_CMD_FW_LOW_LATENCY 0x1 | |
a9196bb0 EC |
2206 | /* enum: Prefer to use firmware for SolarCapture packed stream mode */ |
2207 | #define MC_CMD_FW_PACKED_STREAM 0x2 | |
2208 | /* enum: Prefer to use firmware with fewer features and simpler TX event | |
2209 | * batching but higher TX packet rate | |
2210 | */ | |
2211 | #define MC_CMD_FW_HIGH_TX_RATE 0x3 | |
2212 | /* enum: Reserved value */ | |
2213 | #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 | |
267d9d73 EC |
2214 | /* enum: Only this option is allowed for non-admin functions */ |
2215 | #define MC_CMD_FW_DONT_CARE 0xffffffff | |
05a9320f BH |
2216 | |
2217 | /* MC_CMD_DRV_ATTACH_OUT msgresponse */ | |
2218 | #define MC_CMD_DRV_ATTACH_OUT_LEN 4 | |
23e202b4 | 2219 | /* previous or existing state, see the bitmask at NEW_STATE */ |
05a9320f BH |
2220 | #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 |
2221 | ||
f2b0befd BH |
2222 | /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ |
2223 | #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 | |
23e202b4 | 2224 | /* previous or existing state, see the bitmask at NEW_STATE */ |
f2b0befd BH |
2225 | #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 |
2226 | /* Flags associated with this function */ | |
2227 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 | |
2228 | /* enum: Labels the lowest-numbered function visible to the OS */ | |
2229 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 | |
2230 | /* enum: The function can control the link state of the physical port it is | |
2231 | * bound to. | |
f0d37f42 | 2232 | */ |
f2b0befd BH |
2233 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 |
2234 | /* enum: The function can perform privileged operations */ | |
2235 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 | |
23e202b4 EC |
2236 | /* enum: The function does not have an active port associated with it. The port |
2237 | * refers to the Sorrento external FPGA port. | |
2238 | */ | |
2239 | #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 | |
05a9320f BH |
2240 | |
2241 | ||
2242 | /***********************************/ | |
2243 | /* MC_CMD_SHMUART | |
f0d37f42 SH |
2244 | * Route UART output to circular buffer in shared memory instead. |
2245 | */ | |
2246 | #define MC_CMD_SHMUART 0x1f | |
f0d37f42 | 2247 | |
05a9320f BH |
2248 | /* MC_CMD_SHMUART_IN msgrequest */ |
2249 | #define MC_CMD_SHMUART_IN_LEN 4 | |
f2b0befd | 2250 | /* ??? */ |
05a9320f BH |
2251 | #define MC_CMD_SHMUART_IN_FLAG_OFST 0 |
2252 | ||
2253 | /* MC_CMD_SHMUART_OUT msgresponse */ | |
2254 | #define MC_CMD_SHMUART_OUT_LEN 0 | |
2255 | ||
2256 | ||
f2b0befd BH |
2257 | /***********************************/ |
2258 | /* MC_CMD_PORT_RESET | |
2259 | * Generic per-port reset. There is no equivalent for per-board reset. Locks | |
2260 | * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - | |
2261 | * use MC_CMD_ENTITY_RESET instead. | |
2262 | */ | |
2263 | #define MC_CMD_PORT_RESET 0x20 | |
2264 | ||
75122ec8 SS |
2265 | #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2266 | ||
f2b0befd BH |
2267 | /* MC_CMD_PORT_RESET_IN msgrequest */ |
2268 | #define MC_CMD_PORT_RESET_IN_LEN 0 | |
2269 | ||
2270 | /* MC_CMD_PORT_RESET_OUT msgresponse */ | |
2271 | #define MC_CMD_PORT_RESET_OUT_LEN 0 | |
2272 | ||
2273 | ||
05a9320f BH |
2274 | /***********************************/ |
2275 | /* MC_CMD_ENTITY_RESET | |
f2b0befd BH |
2276 | * Generic per-resource reset. There is no equivalent for per-board reset. |
2277 | * Locks required: None; Return code: 0, ETIME. NOTE: This command is an | |
2278 | * extended version of the deprecated MC_CMD_PORT_RESET with added fields. | |
05a9320f BH |
2279 | */ |
2280 | #define MC_CMD_ENTITY_RESET 0x20 | |
75122ec8 | 2281 | /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ |
05a9320f BH |
2282 | |
2283 | /* MC_CMD_ENTITY_RESET_IN msgrequest */ | |
2284 | #define MC_CMD_ENTITY_RESET_IN_LEN 4 | |
f2b0befd BH |
2285 | /* Optional flags field. Omitting this will perform a "legacy" reset action |
2286 | * (TBD). | |
2287 | */ | |
05a9320f BH |
2288 | #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 |
2289 | #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 | |
2290 | #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 | |
2291 | ||
2292 | /* MC_CMD_ENTITY_RESET_OUT msgresponse */ | |
2293 | #define MC_CMD_ENTITY_RESET_OUT_LEN 0 | |
2294 | ||
2295 | ||
2296 | /***********************************/ | |
2297 | /* MC_CMD_PCIE_CREDITS | |
2298 | * Read instantaneous and minimum flow control thresholds. | |
2299 | */ | |
2300 | #define MC_CMD_PCIE_CREDITS 0x21 | |
2301 | ||
2302 | /* MC_CMD_PCIE_CREDITS_IN msgrequest */ | |
2303 | #define MC_CMD_PCIE_CREDITS_IN_LEN 8 | |
f2b0befd | 2304 | /* poll period. 0 is disabled */ |
05a9320f | 2305 | #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 |
f2b0befd | 2306 | /* wipe statistics */ |
05a9320f BH |
2307 | #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 |
2308 | ||
2309 | /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ | |
2310 | #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 | |
2311 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 | |
2312 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 | |
2313 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 | |
2314 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 | |
2315 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 | |
2316 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 | |
2317 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 | |
2318 | #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 | |
2319 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 | |
2320 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 | |
2321 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 | |
2322 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 | |
2323 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 | |
2324 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 | |
2325 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 | |
2326 | #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 | |
2327 | ||
2328 | ||
2329 | /***********************************/ | |
2330 | /* MC_CMD_RXD_MONITOR | |
2331 | * Get histogram of RX queue fill level. | |
2332 | */ | |
2333 | #define MC_CMD_RXD_MONITOR 0x22 | |
2334 | ||
2335 | /* MC_CMD_RXD_MONITOR_IN msgrequest */ | |
2336 | #define MC_CMD_RXD_MONITOR_IN_LEN 12 | |
2337 | #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 | |
2338 | #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 | |
2339 | #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 | |
2340 | ||
2341 | /* MC_CMD_RXD_MONITOR_OUT msgresponse */ | |
2342 | #define MC_CMD_RXD_MONITOR_OUT_LEN 80 | |
2343 | #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 | |
2344 | #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 | |
2345 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 | |
2346 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 | |
2347 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 | |
2348 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 | |
2349 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 | |
2350 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 | |
2351 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 | |
2352 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 | |
2353 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 | |
2354 | #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 | |
2355 | #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 | |
2356 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 | |
2357 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 | |
2358 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 | |
2359 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 | |
2360 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 | |
2361 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 | |
2362 | #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 | |
2363 | ||
2364 | ||
2365 | /***********************************/ | |
2366 | /* MC_CMD_PUTS | |
f2b0befd | 2367 | * Copy the given ASCII string out onto UART and/or out of the network port. |
05a9320f BH |
2368 | */ |
2369 | #define MC_CMD_PUTS 0x23 | |
2370 | ||
75122ec8 SS |
2371 | #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
2372 | ||
05a9320f BH |
2373 | /* MC_CMD_PUTS_IN msgrequest */ |
2374 | #define MC_CMD_PUTS_IN_LENMIN 13 | |
576eda8b | 2375 | #define MC_CMD_PUTS_IN_LENMAX 252 |
05a9320f BH |
2376 | #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) |
2377 | #define MC_CMD_PUTS_IN_DEST_OFST 0 | |
2378 | #define MC_CMD_PUTS_IN_UART_LBN 0 | |
2379 | #define MC_CMD_PUTS_IN_UART_WIDTH 1 | |
2380 | #define MC_CMD_PUTS_IN_PORT_LBN 1 | |
2381 | #define MC_CMD_PUTS_IN_PORT_WIDTH 1 | |
2382 | #define MC_CMD_PUTS_IN_DHOST_OFST 4 | |
2383 | #define MC_CMD_PUTS_IN_DHOST_LEN 6 | |
2384 | #define MC_CMD_PUTS_IN_STRING_OFST 12 | |
2385 | #define MC_CMD_PUTS_IN_STRING_LEN 1 | |
2386 | #define MC_CMD_PUTS_IN_STRING_MINNUM 1 | |
576eda8b | 2387 | #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 |
05a9320f BH |
2388 | |
2389 | /* MC_CMD_PUTS_OUT msgresponse */ | |
2390 | #define MC_CMD_PUTS_OUT_LEN 0 | |
2391 | ||
2392 | ||
2393 | /***********************************/ | |
2394 | /* MC_CMD_GET_PHY_CFG | |
f2b0befd BH |
2395 | * Report PHY configuration. This guarantees to succeed even if the PHY is in a |
2396 | * 'zombie' state. Locks required: None | |
f0d37f42 SH |
2397 | */ |
2398 | #define MC_CMD_GET_PHY_CFG 0x24 | |
2399 | ||
75122ec8 SS |
2400 | #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2401 | ||
05a9320f BH |
2402 | /* MC_CMD_GET_PHY_CFG_IN msgrequest */ |
2403 | #define MC_CMD_GET_PHY_CFG_IN_LEN 0 | |
2404 | ||
2405 | /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ | |
2406 | #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 | |
f2b0befd | 2407 | /* flags */ |
05a9320f BH |
2408 | #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 |
2409 | #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 | |
2410 | #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 | |
2411 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 | |
2412 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 | |
2413 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 | |
2414 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 | |
2415 | #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 | |
2416 | #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 | |
2417 | #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 | |
2418 | #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 | |
2419 | #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 | |
2420 | #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 | |
2421 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 | |
2422 | #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 | |
f2b0befd | 2423 | /* ?? */ |
05a9320f | 2424 | #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 |
f2b0befd | 2425 | /* Bitmask of supported capabilities */ |
05a9320f BH |
2426 | #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 |
2427 | #define MC_CMD_PHY_CAP_10HDX_LBN 1 | |
2428 | #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 | |
2429 | #define MC_CMD_PHY_CAP_10FDX_LBN 2 | |
2430 | #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 | |
2431 | #define MC_CMD_PHY_CAP_100HDX_LBN 3 | |
2432 | #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 | |
2433 | #define MC_CMD_PHY_CAP_100FDX_LBN 4 | |
2434 | #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 | |
2435 | #define MC_CMD_PHY_CAP_1000HDX_LBN 5 | |
2436 | #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 | |
2437 | #define MC_CMD_PHY_CAP_1000FDX_LBN 6 | |
2438 | #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 | |
2439 | #define MC_CMD_PHY_CAP_10000FDX_LBN 7 | |
2440 | #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 | |
2441 | #define MC_CMD_PHY_CAP_PAUSE_LBN 8 | |
2442 | #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 | |
2443 | #define MC_CMD_PHY_CAP_ASYM_LBN 9 | |
2444 | #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 | |
2445 | #define MC_CMD_PHY_CAP_AN_LBN 10 | |
2446 | #define MC_CMD_PHY_CAP_AN_WIDTH 1 | |
f2b0befd BH |
2447 | #define MC_CMD_PHY_CAP_40000FDX_LBN 11 |
2448 | #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 | |
2449 | #define MC_CMD_PHY_CAP_DDM_LBN 12 | |
2450 | #define MC_CMD_PHY_CAP_DDM_WIDTH 1 | |
2451 | /* ?? */ | |
05a9320f | 2452 | #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 |
f2b0befd | 2453 | /* ?? */ |
05a9320f | 2454 | #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 |
f2b0befd | 2455 | /* ?? */ |
05a9320f | 2456 | #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 |
f2b0befd | 2457 | /* ?? */ |
05a9320f BH |
2458 | #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 |
2459 | #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 | |
f2b0befd | 2460 | /* ?? */ |
05a9320f | 2461 | #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 |
f2b0befd BH |
2462 | /* enum: Xaui. */ |
2463 | #define MC_CMD_MEDIA_XAUI 0x1 | |
2464 | /* enum: CX4. */ | |
2465 | #define MC_CMD_MEDIA_CX4 0x2 | |
2466 | /* enum: KX4. */ | |
2467 | #define MC_CMD_MEDIA_KX4 0x3 | |
2468 | /* enum: XFP Far. */ | |
2469 | #define MC_CMD_MEDIA_XFP 0x4 | |
2470 | /* enum: SFP+. */ | |
2471 | #define MC_CMD_MEDIA_SFP_PLUS 0x5 | |
2472 | /* enum: 10GBaseT. */ | |
2473 | #define MC_CMD_MEDIA_BASE_T 0x6 | |
512bb06c BH |
2474 | /* enum: QSFP+. */ |
2475 | #define MC_CMD_MEDIA_QSFP_PLUS 0x7 | |
05a9320f | 2476 | #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 |
f2b0befd BH |
2477 | /* enum: Native clause 22 */ |
2478 | #define MC_CMD_MMD_CLAUSE22 0x0 | |
05a9320f BH |
2479 | #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ |
2480 | #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ | |
2481 | #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ | |
2482 | #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ | |
2483 | #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ | |
2484 | #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ | |
2485 | #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ | |
f2b0befd BH |
2486 | /* enum: Clause22 proxied over clause45 by PHY. */ |
2487 | #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d | |
05a9320f BH |
2488 | #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ |
2489 | #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ | |
2490 | #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 | |
2491 | #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 | |
2492 | ||
2493 | ||
2494 | /***********************************/ | |
2495 | /* MC_CMD_START_BIST | |
f2b0befd BH |
2496 | * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST |
2497 | * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) | |
f0d37f42 SH |
2498 | */ |
2499 | #define MC_CMD_START_BIST 0x25 | |
05a9320f | 2500 | |
75122ec8 SS |
2501 | #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
2502 | ||
05a9320f BH |
2503 | /* MC_CMD_START_BIST_IN msgrequest */ |
2504 | #define MC_CMD_START_BIST_IN_LEN 4 | |
f2b0befd | 2505 | /* Type of test. */ |
05a9320f | 2506 | #define MC_CMD_START_BIST_IN_TYPE_OFST 0 |
f2b0befd BH |
2507 | /* enum: Run the PHY's short cable BIST. */ |
2508 | #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 | |
2509 | /* enum: Run the PHY's long cable BIST. */ | |
2510 | #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 | |
2511 | /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ | |
2512 | #define MC_CMD_BPX_SERDES_BIST 0x3 | |
2513 | /* enum: Run the MC loopback tests. */ | |
2514 | #define MC_CMD_MC_LOOPBACK_BIST 0x4 | |
2515 | /* enum: Run the PHY's standard BIST. */ | |
2516 | #define MC_CMD_PHY_BIST 0x5 | |
2517 | /* enum: Run MC RAM test. */ | |
2518 | #define MC_CMD_MC_MEM_BIST 0x6 | |
2519 | /* enum: Run Port RAM test. */ | |
2520 | #define MC_CMD_PORT_MEM_BIST 0x7 | |
2521 | /* enum: Run register test. */ | |
2522 | #define MC_CMD_REG_BIST 0x8 | |
05a9320f BH |
2523 | |
2524 | /* MC_CMD_START_BIST_OUT msgresponse */ | |
2525 | #define MC_CMD_START_BIST_OUT_LEN 0 | |
2526 | ||
2527 | ||
2528 | /***********************************/ | |
2529 | /* MC_CMD_POLL_BIST | |
f2b0befd BH |
2530 | * Poll for BIST completion. Returns a single status code, and optionally some |
2531 | * PHY specific bist output. The driver should only consume the BIST output | |
2532 | * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't | |
2533 | * successfully parse the BIST output, it should still respect the pass/Fail in | |
2534 | * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, | |
2535 | * EACCES (if PHY_LOCK is not held). | |
f0d37f42 SH |
2536 | */ |
2537 | #define MC_CMD_POLL_BIST 0x26 | |
05a9320f | 2538 | |
75122ec8 SS |
2539 | #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
2540 | ||
05a9320f BH |
2541 | /* MC_CMD_POLL_BIST_IN msgrequest */ |
2542 | #define MC_CMD_POLL_BIST_IN_LEN 0 | |
2543 | ||
2544 | /* MC_CMD_POLL_BIST_OUT msgresponse */ | |
2545 | #define MC_CMD_POLL_BIST_OUT_LEN 8 | |
f2b0befd | 2546 | /* result */ |
05a9320f | 2547 | #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 |
f2b0befd BH |
2548 | /* enum: Running. */ |
2549 | #define MC_CMD_POLL_BIST_RUNNING 0x1 | |
2550 | /* enum: Passed. */ | |
2551 | #define MC_CMD_POLL_BIST_PASSED 0x2 | |
2552 | /* enum: Failed. */ | |
2553 | #define MC_CMD_POLL_BIST_FAILED 0x3 | |
2554 | /* enum: Timed-out. */ | |
2555 | #define MC_CMD_POLL_BIST_TIMEOUT 0x4 | |
05a9320f BH |
2556 | #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 |
2557 | ||
2558 | /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ | |
2559 | #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 | |
f2b0befd | 2560 | /* result */ |
05a9320f BH |
2561 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
2562 | /* Enum values, see field(s): */ | |
2563 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2564 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 | |
2565 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 | |
2566 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 | |
2567 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 | |
f2b0befd | 2568 | /* Status of each channel A */ |
05a9320f | 2569 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 |
f2b0befd BH |
2570 | /* enum: Ok. */ |
2571 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 | |
2572 | /* enum: Open. */ | |
2573 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 | |
2574 | /* enum: Intra-pair short. */ | |
2575 | #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 | |
2576 | /* enum: Inter-pair short. */ | |
2577 | #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 | |
2578 | /* enum: Busy. */ | |
2579 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 | |
2580 | /* Status of each channel B */ | |
05a9320f BH |
2581 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 |
2582 | /* Enum values, see field(s): */ | |
2583 | /* CABLE_STATUS_A */ | |
f2b0befd | 2584 | /* Status of each channel C */ |
05a9320f BH |
2585 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 |
2586 | /* Enum values, see field(s): */ | |
2587 | /* CABLE_STATUS_A */ | |
f2b0befd | 2588 | /* Status of each channel D */ |
05a9320f BH |
2589 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 |
2590 | /* Enum values, see field(s): */ | |
2591 | /* CABLE_STATUS_A */ | |
2592 | ||
2593 | /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ | |
2594 | #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 | |
f2b0befd | 2595 | /* result */ |
05a9320f BH |
2596 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
2597 | /* Enum values, see field(s): */ | |
2598 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2599 | #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 | |
f2b0befd BH |
2600 | /* enum: Complete. */ |
2601 | #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 | |
2602 | /* enum: Bus switch off I2C write. */ | |
2603 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 | |
2604 | /* enum: Bus switch off I2C no access IO exp. */ | |
2605 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 | |
2606 | /* enum: Bus switch off I2C no access module. */ | |
2607 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 | |
2608 | /* enum: IO exp I2C configure. */ | |
2609 | #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 | |
2610 | /* enum: Bus switch I2C no cross talk. */ | |
2611 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 | |
2612 | /* enum: Module presence. */ | |
2613 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 | |
2614 | /* enum: Module ID I2C access. */ | |
2615 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 | |
2616 | /* enum: Module ID sane value. */ | |
2617 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 | |
2618 | ||
2619 | /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ | |
2620 | #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 | |
2621 | /* result */ | |
2622 | /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ | |
2623 | /* Enum values, see field(s): */ | |
2624 | /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ | |
2625 | #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 | |
2626 | /* enum: Test has completed. */ | |
2627 | #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 | |
2628 | /* enum: RAM test - walk ones. */ | |
2629 | #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 | |
2630 | /* enum: RAM test - walk zeros. */ | |
2631 | #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 | |
2632 | /* enum: RAM test - walking inversions zeros/ones. */ | |
2633 | #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 | |
2634 | /* enum: RAM test - walking inversions checkerboard. */ | |
2635 | #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 | |
2636 | /* enum: Register test - set / clear individual bits. */ | |
2637 | #define MC_CMD_POLL_BIST_MEM_REG 0x5 | |
2638 | /* enum: ECC error detected. */ | |
2639 | #define MC_CMD_POLL_BIST_MEM_ECC 0x6 | |
2640 | /* Failure address, only valid if result is POLL_BIST_FAILED */ | |
2641 | #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 | |
2642 | /* Bus or address space to which the failure address corresponds */ | |
2643 | #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 | |
2644 | /* enum: MC MIPS bus. */ | |
2645 | #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 | |
2646 | /* enum: CSR IREG bus. */ | |
2647 | #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 | |
d29e33d6 | 2648 | /* enum: RX0 DPCPU bus. */ |
f2b0befd BH |
2649 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 |
2650 | /* enum: TX0 DPCPU bus. */ | |
2651 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 | |
2652 | /* enum: TX1 DPCPU bus. */ | |
2653 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 | |
d29e33d6 | 2654 | /* enum: RX0 DICPU bus. */ |
f2b0befd BH |
2655 | #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 |
2656 | /* enum: TX DICPU bus. */ | |
2657 | #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 | |
d29e33d6 BK |
2658 | /* enum: RX1 DPCPU bus. */ |
2659 | #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 | |
2660 | /* enum: RX1 DICPU bus. */ | |
2661 | #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 | |
f2b0befd BH |
2662 | /* Pattern written to RAM / register */ |
2663 | #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 | |
2664 | /* Actual value read from RAM / register */ | |
2665 | #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 | |
2666 | /* ECC error mask */ | |
2667 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 | |
2668 | /* ECC parity error mask */ | |
2669 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 | |
2670 | /* ECC fatal error mask */ | |
2671 | #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 | |
05a9320f BH |
2672 | |
2673 | ||
2674 | /***********************************/ | |
2675 | /* MC_CMD_FLUSH_RX_QUEUES | |
f2b0befd BH |
2676 | * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ |
2677 | * flushes should be initiated via this MCDI operation, rather than via | |
2678 | * directly writing FLUSH_CMD. | |
2679 | * | |
2680 | * The flush is completed (either done/fail) asynchronously (after this command | |
2681 | * returns). The driver must still wait for flush done/failure events as usual. | |
05a9320f BH |
2682 | */ |
2683 | #define MC_CMD_FLUSH_RX_QUEUES 0x27 | |
2684 | ||
2685 | /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ | |
2686 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 | |
2687 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 | |
2688 | #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) | |
2689 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 | |
2690 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 | |
2691 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 | |
2692 | #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 | |
2693 | ||
2694 | /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ | |
2695 | #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 | |
2696 | ||
2697 | ||
2698 | /***********************************/ | |
2699 | /* MC_CMD_GET_LOOPBACK_MODES | |
f2b0befd | 2700 | * Returns a bitmask of loopback modes available at each speed. |
f0d37f42 SH |
2701 | */ |
2702 | #define MC_CMD_GET_LOOPBACK_MODES 0x28 | |
05a9320f | 2703 | |
75122ec8 SS |
2704 | #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2705 | ||
05a9320f BH |
2706 | /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ |
2707 | #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 | |
2708 | ||
2709 | /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ | |
f2b0befd BH |
2710 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 |
2711 | /* Supported loopbacks. */ | |
05a9320f BH |
2712 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 |
2713 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 | |
2714 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 | |
2715 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 | |
f2b0befd BH |
2716 | /* enum: None. */ |
2717 | #define MC_CMD_LOOPBACK_NONE 0x0 | |
2718 | /* enum: Data. */ | |
2719 | #define MC_CMD_LOOPBACK_DATA 0x1 | |
2720 | /* enum: GMAC. */ | |
2721 | #define MC_CMD_LOOPBACK_GMAC 0x2 | |
2722 | /* enum: XGMII. */ | |
2723 | #define MC_CMD_LOOPBACK_XGMII 0x3 | |
2724 | /* enum: XGXS. */ | |
2725 | #define MC_CMD_LOOPBACK_XGXS 0x4 | |
2726 | /* enum: XAUI. */ | |
2727 | #define MC_CMD_LOOPBACK_XAUI 0x5 | |
2728 | /* enum: GMII. */ | |
2729 | #define MC_CMD_LOOPBACK_GMII 0x6 | |
2730 | /* enum: SGMII. */ | |
2731 | #define MC_CMD_LOOPBACK_SGMII 0x7 | |
2732 | /* enum: XGBR. */ | |
2733 | #define MC_CMD_LOOPBACK_XGBR 0x8 | |
2734 | /* enum: XFI. */ | |
2735 | #define MC_CMD_LOOPBACK_XFI 0x9 | |
2736 | /* enum: XAUI Far. */ | |
2737 | #define MC_CMD_LOOPBACK_XAUI_FAR 0xa | |
2738 | /* enum: GMII Far. */ | |
2739 | #define MC_CMD_LOOPBACK_GMII_FAR 0xb | |
2740 | /* enum: SGMII Far. */ | |
2741 | #define MC_CMD_LOOPBACK_SGMII_FAR 0xc | |
2742 | /* enum: XFI Far. */ | |
2743 | #define MC_CMD_LOOPBACK_XFI_FAR 0xd | |
2744 | /* enum: GPhy. */ | |
2745 | #define MC_CMD_LOOPBACK_GPHY 0xe | |
2746 | /* enum: PhyXS. */ | |
2747 | #define MC_CMD_LOOPBACK_PHYXS 0xf | |
2748 | /* enum: PCS. */ | |
2749 | #define MC_CMD_LOOPBACK_PCS 0x10 | |
2750 | /* enum: PMA-PMD. */ | |
2751 | #define MC_CMD_LOOPBACK_PMAPMD 0x11 | |
2752 | /* enum: Cross-Port. */ | |
2753 | #define MC_CMD_LOOPBACK_XPORT 0x12 | |
2754 | /* enum: XGMII-Wireside. */ | |
2755 | #define MC_CMD_LOOPBACK_XGMII_WS 0x13 | |
2756 | /* enum: XAUI Wireside. */ | |
2757 | #define MC_CMD_LOOPBACK_XAUI_WS 0x14 | |
2758 | /* enum: XAUI Wireside Far. */ | |
2759 | #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 | |
2760 | /* enum: XAUI Wireside near. */ | |
2761 | #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 | |
2762 | /* enum: GMII Wireside. */ | |
2763 | #define MC_CMD_LOOPBACK_GMII_WS 0x17 | |
2764 | /* enum: XFI Wireside. */ | |
2765 | #define MC_CMD_LOOPBACK_XFI_WS 0x18 | |
2766 | /* enum: XFI Wireside Far. */ | |
2767 | #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 | |
2768 | /* enum: PhyXS Wireside. */ | |
2769 | #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a | |
2770 | /* enum: PMA lanes MAC-Serdes. */ | |
2771 | #define MC_CMD_LOOPBACK_PMA_INT 0x1b | |
2772 | /* enum: KR Serdes Parallel (Encoder). */ | |
2773 | #define MC_CMD_LOOPBACK_SD_NEAR 0x1c | |
2774 | /* enum: KR Serdes Serial. */ | |
2775 | #define MC_CMD_LOOPBACK_SD_FAR 0x1d | |
2776 | /* enum: PMA lanes MAC-Serdes Wireside. */ | |
2777 | #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e | |
2778 | /* enum: KR Serdes Parallel Wireside (Full PCS). */ | |
2779 | #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f | |
2780 | /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ | |
2781 | #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 | |
2782 | /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ | |
2783 | #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 | |
2784 | /* enum: KR Serdes Serial Wireside. */ | |
2785 | #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 | |
512bb06c BH |
2786 | /* enum: Near side of AOE Siena side port */ |
2787 | #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 | |
a9196bb0 EC |
2788 | /* enum: Medford Wireside datapath loopback */ |
2789 | #define MC_CMD_LOOPBACK_DATA_WS 0x24 | |
2790 | /* enum: Force link up without setting up any physical loopback (snapper use | |
2791 | * only) | |
2792 | */ | |
2793 | #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 | |
f2b0befd | 2794 | /* Supported loopbacks. */ |
05a9320f BH |
2795 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 |
2796 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 | |
2797 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 | |
2798 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 | |
2799 | /* Enum values, see field(s): */ | |
2800 | /* 100M */ | |
f2b0befd | 2801 | /* Supported loopbacks. */ |
05a9320f BH |
2802 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 |
2803 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 | |
2804 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 | |
2805 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 | |
2806 | /* Enum values, see field(s): */ | |
2807 | /* 100M */ | |
f2b0befd | 2808 | /* Supported loopbacks. */ |
05a9320f BH |
2809 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 |
2810 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 | |
2811 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 | |
2812 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 | |
2813 | /* Enum values, see field(s): */ | |
2814 | /* 100M */ | |
f2b0befd BH |
2815 | /* Supported loopbacks. */ |
2816 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 | |
2817 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 | |
2818 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 | |
2819 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 | |
2820 | /* Enum values, see field(s): */ | |
2821 | /* 100M */ | |
05a9320f BH |
2822 | |
2823 | ||
2824 | /***********************************/ | |
2825 | /* MC_CMD_GET_LINK | |
f2b0befd BH |
2826 | * Read the unified MAC/PHY link state. Locks required: None Return code: 0, |
2827 | * ETIME. | |
f0d37f42 SH |
2828 | */ |
2829 | #define MC_CMD_GET_LINK 0x29 | |
05a9320f | 2830 | |
75122ec8 SS |
2831 | #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
2832 | ||
05a9320f BH |
2833 | /* MC_CMD_GET_LINK_IN msgrequest */ |
2834 | #define MC_CMD_GET_LINK_IN_LEN 0 | |
2835 | ||
2836 | /* MC_CMD_GET_LINK_OUT msgresponse */ | |
2837 | #define MC_CMD_GET_LINK_OUT_LEN 28 | |
f2b0befd | 2838 | /* near-side advertised capabilities */ |
05a9320f | 2839 | #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 |
f2b0befd | 2840 | /* link-partner advertised capabilities */ |
05a9320f | 2841 | #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 |
f2b0befd BH |
2842 | /* Autonegotiated speed in mbit/s. The link may still be down even if this |
2843 | * reads non-zero. | |
2844 | */ | |
05a9320f | 2845 | #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 |
f2b0befd | 2846 | /* Current loopback setting. */ |
05a9320f BH |
2847 | #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 |
2848 | /* Enum values, see field(s): */ | |
2849 | /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ | |
2850 | #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 | |
2851 | #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 | |
2852 | #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 | |
2853 | #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 | |
2854 | #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 | |
2855 | #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 | |
2856 | #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 | |
2857 | #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 | |
2858 | #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 | |
512bb06c BH |
2859 | #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 |
2860 | #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 | |
2861 | #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 | |
2862 | #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 | |
f2b0befd | 2863 | /* This returns the negotiated flow control value. */ |
05a9320f | 2864 | #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 |
a9196bb0 EC |
2865 | /* Enum values, see field(s): */ |
2866 | /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ | |
05a9320f BH |
2867 | #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 |
2868 | #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 | |
2869 | #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 | |
2870 | #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 | |
2871 | #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 | |
2872 | #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 | |
2873 | #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 | |
2874 | #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 | |
2875 | #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 | |
2876 | ||
2877 | ||
2878 | /***********************************/ | |
2879 | /* MC_CMD_SET_LINK | |
f2b0befd BH |
2880 | * Write the unified MAC/PHY link configuration. Locks required: None. Return |
2881 | * code: 0, EINVAL, ETIME | |
f0d37f42 SH |
2882 | */ |
2883 | #define MC_CMD_SET_LINK 0x2a | |
05a9320f | 2884 | |
75122ec8 SS |
2885 | #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK |
2886 | ||
05a9320f BH |
2887 | /* MC_CMD_SET_LINK_IN msgrequest */ |
2888 | #define MC_CMD_SET_LINK_IN_LEN 16 | |
f2b0befd | 2889 | /* ??? */ |
05a9320f | 2890 | #define MC_CMD_SET_LINK_IN_CAP_OFST 0 |
f2b0befd | 2891 | /* Flags */ |
05a9320f BH |
2892 | #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 |
2893 | #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 | |
2894 | #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 | |
2895 | #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 | |
2896 | #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 | |
2897 | #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 | |
2898 | #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 | |
f2b0befd | 2899 | /* Loopback mode. */ |
05a9320f BH |
2900 | #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 |
2901 | /* Enum values, see field(s): */ | |
2902 | /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ | |
f2b0befd BH |
2903 | /* A loopback speed of "0" is supported, and means (choose any available |
2904 | * speed). | |
2905 | */ | |
05a9320f BH |
2906 | #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 |
2907 | ||
2908 | /* MC_CMD_SET_LINK_OUT msgresponse */ | |
2909 | #define MC_CMD_SET_LINK_OUT_LEN 0 | |
2910 | ||
2911 | ||
2912 | /***********************************/ | |
2913 | /* MC_CMD_SET_ID_LED | |
f2b0befd | 2914 | * Set identification LED state. Locks required: None. Return code: 0, EINVAL |
f0d37f42 SH |
2915 | */ |
2916 | #define MC_CMD_SET_ID_LED 0x2b | |
05a9320f | 2917 | |
75122ec8 SS |
2918 | #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK |
2919 | ||
05a9320f BH |
2920 | /* MC_CMD_SET_ID_LED_IN msgrequest */ |
2921 | #define MC_CMD_SET_ID_LED_IN_LEN 4 | |
f2b0befd | 2922 | /* Set LED state. */ |
05a9320f BH |
2923 | #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 |
2924 | #define MC_CMD_LED_OFF 0x0 /* enum */ | |
2925 | #define MC_CMD_LED_ON 0x1 /* enum */ | |
2926 | #define MC_CMD_LED_DEFAULT 0x2 /* enum */ | |
2927 | ||
2928 | /* MC_CMD_SET_ID_LED_OUT msgresponse */ | |
2929 | #define MC_CMD_SET_ID_LED_OUT_LEN 0 | |
2930 | ||
2931 | ||
2932 | /***********************************/ | |
2933 | /* MC_CMD_SET_MAC | |
f2b0befd | 2934 | * Set MAC configuration. Locks required: None. Return code: 0, EINVAL |
f0d37f42 SH |
2935 | */ |
2936 | #define MC_CMD_SET_MAC 0x2c | |
05a9320f | 2937 | |
23e202b4 | 2938 | #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
75122ec8 | 2939 | |
05a9320f | 2940 | /* MC_CMD_SET_MAC_IN msgrequest */ |
a9196bb0 | 2941 | #define MC_CMD_SET_MAC_IN_LEN 28 |
f2b0befd BH |
2942 | /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of |
2943 | * EtherII, VLAN, bug16011 padding). | |
2944 | */ | |
05a9320f BH |
2945 | #define MC_CMD_SET_MAC_IN_MTU_OFST 0 |
2946 | #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 | |
2947 | #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 | |
2948 | #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 | |
2949 | #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 | |
2950 | #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 | |
2951 | #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 | |
2952 | #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 | |
2953 | #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 | |
2954 | #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 | |
2955 | #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 | |
2956 | #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 | |
f2b0befd | 2957 | /* enum: Flow control is off. */ |
a9196bb0 | 2958 | #define MC_CMD_FCNTL_OFF 0x0 |
f2b0befd | 2959 | /* enum: Respond to flow control. */ |
a9196bb0 | 2960 | #define MC_CMD_FCNTL_RESPOND 0x1 |
f2b0befd | 2961 | /* enum: Respond to and Issue flow control. */ |
a9196bb0 | 2962 | #define MC_CMD_FCNTL_BIDIR 0x2 |
f2b0befd BH |
2963 | /* enum: Auto neg flow control. */ |
2964 | #define MC_CMD_FCNTL_AUTO 0x3 | |
a9196bb0 EC |
2965 | /* enum: Priority flow control (eftest builds only). */ |
2966 | #define MC_CMD_FCNTL_QBB 0x4 | |
2967 | /* enum: Issue flow control. */ | |
2968 | #define MC_CMD_FCNTL_GENERATE 0x5 | |
2969 | #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 | |
2970 | #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 | |
2971 | #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 | |
05a9320f | 2972 | |
23e202b4 EC |
2973 | /* MC_CMD_SET_MAC_EXT_IN msgrequest */ |
2974 | #define MC_CMD_SET_MAC_EXT_IN_LEN 32 | |
2975 | /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of | |
2976 | * EtherII, VLAN, bug16011 padding). | |
2977 | */ | |
2978 | #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 | |
2979 | #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 | |
2980 | #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 | |
2981 | #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 | |
2982 | #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 | |
2983 | #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 | |
2984 | #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 | |
2985 | #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 | |
2986 | #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 | |
2987 | #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 | |
2988 | #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 | |
2989 | #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 | |
2990 | /* enum: Flow control is off. */ | |
2991 | /* MC_CMD_FCNTL_OFF 0x0 */ | |
2992 | /* enum: Respond to flow control. */ | |
2993 | /* MC_CMD_FCNTL_RESPOND 0x1 */ | |
2994 | /* enum: Respond to and Issue flow control. */ | |
2995 | /* MC_CMD_FCNTL_BIDIR 0x2 */ | |
2996 | /* enum: Auto neg flow control. */ | |
2997 | /* MC_CMD_FCNTL_AUTO 0x3 */ | |
2998 | /* enum: Priority flow control (eftest builds only). */ | |
2999 | /* MC_CMD_FCNTL_QBB 0x4 */ | |
3000 | /* enum: Issue flow control. */ | |
3001 | /* MC_CMD_FCNTL_GENERATE 0x5 */ | |
3002 | #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 | |
3003 | #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 | |
3004 | #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 | |
3005 | /* Select which parameters to configure. A parameter will only be modified if | |
3006 | * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in | |
3007 | * capabilities then this field is ignored (and all flags are assumed to be | |
3008 | * set). | |
3009 | */ | |
3010 | #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 | |
3011 | #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 | |
3012 | #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 | |
3013 | #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 | |
3014 | #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 | |
3015 | #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 | |
3016 | #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 | |
3017 | #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 | |
3018 | #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 | |
3019 | #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 | |
3020 | #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 | |
3021 | ||
05a9320f BH |
3022 | /* MC_CMD_SET_MAC_OUT msgresponse */ |
3023 | #define MC_CMD_SET_MAC_OUT_LEN 0 | |
3024 | ||
23e202b4 EC |
3025 | /* MC_CMD_SET_MAC_V2_OUT msgresponse */ |
3026 | #define MC_CMD_SET_MAC_V2_OUT_LEN 4 | |
3027 | /* MTU as configured after processing the request. See comment at | |
3028 | * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL | |
3029 | * to 0. | |
3030 | */ | |
3031 | #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 | |
3032 | ||
05a9320f BH |
3033 | |
3034 | /***********************************/ | |
3035 | /* MC_CMD_PHY_STATS | |
f2b0befd BH |
3036 | * Get generic PHY statistics. This call returns the statistics for a generic |
3037 | * PHY in a sparse array (indexed by the enumerate). Each value is represented | |
3038 | * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the | |
3039 | * statistics may be read from the message response. If DMA_ADDR != 0, then the | |
3040 | * statistics are dmad to that (page-aligned location). Locks required: None. | |
3041 | * Returns: 0, ETIME | |
f0d37f42 SH |
3042 | */ |
3043 | #define MC_CMD_PHY_STATS 0x2d | |
f0d37f42 | 3044 | |
75122ec8 SS |
3045 | #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK |
3046 | ||
05a9320f BH |
3047 | /* MC_CMD_PHY_STATS_IN msgrequest */ |
3048 | #define MC_CMD_PHY_STATS_IN_LEN 8 | |
f2b0befd | 3049 | /* ??? */ |
05a9320f BH |
3050 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 |
3051 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 | |
3052 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 | |
3053 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 | |
3054 | ||
3055 | /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ | |
3056 | #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 | |
3057 | ||
3058 | /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ | |
3059 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) | |
3060 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 | |
3061 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 | |
3062 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS | |
f2b0befd BH |
3063 | /* enum: OUI. */ |
3064 | #define MC_CMD_OUI 0x0 | |
3065 | /* enum: PMA-PMD Link Up. */ | |
3066 | #define MC_CMD_PMA_PMD_LINK_UP 0x1 | |
3067 | /* enum: PMA-PMD RX Fault. */ | |
3068 | #define MC_CMD_PMA_PMD_RX_FAULT 0x2 | |
3069 | /* enum: PMA-PMD TX Fault. */ | |
3070 | #define MC_CMD_PMA_PMD_TX_FAULT 0x3 | |
3071 | /* enum: PMA-PMD Signal */ | |
3072 | #define MC_CMD_PMA_PMD_SIGNAL 0x4 | |
3073 | /* enum: PMA-PMD SNR A. */ | |
3074 | #define MC_CMD_PMA_PMD_SNR_A 0x5 | |
3075 | /* enum: PMA-PMD SNR B. */ | |
3076 | #define MC_CMD_PMA_PMD_SNR_B 0x6 | |
3077 | /* enum: PMA-PMD SNR C. */ | |
3078 | #define MC_CMD_PMA_PMD_SNR_C 0x7 | |
3079 | /* enum: PMA-PMD SNR D. */ | |
3080 | #define MC_CMD_PMA_PMD_SNR_D 0x8 | |
3081 | /* enum: PCS Link Up. */ | |
3082 | #define MC_CMD_PCS_LINK_UP 0x9 | |
3083 | /* enum: PCS RX Fault. */ | |
3084 | #define MC_CMD_PCS_RX_FAULT 0xa | |
3085 | /* enum: PCS TX Fault. */ | |
3086 | #define MC_CMD_PCS_TX_FAULT 0xb | |
3087 | /* enum: PCS BER. */ | |
3088 | #define MC_CMD_PCS_BER 0xc | |
3089 | /* enum: PCS Block Errors. */ | |
3090 | #define MC_CMD_PCS_BLOCK_ERRORS 0xd | |
3091 | /* enum: PhyXS Link Up. */ | |
3092 | #define MC_CMD_PHYXS_LINK_UP 0xe | |
3093 | /* enum: PhyXS RX Fault. */ | |
3094 | #define MC_CMD_PHYXS_RX_FAULT 0xf | |
3095 | /* enum: PhyXS TX Fault. */ | |
3096 | #define MC_CMD_PHYXS_TX_FAULT 0x10 | |
3097 | /* enum: PhyXS Align. */ | |
3098 | #define MC_CMD_PHYXS_ALIGN 0x11 | |
3099 | /* enum: PhyXS Sync. */ | |
3100 | #define MC_CMD_PHYXS_SYNC 0x12 | |
3101 | /* enum: AN link-up. */ | |
3102 | #define MC_CMD_AN_LINK_UP 0x13 | |
3103 | /* enum: AN Complete. */ | |
3104 | #define MC_CMD_AN_COMPLETE 0x14 | |
3105 | /* enum: AN 10GBaseT Status. */ | |
3106 | #define MC_CMD_AN_10GBT_STATUS 0x15 | |
3107 | /* enum: Clause 22 Link-Up. */ | |
3108 | #define MC_CMD_CL22_LINK_UP 0x16 | |
3109 | /* enum: (Last entry) */ | |
3110 | #define MC_CMD_PHY_NSTATS 0x17 | |
05a9320f BH |
3111 | |
3112 | ||
3113 | /***********************************/ | |
3114 | /* MC_CMD_MAC_STATS | |
f2b0befd BH |
3115 | * Get generic MAC statistics. This call returns unified statistics maintained |
3116 | * by the MC as it switches between the GMAC and XMAC. The MC will write out | |
3117 | * all supported stats. The driver should zero initialise the buffer to | |
3118 | * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is | |
3119 | * performed, and the statistics may be read from the message response. If | |
3120 | * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). | |
a9196bb0 EC |
3121 | * Locks required: None. The PERIODIC_CLEAR option is not used and now has no |
3122 | * effect. Returns: 0, ETIME | |
f0d37f42 | 3123 | */ |
05a9320f | 3124 | #define MC_CMD_MAC_STATS 0x2e |
f0d37f42 | 3125 | |
75122ec8 SS |
3126 | #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
3127 | ||
05a9320f | 3128 | /* MC_CMD_MAC_STATS_IN msgrequest */ |
d7788196 | 3129 | #define MC_CMD_MAC_STATS_IN_LEN 20 |
f2b0befd | 3130 | /* ??? */ |
05a9320f BH |
3131 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 |
3132 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 | |
3133 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 | |
3134 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 | |
3135 | #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 | |
3136 | #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 | |
3137 | #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 | |
3138 | #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 | |
3139 | #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 | |
3140 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 | |
3141 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 | |
3142 | #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 | |
3143 | #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 | |
3144 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 | |
3145 | #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 | |
3146 | #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 | |
3147 | #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 | |
3148 | #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 | |
3149 | #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 | |
3150 | #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 | |
d7788196 DP |
3151 | /* port id so vadapter stats can be provided */ |
3152 | #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 | |
05a9320f BH |
3153 | |
3154 | /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ | |
3155 | #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 | |
3156 | ||
3157 | /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ | |
3158 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) | |
3159 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 | |
3160 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 | |
3161 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 | |
3162 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 | |
3163 | #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS | |
3164 | #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ | |
a9196bb0 | 3165 | #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ |
05a9320f BH |
3166 | #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ |
3167 | #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ | |
3168 | #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ | |
3169 | #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ | |
3170 | #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ | |
3171 | #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ | |
3172 | #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ | |
3173 | #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ | |
3174 | #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ | |
3175 | #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ | |
3176 | #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ | |
3177 | #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ | |
3178 | #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ | |
3179 | #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ | |
3180 | #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ | |
3181 | #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ | |
3182 | #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ | |
3183 | #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ | |
3184 | #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ | |
3185 | #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ | |
3186 | #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ | |
3187 | #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ | |
3188 | #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ | |
3189 | #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ | |
3190 | #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ | |
3191 | #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ | |
3192 | #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ | |
3193 | #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ | |
3194 | #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ | |
3195 | #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ | |
3196 | #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ | |
3197 | #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ | |
3198 | #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ | |
3199 | #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ | |
3200 | #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ | |
3201 | #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ | |
3202 | #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ | |
3203 | #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ | |
3204 | #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ | |
3205 | #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ | |
3206 | #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ | |
3207 | #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ | |
3208 | #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ | |
3209 | #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ | |
3210 | #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ | |
3211 | #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ | |
3212 | #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ | |
3213 | #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ | |
3214 | #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ | |
3215 | #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ | |
3216 | #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ | |
3217 | #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ | |
3218 | #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ | |
3219 | #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ | |
3220 | #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ | |
3221 | #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ | |
3222 | #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ | |
3223 | #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ | |
3224 | #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ | |
2ca10a75 MS |
3225 | /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
3226 | * capability only. | |
3227 | */ | |
3228 | #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c | |
3229 | /* enum: PM discard_bb_overflow counter. Valid for EF10 with | |
3230 | * PM_AND_RXDP_COUNTERS capability only. | |
3231 | */ | |
3232 | #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d | |
3233 | /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS | |
3234 | * capability only. | |
3235 | */ | |
3236 | #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e | |
3237 | /* enum: PM discard_vfifo_full counter. Valid for EF10 with | |
3238 | * PM_AND_RXDP_COUNTERS capability only. | |
3239 | */ | |
3240 | #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f | |
3241 | /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS | |
3242 | * capability only. | |
3243 | */ | |
3244 | #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 | |
3245 | /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS | |
3246 | * capability only. | |
3247 | */ | |
3248 | #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 | |
3249 | /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS | |
3250 | * capability only. | |
3251 | */ | |
3252 | #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 | |
3253 | /* enum: RXDP counter: Number of packets dropped due to the queue being | |
3254 | * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. | |
3255 | */ | |
3256 | #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 | |
3257 | /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 | |
3258 | * with PM_AND_RXDP_COUNTERS capability only. | |
3259 | */ | |
3260 | #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 | |
3261 | /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with | |
3262 | * PM_AND_RXDP_COUNTERS capability only. | |
3263 | */ | |
3264 | #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 | |
a9196bb0 EC |
3265 | /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. |
3266 | * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. | |
2ca10a75 | 3267 | */ |
e80ca013 | 3268 | #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 |
2ca10a75 MS |
3269 | /* enum: RXDP counter: Number of times the DPCPU waited for an existing |
3270 | * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. | |
3271 | */ | |
e80ca013 | 3272 | #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 |
3c36a2ad DP |
3273 | #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ |
3274 | #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ | |
3275 | #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ | |
3276 | #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ | |
3277 | #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ | |
3278 | #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ | |
3279 | #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ | |
3280 | #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ | |
3281 | #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ | |
3282 | #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ | |
3283 | #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ | |
3284 | #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ | |
3285 | #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ | |
3286 | #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ | |
3287 | #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ | |
3288 | #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ | |
3289 | #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ | |
3290 | #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ | |
3291 | #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ | |
3292 | #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ | |
2ca10a75 MS |
3293 | /* enum: Start of GMAC stats buffer space, for Siena only. */ |
3294 | #define MC_CMD_GMAC_DMABUF_START 0x40 | |
3295 | /* enum: End of GMAC stats buffer space, for Siena only. */ | |
3296 | #define MC_CMD_GMAC_DMABUF_END 0x5f | |
05a9320f BH |
3297 | #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ |
3298 | #define MC_CMD_MAC_NSTATS 0x61 /* enum */ | |
3299 | ||
3300 | ||
3301 | /***********************************/ | |
3302 | /* MC_CMD_SRIOV | |
3303 | * to be documented | |
3304 | */ | |
3305 | #define MC_CMD_SRIOV 0x30 | |
3306 | ||
3307 | /* MC_CMD_SRIOV_IN msgrequest */ | |
3308 | #define MC_CMD_SRIOV_IN_LEN 12 | |
3309 | #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 | |
3310 | #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 | |
3311 | #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 | |
3312 | ||
3313 | /* MC_CMD_SRIOV_OUT msgresponse */ | |
3314 | #define MC_CMD_SRIOV_OUT_LEN 8 | |
3315 | #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 | |
3316 | #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 | |
3317 | ||
3318 | /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ | |
3319 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 | |
f2b0befd | 3320 | /* this is only used for the first record */ |
05a9320f BH |
3321 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 |
3322 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 | |
3323 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 | |
3324 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 | |
3325 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 | |
3326 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 | |
3327 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 | |
3328 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 | |
3329 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 | |
3330 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 | |
3331 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 | |
3332 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 | |
3333 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 | |
3334 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ | |
3335 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 | |
3336 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 | |
3337 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 | |
3338 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 | |
3339 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 | |
3340 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 | |
3341 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 | |
3342 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 | |
3343 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 | |
3344 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 | |
3345 | #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 | |
3346 | ||
3347 | ||
3348 | /***********************************/ | |
3349 | /* MC_CMD_MEMCPY | |
f2b0befd BH |
3350 | * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data |
3351 | * embedded directly in the command. | |
3352 | * | |
3353 | * A common pattern is for a client to use generation counts to signal a dma | |
3354 | * update of a datastructure. To facilitate this, this MCDI operation can | |
3355 | * contain multiple requests which are executed in strict order. Requests take | |
3356 | * the form of duplicating the entire MCDI request continuously (including the | |
3357 | * requests record, which is ignored in all but the first structure) | |
3358 | * | |
3359 | * The source data can either come from a DMA from the host, or it can be | |
3360 | * embedded within the request directly, thereby eliminating a DMA read. To | |
3361 | * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and | |
3362 | * ADDR_LO=offset, and inserts the data at %offset from the start of the | |
3363 | * payload. It's the callers responsibility to ensure that the embedded data | |
3364 | * doesn't overlap the records. | |
3365 | * | |
3366 | * Returns: 0, EINVAL (invalid RID) | |
05a9320f BH |
3367 | */ |
3368 | #define MC_CMD_MEMCPY 0x31 | |
3369 | ||
3370 | /* MC_CMD_MEMCPY_IN msgrequest */ | |
3371 | #define MC_CMD_MEMCPY_IN_LENMIN 32 | |
3372 | #define MC_CMD_MEMCPY_IN_LENMAX 224 | |
3373 | #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) | |
f2b0befd | 3374 | /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ |
05a9320f BH |
3375 | #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 |
3376 | #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 | |
3377 | #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 | |
3378 | #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 | |
3379 | ||
3380 | /* MC_CMD_MEMCPY_OUT msgresponse */ | |
3381 | #define MC_CMD_MEMCPY_OUT_LEN 0 | |
3382 | ||
3383 | ||
3384 | /***********************************/ | |
3385 | /* MC_CMD_WOL_FILTER_SET | |
3386 | * Set a WoL filter. | |
f0d37f42 SH |
3387 | */ |
3388 | #define MC_CMD_WOL_FILTER_SET 0x32 | |
05a9320f | 3389 | |
75122ec8 SS |
3390 | #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK |
3391 | ||
05a9320f BH |
3392 | /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ |
3393 | #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 | |
3394 | #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 | |
3395 | #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ | |
3396 | #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ | |
f2b0befd | 3397 | /* A type value of 1 is unused. */ |
05a9320f | 3398 | #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 |
f2b0befd BH |
3399 | /* enum: Magic */ |
3400 | #define MC_CMD_WOL_TYPE_MAGIC 0x0 | |
3401 | /* enum: MS Windows Magic */ | |
3402 | #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 | |
3403 | /* enum: IPv4 Syn */ | |
3404 | #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 | |
3405 | /* enum: IPv6 Syn */ | |
3406 | #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 | |
3407 | /* enum: Bitmap */ | |
3408 | #define MC_CMD_WOL_TYPE_BITMAP 0x5 | |
3409 | /* enum: Link */ | |
3410 | #define MC_CMD_WOL_TYPE_LINK 0x6 | |
3411 | /* enum: (Above this for future use) */ | |
3412 | #define MC_CMD_WOL_TYPE_MAX 0x7 | |
05a9320f BH |
3413 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 |
3414 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 | |
3415 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 | |
3416 | ||
3417 | /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ | |
3418 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 | |
3419 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3420 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3421 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 | |
3422 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 | |
3423 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 | |
3424 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 | |
3425 | ||
3426 | /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ | |
3427 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 | |
3428 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3429 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3430 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 | |
3431 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 | |
3432 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 | |
3433 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 | |
3434 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 | |
3435 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 | |
3436 | ||
3437 | /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ | |
3438 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 | |
3439 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3440 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3441 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 | |
3442 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 | |
3443 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 | |
3444 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 | |
3445 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 | |
3446 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 | |
3447 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 | |
3448 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 | |
3449 | ||
3450 | /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ | |
3451 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 | |
3452 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3453 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3454 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 | |
3455 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 | |
3456 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 | |
3457 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 | |
3458 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 | |
3459 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 | |
3460 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 | |
3461 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 | |
3462 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 | |
3463 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 | |
3464 | ||
3465 | /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ | |
3466 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 | |
3467 | /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ | |
3468 | /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ | |
3469 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 | |
3470 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 | |
3471 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 | |
3472 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 | |
3473 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 | |
3474 | ||
3475 | /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ | |
3476 | #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 | |
3477 | #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 | |
3478 | ||
3479 | ||
3480 | /***********************************/ | |
3481 | /* MC_CMD_WOL_FILTER_REMOVE | |
f2b0befd | 3482 | * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS |
f0d37f42 SH |
3483 | */ |
3484 | #define MC_CMD_WOL_FILTER_REMOVE 0x33 | |
f0d37f42 | 3485 | |
75122ec8 SS |
3486 | #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK |
3487 | ||
05a9320f BH |
3488 | /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ |
3489 | #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 | |
3490 | #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 | |
f0d37f42 | 3491 | |
05a9320f BH |
3492 | /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ |
3493 | #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 | |
3494 | ||
3495 | ||
3496 | /***********************************/ | |
3497 | /* MC_CMD_WOL_FILTER_RESET | |
f2b0befd BH |
3498 | * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, |
3499 | * ENOSYS | |
f0d37f42 SH |
3500 | */ |
3501 | #define MC_CMD_WOL_FILTER_RESET 0x34 | |
f0d37f42 | 3502 | |
75122ec8 SS |
3503 | #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK |
3504 | ||
05a9320f BH |
3505 | /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ |
3506 | #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 | |
3507 | #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 | |
3508 | #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ | |
3509 | #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ | |
3510 | ||
3511 | /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ | |
3512 | #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 | |
3513 | ||
3514 | ||
3515 | /***********************************/ | |
3516 | /* MC_CMD_SET_MCAST_HASH | |
f2b0befd | 3517 | * Set the MCAST hash value without otherwise reconfiguring the MAC |
f0d37f42 SH |
3518 | */ |
3519 | #define MC_CMD_SET_MCAST_HASH 0x35 | |
f0d37f42 | 3520 | |
05a9320f BH |
3521 | /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ |
3522 | #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 | |
3523 | #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 | |
3524 | #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 | |
3525 | #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 | |
3526 | #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 | |
3527 | ||
3528 | /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ | |
3529 | #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 | |
3530 | ||
3531 | ||
3532 | /***********************************/ | |
3533 | /* MC_CMD_NVRAM_TYPES | |
f2b0befd BH |
3534 | * Return bitfield indicating available types of virtual NVRAM partitions. |
3535 | * Locks required: none. Returns: 0 | |
f0d37f42 SH |
3536 | */ |
3537 | #define MC_CMD_NVRAM_TYPES 0x36 | |
05a9320f | 3538 | |
75122ec8 SS |
3539 | #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3540 | ||
05a9320f BH |
3541 | /* MC_CMD_NVRAM_TYPES_IN msgrequest */ |
3542 | #define MC_CMD_NVRAM_TYPES_IN_LEN 0 | |
3543 | ||
3544 | /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ | |
3545 | #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 | |
f2b0befd | 3546 | /* Bit mask of supported types. */ |
05a9320f | 3547 | #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 |
f2b0befd BH |
3548 | /* enum: Disabled callisto. */ |
3549 | #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 | |
3550 | /* enum: MC firmware. */ | |
3551 | #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 | |
3552 | /* enum: MC backup firmware. */ | |
3553 | #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 | |
3554 | /* enum: Static configuration Port0. */ | |
3555 | #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 | |
3556 | /* enum: Static configuration Port1. */ | |
3557 | #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 | |
3558 | /* enum: Dynamic configuration Port0. */ | |
3559 | #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 | |
3560 | /* enum: Dynamic configuration Port1. */ | |
3561 | #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 | |
3562 | /* enum: Expansion Rom. */ | |
3563 | #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 | |
3564 | /* enum: Expansion Rom Configuration Port0. */ | |
3565 | #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 | |
3566 | /* enum: Expansion Rom Configuration Port1. */ | |
3567 | #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 | |
3568 | /* enum: Phy Configuration Port0. */ | |
3569 | #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa | |
3570 | /* enum: Phy Configuration Port1. */ | |
3571 | #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb | |
3572 | /* enum: Log. */ | |
3573 | #define MC_CMD_NVRAM_TYPE_LOG 0xc | |
3574 | /* enum: FPGA image. */ | |
3575 | #define MC_CMD_NVRAM_TYPE_FPGA 0xd | |
3576 | /* enum: FPGA backup image */ | |
3577 | #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe | |
3578 | /* enum: FC firmware. */ | |
3579 | #define MC_CMD_NVRAM_TYPE_FC_FW 0xf | |
3580 | /* enum: FC backup firmware. */ | |
3581 | #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 | |
3582 | /* enum: CPLD image. */ | |
3583 | #define MC_CMD_NVRAM_TYPE_CPLD 0x11 | |
3584 | /* enum: Licensing information. */ | |
3585 | #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 | |
3586 | /* enum: FC Log. */ | |
3587 | #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 | |
a9196bb0 EC |
3588 | /* enum: Additional flash on FPGA. */ |
3589 | #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 | |
05a9320f BH |
3590 | |
3591 | ||
3592 | /***********************************/ | |
3593 | /* MC_CMD_NVRAM_INFO | |
f2b0befd BH |
3594 | * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, |
3595 | * EINVAL (bad type). | |
f0d37f42 SH |
3596 | */ |
3597 | #define MC_CMD_NVRAM_INFO 0x37 | |
05a9320f | 3598 | |
75122ec8 SS |
3599 | #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3600 | ||
05a9320f BH |
3601 | /* MC_CMD_NVRAM_INFO_IN msgrequest */ |
3602 | #define MC_CMD_NVRAM_INFO_IN_LEN 4 | |
3603 | #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 | |
3604 | /* Enum values, see field(s): */ | |
3605 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3606 | ||
3607 | /* MC_CMD_NVRAM_INFO_OUT msgresponse */ | |
3608 | #define MC_CMD_NVRAM_INFO_OUT_LEN 24 | |
3609 | #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 | |
3610 | /* Enum values, see field(s): */ | |
3611 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3612 | #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 | |
3613 | #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 | |
3614 | #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 | |
3615 | #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 | |
3616 | #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 | |
f2b0befd BH |
3617 | #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 |
3618 | #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 | |
d29e33d6 BK |
3619 | #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 |
3620 | #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 | |
f2b0befd BH |
3621 | #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 |
3622 | #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 | |
05a9320f BH |
3623 | #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 |
3624 | #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 | |
3625 | ||
23e202b4 EC |
3626 | /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ |
3627 | #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 | |
3628 | #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 | |
3629 | /* Enum values, see field(s): */ | |
3630 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3631 | #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 | |
3632 | #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 | |
3633 | #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 | |
3634 | #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 | |
3635 | #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 | |
3636 | #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 | |
3637 | #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 | |
3638 | #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 | |
3639 | #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 | |
3640 | #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 | |
3641 | #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 | |
3642 | /* Writes must be multiples of this size. Added to support the MUM on Sorrento. | |
3643 | */ | |
3644 | #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 | |
3645 | ||
05a9320f BH |
3646 | |
3647 | /***********************************/ | |
3648 | /* MC_CMD_NVRAM_UPDATE_START | |
f2b0befd BH |
3649 | * Start a group of update operations on a virtual NVRAM partition. Locks |
3650 | * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if | |
3651 | * PHY_LOCK required and not held). | |
f0d37f42 SH |
3652 | */ |
3653 | #define MC_CMD_NVRAM_UPDATE_START 0x38 | |
f0d37f42 | 3654 | |
75122ec8 SS |
3655 | #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3656 | ||
05a9320f BH |
3657 | /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ |
3658 | #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 | |
3659 | #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 | |
3660 | /* Enum values, see field(s): */ | |
3661 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3662 | ||
3663 | /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ | |
3664 | #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 | |
3665 | ||
3666 | ||
3667 | /***********************************/ | |
3668 | /* MC_CMD_NVRAM_READ | |
f2b0befd BH |
3669 | * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if |
3670 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
3671 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
3672 | */ |
3673 | #define MC_CMD_NVRAM_READ 0x39 | |
05a9320f | 3674 | |
75122ec8 SS |
3675 | #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3676 | ||
05a9320f BH |
3677 | /* MC_CMD_NVRAM_READ_IN msgrequest */ |
3678 | #define MC_CMD_NVRAM_READ_IN_LEN 12 | |
3679 | #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 | |
3680 | /* Enum values, see field(s): */ | |
3681 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3682 | #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 | |
f2b0befd | 3683 | /* amount to read in bytes */ |
05a9320f BH |
3684 | #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 |
3685 | ||
23e202b4 EC |
3686 | /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ |
3687 | #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 | |
3688 | #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 | |
3689 | /* Enum values, see field(s): */ | |
3690 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3691 | #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 | |
3692 | /* amount to read in bytes */ | |
3693 | #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 | |
3694 | /* Optional control info. If a partition is stored with an A/B versioning | |
3695 | * scheme (i.e. in more than one physical partition in NVRAM) the host can set | |
3696 | * this to control which underlying physical partition is used to read data | |
3697 | * from. This allows it to perform a read-modify-write-verify with the write | |
3698 | * lock continuously held by calling NVRAM_UPDATE_START, reading the old | |
3699 | * contents using MODE=TARGET_CURRENT, overwriting the old partition and then | |
3700 | * verifying by reading with MODE=TARGET_BACKUP. | |
3701 | */ | |
3702 | #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 | |
3703 | /* enum: Same as omitting MODE: caller sees data in current partition unless it | |
3704 | * holds the write lock in which case it sees data in the partition it is | |
3705 | * updating. | |
3706 | */ | |
3707 | #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 | |
3708 | /* enum: Read from the current partition of an A/B pair, even if holding the | |
3709 | * write lock. | |
3710 | */ | |
3711 | #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 | |
3712 | /* enum: Read from the non-current (i.e. to be updated) partition of an A/B | |
3713 | * pair | |
3714 | */ | |
3715 | #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 | |
3716 | ||
05a9320f BH |
3717 | /* MC_CMD_NVRAM_READ_OUT msgresponse */ |
3718 | #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 | |
576eda8b | 3719 | #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 |
05a9320f BH |
3720 | #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) |
3721 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 | |
3722 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 | |
3723 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 | |
576eda8b | 3724 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 |
05a9320f BH |
3725 | |
3726 | ||
3727 | /***********************************/ | |
3728 | /* MC_CMD_NVRAM_WRITE | |
f2b0befd BH |
3729 | * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if |
3730 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
3731 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
3732 | */ |
3733 | #define MC_CMD_NVRAM_WRITE 0x3a | |
05a9320f | 3734 | |
75122ec8 SS |
3735 | #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3736 | ||
05a9320f BH |
3737 | /* MC_CMD_NVRAM_WRITE_IN msgrequest */ |
3738 | #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 | |
576eda8b | 3739 | #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 |
05a9320f BH |
3740 | #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) |
3741 | #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 | |
3742 | /* Enum values, see field(s): */ | |
3743 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3744 | #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 | |
3745 | #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 | |
3746 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 | |
3747 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 | |
3748 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 | |
576eda8b | 3749 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 |
05a9320f BH |
3750 | |
3751 | /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ | |
3752 | #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 | |
3753 | ||
3754 | ||
3755 | /***********************************/ | |
3756 | /* MC_CMD_NVRAM_ERASE | |
f2b0befd BH |
3757 | * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if |
3758 | * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if | |
3759 | * PHY_LOCK required and not held) | |
f0d37f42 SH |
3760 | */ |
3761 | #define MC_CMD_NVRAM_ERASE 0x3b | |
05a9320f | 3762 | |
75122ec8 SS |
3763 | #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3764 | ||
05a9320f BH |
3765 | /* MC_CMD_NVRAM_ERASE_IN msgrequest */ |
3766 | #define MC_CMD_NVRAM_ERASE_IN_LEN 12 | |
3767 | #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 | |
3768 | /* Enum values, see field(s): */ | |
3769 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3770 | #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 | |
3771 | #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 | |
3772 | ||
3773 | /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ | |
3774 | #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 | |
3775 | ||
3776 | ||
3777 | /***********************************/ | |
3778 | /* MC_CMD_NVRAM_UPDATE_FINISH | |
f2b0befd BH |
3779 | * Finish a group of update operations on a virtual NVRAM partition. Locks |
3780 | * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad | |
3781 | * type/offset/length), EACCES (if PHY_LOCK required and not held) | |
f0d37f42 SH |
3782 | */ |
3783 | #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c | |
f0d37f42 | 3784 | |
75122ec8 SS |
3785 | #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3786 | ||
05a9320f BH |
3787 | /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ |
3788 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 | |
3789 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 | |
3790 | /* Enum values, see field(s): */ | |
3791 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
3792 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 | |
3793 | ||
3794 | /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ | |
3795 | #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 | |
3796 | ||
3797 | ||
3798 | /***********************************/ | |
3799 | /* MC_CMD_REBOOT | |
5297a98d | 3800 | * Reboot the MC. |
f2b0befd BH |
3801 | * |
3802 | * The AFTER_ASSERTION flag is intended to be used when the driver notices an | |
3803 | * assertion failure (at which point it is expected to perform a complete tear | |
3804 | * down and reinitialise), to allow both ports to reset the MC once in an | |
3805 | * atomic fashion. | |
3806 | * | |
3807 | * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, | |
3808 | * which means that they will automatically reboot out of the assertion | |
3809 | * handler, so this is in practise an optional operation. It is still | |
3810 | * recommended that drivers execute this to support custom firmwares with | |
3811 | * REBOOT_ON_ASSERT=0. | |
3812 | * | |
3813 | * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, | |
3814 | * DATALEN=0 | |
f0d37f42 SH |
3815 | */ |
3816 | #define MC_CMD_REBOOT 0x3d | |
f0d37f42 | 3817 | |
75122ec8 SS |
3818 | #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3819 | ||
05a9320f BH |
3820 | /* MC_CMD_REBOOT_IN msgrequest */ |
3821 | #define MC_CMD_REBOOT_IN_LEN 4 | |
3822 | #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 | |
3823 | #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ | |
3824 | ||
3825 | /* MC_CMD_REBOOT_OUT msgresponse */ | |
3826 | #define MC_CMD_REBOOT_OUT_LEN 0 | |
3827 | ||
3828 | ||
3829 | /***********************************/ | |
3830 | /* MC_CMD_SCHEDINFO | |
f2b0befd BH |
3831 | * Request scheduler info. Locks required: NONE. Returns: An array of |
3832 | * (timeslice,maximum overrun), one for each thread, in ascending order of | |
3833 | * thread address. | |
f0d37f42 SH |
3834 | */ |
3835 | #define MC_CMD_SCHEDINFO 0x3e | |
f0d37f42 | 3836 | |
a9196bb0 EC |
3837 | #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3838 | ||
05a9320f BH |
3839 | /* MC_CMD_SCHEDINFO_IN msgrequest */ |
3840 | #define MC_CMD_SCHEDINFO_IN_LEN 0 | |
f0d37f42 | 3841 | |
05a9320f BH |
3842 | /* MC_CMD_SCHEDINFO_OUT msgresponse */ |
3843 | #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 | |
3844 | #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 | |
3845 | #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) | |
3846 | #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 | |
3847 | #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 | |
3848 | #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 | |
3849 | #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 | |
3850 | ||
3851 | ||
3852 | /***********************************/ | |
3853 | /* MC_CMD_REBOOT_MODE | |
f2b0befd BH |
3854 | * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot |
3855 | * mode to the specified value. Returns the old mode. | |
f0d37f42 SH |
3856 | */ |
3857 | #define MC_CMD_REBOOT_MODE 0x3f | |
05a9320f | 3858 | |
75122ec8 SS |
3859 | #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3860 | ||
05a9320f BH |
3861 | /* MC_CMD_REBOOT_MODE_IN msgrequest */ |
3862 | #define MC_CMD_REBOOT_MODE_IN_LEN 4 | |
3863 | #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 | |
f2b0befd BH |
3864 | /* enum: Normal. */ |
3865 | #define MC_CMD_REBOOT_MODE_NORMAL 0x0 | |
3866 | /* enum: Power-on Reset. */ | |
3867 | #define MC_CMD_REBOOT_MODE_POR 0x2 | |
3868 | /* enum: Snapper. */ | |
3869 | #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 | |
3870 | /* enum: snapper fake POR */ | |
3871 | #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 | |
3872 | #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 | |
3873 | #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 | |
05a9320f BH |
3874 | |
3875 | /* MC_CMD_REBOOT_MODE_OUT msgresponse */ | |
3876 | #define MC_CMD_REBOOT_MODE_OUT_LEN 4 | |
3877 | #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 | |
3878 | ||
3879 | ||
3880 | /***********************************/ | |
3881 | /* MC_CMD_SENSOR_INFO | |
f0d37f42 | 3882 | * Returns information about every available sensor. |
f2b0befd BH |
3883 | * |
3884 | * Each sensor has a single (16bit) value, and a corresponding state. The | |
3885 | * mapping between value and state is nominally determined by the MC, but may | |
3886 | * be implemented using up to 2 ranges per sensor. | |
3887 | * | |
3888 | * This call returns a mask (32bit) of the sensors that are supported by this | |
3889 | * platform, then an array of sensor information structures, in order of sensor | |
3890 | * type (but without gaps for unimplemented sensors). Each structure defines | |
3891 | * the ranges for the corresponding sensor. An unused range is indicated by | |
3892 | * equal limit values. If one range is used, a value outside that range results | |
3893 | * in STATE_FATAL. If two ranges are used, a value outside the second range | |
3894 | * results in STATE_FATAL while a value outside the first and inside the second | |
3895 | * range results in STATE_WARNING. | |
3896 | * | |
3897 | * Sensor masks and sensor information arrays are organised into pages. For | |
3898 | * backward compatibility, older host software can only use sensors in page 0. | |
3899 | * Bit 32 in the sensor mask was previously unused, and is no reserved for use | |
3900 | * as the next page flag. | |
3901 | * | |
3902 | * If the request does not contain a PAGE value then firmware will only return | |
3903 | * page 0 of sensor information, with bit 31 in the sensor mask cleared. | |
3904 | * | |
3905 | * If the request contains a PAGE value then firmware responds with the sensor | |
3906 | * mask and sensor information array for that page of sensors. In this case bit | |
3907 | * 31 in the mask is set if another page exists. | |
3908 | * | |
3909 | * Locks required: None Returns: 0 | |
f0d37f42 SH |
3910 | */ |
3911 | #define MC_CMD_SENSOR_INFO 0x41 | |
f0d37f42 | 3912 | |
75122ec8 SS |
3913 | #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
3914 | ||
05a9320f BH |
3915 | /* MC_CMD_SENSOR_INFO_IN msgrequest */ |
3916 | #define MC_CMD_SENSOR_INFO_IN_LEN 0 | |
3917 | ||
f2b0befd BH |
3918 | /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ |
3919 | #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 | |
3920 | /* Which page of sensors to report. | |
3921 | * | |
3922 | * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). | |
3923 | * | |
3924 | * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. | |
3925 | */ | |
3926 | #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 | |
3927 | ||
05a9320f | 3928 | /* MC_CMD_SENSOR_INFO_OUT msgresponse */ |
512bb06c | 3929 | #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 |
05a9320f BH |
3930 | #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 |
3931 | #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) | |
3932 | #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 | |
f2b0befd BH |
3933 | /* enum: Controller temperature: degC */ |
3934 | #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 | |
3935 | /* enum: Phy common temperature: degC */ | |
3936 | #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 | |
3937 | /* enum: Controller cooling: bool */ | |
3938 | #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 | |
3939 | /* enum: Phy 0 temperature: degC */ | |
3940 | #define MC_CMD_SENSOR_PHY0_TEMP 0x3 | |
3941 | /* enum: Phy 0 cooling: bool */ | |
3942 | #define MC_CMD_SENSOR_PHY0_COOLING 0x4 | |
3943 | /* enum: Phy 1 temperature: degC */ | |
3944 | #define MC_CMD_SENSOR_PHY1_TEMP 0x5 | |
3945 | /* enum: Phy 1 cooling: bool */ | |
3946 | #define MC_CMD_SENSOR_PHY1_COOLING 0x6 | |
3947 | /* enum: 1.0v power: mV */ | |
3948 | #define MC_CMD_SENSOR_IN_1V0 0x7 | |
3949 | /* enum: 1.2v power: mV */ | |
3950 | #define MC_CMD_SENSOR_IN_1V2 0x8 | |
3951 | /* enum: 1.8v power: mV */ | |
3952 | #define MC_CMD_SENSOR_IN_1V8 0x9 | |
3953 | /* enum: 2.5v power: mV */ | |
3954 | #define MC_CMD_SENSOR_IN_2V5 0xa | |
3955 | /* enum: 3.3v power: mV */ | |
3956 | #define MC_CMD_SENSOR_IN_3V3 0xb | |
3957 | /* enum: 12v power: mV */ | |
3958 | #define MC_CMD_SENSOR_IN_12V0 0xc | |
3959 | /* enum: 1.2v analogue power: mV */ | |
3960 | #define MC_CMD_SENSOR_IN_1V2A 0xd | |
3961 | /* enum: reference voltage: mV */ | |
3962 | #define MC_CMD_SENSOR_IN_VREF 0xe | |
3963 | /* enum: AOE FPGA power: mV */ | |
3964 | #define MC_CMD_SENSOR_OUT_VAOE 0xf | |
3965 | /* enum: AOE FPGA temperature: degC */ | |
3966 | #define MC_CMD_SENSOR_AOE_TEMP 0x10 | |
3967 | /* enum: AOE FPGA PSU temperature: degC */ | |
3968 | #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 | |
3969 | /* enum: AOE PSU temperature: degC */ | |
3970 | #define MC_CMD_SENSOR_PSU_TEMP 0x12 | |
3971 | /* enum: Fan 0 speed: RPM */ | |
3972 | #define MC_CMD_SENSOR_FAN_0 0x13 | |
3973 | /* enum: Fan 1 speed: RPM */ | |
3974 | #define MC_CMD_SENSOR_FAN_1 0x14 | |
3975 | /* enum: Fan 2 speed: RPM */ | |
3976 | #define MC_CMD_SENSOR_FAN_2 0x15 | |
3977 | /* enum: Fan 3 speed: RPM */ | |
3978 | #define MC_CMD_SENSOR_FAN_3 0x16 | |
3979 | /* enum: Fan 4 speed: RPM */ | |
3980 | #define MC_CMD_SENSOR_FAN_4 0x17 | |
3981 | /* enum: AOE FPGA input power: mV */ | |
3982 | #define MC_CMD_SENSOR_IN_VAOE 0x18 | |
3983 | /* enum: AOE FPGA current: mA */ | |
3984 | #define MC_CMD_SENSOR_OUT_IAOE 0x19 | |
3985 | /* enum: AOE FPGA input current: mA */ | |
3986 | #define MC_CMD_SENSOR_IN_IAOE 0x1a | |
3987 | /* enum: NIC power consumption: W */ | |
3988 | #define MC_CMD_SENSOR_NIC_POWER 0x1b | |
3989 | /* enum: 0.9v power voltage: mV */ | |
3990 | #define MC_CMD_SENSOR_IN_0V9 0x1c | |
3991 | /* enum: 0.9v power current: mA */ | |
3992 | #define MC_CMD_SENSOR_IN_I0V9 0x1d | |
3993 | /* enum: 1.2v power current: mA */ | |
3994 | #define MC_CMD_SENSOR_IN_I1V2 0x1e | |
3995 | /* enum: Not a sensor: reserved for the next page flag */ | |
3996 | #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f | |
3997 | /* enum: 0.9v power voltage (at ADC): mV */ | |
3998 | #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 | |
3999 | /* enum: Controller temperature 2: degC */ | |
4000 | #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 | |
4001 | /* enum: Voltage regulator internal temperature: degC */ | |
4002 | #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 | |
4003 | /* enum: 0.9V voltage regulator temperature: degC */ | |
4004 | #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 | |
4005 | /* enum: 1.2V voltage regulator temperature: degC */ | |
4006 | #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 | |
4007 | /* enum: controller internal temperature sensor voltage (internal ADC): mV */ | |
4008 | #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 | |
4009 | /* enum: controller internal temperature (internal ADC): degC */ | |
4010 | #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 | |
4011 | /* enum: controller internal temperature sensor voltage (external ADC): mV */ | |
4012 | #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 | |
4013 | /* enum: controller internal temperature (external ADC): degC */ | |
4014 | #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 | |
4015 | /* enum: ambient temperature: degC */ | |
4016 | #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 | |
4017 | /* enum: air flow: bool */ | |
4018 | #define MC_CMD_SENSOR_AIRFLOW 0x2a | |
4019 | /* enum: voltage between VSS08D and VSS08D at CSR: mV */ | |
4020 | #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b | |
4021 | /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ | |
4022 | #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c | |
512bb06c BH |
4023 | /* enum: Hotpoint temperature: degC */ |
4024 | #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d | |
a9196bb0 EC |
4025 | /* enum: Port 0 PHY power switch over-current: bool */ |
4026 | #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e | |
4027 | /* enum: Port 1 PHY power switch over-current: bool */ | |
4028 | #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f | |
4029 | /* enum: Mop-up microcontroller reference voltage (millivolts) */ | |
4030 | #define MC_CMD_SENSOR_MUM_VCC 0x30 | |
4031 | /* enum: 0.9v power phase A voltage: mV */ | |
4032 | #define MC_CMD_SENSOR_IN_0V9_A 0x31 | |
4033 | /* enum: 0.9v power phase A current: mA */ | |
4034 | #define MC_CMD_SENSOR_IN_I0V9_A 0x32 | |
4035 | /* enum: 0.9V voltage regulator phase A temperature: degC */ | |
4036 | #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 | |
4037 | /* enum: 0.9v power phase B voltage: mV */ | |
4038 | #define MC_CMD_SENSOR_IN_0V9_B 0x34 | |
4039 | /* enum: 0.9v power phase B current: mA */ | |
4040 | #define MC_CMD_SENSOR_IN_I0V9_B 0x35 | |
4041 | /* enum: 0.9V voltage regulator phase B temperature: degC */ | |
4042 | #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 | |
4043 | /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ | |
4044 | #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 | |
4045 | /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ | |
4046 | #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 | |
4047 | /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ | |
4048 | #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 | |
4049 | /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ | |
4050 | #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a | |
23e202b4 EC |
4051 | /* enum: CCOM RTS temperature: degC */ |
4052 | #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b | |
a9196bb0 EC |
4053 | /* enum: Not a sensor: reserved for the next page flag */ |
4054 | #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f | |
4055 | /* enum: controller internal temperature sensor voltage on master core | |
4056 | * (internal ADC): mV | |
4057 | */ | |
4058 | #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 | |
4059 | /* enum: controller internal temperature on master core (internal ADC): degC */ | |
4060 | #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 | |
4061 | /* enum: controller internal temperature sensor voltage on master core | |
4062 | * (external ADC): mV | |
4063 | */ | |
4064 | #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 | |
4065 | /* enum: controller internal temperature on master core (external ADC): degC */ | |
4066 | #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 | |
4067 | /* enum: controller internal temperature on slave core sensor voltage (internal | |
4068 | * ADC): mV | |
4069 | */ | |
4070 | #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 | |
4071 | /* enum: controller internal temperature on slave core (internal ADC): degC */ | |
4072 | #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 | |
4073 | /* enum: controller internal temperature on slave core sensor voltage (external | |
4074 | * ADC): mV | |
4075 | */ | |
4076 | #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 | |
4077 | /* enum: controller internal temperature on slave core (external ADC): degC */ | |
4078 | #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 | |
4079 | /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ | |
4080 | #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 | |
4081 | /* enum: Temperature of SODIMM 0 (if installed): degC */ | |
4082 | #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a | |
4083 | /* enum: Temperature of SODIMM 1 (if installed): degC */ | |
4084 | #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b | |
4085 | /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ | |
4086 | #define MC_CMD_SENSOR_PHY0_VCC 0x4c | |
4087 | /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ | |
4088 | #define MC_CMD_SENSOR_PHY1_VCC 0x4d | |
23e202b4 EC |
4089 | /* enum: Controller die temperature (TDIODE): degC */ |
4090 | #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e | |
4091 | /* enum: Board temperature (front): degC */ | |
4092 | #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f | |
4093 | /* enum: Board temperature (back): degC */ | |
4094 | #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 | |
f2b0befd | 4095 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ |
05a9320f BH |
4096 | #define MC_CMD_SENSOR_ENTRY_OFST 4 |
4097 | #define MC_CMD_SENSOR_ENTRY_LEN 8 | |
4098 | #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 | |
4099 | #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 | |
512bb06c | 4100 | #define MC_CMD_SENSOR_ENTRY_MINNUM 0 |
05a9320f BH |
4101 | #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 |
4102 | ||
f2b0befd | 4103 | /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ |
512bb06c | 4104 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 |
f2b0befd BH |
4105 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 |
4106 | #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) | |
4107 | #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 | |
4108 | /* Enum values, see field(s): */ | |
4109 | /* MC_CMD_SENSOR_INFO_OUT */ | |
4110 | #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 | |
4111 | #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 | |
4112 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ | |
4113 | /* MC_CMD_SENSOR_ENTRY_OFST 4 */ | |
4114 | /* MC_CMD_SENSOR_ENTRY_LEN 8 */ | |
4115 | /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ | |
4116 | /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ | |
512bb06c | 4117 | /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ |
f2b0befd BH |
4118 | /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ |
4119 | ||
05a9320f BH |
4120 | /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ |
4121 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 | |
4122 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 | |
4123 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 | |
4124 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 | |
4125 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 | |
4126 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 | |
4127 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 | |
4128 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 | |
4129 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 | |
4130 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 | |
4131 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 | |
4132 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 | |
4133 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 | |
4134 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 | |
4135 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 | |
4136 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 | |
4137 | #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 | |
4138 | ||
4139 | ||
4140 | /***********************************/ | |
f0d37f42 | 4141 | /* MC_CMD_READ_SENSORS |
f2b0befd BH |
4142 | * Returns the current reading from each sensor. DMAs an array of sensor |
4143 | * readings, in order of sensor type (but without gaps for unimplemented | |
4144 | * sensors), into host memory. Each array element is a | |
4145 | * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. | |
4146 | * | |
4147 | * If the request does not contain the LENGTH field then only sensors 0 to 30 | |
4148 | * are reported, to avoid DMA buffer overflow in older host software. If the | |
4149 | * sensor reading require more space than the LENGTH allows, then return | |
4150 | * EINVAL. | |
4151 | * | |
4152 | * The MC will send a SENSOREVT event every time any sensor changes state. The | |
4153 | * driver is responsible for ensuring that it doesn't miss any events. The | |
4154 | * board will function normally if all sensors are in STATE_OK or | |
4155 | * STATE_WARNING. Otherwise the board should not be expected to function. | |
f0d37f42 SH |
4156 | */ |
4157 | #define MC_CMD_READ_SENSORS 0x42 | |
f0d37f42 | 4158 | |
75122ec8 SS |
4159 | #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4160 | ||
05a9320f BH |
4161 | /* MC_CMD_READ_SENSORS_IN msgrequest */ |
4162 | #define MC_CMD_READ_SENSORS_IN_LEN 8 | |
f2b0befd | 4163 | /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ |
05a9320f BH |
4164 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 |
4165 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 | |
4166 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 | |
4167 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 | |
4168 | ||
f2b0befd BH |
4169 | /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ |
4170 | #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 | |
23e202b4 | 4171 | /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ |
f2b0befd BH |
4172 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 |
4173 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 | |
4174 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 | |
4175 | #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 | |
4176 | /* Size in bytes of host buffer. */ | |
4177 | #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 | |
4178 | ||
05a9320f BH |
4179 | /* MC_CMD_READ_SENSORS_OUT msgresponse */ |
4180 | #define MC_CMD_READ_SENSORS_OUT_LEN 0 | |
4181 | ||
f2b0befd BH |
4182 | /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ |
4183 | #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 | |
4184 | ||
05a9320f | 4185 | /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ |
f2b0befd | 4186 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 |
05a9320f BH |
4187 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 |
4188 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 | |
4189 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 | |
4190 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 | |
4191 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 | |
4192 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 | |
f2b0befd BH |
4193 | /* enum: Ok. */ |
4194 | #define MC_CMD_SENSOR_STATE_OK 0x0 | |
4195 | /* enum: Breached warning threshold. */ | |
4196 | #define MC_CMD_SENSOR_STATE_WARNING 0x1 | |
4197 | /* enum: Breached fatal threshold. */ | |
4198 | #define MC_CMD_SENSOR_STATE_FATAL 0x2 | |
4199 | /* enum: Fault with sensor. */ | |
4200 | #define MC_CMD_SENSOR_STATE_BROKEN 0x3 | |
4201 | /* enum: Sensor is working but does not currently have a reading. */ | |
4202 | #define MC_CMD_SENSOR_STATE_NO_READING 0x4 | |
a9196bb0 EC |
4203 | /* enum: Sensor initialisation failed. */ |
4204 | #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 | |
05a9320f BH |
4205 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 |
4206 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 | |
f2b0befd BH |
4207 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 |
4208 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 | |
4209 | /* Enum values, see field(s): */ | |
4210 | /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ | |
4211 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 | |
4212 | #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 | |
05a9320f BH |
4213 | |
4214 | ||
4215 | /***********************************/ | |
4216 | /* MC_CMD_GET_PHY_STATE | |
f2b0befd BH |
4217 | * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot |
4218 | * (e.g. due to missing or corrupted firmware). Locks required: None. Return | |
4219 | * code: 0 | |
f0d37f42 SH |
4220 | */ |
4221 | #define MC_CMD_GET_PHY_STATE 0x43 | |
4222 | ||
75122ec8 SS |
4223 | #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4224 | ||
05a9320f BH |
4225 | /* MC_CMD_GET_PHY_STATE_IN msgrequest */ |
4226 | #define MC_CMD_GET_PHY_STATE_IN_LEN 0 | |
f0d37f42 | 4227 | |
05a9320f BH |
4228 | /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ |
4229 | #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 | |
4230 | #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 | |
f2b0befd BH |
4231 | /* enum: Ok. */ |
4232 | #define MC_CMD_PHY_STATE_OK 0x1 | |
4233 | /* enum: Faulty. */ | |
4234 | #define MC_CMD_PHY_STATE_ZOMBIE 0x2 | |
f0d37f42 | 4235 | |
05a9320f BH |
4236 | |
4237 | /***********************************/ | |
4238 | /* MC_CMD_SETUP_8021QBB | |
f2b0befd BH |
4239 | * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to |
4240 | * disable 802.Qbb for a given priority. | |
05a9320f | 4241 | */ |
f0d37f42 | 4242 | #define MC_CMD_SETUP_8021QBB 0x44 |
f0d37f42 | 4243 | |
05a9320f BH |
4244 | /* MC_CMD_SETUP_8021QBB_IN msgrequest */ |
4245 | #define MC_CMD_SETUP_8021QBB_IN_LEN 32 | |
4246 | #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 | |
4247 | #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 | |
f0d37f42 | 4248 | |
05a9320f BH |
4249 | /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ |
4250 | #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 | |
f0d37f42 SH |
4251 | |
4252 | ||
05a9320f BH |
4253 | /***********************************/ |
4254 | /* MC_CMD_WOL_FILTER_GET | |
f2b0befd | 4255 | * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS |
f0d37f42 | 4256 | */ |
05a9320f | 4257 | #define MC_CMD_WOL_FILTER_GET 0x45 |
f0d37f42 | 4258 | |
75122ec8 SS |
4259 | #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK |
4260 | ||
05a9320f BH |
4261 | /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ |
4262 | #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 | |
f0d37f42 | 4263 | |
05a9320f BH |
4264 | /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ |
4265 | #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 | |
4266 | #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 | |
f0d37f42 | 4267 | |
f0d37f42 | 4268 | |
05a9320f BH |
4269 | /***********************************/ |
4270 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD | |
f2b0befd BH |
4271 | * Add a protocol offload to NIC for lights-out state. Locks required: None. |
4272 | * Returns: 0, ENOSYS | |
05a9320f BH |
4273 | */ |
4274 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 | |
f0d37f42 | 4275 | |
75122ec8 SS |
4276 | #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK |
4277 | ||
05a9320f BH |
4278 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ |
4279 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 | |
4280 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 | |
4281 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) | |
4282 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 | |
4283 | #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ | |
4284 | #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ | |
4285 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 | |
4286 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 | |
4287 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 | |
4288 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 | |
4289 | ||
4290 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ | |
4291 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 | |
4292 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ | |
4293 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 | |
4294 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 | |
4295 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 | |
4296 | ||
4297 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ | |
4298 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 | |
4299 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ | |
4300 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 | |
4301 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 | |
4302 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 | |
4303 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 | |
4304 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 | |
4305 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 | |
4306 | ||
4307 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ | |
4308 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 | |
4309 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 | |
4310 | ||
4311 | ||
4312 | /***********************************/ | |
4313 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD | |
f2b0befd BH |
4314 | * Remove a protocol offload from NIC for lights-out state. Locks required: |
4315 | * None. Returns: 0, ENOSYS | |
f0d37f42 SH |
4316 | */ |
4317 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 | |
f0d37f42 | 4318 | |
75122ec8 SS |
4319 | #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK |
4320 | ||
05a9320f BH |
4321 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ |
4322 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 | |
4323 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 | |
4324 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 | |
f0d37f42 | 4325 | |
05a9320f BH |
4326 | /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ |
4327 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 | |
f0d37f42 SH |
4328 | |
4329 | ||
05a9320f BH |
4330 | /***********************************/ |
4331 | /* MC_CMD_MAC_RESET_RESTORE | |
f2b0befd | 4332 | * Restore MAC after block reset. Locks required: None. Returns: 0. |
f0d37f42 | 4333 | */ |
f0d37f42 | 4334 | #define MC_CMD_MAC_RESET_RESTORE 0x48 |
f0d37f42 | 4335 | |
05a9320f BH |
4336 | /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ |
4337 | #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 | |
4338 | ||
4339 | /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ | |
4340 | #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 | |
5297a98d | 4341 | |
5297a98d | 4342 | |
05a9320f BH |
4343 | /***********************************/ |
4344 | /* MC_CMD_TESTASSERT | |
f2b0befd BH |
4345 | * Deliberately trigger an assert-detonation in the firmware for testing |
4346 | * purposes (i.e. to allow tests that the driver copes gracefully). Locks | |
4347 | * required: None Returns: 0 | |
05a9320f | 4348 | */ |
5297a98d | 4349 | #define MC_CMD_TESTASSERT 0x49 |
5297a98d | 4350 | |
75122ec8 SS |
4351 | #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4352 | ||
05a9320f BH |
4353 | /* MC_CMD_TESTASSERT_IN msgrequest */ |
4354 | #define MC_CMD_TESTASSERT_IN_LEN 0 | |
4355 | ||
4356 | /* MC_CMD_TESTASSERT_OUT msgresponse */ | |
4357 | #define MC_CMD_TESTASSERT_OUT_LEN 0 | |
4358 | ||
4359 | ||
4360 | /***********************************/ | |
4361 | /* MC_CMD_WORKAROUND | |
f2b0befd BH |
4362 | * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't |
4363 | * understand the given workaround number - which should not be treated as a | |
4364 | * hard error by client code. This op does not imply any semantics about each | |
4365 | * workaround, that's between the driver and the mcfw on a per-workaround | |
4366 | * basis. Locks required: None. Returns: 0, EINVAL . | |
5297a98d BH |
4367 | */ |
4368 | #define MC_CMD_WORKAROUND 0x4a | |
05a9320f | 4369 | |
75122ec8 SS |
4370 | #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4371 | ||
05a9320f BH |
4372 | /* MC_CMD_WORKAROUND_IN msgrequest */ |
4373 | #define MC_CMD_WORKAROUND_IN_LEN 8 | |
a9196bb0 | 4374 | /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ |
05a9320f | 4375 | #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 |
f2b0befd BH |
4376 | /* enum: Bug 17230 work around. */ |
4377 | #define MC_CMD_WORKAROUND_BUG17230 0x1 | |
4378 | /* enum: Bug 35388 work around (unsafe EVQ writes). */ | |
4379 | #define MC_CMD_WORKAROUND_BUG35388 0x2 | |
4380 | /* enum: Bug35017 workaround (A64 tables must be identity map) */ | |
4381 | #define MC_CMD_WORKAROUND_BUG35017 0x3 | |
a9196bb0 EC |
4382 | /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ |
4383 | #define MC_CMD_WORKAROUND_BUG41750 0x4 | |
4384 | /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution | |
4385 | * - before adding code that queries this workaround, remember that there's | |
4386 | * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, | |
4387 | * and will hence (incorrectly) report that the bug doesn't exist. | |
4388 | */ | |
4389 | #define MC_CMD_WORKAROUND_BUG42008 0x5 | |
4390 | /* enum: Bug 26807 features present in firmware (multicast filter chaining) | |
4391 | * This feature cannot be turned on/off while there are any filters already | |
4392 | * present. The behaviour in such case depends on the acting client's privilege | |
4393 | * level. If the client has the admin privilege, then all functions that have | |
4394 | * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise | |
4395 | * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. | |
4396 | */ | |
4397 | #define MC_CMD_WORKAROUND_BUG26807 0x6 | |
d29e33d6 BK |
4398 | /* enum: Bug 61265 work around (broken EVQ TMR writes). */ |
4399 | #define MC_CMD_WORKAROUND_BUG61265 0x7 | |
a9196bb0 EC |
4400 | /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable |
4401 | * the workaround | |
4402 | */ | |
05a9320f BH |
4403 | #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 |
4404 | ||
4405 | /* MC_CMD_WORKAROUND_OUT msgresponse */ | |
4406 | #define MC_CMD_WORKAROUND_OUT_LEN 0 | |
4407 | ||
a9196bb0 EC |
4408 | /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used |
4409 | * when (TYPE == MC_CMD_WORKAROUND_BUG26807) | |
4410 | */ | |
4411 | #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 | |
4412 | #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 | |
4413 | #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 | |
4414 | #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 | |
4415 | ||
05a9320f BH |
4416 | |
4417 | /***********************************/ | |
4418 | /* MC_CMD_GET_PHY_MEDIA_INFO | |
f2b0befd BH |
4419 | * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for |
4420 | * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG | |
4421 | * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the | |
4422 | * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 | |
4423 | * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. | |
5297a98d BH |
4424 | */ |
4425 | #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b | |
05a9320f | 4426 | |
75122ec8 SS |
4427 | #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4428 | ||
05a9320f BH |
4429 | /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ |
4430 | #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 | |
4431 | #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 | |
4432 | ||
4433 | /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ | |
4434 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 | |
576eda8b | 4435 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 |
05a9320f | 4436 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) |
f2b0befd | 4437 | /* in bytes */ |
05a9320f BH |
4438 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 |
4439 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 | |
4440 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 | |
4441 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 | |
576eda8b | 4442 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 |
05a9320f BH |
4443 | |
4444 | ||
4445 | /***********************************/ | |
4446 | /* MC_CMD_NVRAM_TEST | |
f2b0befd BH |
4447 | * Test a particular NVRAM partition for valid contents (where "valid" depends |
4448 | * on the type of partition). | |
5297a98d BH |
4449 | */ |
4450 | #define MC_CMD_NVRAM_TEST 0x4c | |
05a9320f | 4451 | |
75122ec8 SS |
4452 | #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4453 | ||
05a9320f BH |
4454 | /* MC_CMD_NVRAM_TEST_IN msgrequest */ |
4455 | #define MC_CMD_NVRAM_TEST_IN_LEN 4 | |
4456 | #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 | |
4457 | /* Enum values, see field(s): */ | |
4458 | /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ | |
4459 | ||
4460 | /* MC_CMD_NVRAM_TEST_OUT msgresponse */ | |
4461 | #define MC_CMD_NVRAM_TEST_OUT_LEN 4 | |
4462 | #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 | |
f2b0befd BH |
4463 | /* enum: Passed. */ |
4464 | #define MC_CMD_NVRAM_TEST_PASS 0x0 | |
4465 | /* enum: Failed. */ | |
4466 | #define MC_CMD_NVRAM_TEST_FAIL 0x1 | |
4467 | /* enum: Not supported. */ | |
4468 | #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 | |
05a9320f BH |
4469 | |
4470 | ||
4471 | /***********************************/ | |
4472 | /* MC_CMD_MRSFP_TWEAK | |
f2b0befd BH |
4473 | * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. |
4474 | * I2C I/O expander bits are always read; if equaliser parameters are supplied, | |
4475 | * they are configured first. Locks required: None. Return code: 0, EINVAL. | |
5297a98d BH |
4476 | */ |
4477 | #define MC_CMD_MRSFP_TWEAK 0x4d | |
05a9320f BH |
4478 | |
4479 | /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ | |
4480 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 | |
f2b0befd | 4481 | /* 0-6 low->high de-emph. */ |
05a9320f | 4482 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 |
f2b0befd | 4483 | /* 0-8 low->high ref.V */ |
05a9320f | 4484 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 |
f2b0befd | 4485 | /* 0-8 0-8 low->high boost */ |
05a9320f | 4486 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 |
f2b0befd | 4487 | /* 0-8 low->high ref.V */ |
05a9320f BH |
4488 | #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 |
4489 | ||
4490 | /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ | |
4491 | #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 | |
4492 | ||
4493 | /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ | |
4494 | #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 | |
f2b0befd | 4495 | /* input bits */ |
05a9320f | 4496 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 |
f2b0befd | 4497 | /* output bits */ |
05a9320f | 4498 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 |
f2b0befd | 4499 | /* direction */ |
05a9320f | 4500 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 |
f2b0befd BH |
4501 | /* enum: Out. */ |
4502 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 | |
4503 | /* enum: In. */ | |
4504 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 | |
05a9320f BH |
4505 | |
4506 | ||
4507 | /***********************************/ | |
4508 | /* MC_CMD_SENSOR_SET_LIMS | |
f2b0befd BH |
4509 | * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: |
4510 | * ENOENT if the sensor specified does not exist, EINVAL if the limits are out | |
4511 | * of range. | |
fbcfe8e1 BH |
4512 | */ |
4513 | #define MC_CMD_SENSOR_SET_LIMS 0x4e | |
05a9320f | 4514 | |
75122ec8 SS |
4515 | #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4516 | ||
05a9320f BH |
4517 | /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ |
4518 | #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 | |
4519 | #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 | |
4520 | /* Enum values, see field(s): */ | |
4521 | /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ | |
f2b0befd | 4522 | /* interpretation is is sensor-specific. */ |
05a9320f | 4523 | #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 |
f2b0befd | 4524 | /* interpretation is is sensor-specific. */ |
05a9320f | 4525 | #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 |
f2b0befd | 4526 | /* interpretation is is sensor-specific. */ |
05a9320f | 4527 | #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 |
f2b0befd | 4528 | /* interpretation is is sensor-specific. */ |
05a9320f BH |
4529 | #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 |
4530 | ||
4531 | /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ | |
4532 | #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 | |
4533 | ||
4534 | ||
4535 | /***********************************/ | |
4536 | /* MC_CMD_GET_RESOURCE_LIMITS | |
4537 | */ | |
4538 | #define MC_CMD_GET_RESOURCE_LIMITS 0x4f | |
4539 | ||
4540 | /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ | |
4541 | #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 | |
4542 | ||
4543 | /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ | |
4544 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 | |
4545 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 | |
4546 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 | |
4547 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 | |
4548 | #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 | |
4549 | ||
f2b0befd BH |
4550 | |
4551 | /***********************************/ | |
4552 | /* MC_CMD_NVRAM_PARTITIONS | |
4553 | * Reads the list of available virtual NVRAM partition types. Locks required: | |
4554 | * none. Returns: 0, EINVAL (bad type). | |
4555 | */ | |
4556 | #define MC_CMD_NVRAM_PARTITIONS 0x51 | |
4557 | ||
75122ec8 SS |
4558 | #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4559 | ||
f2b0befd BH |
4560 | /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ |
4561 | #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 | |
4562 | ||
4563 | /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ | |
4564 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 | |
4565 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 | |
4566 | #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) | |
4567 | /* total number of partitions */ | |
4568 | #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 | |
4569 | /* type ID code for each of NUM_PARTITIONS partitions */ | |
4570 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 | |
4571 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 | |
4572 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 | |
4573 | #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 | |
4574 | ||
4575 | ||
4576 | /***********************************/ | |
4577 | /* MC_CMD_NVRAM_METADATA | |
4578 | * Reads soft metadata for a virtual NVRAM partition type. Locks required: | |
4579 | * none. Returns: 0, EINVAL (bad type). | |
4580 | */ | |
4581 | #define MC_CMD_NVRAM_METADATA 0x52 | |
4582 | ||
75122ec8 SS |
4583 | #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
4584 | ||
f2b0befd BH |
4585 | /* MC_CMD_NVRAM_METADATA_IN msgrequest */ |
4586 | #define MC_CMD_NVRAM_METADATA_IN_LEN 4 | |
4587 | /* Partition type ID code */ | |
4588 | #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 | |
4589 | ||
4590 | /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ | |
4591 | #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 | |
4592 | #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 | |
4593 | #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) | |
4594 | /* Partition type ID code */ | |
4595 | #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 | |
4596 | #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 | |
4597 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 | |
4598 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 | |
4599 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 | |
4600 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 | |
4601 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 | |
4602 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 | |
4603 | /* Subtype ID code for content of this partition */ | |
4604 | #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 | |
4605 | /* 1st component of W.X.Y.Z version number for content of this partition */ | |
4606 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 | |
4607 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 | |
4608 | /* 2nd component of W.X.Y.Z version number for content of this partition */ | |
4609 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 | |
4610 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 | |
4611 | /* 3rd component of W.X.Y.Z version number for content of this partition */ | |
4612 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 | |
4613 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 | |
4614 | /* 4th component of W.X.Y.Z version number for content of this partition */ | |
4615 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 | |
4616 | #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 | |
4617 | /* Zero-terminated string describing the content of this partition */ | |
4618 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 | |
4619 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 | |
4620 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 | |
4621 | #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 | |
4622 | ||
4623 | ||
4624 | /***********************************/ | |
4625 | /* MC_CMD_GET_MAC_ADDRESSES | |
a9196bb0 | 4626 | * Returns the base MAC, count and stride for the requesting function |
f2b0befd BH |
4627 | */ |
4628 | #define MC_CMD_GET_MAC_ADDRESSES 0x55 | |
4629 | ||
75122ec8 SS |
4630 | #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
4631 | ||
f2b0befd BH |
4632 | /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ |
4633 | #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 | |
4634 | ||
4635 | /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ | |
4636 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 | |
4637 | /* Base MAC address */ | |
4638 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 | |
4639 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 | |
4640 | /* Padding */ | |
4641 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 | |
4642 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 | |
4643 | /* Number of allocated MAC addresses */ | |
4644 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 | |
4645 | /* Spacing of allocated MAC addresses */ | |
4646 | #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 | |
4647 | ||
a9196bb0 EC |
4648 | |
4649 | /***********************************/ | |
4650 | /* MC_CMD_CLP | |
4651 | * Perform a CLP related operation | |
4652 | */ | |
4653 | #define MC_CMD_CLP 0x56 | |
4654 | ||
4655 | #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
4656 | ||
4657 | /* MC_CMD_CLP_IN msgrequest */ | |
4658 | #define MC_CMD_CLP_IN_LEN 4 | |
4659 | /* Sub operation */ | |
4660 | #define MC_CMD_CLP_IN_OP_OFST 0 | |
4661 | /* enum: Return to factory default settings */ | |
4662 | #define MC_CMD_CLP_OP_DEFAULT 0x1 | |
4663 | /* enum: Set MAC address */ | |
4664 | #define MC_CMD_CLP_OP_SET_MAC 0x2 | |
4665 | /* enum: Get MAC address */ | |
4666 | #define MC_CMD_CLP_OP_GET_MAC 0x3 | |
4667 | /* enum: Set UEFI/GPXE boot mode */ | |
4668 | #define MC_CMD_CLP_OP_SET_BOOT 0x4 | |
4669 | /* enum: Get UEFI/GPXE boot mode */ | |
4670 | #define MC_CMD_CLP_OP_GET_BOOT 0x5 | |
4671 | ||
4672 | /* MC_CMD_CLP_OUT msgresponse */ | |
4673 | #define MC_CMD_CLP_OUT_LEN 0 | |
4674 | ||
4675 | /* MC_CMD_CLP_IN_DEFAULT msgrequest */ | |
4676 | #define MC_CMD_CLP_IN_DEFAULT_LEN 4 | |
4677 | /* MC_CMD_CLP_IN_OP_OFST 0 */ | |
4678 | ||
4679 | /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ | |
4680 | #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 | |
4681 | ||
4682 | /* MC_CMD_CLP_IN_SET_MAC msgrequest */ | |
4683 | #define MC_CMD_CLP_IN_SET_MAC_LEN 12 | |
4684 | /* MC_CMD_CLP_IN_OP_OFST 0 */ | |
4685 | /* MAC address assigned to port */ | |
4686 | #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 | |
4687 | #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 | |
4688 | /* Padding */ | |
4689 | #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 | |
4690 | #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 | |
4691 | ||
4692 | /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ | |
4693 | #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 | |
4694 | ||
4695 | /* MC_CMD_CLP_IN_GET_MAC msgrequest */ | |
4696 | #define MC_CMD_CLP_IN_GET_MAC_LEN 4 | |
4697 | /* MC_CMD_CLP_IN_OP_OFST 0 */ | |
4698 | ||
4699 | /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ | |
4700 | #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 | |
4701 | /* MAC address assigned to port */ | |
4702 | #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 | |
4703 | #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 | |
4704 | /* Padding */ | |
4705 | #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 | |
4706 | #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 | |
4707 | ||
4708 | /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ | |
4709 | #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 | |
4710 | /* MC_CMD_CLP_IN_OP_OFST 0 */ | |
4711 | /* Boot flag */ | |
4712 | #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 | |
4713 | #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 | |
4714 | ||
4715 | /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ | |
4716 | #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 | |
4717 | ||
4718 | /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ | |
4719 | #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 | |
4720 | /* MC_CMD_CLP_IN_OP_OFST 0 */ | |
4721 | ||
4722 | /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ | |
4723 | #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 | |
4724 | /* Boot flag */ | |
4725 | #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 | |
4726 | #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 | |
4727 | /* Padding */ | |
4728 | #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 | |
4729 | #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 | |
4730 | ||
4731 | ||
4732 | /***********************************/ | |
4733 | /* MC_CMD_MUM | |
4734 | * Perform a MUM operation | |
4735 | */ | |
4736 | #define MC_CMD_MUM 0x57 | |
4737 | ||
4738 | #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
4739 | ||
4740 | /* MC_CMD_MUM_IN msgrequest */ | |
4741 | #define MC_CMD_MUM_IN_LEN 4 | |
4742 | #define MC_CMD_MUM_IN_OP_HDR_OFST 0 | |
4743 | #define MC_CMD_MUM_IN_OP_LBN 0 | |
4744 | #define MC_CMD_MUM_IN_OP_WIDTH 8 | |
4745 | /* enum: NULL MCDI command to MUM */ | |
4746 | #define MC_CMD_MUM_OP_NULL 0x1 | |
4747 | /* enum: Get MUM version */ | |
4748 | #define MC_CMD_MUM_OP_GET_VERSION 0x2 | |
4749 | /* enum: Issue raw I2C command to MUM */ | |
4750 | #define MC_CMD_MUM_OP_RAW_CMD 0x3 | |
4751 | /* enum: Read from registers on devices connected to MUM. */ | |
4752 | #define MC_CMD_MUM_OP_READ 0x4 | |
4753 | /* enum: Write to registers on devices connected to MUM. */ | |
4754 | #define MC_CMD_MUM_OP_WRITE 0x5 | |
4755 | /* enum: Control UART logging. */ | |
4756 | #define MC_CMD_MUM_OP_LOG 0x6 | |
4757 | /* enum: Operations on MUM GPIO lines */ | |
4758 | #define MC_CMD_MUM_OP_GPIO 0x7 | |
4759 | /* enum: Get sensor readings from MUM */ | |
4760 | #define MC_CMD_MUM_OP_READ_SENSORS 0x8 | |
4761 | /* enum: Initiate clock programming on the MUM */ | |
4762 | #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 | |
4763 | /* enum: Initiate FPGA load from flash on the MUM */ | |
4764 | #define MC_CMD_MUM_OP_FPGA_LOAD 0xa | |
4765 | /* enum: Request sensor reading from MUM ADC resulting from earlier request via | |
4766 | * MUM ATB | |
4767 | */ | |
4768 | #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb | |
4769 | /* enum: Send commands relating to the QSFP ports via the MUM for PHY | |
4770 | * operations | |
4771 | */ | |
4772 | #define MC_CMD_MUM_OP_QSFP 0xc | |
23e202b4 EC |
4773 | /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage |
4774 | * level) from MUM | |
4775 | */ | |
4776 | #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd | |
a9196bb0 EC |
4777 | |
4778 | /* MC_CMD_MUM_IN_NULL msgrequest */ | |
4779 | #define MC_CMD_MUM_IN_NULL_LEN 4 | |
4780 | /* MUM cmd header */ | |
4781 | #define MC_CMD_MUM_IN_CMD_OFST 0 | |
4782 | ||
4783 | /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ | |
4784 | #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 | |
4785 | /* MUM cmd header */ | |
4786 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4787 | ||
4788 | /* MC_CMD_MUM_IN_READ msgrequest */ | |
4789 | #define MC_CMD_MUM_IN_READ_LEN 16 | |
4790 | /* MUM cmd header */ | |
4791 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4792 | /* ID of (device connected to MUM) to read from registers of */ | |
4793 | #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 | |
4794 | /* enum: Hittite HMC1035 clock generator on Sorrento board */ | |
4795 | #define MC_CMD_MUM_DEV_HITTITE 0x1 | |
4796 | /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ | |
4797 | #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 | |
4798 | /* 32-bit address to read from */ | |
4799 | #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 | |
4800 | /* Number of words to read. */ | |
4801 | #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 | |
4802 | ||
4803 | /* MC_CMD_MUM_IN_WRITE msgrequest */ | |
4804 | #define MC_CMD_MUM_IN_WRITE_LENMIN 16 | |
4805 | #define MC_CMD_MUM_IN_WRITE_LENMAX 252 | |
4806 | #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) | |
4807 | /* MUM cmd header */ | |
4808 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4809 | /* ID of (device connected to MUM) to write to registers of */ | |
4810 | #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 | |
4811 | /* enum: Hittite HMC1035 clock generator on Sorrento board */ | |
4812 | /* MC_CMD_MUM_DEV_HITTITE 0x1 */ | |
4813 | /* 32-bit address to write to */ | |
4814 | #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 | |
4815 | /* Words to write */ | |
4816 | #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 | |
4817 | #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 | |
4818 | #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 | |
4819 | #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 | |
4820 | ||
4821 | /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ | |
4822 | #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 | |
4823 | #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 | |
4824 | #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) | |
4825 | /* MUM cmd header */ | |
4826 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4827 | /* MUM I2C cmd code */ | |
4828 | #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 | |
4829 | /* Number of bytes to write */ | |
4830 | #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 | |
4831 | /* Number of bytes to read */ | |
4832 | #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 | |
4833 | /* Bytes to write */ | |
4834 | #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 | |
4835 | #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 | |
4836 | #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 | |
4837 | #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 | |
4838 | ||
4839 | /* MC_CMD_MUM_IN_LOG msgrequest */ | |
4840 | #define MC_CMD_MUM_IN_LOG_LEN 8 | |
4841 | /* MUM cmd header */ | |
4842 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4843 | #define MC_CMD_MUM_IN_LOG_OP_OFST 4 | |
4844 | #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ | |
4845 | ||
4846 | /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ | |
4847 | #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 | |
4848 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4849 | /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ | |
4850 | /* Enable/disable debug output to UART */ | |
4851 | #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 | |
4852 | ||
4853 | /* MC_CMD_MUM_IN_GPIO msgrequest */ | |
4854 | #define MC_CMD_MUM_IN_GPIO_LEN 8 | |
4855 | /* MUM cmd header */ | |
4856 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4857 | #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 | |
4858 | #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 | |
4859 | #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 | |
4860 | #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ | |
4861 | #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ | |
4862 | #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ | |
4863 | #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ | |
4864 | #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ | |
4865 | #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ | |
4866 | ||
4867 | /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ | |
4868 | #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 | |
4869 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4870 | #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 | |
4871 | ||
4872 | /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ | |
4873 | #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 | |
4874 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4875 | #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 | |
4876 | /* The first 32-bit word to be written to the GPIO OUT register. */ | |
4877 | #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 | |
4878 | /* The second 32-bit word to be written to the GPIO OUT register. */ | |
4879 | #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 | |
4880 | ||
4881 | /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ | |
4882 | #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 | |
4883 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4884 | #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 | |
4885 | ||
4886 | /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ | |
4887 | #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 | |
4888 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4889 | #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 | |
4890 | /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ | |
4891 | #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 | |
4892 | /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ | |
4893 | #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 | |
4894 | ||
4895 | /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ | |
4896 | #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 | |
4897 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4898 | #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 | |
4899 | ||
4900 | /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ | |
4901 | #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 | |
4902 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4903 | #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 | |
4904 | #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 | |
4905 | #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 | |
4906 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ | |
4907 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ | |
4908 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ | |
4909 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ | |
4910 | #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 | |
4911 | #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 | |
4912 | ||
4913 | /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ | |
4914 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 | |
4915 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4916 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 | |
4917 | ||
4918 | /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ | |
4919 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 | |
4920 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4921 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 | |
4922 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 | |
4923 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 | |
4924 | ||
4925 | /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ | |
4926 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 | |
4927 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4928 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 | |
4929 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 | |
4930 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 | |
4931 | ||
4932 | /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ | |
4933 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 | |
4934 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4935 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 | |
4936 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 | |
4937 | #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 | |
4938 | ||
4939 | /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ | |
4940 | #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 | |
4941 | /* MUM cmd header */ | |
4942 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4943 | #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 | |
4944 | #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 | |
4945 | #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 | |
4946 | #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 | |
4947 | #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 | |
4948 | ||
4949 | /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ | |
4950 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 | |
4951 | /* MUM cmd header */ | |
4952 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4953 | /* Bit-mask of clocks to be programmed */ | |
4954 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 | |
4955 | #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ | |
4956 | #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ | |
4957 | #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ | |
4958 | /* Control flags for clock programming */ | |
4959 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 | |
4960 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 | |
4961 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 | |
23e202b4 EC |
4962 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 |
4963 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 | |
4964 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 | |
4965 | #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 | |
a9196bb0 EC |
4966 | |
4967 | /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ | |
4968 | #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 | |
4969 | /* MUM cmd header */ | |
4970 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4971 | /* Enable/Disable FPGA config from flash */ | |
4972 | #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 | |
4973 | ||
4974 | /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ | |
4975 | #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 | |
4976 | /* MUM cmd header */ | |
4977 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4978 | ||
4979 | /* MC_CMD_MUM_IN_QSFP msgrequest */ | |
4980 | #define MC_CMD_MUM_IN_QSFP_LEN 12 | |
4981 | /* MUM cmd header */ | |
4982 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4983 | #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 | |
4984 | #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 | |
4985 | #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 | |
4986 | #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ | |
4987 | #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ | |
4988 | #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ | |
4989 | #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ | |
4990 | #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ | |
4991 | #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ | |
4992 | #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 | |
4993 | ||
4994 | /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ | |
4995 | #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 | |
4996 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
4997 | #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 | |
4998 | #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 | |
4999 | #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 | |
5000 | ||
5001 | /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ | |
5002 | #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 | |
5003 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
5004 | #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 | |
5005 | #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 | |
5006 | #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 | |
5007 | #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 | |
5008 | #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 | |
5009 | ||
5010 | /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ | |
5011 | #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 | |
5012 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
5013 | #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 | |
5014 | #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 | |
5015 | ||
5016 | /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ | |
5017 | #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 | |
5018 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
5019 | #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 | |
5020 | #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 | |
5021 | #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 | |
5022 | ||
5023 | /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ | |
5024 | #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 | |
5025 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
5026 | #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 | |
5027 | #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 | |
5028 | ||
5029 | /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ | |
5030 | #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 | |
5031 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
5032 | #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 | |
5033 | #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 | |
5034 | ||
23e202b4 EC |
5035 | /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ |
5036 | #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 | |
5037 | /* MUM cmd header */ | |
5038 | /* MC_CMD_MUM_IN_CMD_OFST 0 */ | |
5039 | ||
a9196bb0 EC |
5040 | /* MC_CMD_MUM_OUT msgresponse */ |
5041 | #define MC_CMD_MUM_OUT_LEN 0 | |
5042 | ||
5043 | /* MC_CMD_MUM_OUT_NULL msgresponse */ | |
5044 | #define MC_CMD_MUM_OUT_NULL_LEN 0 | |
5045 | ||
5046 | /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ | |
5047 | #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 | |
5048 | #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 | |
5049 | #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 | |
5050 | #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 | |
5051 | #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 | |
5052 | #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 | |
5053 | ||
5054 | /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ | |
5055 | #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 | |
5056 | #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 | |
5057 | #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) | |
5058 | /* returned data */ | |
5059 | #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 | |
5060 | #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 | |
5061 | #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 | |
5062 | #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 | |
5063 | ||
5064 | /* MC_CMD_MUM_OUT_READ msgresponse */ | |
5065 | #define MC_CMD_MUM_OUT_READ_LENMIN 4 | |
5066 | #define MC_CMD_MUM_OUT_READ_LENMAX 252 | |
5067 | #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) | |
5068 | #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 | |
5069 | #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 | |
5070 | #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 | |
5071 | #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 | |
5072 | ||
5073 | /* MC_CMD_MUM_OUT_WRITE msgresponse */ | |
5074 | #define MC_CMD_MUM_OUT_WRITE_LEN 0 | |
5075 | ||
5076 | /* MC_CMD_MUM_OUT_LOG msgresponse */ | |
5077 | #define MC_CMD_MUM_OUT_LOG_LEN 0 | |
5078 | ||
5079 | /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ | |
5080 | #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 | |
5081 | ||
5082 | /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ | |
5083 | #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 | |
5084 | /* The first 32-bit word read from the GPIO IN register. */ | |
5085 | #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 | |
5086 | /* The second 32-bit word read from the GPIO IN register. */ | |
5087 | #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 | |
5088 | ||
5089 | /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ | |
5090 | #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 | |
5091 | ||
5092 | /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ | |
5093 | #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 | |
5094 | /* The first 32-bit word read from the GPIO OUT register. */ | |
5095 | #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 | |
5096 | /* The second 32-bit word read from the GPIO OUT register. */ | |
5097 | #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 | |
5098 | ||
5099 | /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ | |
5100 | #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 | |
5101 | ||
5102 | /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ | |
5103 | #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 | |
5104 | #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 | |
5105 | #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 | |
5106 | ||
5107 | /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ | |
5108 | #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 | |
5109 | #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 | |
5110 | ||
5111 | /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ | |
5112 | #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 | |
5113 | ||
5114 | /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ | |
5115 | #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 | |
5116 | ||
5117 | /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ | |
5118 | #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 | |
5119 | ||
5120 | /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ | |
5121 | #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 | |
5122 | #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 | |
5123 | #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) | |
5124 | #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 | |
5125 | #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 | |
5126 | #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 | |
5127 | #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 | |
5128 | #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 | |
5129 | #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 | |
5130 | #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 | |
5131 | #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 | |
5132 | #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 | |
5133 | #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 | |
5134 | ||
5135 | /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ | |
5136 | #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 | |
5137 | #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 | |
5138 | ||
5139 | /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ | |
5140 | #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 | |
5141 | ||
5142 | /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ | |
5143 | #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 | |
5144 | #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 | |
5145 | ||
5146 | /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ | |
5147 | #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 | |
5148 | ||
5149 | /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ | |
5150 | #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 | |
5151 | #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 | |
5152 | #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 | |
5153 | #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 | |
5154 | #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 | |
5155 | #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 | |
5156 | #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 | |
5157 | ||
5158 | /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ | |
5159 | #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 | |
5160 | #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 | |
5161 | ||
5162 | /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ | |
5163 | #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 | |
5164 | #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 | |
5165 | #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) | |
5166 | /* in bytes */ | |
5167 | #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 | |
5168 | #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 | |
5169 | #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 | |
5170 | #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 | |
5171 | #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 | |
5172 | ||
5173 | /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ | |
5174 | #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 | |
5175 | #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 | |
5176 | #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 | |
5177 | ||
5178 | /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ | |
5179 | #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 | |
5180 | #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 | |
5181 | ||
23e202b4 EC |
5182 | /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ |
5183 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 | |
5184 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 | |
5185 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) | |
5186 | /* Discrete (soldered) DDR resistor strap info */ | |
5187 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 | |
5188 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 | |
5189 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 | |
5190 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 | |
5191 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 | |
5192 | /* Number of SODIMM info records */ | |
5193 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 | |
5194 | /* Array of SODIMM info records */ | |
5195 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 | |
5196 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 | |
5197 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 | |
5198 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 | |
5199 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 | |
5200 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 | |
5201 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 | |
5202 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 | |
5203 | /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ | |
5204 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 | |
5205 | /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ | |
5206 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 | |
5207 | /* enum: Total number of SODIMM banks */ | |
5208 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 | |
5209 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 | |
5210 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 | |
5211 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 | |
5212 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 | |
5213 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 | |
5214 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 | |
5215 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ | |
5216 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ | |
5217 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ | |
5218 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ | |
5219 | /* enum: Values 5-15 are reserved for future usage */ | |
5220 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 | |
5221 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 | |
5222 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 | |
5223 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 | |
5224 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 | |
5225 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 | |
5226 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 | |
5227 | /* enum: No module present */ | |
5228 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 | |
5229 | /* enum: Module present supported and powered on */ | |
5230 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 | |
5231 | /* enum: Module present but bad type */ | |
5232 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 | |
5233 | /* enum: Module present but incompatible voltage */ | |
5234 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 | |
5235 | /* enum: Module present but unknown SPD */ | |
5236 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 | |
5237 | /* enum: Module present but slot cannot support it */ | |
5238 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 | |
5239 | /* enum: Modules may or may not be present, but cannot establish contact by I2C | |
5240 | */ | |
5241 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 | |
5242 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 | |
5243 | #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 | |
5244 | ||
05a9320f | 5245 | /* MC_CMD_RESOURCE_SPECIFIER enum */ |
f2b0befd BH |
5246 | /* enum: Any */ |
5247 | #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff | |
5248 | /* enum: None */ | |
5249 | #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe | |
5250 | ||
5251 | /* EVB_PORT_ID structuredef */ | |
5252 | #define EVB_PORT_ID_LEN 4 | |
5253 | #define EVB_PORT_ID_PORT_ID_OFST 0 | |
5254 | /* enum: An invalid port handle. */ | |
5255 | #define EVB_PORT_ID_NULL 0x0 | |
5256 | /* enum: The port assigned to this function.. */ | |
5257 | #define EVB_PORT_ID_ASSIGNED 0x1000000 | |
5258 | /* enum: External network port 0 */ | |
5259 | #define EVB_PORT_ID_MAC0 0x2000000 | |
5260 | /* enum: External network port 1 */ | |
5261 | #define EVB_PORT_ID_MAC1 0x2000001 | |
5262 | /* enum: External network port 2 */ | |
5263 | #define EVB_PORT_ID_MAC2 0x2000002 | |
5264 | /* enum: External network port 3 */ | |
5265 | #define EVB_PORT_ID_MAC3 0x2000003 | |
5266 | #define EVB_PORT_ID_PORT_ID_LBN 0 | |
5267 | #define EVB_PORT_ID_PORT_ID_WIDTH 32 | |
5268 | ||
5269 | /* EVB_VLAN_TAG structuredef */ | |
5270 | #define EVB_VLAN_TAG_LEN 2 | |
5271 | /* The VLAN tag value */ | |
5272 | #define EVB_VLAN_TAG_VLAN_ID_LBN 0 | |
5273 | #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 | |
5274 | #define EVB_VLAN_TAG_MODE_LBN 12 | |
5275 | #define EVB_VLAN_TAG_MODE_WIDTH 4 | |
5276 | /* enum: Insert the VLAN. */ | |
5277 | #define EVB_VLAN_TAG_INSERT 0x0 | |
5278 | /* enum: Replace the VLAN if already present. */ | |
5279 | #define EVB_VLAN_TAG_REPLACE 0x1 | |
5280 | ||
5281 | /* BUFTBL_ENTRY structuredef */ | |
5282 | #define BUFTBL_ENTRY_LEN 12 | |
5283 | /* the owner ID */ | |
5284 | #define BUFTBL_ENTRY_OID_OFST 0 | |
5285 | #define BUFTBL_ENTRY_OID_LEN 2 | |
5286 | #define BUFTBL_ENTRY_OID_LBN 0 | |
5287 | #define BUFTBL_ENTRY_OID_WIDTH 16 | |
5288 | /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ | |
5289 | #define BUFTBL_ENTRY_PGSZ_OFST 2 | |
5290 | #define BUFTBL_ENTRY_PGSZ_LEN 2 | |
5291 | #define BUFTBL_ENTRY_PGSZ_LBN 16 | |
5292 | #define BUFTBL_ENTRY_PGSZ_WIDTH 16 | |
5293 | /* the raw 64-bit address field from the SMC, not adjusted for page size */ | |
5294 | #define BUFTBL_ENTRY_RAWADDR_OFST 4 | |
5295 | #define BUFTBL_ENTRY_RAWADDR_LEN 8 | |
5296 | #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 | |
5297 | #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 | |
5298 | #define BUFTBL_ENTRY_RAWADDR_LBN 32 | |
5299 | #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 | |
5300 | ||
5301 | /* NVRAM_PARTITION_TYPE structuredef */ | |
5302 | #define NVRAM_PARTITION_TYPE_LEN 2 | |
5303 | #define NVRAM_PARTITION_TYPE_ID_OFST 0 | |
5304 | #define NVRAM_PARTITION_TYPE_ID_LEN 2 | |
5305 | /* enum: Primary MC firmware partition */ | |
5306 | #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 | |
5307 | /* enum: Secondary MC firmware partition */ | |
5308 | #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 | |
5309 | /* enum: Expansion ROM partition */ | |
5310 | #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 | |
5311 | /* enum: Static configuration TLV partition */ | |
5312 | #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 | |
5313 | /* enum: Dynamic configuration TLV partition */ | |
5314 | #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 | |
5315 | /* enum: Expansion ROM configuration data for port 0 */ | |
5316 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 | |
23e202b4 EC |
5317 | /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ |
5318 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 | |
f2b0befd BH |
5319 | /* enum: Expansion ROM configuration data for port 1 */ |
5320 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 | |
5321 | /* enum: Expansion ROM configuration data for port 2 */ | |
5322 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 | |
5323 | /* enum: Expansion ROM configuration data for port 3 */ | |
5324 | #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 | |
5325 | /* enum: Non-volatile log output partition */ | |
5326 | #define NVRAM_PARTITION_TYPE_LOG 0x700 | |
23e202b4 EC |
5327 | /* enum: Non-volatile log output of second core on dual-core device */ |
5328 | #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 | |
f2b0befd BH |
5329 | /* enum: Device state dump output partition */ |
5330 | #define NVRAM_PARTITION_TYPE_DUMP 0x800 | |
5331 | /* enum: Application license key storage partition */ | |
5332 | #define NVRAM_PARTITION_TYPE_LICENSE 0x900 | |
bedca866 MS |
5333 | /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ |
5334 | #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 | |
5335 | /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ | |
5336 | #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff | |
a9196bb0 EC |
5337 | /* enum: Primary FPGA partition */ |
5338 | #define NVRAM_PARTITION_TYPE_FPGA 0xb00 | |
5339 | /* enum: Secondary FPGA partition */ | |
5340 | #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 | |
5341 | /* enum: FC firmware partition */ | |
5342 | #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 | |
5343 | /* enum: FC License partition */ | |
5344 | #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 | |
5345 | /* enum: Non-volatile log output partition for FC */ | |
5346 | #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 | |
5347 | /* enum: MUM firmware partition */ | |
5348 | #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 | |
5349 | /* enum: MUM Non-volatile log output partition. */ | |
5350 | #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 | |
5351 | /* enum: MUM Application table partition. */ | |
5352 | #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 | |
5353 | /* enum: MUM boot rom partition. */ | |
5354 | #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 | |
5355 | /* enum: MUM production signatures & calibration rom partition. */ | |
5356 | #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 | |
5357 | /* enum: MUM user signatures & calibration rom partition. */ | |
5358 | #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 | |
5359 | /* enum: MUM fuses and lockbits partition. */ | |
5360 | #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 | |
23e202b4 EC |
5361 | /* enum: UEFI expansion ROM if separate from PXE */ |
5362 | #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 | |
5363 | /* enum: Spare partition 0 */ | |
5364 | #define NVRAM_PARTITION_TYPE_SPARE_0 0x1000 | |
5365 | /* enum: Spare partition 1 */ | |
5366 | #define NVRAM_PARTITION_TYPE_SPARE_1 0x1100 | |
5367 | /* enum: Spare partition 2 */ | |
5368 | #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 | |
5369 | /* enum: Spare partition 3 */ | |
5370 | #define NVRAM_PARTITION_TYPE_SPARE_3 0x1300 | |
5371 | /* enum: Spare partition 4 */ | |
5372 | #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 | |
5373 | /* enum: Spare partition 5 */ | |
5374 | #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 | |
f2b0befd BH |
5375 | /* enum: Start of reserved value range (firmware may use for any purpose) */ |
5376 | #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 | |
5377 | /* enum: End of reserved value range (firmware may use for any purpose) */ | |
5378 | #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd | |
5379 | /* enum: Recovery partition map (provided if real map is missing or corrupt) */ | |
5380 | #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe | |
5381 | /* enum: Partition map (real map as stored in flash) */ | |
5382 | #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff | |
5383 | #define NVRAM_PARTITION_TYPE_ID_LBN 0 | |
5384 | #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 | |
5385 | ||
512bb06c BH |
5386 | /* LICENSED_APP_ID structuredef */ |
5387 | #define LICENSED_APP_ID_LEN 4 | |
5388 | #define LICENSED_APP_ID_ID_OFST 0 | |
5389 | /* enum: OpenOnload */ | |
a9196bb0 | 5390 | #define LICENSED_APP_ID_ONLOAD 0x1 |
512bb06c | 5391 | /* enum: PTP timestamping */ |
a9196bb0 | 5392 | #define LICENSED_APP_ID_PTP 0x2 |
512bb06c | 5393 | /* enum: SolarCapture Pro */ |
a9196bb0 EC |
5394 | #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 |
5395 | /* enum: SolarSecure filter engine */ | |
5396 | #define LICENSED_APP_ID_SOLARSECURE 0x8 | |
5397 | /* enum: Performance monitor */ | |
5398 | #define LICENSED_APP_ID_PERF_MONITOR 0x10 | |
5399 | /* enum: SolarCapture Live */ | |
5400 | #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 | |
5401 | /* enum: Capture SolarSystem */ | |
5402 | #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 | |
5403 | /* enum: Network Access Control */ | |
5404 | #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 | |
512bb06c BH |
5405 | #define LICENSED_APP_ID_ID_LBN 0 |
5406 | #define LICENSED_APP_ID_ID_WIDTH 32 | |
5407 | ||
23e202b4 EC |
5408 | /* LICENSED_FEATURES structuredef */ |
5409 | #define LICENSED_FEATURES_LEN 8 | |
5410 | /* Bitmask of licensed firmware features */ | |
5411 | #define LICENSED_FEATURES_MASK_OFST 0 | |
5412 | #define LICENSED_FEATURES_MASK_LEN 8 | |
5413 | #define LICENSED_FEATURES_MASK_LO_OFST 0 | |
5414 | #define LICENSED_FEATURES_MASK_HI_OFST 4 | |
5415 | #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 | |
5416 | #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 | |
5417 | #define LICENSED_FEATURES_PIO_LBN 1 | |
5418 | #define LICENSED_FEATURES_PIO_WIDTH 1 | |
5419 | #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 | |
5420 | #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 | |
5421 | #define LICENSED_FEATURES_CLOCK_LBN 3 | |
5422 | #define LICENSED_FEATURES_CLOCK_WIDTH 1 | |
5423 | #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 | |
5424 | #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 | |
5425 | #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 | |
5426 | #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 | |
5427 | #define LICENSED_FEATURES_RX_SNIFF_LBN 6 | |
5428 | #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 | |
5429 | #define LICENSED_FEATURES_TX_SNIFF_LBN 7 | |
5430 | #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 | |
5431 | #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 | |
5432 | #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 | |
5433 | #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 | |
5434 | #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 | |
5435 | #define LICENSED_FEATURES_MASK_LBN 0 | |
5436 | #define LICENSED_FEATURES_MASK_WIDTH 64 | |
5437 | ||
5438 | /* LICENSED_V3_APPS structuredef */ | |
5439 | #define LICENSED_V3_APPS_LEN 8 | |
5440 | /* Bitmask of licensed applications */ | |
5441 | #define LICENSED_V3_APPS_MASK_OFST 0 | |
5442 | #define LICENSED_V3_APPS_MASK_LEN 8 | |
5443 | #define LICENSED_V3_APPS_MASK_LO_OFST 0 | |
5444 | #define LICENSED_V3_APPS_MASK_HI_OFST 4 | |
5445 | #define LICENSED_V3_APPS_ONLOAD_LBN 0 | |
5446 | #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 | |
5447 | #define LICENSED_V3_APPS_PTP_LBN 1 | |
5448 | #define LICENSED_V3_APPS_PTP_WIDTH 1 | |
5449 | #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 | |
5450 | #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 | |
5451 | #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 | |
5452 | #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 | |
5453 | #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 | |
5454 | #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 | |
5455 | #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 | |
5456 | #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 | |
5457 | #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 | |
5458 | #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 | |
5459 | #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 | |
5460 | #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 | |
5461 | #define LICENSED_V3_APPS_MASK_LBN 0 | |
5462 | #define LICENSED_V3_APPS_MASK_WIDTH 64 | |
5463 | ||
5464 | /* LICENSED_V3_FEATURES structuredef */ | |
5465 | #define LICENSED_V3_FEATURES_LEN 8 | |
5466 | /* Bitmask of licensed firmware features */ | |
5467 | #define LICENSED_V3_FEATURES_MASK_OFST 0 | |
5468 | #define LICENSED_V3_FEATURES_MASK_LEN 8 | |
5469 | #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 | |
5470 | #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 | |
5471 | #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 | |
5472 | #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 | |
5473 | #define LICENSED_V3_FEATURES_PIO_LBN 1 | |
5474 | #define LICENSED_V3_FEATURES_PIO_WIDTH 1 | |
5475 | #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 | |
5476 | #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 | |
5477 | #define LICENSED_V3_FEATURES_CLOCK_LBN 3 | |
5478 | #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 | |
5479 | #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 | |
5480 | #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 | |
5481 | #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 | |
5482 | #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 | |
5483 | #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 | |
5484 | #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 | |
5485 | #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 | |
5486 | #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 | |
5487 | #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 | |
5488 | #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 | |
d29e33d6 BK |
5489 | #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 |
5490 | #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 | |
23e202b4 EC |
5491 | #define LICENSED_V3_FEATURES_MASK_LBN 0 |
5492 | #define LICENSED_V3_FEATURES_MASK_WIDTH 64 | |
5493 | ||
a9196bb0 EC |
5494 | /* TX_TIMESTAMP_EVENT structuredef */ |
5495 | #define TX_TIMESTAMP_EVENT_LEN 6 | |
5496 | /* lower 16 bits of timestamp data */ | |
5497 | #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 | |
5498 | #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 | |
5499 | #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 | |
5500 | #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 | |
5501 | /* Type of TX event, ordinary TX completion, low or high part of TX timestamp | |
5502 | */ | |
5503 | #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 | |
5504 | #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 | |
5505 | /* enum: This is a TX completion event, not a timestamp */ | |
5506 | #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 | |
5507 | /* enum: This is the low part of a TX timestamp event */ | |
5508 | #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 | |
5509 | /* enum: This is the high part of a TX timestamp event */ | |
5510 | #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 | |
5511 | #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 | |
5512 | #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 | |
5513 | /* upper 16 bits of timestamp data */ | |
5514 | #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 | |
5515 | #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 | |
5516 | #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 | |
5517 | #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 | |
5518 | ||
5519 | /* RSS_MODE structuredef */ | |
5520 | #define RSS_MODE_LEN 1 | |
5521 | /* The RSS mode for a particular packet type is a value from 0 - 15 which can | |
5522 | * be considered as 4 bits selecting which fields are included in the hash. (A | |
5523 | * value 0 effectively disables RSS spreading for the packet type.) The YAML | |
5524 | * generation tools require this structure to be a whole number of bytes wide, | |
5525 | * but only 4 bits are relevant. | |
5526 | */ | |
5527 | #define RSS_MODE_HASH_SELECTOR_OFST 0 | |
5528 | #define RSS_MODE_HASH_SELECTOR_LEN 1 | |
5529 | #define RSS_MODE_HASH_SRC_ADDR_LBN 0 | |
5530 | #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 | |
5531 | #define RSS_MODE_HASH_DST_ADDR_LBN 1 | |
5532 | #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 | |
5533 | #define RSS_MODE_HASH_SRC_PORT_LBN 2 | |
5534 | #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 | |
5535 | #define RSS_MODE_HASH_DST_PORT_LBN 3 | |
5536 | #define RSS_MODE_HASH_DST_PORT_WIDTH 1 | |
5537 | #define RSS_MODE_HASH_SELECTOR_LBN 0 | |
5538 | #define RSS_MODE_HASH_SELECTOR_WIDTH 8 | |
4392dc69 EC |
5539 | |
5540 | ||
f2b0befd BH |
5541 | /***********************************/ |
5542 | /* MC_CMD_READ_REGS | |
5543 | * Get a dump of the MCPU registers | |
5544 | */ | |
5545 | #define MC_CMD_READ_REGS 0x50 | |
5546 | ||
75122ec8 SS |
5547 | #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
5548 | ||
f2b0befd BH |
5549 | /* MC_CMD_READ_REGS_IN msgrequest */ |
5550 | #define MC_CMD_READ_REGS_IN_LEN 0 | |
5551 | ||
5552 | /* MC_CMD_READ_REGS_OUT msgresponse */ | |
5553 | #define MC_CMD_READ_REGS_OUT_LEN 308 | |
5554 | /* Whether the corresponding register entry contains a valid value */ | |
5555 | #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 | |
5556 | #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 | |
5557 | /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, | |
5558 | * fir, fp) | |
5559 | */ | |
5560 | #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 | |
5561 | #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 | |
5562 | #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 | |
5563 | ||
5564 | ||
5565 | /***********************************/ | |
5566 | /* MC_CMD_INIT_EVQ | |
5567 | * Set up an event queue according to the supplied parameters. The IN arguments | |
5568 | * end with an address for each 4k of host memory required to back the EVQ. | |
5569 | */ | |
5570 | #define MC_CMD_INIT_EVQ 0x80 | |
5571 | ||
75122ec8 SS |
5572 | #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5573 | ||
f2b0befd BH |
5574 | /* MC_CMD_INIT_EVQ_IN msgrequest */ |
5575 | #define MC_CMD_INIT_EVQ_IN_LENMIN 44 | |
5576 | #define MC_CMD_INIT_EVQ_IN_LENMAX 548 | |
5577 | #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) | |
5578 | /* Size, in entries */ | |
5579 | #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 | |
5580 | /* Desired instance. Must be set to a specific instance, which is a function | |
5581 | * local queue index. | |
5582 | */ | |
5583 | #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 | |
5584 | /* The initial timer value. The load value is ignored if the timer mode is DIS. | |
5585 | */ | |
5586 | #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 | |
5587 | /* The reload value is ignored in one-shot modes */ | |
5588 | #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 | |
5589 | /* tbd */ | |
5590 | #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 | |
5591 | #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 | |
5592 | #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 | |
5593 | #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 | |
5594 | #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 | |
5595 | #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 | |
5596 | #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 | |
5597 | #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 | |
5598 | #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 | |
5599 | #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 | |
5600 | #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 | |
5601 | #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 | |
5602 | #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 | |
23e202b4 EC |
5603 | #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 |
5604 | #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 | |
f2b0befd BH |
5605 | #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 |
5606 | /* enum: Disabled */ | |
5607 | #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 | |
5608 | /* enum: Immediate */ | |
5609 | #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 | |
5610 | /* enum: Triggered */ | |
5611 | #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 | |
5612 | /* enum: Hold-off */ | |
5613 | #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 | |
5614 | /* Target EVQ for wakeups if in wakeup mode. */ | |
5615 | #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 | |
5616 | /* Target interrupt if in interrupting mode (note union with target EVQ). Use | |
5617 | * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test | |
5618 | * purposes. | |
5619 | */ | |
5620 | #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 | |
5621 | /* Event Counter Mode. */ | |
5622 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 | |
5623 | /* enum: Disabled */ | |
5624 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 | |
5625 | /* enum: Disabled */ | |
5626 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 | |
5627 | /* enum: Disabled */ | |
5628 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 | |
5629 | /* enum: Disabled */ | |
5630 | #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 | |
5631 | /* Event queue packet count threshold. */ | |
5632 | #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 | |
5633 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
5634 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 | |
5635 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 | |
5636 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 | |
5637 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 | |
5638 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 | |
5639 | #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 | |
5640 | ||
5641 | /* MC_CMD_INIT_EVQ_OUT msgresponse */ | |
5642 | #define MC_CMD_INIT_EVQ_OUT_LEN 4 | |
5643 | /* Only valid if INTRFLAG was true */ | |
5644 | #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 | |
5645 | ||
d29e33d6 BK |
5646 | /* MC_CMD_INIT_EVQ_V2_IN msgrequest */ |
5647 | #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 | |
5648 | #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 | |
5649 | #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) | |
5650 | /* Size, in entries */ | |
5651 | #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 | |
5652 | /* Desired instance. Must be set to a specific instance, which is a function | |
5653 | * local queue index. | |
5654 | */ | |
5655 | #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 | |
5656 | /* The initial timer value. The load value is ignored if the timer mode is DIS. | |
5657 | */ | |
5658 | #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 | |
5659 | /* The reload value is ignored in one-shot modes */ | |
5660 | #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 | |
5661 | /* tbd */ | |
5662 | #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 | |
5663 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 | |
5664 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 | |
5665 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 | |
5666 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 | |
5667 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 | |
5668 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 | |
5669 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 | |
5670 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 | |
5671 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 | |
5672 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 | |
5673 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 | |
5674 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 | |
5675 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 | |
5676 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 | |
5677 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 | |
5678 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 | |
5679 | /* enum: All initialisation flags specified by host. */ | |
5680 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 | |
5681 | /* enum: MEDFORD only. Certain initialisation flags specified by host may be | |
5682 | * over-ridden by firmware based on licenses and firmware variant in order to | |
5683 | * provide the lowest latency achievable. See | |
5684 | * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. | |
5685 | */ | |
5686 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 | |
5687 | /* enum: MEDFORD only. Certain initialisation flags specified by host may be | |
5688 | * over-ridden by firmware based on licenses and firmware variant in order to | |
5689 | * provide the best throughput achievable. See | |
5690 | * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. | |
5691 | */ | |
5692 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 | |
5693 | /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by | |
5694 | * firmware based on licenses and firmware variant. See | |
5695 | * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. | |
5696 | */ | |
5697 | #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 | |
5698 | #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 | |
5699 | /* enum: Disabled */ | |
5700 | #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 | |
5701 | /* enum: Immediate */ | |
5702 | #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 | |
5703 | /* enum: Triggered */ | |
5704 | #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 | |
5705 | /* enum: Hold-off */ | |
5706 | #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 | |
5707 | /* Target EVQ for wakeups if in wakeup mode. */ | |
5708 | #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 | |
5709 | /* Target interrupt if in interrupting mode (note union with target EVQ). Use | |
5710 | * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test | |
5711 | * purposes. | |
5712 | */ | |
5713 | #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 | |
5714 | /* Event Counter Mode. */ | |
5715 | #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 | |
5716 | /* enum: Disabled */ | |
5717 | #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 | |
5718 | /* enum: Disabled */ | |
5719 | #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 | |
5720 | /* enum: Disabled */ | |
5721 | #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 | |
5722 | /* enum: Disabled */ | |
5723 | #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 | |
5724 | /* Event queue packet count threshold. */ | |
5725 | #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 | |
5726 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
5727 | #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 | |
5728 | #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 | |
5729 | #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 | |
5730 | #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 | |
5731 | #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 | |
5732 | #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 | |
5733 | ||
5734 | /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ | |
5735 | #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 | |
5736 | /* Only valid if INTRFLAG was true */ | |
5737 | #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 | |
5738 | /* Actual configuration applied on the card */ | |
5739 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 | |
5740 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 | |
5741 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 | |
5742 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 | |
5743 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 | |
5744 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 | |
5745 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 | |
5746 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 | |
5747 | #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 | |
5748 | ||
f2b0befd BH |
5749 | /* QUEUE_CRC_MODE structuredef */ |
5750 | #define QUEUE_CRC_MODE_LEN 1 | |
5751 | #define QUEUE_CRC_MODE_MODE_LBN 0 | |
5752 | #define QUEUE_CRC_MODE_MODE_WIDTH 4 | |
5753 | /* enum: No CRC. */ | |
5754 | #define QUEUE_CRC_MODE_NONE 0x0 | |
5755 | /* enum: CRC Fiber channel over ethernet. */ | |
5756 | #define QUEUE_CRC_MODE_FCOE 0x1 | |
5757 | /* enum: CRC (digest) iSCSI header only. */ | |
5758 | #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 | |
5759 | /* enum: CRC (digest) iSCSI header and payload. */ | |
5760 | #define QUEUE_CRC_MODE_ISCSI 0x3 | |
5761 | /* enum: CRC Fiber channel over IP over ethernet. */ | |
5762 | #define QUEUE_CRC_MODE_FCOIPOE 0x4 | |
5763 | /* enum: CRC MPA. */ | |
5764 | #define QUEUE_CRC_MODE_MPA 0x5 | |
5765 | #define QUEUE_CRC_MODE_SPARE_LBN 4 | |
5766 | #define QUEUE_CRC_MODE_SPARE_WIDTH 4 | |
5767 | ||
5768 | ||
5769 | /***********************************/ | |
5770 | /* MC_CMD_INIT_RXQ | |
5771 | * set up a receive queue according to the supplied parameters. The IN | |
5772 | * arguments end with an address for each 4k of host memory required to back | |
5773 | * the RXQ. | |
5774 | */ | |
5775 | #define MC_CMD_INIT_RXQ 0x81 | |
5776 | ||
75122ec8 SS |
5777 | #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5778 | ||
a9196bb0 EC |
5779 | /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version |
5780 | * in new code. | |
5781 | */ | |
f2b0befd BH |
5782 | #define MC_CMD_INIT_RXQ_IN_LENMIN 36 |
5783 | #define MC_CMD_INIT_RXQ_IN_LENMAX 252 | |
5784 | #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) | |
5785 | /* Size, in entries */ | |
5786 | #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 | |
5787 | /* The EVQ to send events to. This is an index originally specified to INIT_EVQ | |
5788 | */ | |
5789 | #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 | |
5790 | /* The value to put in the event data. Check hardware spec. for valid range. */ | |
5791 | #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 | |
5792 | /* Desired instance. Must be set to a specific instance, which is a function | |
5793 | * local queue index. | |
5794 | */ | |
5795 | #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 | |
5796 | /* There will be more flags here. */ | |
5797 | #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 | |
5798 | #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 | |
5799 | #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 | |
5800 | #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 | |
5801 | #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 | |
5802 | #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 | |
5803 | #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 | |
5804 | #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 | |
5805 | #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 | |
5806 | #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 | |
5807 | #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 | |
5808 | #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 | |
5809 | #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 | |
512bb06c BH |
5810 | #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 |
5811 | #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 | |
d29e33d6 BK |
5812 | #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 |
5813 | #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 | |
f2b0befd BH |
5814 | /* Owner ID to use if in buffer mode (zero if physical) */ |
5815 | #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 | |
5816 | /* The port ID associated with the v-adaptor which should contain this DMAQ. */ | |
5817 | #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 | |
5818 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
5819 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 | |
5820 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 | |
5821 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 | |
5822 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 | |
5823 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 | |
5824 | #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 | |
5825 | ||
a9196bb0 EC |
5826 | /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode |
5827 | * flags | |
5828 | */ | |
5829 | #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 | |
5830 | /* Size, in entries */ | |
5831 | #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 | |
5832 | /* The EVQ to send events to. This is an index originally specified to INIT_EVQ | |
5833 | */ | |
5834 | #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 | |
5835 | /* The value to put in the event data. Check hardware spec. for valid range. */ | |
5836 | #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 | |
5837 | /* Desired instance. Must be set to a specific instance, which is a function | |
5838 | * local queue index. | |
5839 | */ | |
5840 | #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 | |
5841 | /* There will be more flags here. */ | |
5842 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 | |
5843 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 | |
5844 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 | |
5845 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 | |
5846 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 | |
5847 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 | |
5848 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 | |
5849 | #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 | |
5850 | #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 | |
5851 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 | |
5852 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 | |
5853 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 | |
5854 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 | |
5855 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 | |
5856 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 | |
5857 | #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 | |
5858 | #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 | |
5859 | /* enum: One packet per descriptor (for normal networking) */ | |
5860 | #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 | |
5861 | /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ | |
5862 | #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 | |
5863 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 | |
5864 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 | |
5865 | #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 | |
5866 | #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 | |
5867 | #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ | |
5868 | #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ | |
5869 | #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ | |
5870 | #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ | |
5871 | #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ | |
5872 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 | |
5873 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 | |
23e202b4 EC |
5874 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 |
5875 | #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 | |
a9196bb0 EC |
5876 | /* Owner ID to use if in buffer mode (zero if physical) */ |
5877 | #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 | |
5878 | /* The port ID associated with the v-adaptor which should contain this DMAQ. */ | |
5879 | #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 | |
5880 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
5881 | #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 | |
5882 | #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 | |
5883 | #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 | |
5884 | #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 | |
5885 | #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 | |
5886 | /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ | |
5887 | #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 | |
5888 | ||
f2b0befd BH |
5889 | /* MC_CMD_INIT_RXQ_OUT msgresponse */ |
5890 | #define MC_CMD_INIT_RXQ_OUT_LEN 0 | |
5891 | ||
a9196bb0 EC |
5892 | /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ |
5893 | #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 | |
5894 | ||
f2b0befd BH |
5895 | |
5896 | /***********************************/ | |
5897 | /* MC_CMD_INIT_TXQ | |
5898 | */ | |
5899 | #define MC_CMD_INIT_TXQ 0x82 | |
5900 | ||
75122ec8 SS |
5901 | #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
5902 | ||
a9196bb0 EC |
5903 | /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version |
5904 | * in new code. | |
5905 | */ | |
f2b0befd BH |
5906 | #define MC_CMD_INIT_TXQ_IN_LENMIN 36 |
5907 | #define MC_CMD_INIT_TXQ_IN_LENMAX 252 | |
5908 | #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) | |
5909 | /* Size, in entries */ | |
5910 | #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 | |
5911 | /* The EVQ to send events to. This is an index originally specified to | |
5912 | * INIT_EVQ. | |
5913 | */ | |
5914 | #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 | |
5915 | /* The value to put in the event data. Check hardware spec. for valid range. */ | |
5916 | #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 | |
5917 | /* Desired instance. Must be set to a specific instance, which is a function | |
5918 | * local queue index. | |
5919 | */ | |
5920 | #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 | |
5921 | /* There will be more flags here. */ | |
5922 | #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 | |
5923 | #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 | |
5924 | #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 | |
5925 | #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 | |
5926 | #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 | |
5927 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 | |
5928 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 | |
5929 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 | |
5930 | #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 | |
5931 | #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 | |
5932 | #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 | |
5933 | #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 | |
5934 | #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 | |
5935 | #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 | |
5936 | #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 | |
a9196bb0 EC |
5937 | #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 |
5938 | #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 | |
5939 | #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 | |
5940 | #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 | |
f2b0befd BH |
5941 | /* Owner ID to use if in buffer mode (zero if physical) */ |
5942 | #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 | |
5943 | /* The port ID associated with the v-adaptor which should contain this DMAQ. */ | |
5944 | #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 | |
5945 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
5946 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 | |
5947 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 | |
5948 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 | |
5949 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 | |
5950 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 | |
5951 | #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 | |
5952 | ||
a9196bb0 EC |
5953 | /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode |
5954 | * flags | |
5955 | */ | |
5956 | #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 | |
5957 | /* Size, in entries */ | |
5958 | #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 | |
5959 | /* The EVQ to send events to. This is an index originally specified to | |
5960 | * INIT_EVQ. | |
5961 | */ | |
5962 | #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 | |
5963 | /* The value to put in the event data. Check hardware spec. for valid range. */ | |
5964 | #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 | |
5965 | /* Desired instance. Must be set to a specific instance, which is a function | |
5966 | * local queue index. | |
5967 | */ | |
5968 | #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 | |
5969 | /* There will be more flags here. */ | |
5970 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 | |
5971 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 | |
5972 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 | |
5973 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 | |
5974 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 | |
5975 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 | |
5976 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 | |
5977 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 | |
5978 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 | |
5979 | #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 | |
5980 | #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 | |
5981 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 | |
5982 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 | |
5983 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 | |
5984 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 | |
5985 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 | |
5986 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 | |
5987 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 | |
5988 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 | |
23e202b4 EC |
5989 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 |
5990 | #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 | |
a9196bb0 EC |
5991 | /* Owner ID to use if in buffer mode (zero if physical) */ |
5992 | #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 | |
5993 | /* The port ID associated with the v-adaptor which should contain this DMAQ. */ | |
5994 | #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 | |
5995 | /* 64-bit address of 4k of 4k-aligned host memory buffer */ | |
5996 | #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 | |
5997 | #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 | |
5998 | #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 | |
5999 | #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 | |
6000 | #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 | |
6001 | #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 | |
6002 | /* Flags related to Qbb flow control mode. */ | |
6003 | #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 | |
6004 | #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 | |
6005 | #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 | |
6006 | #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 | |
6007 | #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 | |
6008 | ||
f2b0befd BH |
6009 | /* MC_CMD_INIT_TXQ_OUT msgresponse */ |
6010 | #define MC_CMD_INIT_TXQ_OUT_LEN 0 | |
6011 | ||
6012 | ||
6013 | /***********************************/ | |
6014 | /* MC_CMD_FINI_EVQ | |
6015 | * Teardown an EVQ. | |
6016 | * | |
6017 | * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first | |
6018 | * or the operation will fail with EBUSY | |
6019 | */ | |
6020 | #define MC_CMD_FINI_EVQ 0x83 | |
6021 | ||
75122ec8 SS |
6022 | #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6023 | ||
f2b0befd BH |
6024 | /* MC_CMD_FINI_EVQ_IN msgrequest */ |
6025 | #define MC_CMD_FINI_EVQ_IN_LEN 4 | |
6026 | /* Instance of EVQ to destroy. Should be the same instance as that previously | |
6027 | * passed to INIT_EVQ | |
6028 | */ | |
6029 | #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 | |
6030 | ||
6031 | /* MC_CMD_FINI_EVQ_OUT msgresponse */ | |
6032 | #define MC_CMD_FINI_EVQ_OUT_LEN 0 | |
6033 | ||
6034 | ||
6035 | /***********************************/ | |
6036 | /* MC_CMD_FINI_RXQ | |
6037 | * Teardown a RXQ. | |
6038 | */ | |
6039 | #define MC_CMD_FINI_RXQ 0x84 | |
6040 | ||
75122ec8 SS |
6041 | #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6042 | ||
f2b0befd BH |
6043 | /* MC_CMD_FINI_RXQ_IN msgrequest */ |
6044 | #define MC_CMD_FINI_RXQ_IN_LEN 4 | |
6045 | /* Instance of RXQ to destroy */ | |
6046 | #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 | |
6047 | ||
6048 | /* MC_CMD_FINI_RXQ_OUT msgresponse */ | |
6049 | #define MC_CMD_FINI_RXQ_OUT_LEN 0 | |
6050 | ||
6051 | ||
6052 | /***********************************/ | |
6053 | /* MC_CMD_FINI_TXQ | |
6054 | * Teardown a TXQ. | |
6055 | */ | |
6056 | #define MC_CMD_FINI_TXQ 0x85 | |
6057 | ||
75122ec8 SS |
6058 | #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6059 | ||
f2b0befd BH |
6060 | /* MC_CMD_FINI_TXQ_IN msgrequest */ |
6061 | #define MC_CMD_FINI_TXQ_IN_LEN 4 | |
6062 | /* Instance of TXQ to destroy */ | |
6063 | #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 | |
6064 | ||
6065 | /* MC_CMD_FINI_TXQ_OUT msgresponse */ | |
6066 | #define MC_CMD_FINI_TXQ_OUT_LEN 0 | |
6067 | ||
6068 | ||
6069 | /***********************************/ | |
6070 | /* MC_CMD_DRIVER_EVENT | |
6071 | * Generate an event on an EVQ belonging to the function issuing the command. | |
6072 | */ | |
6073 | #define MC_CMD_DRIVER_EVENT 0x86 | |
6074 | ||
75122ec8 SS |
6075 | #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6076 | ||
f2b0befd BH |
6077 | /* MC_CMD_DRIVER_EVENT_IN msgrequest */ |
6078 | #define MC_CMD_DRIVER_EVENT_IN_LEN 12 | |
6079 | /* Handle of target EVQ */ | |
6080 | #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 | |
6081 | /* Bits 0 - 63 of event */ | |
6082 | #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 | |
6083 | #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 | |
6084 | #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 | |
6085 | #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 | |
6086 | ||
6087 | /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ | |
6088 | #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 | |
6089 | ||
6090 | ||
6091 | /***********************************/ | |
6092 | /* MC_CMD_PROXY_CMD | |
6093 | * Execute an arbitrary MCDI command on behalf of a different function, subject | |
6094 | * to security restrictions. The command to be proxied follows immediately | |
6095 | * afterward in the host buffer (or on the UART). This command supercedes | |
6096 | * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. | |
6097 | */ | |
6098 | #define MC_CMD_PROXY_CMD 0x5b | |
6099 | ||
75122ec8 SS |
6100 | #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6101 | ||
f2b0befd BH |
6102 | /* MC_CMD_PROXY_CMD_IN msgrequest */ |
6103 | #define MC_CMD_PROXY_CMD_IN_LEN 4 | |
6104 | /* The handle of the target function. */ | |
6105 | #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 | |
6106 | #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 | |
6107 | #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 | |
6108 | #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 | |
6109 | #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 | |
6110 | #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ | |
6111 | ||
512bb06c BH |
6112 | /* MC_CMD_PROXY_CMD_OUT msgresponse */ |
6113 | #define MC_CMD_PROXY_CMD_OUT_LEN 0 | |
6114 | ||
a9196bb0 EC |
6115 | /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to |
6116 | * manage proxied requests | |
6117 | */ | |
6118 | #define MC_PROXY_STATUS_BUFFER_LEN 16 | |
6119 | /* Handle allocated by the firmware for this proxy transaction */ | |
6120 | #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 | |
6121 | /* enum: An invalid handle. */ | |
6122 | #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 | |
6123 | #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 | |
6124 | #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 | |
6125 | /* The requesting physical function number */ | |
6126 | #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 | |
6127 | #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 | |
6128 | #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 | |
6129 | #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 | |
6130 | /* The requesting virtual function number. Set to VF_NULL if the target is a | |
6131 | * PF. | |
6132 | */ | |
6133 | #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 | |
6134 | #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 | |
6135 | #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 | |
6136 | #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 | |
6137 | /* The target function RID. */ | |
6138 | #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 | |
6139 | #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 | |
6140 | #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 | |
6141 | #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 | |
6142 | /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ | |
6143 | #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 | |
6144 | #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 | |
6145 | #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 | |
6146 | #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 | |
6147 | /* If a request is authorized rather than carried out by the host, this is the | |
6148 | * elevated privilege mask granted to the requesting function. | |
6149 | */ | |
6150 | #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 | |
6151 | #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 | |
6152 | #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 | |
6153 | ||
6154 | ||
6155 | /***********************************/ | |
6156 | /* MC_CMD_PROXY_CONFIGURE | |
6157 | * Enable/disable authorization of MCDI requests from unprivileged functions by | |
6158 | * a designated admin function | |
6159 | */ | |
6160 | #define MC_CMD_PROXY_CONFIGURE 0x58 | |
6161 | ||
6162 | #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
6163 | ||
6164 | /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ | |
6165 | #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 | |
6166 | #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 | |
6167 | #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 | |
6168 | #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 | |
6169 | /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS | |
6170 | * of blocks, each of the size REQUEST_BLOCK_SIZE. | |
6171 | */ | |
6172 | #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 | |
6173 | #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 | |
6174 | #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 | |
6175 | #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 | |
6176 | /* Must be a power of 2 */ | |
6177 | #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 | |
6178 | /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS | |
6179 | * of blocks, each of the size REPLY_BLOCK_SIZE. | |
6180 | */ | |
6181 | #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 | |
6182 | #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 | |
6183 | #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 | |
6184 | #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 | |
6185 | /* Must be a power of 2 */ | |
6186 | #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 | |
6187 | /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS | |
6188 | * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if | |
6189 | * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. | |
6190 | */ | |
6191 | #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 | |
6192 | #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 | |
6193 | #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 | |
6194 | #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 | |
6195 | /* Must be a power of 2, or zero if this buffer is not provided */ | |
6196 | #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 | |
6197 | /* Applies to all three buffers */ | |
6198 | #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 | |
6199 | /* A bit mask defining which MCDI operations may be proxied */ | |
6200 | #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 | |
6201 | #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 | |
6202 | ||
23e202b4 EC |
6203 | /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ |
6204 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 | |
6205 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 | |
6206 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 | |
6207 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 | |
6208 | /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS | |
6209 | * of blocks, each of the size REQUEST_BLOCK_SIZE. | |
6210 | */ | |
6211 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 | |
6212 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 | |
6213 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 | |
6214 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 | |
6215 | /* Must be a power of 2 */ | |
6216 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 | |
6217 | /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS | |
6218 | * of blocks, each of the size REPLY_BLOCK_SIZE. | |
6219 | */ | |
6220 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 | |
6221 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 | |
6222 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 | |
6223 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 | |
6224 | /* Must be a power of 2 */ | |
6225 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 | |
6226 | /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS | |
6227 | * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if | |
6228 | * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. | |
6229 | */ | |
6230 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 | |
6231 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 | |
6232 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 | |
6233 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 | |
6234 | /* Must be a power of 2, or zero if this buffer is not provided */ | |
6235 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 | |
6236 | /* Applies to all three buffers */ | |
6237 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 | |
6238 | /* A bit mask defining which MCDI operations may be proxied */ | |
6239 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 | |
6240 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 | |
6241 | #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 | |
6242 | ||
a9196bb0 EC |
6243 | /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ |
6244 | #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 | |
6245 | ||
6246 | ||
6247 | /***********************************/ | |
6248 | /* MC_CMD_PROXY_COMPLETE | |
6249 | * Tells FW that a requested proxy operation has either been completed (by | |
6250 | * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the | |
6251 | * function that enabled proxying/authorization (by using | |
6252 | * MC_CMD_PROXY_CONFIGURE). | |
6253 | */ | |
6254 | #define MC_CMD_PROXY_COMPLETE 0x5f | |
6255 | ||
6256 | #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
6257 | ||
6258 | /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ | |
6259 | #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 | |
6260 | #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 | |
6261 | #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 | |
6262 | /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply | |
6263 | * is stored in the REPLY_BUFF. | |
6264 | */ | |
6265 | #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 | |
6266 | /* enum: The operation has been authorized. The originating function may now | |
6267 | * try again. | |
6268 | */ | |
6269 | #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 | |
6270 | /* enum: The operation has been declined. */ | |
6271 | #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 | |
6272 | /* enum: The authorization failed because the relevant application did not | |
6273 | * respond in time. | |
6274 | */ | |
6275 | #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 | |
6276 | #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 | |
6277 | ||
6278 | /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ | |
6279 | #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 | |
6280 | ||
f2b0befd BH |
6281 | |
6282 | /***********************************/ | |
6283 | /* MC_CMD_ALLOC_BUFTBL_CHUNK | |
6284 | * Allocate a set of buffer table entries using the specified owner ID. This | |
6285 | * operation allocates the required buffer table entries (and fails if it | |
6286 | * cannot do so). The buffer table entries will initially be zeroed. | |
6287 | */ | |
6288 | #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 | |
6289 | ||
75122ec8 SS |
6290 | #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
6291 | ||
f2b0befd BH |
6292 | /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ |
6293 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 | |
6294 | /* Owner ID to use */ | |
6295 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 | |
6296 | /* Size of buffer table pages to use, in bytes (note that only a few values are | |
6297 | * legal on any specific hardware). | |
6298 | */ | |
6299 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 | |
6300 | ||
6301 | /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ | |
6302 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 | |
6303 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 | |
6304 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 | |
6305 | /* Buffer table IDs for use in DMA descriptors. */ | |
6306 | #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 | |
6307 | ||
6308 | ||
6309 | /***********************************/ | |
6310 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES | |
6311 | * Reprogram a set of buffer table entries in the specified chunk. | |
6312 | */ | |
6313 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 | |
6314 | ||
75122ec8 SS |
6315 | #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
6316 | ||
f2b0befd BH |
6317 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ |
6318 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 | |
512bb06c | 6319 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 |
f2b0befd BH |
6320 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) |
6321 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 | |
6322 | /* ID */ | |
6323 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 | |
6324 | /* Num entries */ | |
6325 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 | |
6326 | /* Buffer table entry address */ | |
6327 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 | |
6328 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 | |
6329 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 | |
6330 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 | |
6331 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 | |
512bb06c | 6332 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 |
f2b0befd BH |
6333 | |
6334 | /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ | |
6335 | #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 | |
6336 | ||
6337 | ||
6338 | /***********************************/ | |
6339 | /* MC_CMD_FREE_BUFTBL_CHUNK | |
6340 | */ | |
6341 | #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 | |
6342 | ||
75122ec8 SS |
6343 | #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
6344 | ||
f2b0befd BH |
6345 | /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ |
6346 | #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 | |
6347 | #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 | |
6348 | ||
6349 | /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ | |
6350 | #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 | |
6351 | ||
a9196bb0 EC |
6352 | /* PORT_CONFIG_ENTRY structuredef */ |
6353 | #define PORT_CONFIG_ENTRY_LEN 16 | |
6354 | /* External port number (label) */ | |
6355 | #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 | |
6356 | #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 | |
6357 | #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 | |
6358 | #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 | |
6359 | /* Port core location */ | |
6360 | #define PORT_CONFIG_ENTRY_CORE_OFST 1 | |
6361 | #define PORT_CONFIG_ENTRY_CORE_LEN 1 | |
6362 | #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ | |
6363 | #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ | |
6364 | #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ | |
6365 | #define PORT_CONFIG_ENTRY_CORE_LBN 8 | |
6366 | #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 | |
6367 | /* Internal number (HW resource) relative to the core */ | |
6368 | #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 | |
6369 | #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 | |
6370 | #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 | |
6371 | #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 | |
6372 | /* Reserved */ | |
6373 | #define PORT_CONFIG_ENTRY_RSVD_OFST 3 | |
6374 | #define PORT_CONFIG_ENTRY_RSVD_LEN 1 | |
6375 | #define PORT_CONFIG_ENTRY_RSVD_LBN 24 | |
6376 | #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 | |
6377 | /* Bitmask of KR lanes used by the port */ | |
6378 | #define PORT_CONFIG_ENTRY_LANES_OFST 4 | |
6379 | #define PORT_CONFIG_ENTRY_LANES_LBN 32 | |
6380 | #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 | |
6381 | /* Port capabilities (MC_CMD_PHY_CAP_*) */ | |
6382 | #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 | |
6383 | #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 | |
6384 | #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 | |
6385 | /* Reserved (align to 16 bytes) */ | |
6386 | #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 | |
6387 | #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 | |
6388 | #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 | |
6389 | ||
f2b0befd BH |
6390 | |
6391 | /***********************************/ | |
6392 | /* MC_CMD_FILTER_OP | |
6393 | * Multiplexed MCDI call for filter operations | |
6394 | */ | |
6395 | #define MC_CMD_FILTER_OP 0x8a | |
6396 | ||
75122ec8 SS |
6397 | #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6398 | ||
f2b0befd BH |
6399 | /* MC_CMD_FILTER_OP_IN msgrequest */ |
6400 | #define MC_CMD_FILTER_OP_IN_LEN 108 | |
6401 | /* identifies the type of operation requested */ | |
6402 | #define MC_CMD_FILTER_OP_IN_OP_OFST 0 | |
6403 | /* enum: single-recipient filter insert */ | |
6404 | #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 | |
6405 | /* enum: single-recipient filter remove */ | |
6406 | #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 | |
6407 | /* enum: multi-recipient filter subscribe */ | |
6408 | #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 | |
6409 | /* enum: multi-recipient filter unsubscribe */ | |
6410 | #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 | |
6411 | /* enum: replace one recipient with another (warning - the filter handle may | |
6412 | * change) | |
6413 | */ | |
6414 | #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 | |
6415 | /* filter handle (for remove / unsubscribe operations) */ | |
6416 | #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 | |
6417 | #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 | |
6418 | #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 | |
6419 | #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 | |
6420 | /* The port ID associated with the v-adaptor which should contain this filter. | |
6421 | */ | |
6422 | #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 | |
6423 | /* fields to include in match criteria */ | |
6424 | #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 | |
6425 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 | |
6426 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 | |
6427 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 | |
6428 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 | |
6429 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 | |
6430 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 | |
6431 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 | |
6432 | #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 | |
6433 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 | |
6434 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 | |
6435 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 | |
6436 | #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 | |
6437 | #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 | |
6438 | #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 | |
6439 | #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 | |
6440 | #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 | |
6441 | #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 | |
6442 | #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 | |
6443 | #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 | |
6444 | #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 | |
6445 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 | |
6446 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 | |
6447 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 | |
6448 | #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 | |
6449 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 | |
6450 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 | |
6451 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 | |
6452 | #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 | |
6453 | /* receive destination */ | |
6454 | #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 | |
6455 | /* enum: drop packets */ | |
6456 | #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 | |
6457 | /* enum: receive to host */ | |
6458 | #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 | |
6459 | /* enum: receive to MC */ | |
6460 | #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 | |
a9196bb0 | 6461 | /* enum: loop back to TXDP 0 */ |
f2b0befd | 6462 | #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 |
a9196bb0 | 6463 | /* enum: loop back to TXDP 1 */ |
f2b0befd BH |
6464 | #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 |
6465 | /* receive queue handle (for multiple queue modes, this is the base queue) */ | |
6466 | #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 | |
6467 | /* receive mode */ | |
6468 | #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 | |
6469 | /* enum: receive to just the specified queue */ | |
6470 | #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 | |
6471 | /* enum: receive to multiple queues using RSS context */ | |
6472 | #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 | |
6473 | /* enum: receive to multiple queues using .1p mapping */ | |
6474 | #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 | |
6475 | /* enum: install a filter entry that will never match; for test purposes only | |
6476 | */ | |
6477 | #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 | |
6478 | /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for | |
6479 | * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or | |
a9196bb0 | 6480 | * MC_CMD_DOT1P_MAPPING_ALLOC. |
f2b0befd BH |
6481 | */ |
6482 | #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 | |
6483 | /* transmit domain (reserved; set to 0) */ | |
6484 | #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 | |
6485 | /* transmit destination (either set the MAC and/or PM bits for explicit | |
6486 | * control, or set this field to TX_DEST_DEFAULT for sensible default | |
6487 | * behaviour) | |
6488 | */ | |
6489 | #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 | |
6490 | /* enum: request default behaviour (based on filter type) */ | |
6491 | #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff | |
6492 | #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 | |
6493 | #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 | |
6494 | #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 | |
6495 | #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 | |
6496 | /* source MAC address to match (as bytes in network order) */ | |
6497 | #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 | |
6498 | #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 | |
6499 | /* source port to match (as bytes in network order) */ | |
6500 | #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 | |
6501 | #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 | |
6502 | /* destination MAC address to match (as bytes in network order) */ | |
6503 | #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 | |
6504 | #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 | |
6505 | /* destination port to match (as bytes in network order) */ | |
6506 | #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 | |
6507 | #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 | |
6508 | /* Ethernet type to match (as bytes in network order) */ | |
6509 | #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 | |
6510 | #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 | |
6511 | /* Inner VLAN tag to match (as bytes in network order) */ | |
6512 | #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 | |
6513 | #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 | |
6514 | /* Outer VLAN tag to match (as bytes in network order) */ | |
6515 | #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 | |
6516 | #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 | |
6517 | /* IP protocol to match (in low byte; set high byte to 0) */ | |
6518 | #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 | |
6519 | #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 | |
6520 | /* Firmware defined register 0 to match (reserved; set to 0) */ | |
6521 | #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 | |
6522 | /* Firmware defined register 1 to match (reserved; set to 0) */ | |
6523 | #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 | |
6524 | /* source IP address to match (as bytes in network order; set last 12 bytes to | |
6525 | * 0 for IPv4 address) | |
6526 | */ | |
6527 | #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 | |
6528 | #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 | |
6529 | /* destination IP address to match (as bytes in network order; set last 12 | |
6530 | * bytes to 0 for IPv4 address) | |
6531 | */ | |
6532 | #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 | |
6533 | #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 | |
6534 | ||
a9196bb0 EC |
6535 | /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to |
6536 | * include handling of VXLAN/NVGRE encapsulated frame filtering (which is | |
6537 | * supported on Medford only). | |
6538 | */ | |
6539 | #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 | |
6540 | /* identifies the type of operation requested */ | |
6541 | #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 | |
6542 | /* Enum values, see field(s): */ | |
6543 | /* MC_CMD_FILTER_OP_IN/OP */ | |
6544 | /* filter handle (for remove / unsubscribe operations) */ | |
6545 | #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 | |
6546 | #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 | |
6547 | #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 | |
6548 | #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 | |
6549 | /* The port ID associated with the v-adaptor which should contain this filter. | |
6550 | */ | |
6551 | #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 | |
6552 | /* fields to include in match criteria */ | |
6553 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 | |
6554 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 | |
6555 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 | |
6556 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 | |
6557 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 | |
6558 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 | |
6559 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 | |
6560 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 | |
6561 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 | |
6562 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 | |
6563 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 | |
6564 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 | |
6565 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 | |
6566 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 | |
6567 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 | |
6568 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 | |
6569 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 | |
6570 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 | |
6571 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 | |
6572 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 | |
6573 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 | |
6574 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 | |
6575 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 | |
6576 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 | |
6577 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 | |
6578 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 | |
6579 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 | |
6580 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 | |
6581 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 | |
6582 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 | |
6583 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 | |
6584 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 | |
6585 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 | |
6586 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 | |
6587 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 | |
6588 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 | |
6589 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 | |
6590 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 | |
6591 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 | |
6592 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 | |
6593 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 | |
6594 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 | |
6595 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 | |
6596 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 | |
6597 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 | |
6598 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 | |
6599 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 | |
6600 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 | |
6601 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 | |
6602 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 | |
6603 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 | |
6604 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 | |
6605 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 | |
6606 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 | |
6607 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 | |
6608 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 | |
6609 | #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 | |
6610 | /* receive destination */ | |
6611 | #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 | |
6612 | /* enum: drop packets */ | |
6613 | #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 | |
6614 | /* enum: receive to host */ | |
6615 | #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 | |
6616 | /* enum: receive to MC */ | |
6617 | #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 | |
6618 | /* enum: loop back to TXDP 0 */ | |
6619 | #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 | |
6620 | /* enum: loop back to TXDP 1 */ | |
6621 | #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 | |
6622 | /* receive queue handle (for multiple queue modes, this is the base queue) */ | |
6623 | #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 | |
6624 | /* receive mode */ | |
6625 | #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 | |
6626 | /* enum: receive to just the specified queue */ | |
6627 | #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 | |
6628 | /* enum: receive to multiple queues using RSS context */ | |
6629 | #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 | |
6630 | /* enum: receive to multiple queues using .1p mapping */ | |
6631 | #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 | |
6632 | /* enum: install a filter entry that will never match; for test purposes only | |
6633 | */ | |
6634 | #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 | |
6635 | /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for | |
6636 | * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or | |
6637 | * MC_CMD_DOT1P_MAPPING_ALLOC. | |
6638 | */ | |
6639 | #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 | |
6640 | /* transmit domain (reserved; set to 0) */ | |
6641 | #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 | |
6642 | /* transmit destination (either set the MAC and/or PM bits for explicit | |
6643 | * control, or set this field to TX_DEST_DEFAULT for sensible default | |
6644 | * behaviour) | |
6645 | */ | |
6646 | #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 | |
6647 | /* enum: request default behaviour (based on filter type) */ | |
6648 | #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff | |
6649 | #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 | |
6650 | #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 | |
6651 | #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 | |
6652 | #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 | |
6653 | /* source MAC address to match (as bytes in network order) */ | |
6654 | #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 | |
6655 | #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 | |
6656 | /* source port to match (as bytes in network order) */ | |
6657 | #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 | |
6658 | #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 | |
6659 | /* destination MAC address to match (as bytes in network order) */ | |
6660 | #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 | |
6661 | #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 | |
6662 | /* destination port to match (as bytes in network order) */ | |
6663 | #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 | |
6664 | #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 | |
6665 | /* Ethernet type to match (as bytes in network order) */ | |
6666 | #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 | |
6667 | #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 | |
6668 | /* Inner VLAN tag to match (as bytes in network order) */ | |
6669 | #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 | |
6670 | #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 | |
6671 | /* Outer VLAN tag to match (as bytes in network order) */ | |
6672 | #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 | |
6673 | #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 | |
6674 | /* IP protocol to match (in low byte; set high byte to 0) */ | |
6675 | #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 | |
6676 | #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 | |
6677 | /* Firmware defined register 0 to match (reserved; set to 0) */ | |
6678 | #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 | |
6679 | /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP | |
6680 | * protocol is GRE) to match (as bytes in network order; set last byte to 0 for | |
6681 | * VXLAN/NVGRE, or 1 for Geneve) | |
6682 | */ | |
6683 | #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 | |
6684 | #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 | |
6685 | #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 | |
6686 | #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 | |
6687 | #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 | |
6688 | /* enum: Match VXLAN traffic with this VNI */ | |
6689 | #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 | |
6690 | /* enum: Match Geneve traffic with this VNI */ | |
6691 | #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 | |
6692 | /* enum: Reserved for experimental development use */ | |
6693 | #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe | |
6694 | #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 | |
6695 | #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 | |
6696 | #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 | |
6697 | #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 | |
6698 | /* enum: Match NVGRE traffic with this VSID */ | |
6699 | #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 | |
6700 | /* source IP address to match (as bytes in network order; set last 12 bytes to | |
6701 | * 0 for IPv4 address) | |
6702 | */ | |
6703 | #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 | |
6704 | #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 | |
6705 | /* destination IP address to match (as bytes in network order; set last 12 | |
6706 | * bytes to 0 for IPv4 address) | |
6707 | */ | |
6708 | #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 | |
6709 | #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 | |
6710 | /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network | |
6711 | * order) | |
6712 | */ | |
6713 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 | |
6714 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 | |
6715 | /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ | |
6716 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 | |
6717 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 | |
6718 | /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in | |
6719 | * network order) | |
6720 | */ | |
6721 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 | |
6722 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 | |
6723 | /* VXLAN/NVGRE inner frame destination port to match (as bytes in network | |
6724 | * order) | |
6725 | */ | |
6726 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 | |
6727 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 | |
6728 | /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) | |
6729 | */ | |
6730 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 | |
6731 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 | |
6732 | /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) | |
6733 | */ | |
6734 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 | |
6735 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 | |
6736 | /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) | |
6737 | */ | |
6738 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 | |
6739 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 | |
6740 | /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to | |
6741 | * 0) | |
6742 | */ | |
6743 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 | |
6744 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 | |
6745 | /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set | |
6746 | * to 0) | |
6747 | */ | |
6748 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 | |
6749 | /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set | |
6750 | * to 0) | |
6751 | */ | |
6752 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 | |
6753 | /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network | |
6754 | * order; set last 12 bytes to 0 for IPv4 address) | |
6755 | */ | |
6756 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 | |
6757 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 | |
6758 | /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network | |
6759 | * order; set last 12 bytes to 0 for IPv4 address) | |
6760 | */ | |
6761 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 | |
6762 | #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 | |
6763 | ||
f2b0befd BH |
6764 | /* MC_CMD_FILTER_OP_OUT msgresponse */ |
6765 | #define MC_CMD_FILTER_OP_OUT_LEN 12 | |
6766 | /* identifies the type of operation requested */ | |
6767 | #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 | |
6768 | /* Enum values, see field(s): */ | |
6769 | /* MC_CMD_FILTER_OP_IN/OP */ | |
6770 | /* Returned filter handle (for insert / subscribe operations). Note that these | |
6771 | * handles should be considered opaque to the host, although a value of | |
6772 | * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. | |
6773 | */ | |
6774 | #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 | |
6775 | #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 | |
6776 | #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 | |
6777 | #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 | |
a9196bb0 EC |
6778 | /* enum: guaranteed invalid filter handle (low 32 bits) */ |
6779 | #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff | |
6780 | /* enum: guaranteed invalid filter handle (high 32 bits) */ | |
6781 | #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff | |
6782 | ||
6783 | /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ | |
6784 | #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 | |
6785 | /* identifies the type of operation requested */ | |
6786 | #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 | |
6787 | /* Enum values, see field(s): */ | |
6788 | /* MC_CMD_FILTER_OP_EXT_IN/OP */ | |
6789 | /* Returned filter handle (for insert / subscribe operations). Note that these | |
6790 | * handles should be considered opaque to the host, although a value of | |
6791 | * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. | |
6792 | */ | |
6793 | #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 | |
6794 | #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 | |
6795 | #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 | |
6796 | #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 | |
6797 | /* Enum values, see field(s): */ | |
6798 | /* MC_CMD_FILTER_OP_OUT/HANDLE */ | |
f2b0befd BH |
6799 | |
6800 | ||
6801 | /***********************************/ | |
6802 | /* MC_CMD_GET_PARSER_DISP_INFO | |
6803 | * Get information related to the parser-dispatcher subsystem | |
6804 | */ | |
6805 | #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 | |
6806 | ||
75122ec8 SS |
6807 | #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6808 | ||
f2b0befd BH |
6809 | /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ |
6810 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 | |
6811 | /* identifies the type of operation requested */ | |
6812 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 | |
6813 | /* enum: read the list of supported RX filter matches */ | |
6814 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 | |
a9196bb0 EC |
6815 | /* enum: read flags indicating restrictions on filter insertion for the calling |
6816 | * client | |
6817 | */ | |
6818 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 | |
23e202b4 EC |
6819 | /* enum: read properties relating to security rules (Medford-only; for use by |
6820 | * SolarSecure apps, not directly by drivers. See SF-114946-SW.) | |
6821 | */ | |
6822 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 | |
6823 | /* enum: read the list of supported RX filter matches for VXLAN/NVGRE | |
6824 | * encapsulated frames, which follow a different match sequence to normal | |
6825 | * frames (Medford only) | |
6826 | */ | |
6827 | #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 | |
f2b0befd BH |
6828 | |
6829 | /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ | |
6830 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 | |
6831 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 | |
6832 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) | |
6833 | /* identifies the type of operation requested */ | |
6834 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 | |
6835 | /* Enum values, see field(s): */ | |
6836 | /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ | |
6837 | /* number of supported match types */ | |
6838 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 | |
6839 | /* array of supported match types (valid MATCH_FIELDS values for | |
6840 | * MC_CMD_FILTER_OP) sorted in decreasing priority order | |
6841 | */ | |
6842 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 | |
6843 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 | |
6844 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 | |
6845 | #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 | |
6846 | ||
a9196bb0 EC |
6847 | /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ |
6848 | #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 | |
6849 | /* identifies the type of operation requested */ | |
6850 | #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 | |
6851 | /* Enum values, see field(s): */ | |
6852 | /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ | |
6853 | /* bitfield of filter insertion restrictions */ | |
6854 | #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 | |
6855 | #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 | |
6856 | #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 | |
6857 | ||
f2b0befd BH |
6858 | |
6859 | /***********************************/ | |
6860 | /* MC_CMD_PARSER_DISP_RW | |
23e202b4 EC |
6861 | * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. |
6862 | * Please note that this interface is only of use to debug tools which have | |
6863 | * knowledge of firmware and hardware data structures; nothing here is intended | |
6864 | * for use by normal driver code. | |
f2b0befd BH |
6865 | */ |
6866 | #define MC_CMD_PARSER_DISP_RW 0xe5 | |
6867 | ||
75122ec8 SS |
6868 | #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6869 | ||
f2b0befd BH |
6870 | /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ |
6871 | #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 | |
6872 | /* identifies the target of the operation */ | |
6873 | #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 | |
6874 | /* enum: RX dispatcher CPU */ | |
6875 | #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 | |
6876 | /* enum: TX dispatcher CPU */ | |
6877 | #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 | |
a9196bb0 | 6878 | /* enum: Lookup engine (with original metadata format) */ |
f2b0befd | 6879 | #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 |
a9196bb0 EC |
6880 | /* enum: Lookup engine (with requested metadata format) */ |
6881 | #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 | |
23e202b4 EC |
6882 | /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ |
6883 | #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 | |
6884 | /* enum: RX1 dispatcher CPU (only valid for Medford) */ | |
6885 | #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 | |
6886 | /* enum: Miscellaneous other state (only valid for Medford) */ | |
6887 | #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 | |
f2b0befd BH |
6888 | /* identifies the type of operation requested */ |
6889 | #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 | |
6890 | /* enum: read a word of DICPU DMEM or a LUE entry */ | |
6891 | #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 | |
6892 | /* enum: write a word of DICPU DMEM or a LUE entry */ | |
6893 | #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 | |
6894 | /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ | |
6895 | #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 | |
23e202b4 | 6896 | /* data memory address (DICPU targets) or LUE index (LUE targets) */ |
f2b0befd | 6897 | #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 |
23e202b4 EC |
6898 | /* selector (for MISC_STATE target) */ |
6899 | #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 | |
6900 | /* enum: Port to datapath mapping */ | |
6901 | #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 | |
f2b0befd BH |
6902 | /* value to write (for DMEM writes) */ |
6903 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 | |
6904 | /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ | |
6905 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 | |
6906 | /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ | |
6907 | #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 | |
a9196bb0 EC |
6908 | /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ |
6909 | #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 | |
f2b0befd BH |
6910 | /* value to write (for LUE writes) */ |
6911 | #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 | |
6912 | #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 | |
6913 | ||
6914 | /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ | |
6915 | #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 | |
6916 | /* value read (for DMEM reads) */ | |
6917 | #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 | |
6918 | /* value read (for LUE reads) */ | |
6919 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 | |
6920 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 | |
6921 | /* up to 8 32-bit words of additional soft state from the LUE manager (the | |
6922 | * exact content is firmware-dependent and intended only for debug use) | |
6923 | */ | |
6924 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 | |
6925 | #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 | |
23e202b4 EC |
6926 | /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ |
6927 | #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 | |
6928 | #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 | |
6929 | #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 | |
6930 | #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ | |
6931 | #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ | |
f2b0befd BH |
6932 | |
6933 | ||
6934 | /***********************************/ | |
6935 | /* MC_CMD_GET_PF_COUNT | |
6936 | * Get number of PFs on the device. | |
6937 | */ | |
6938 | #define MC_CMD_GET_PF_COUNT 0xb6 | |
6939 | ||
75122ec8 SS |
6940 | #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6941 | ||
f2b0befd BH |
6942 | /* MC_CMD_GET_PF_COUNT_IN msgrequest */ |
6943 | #define MC_CMD_GET_PF_COUNT_IN_LEN 0 | |
6944 | ||
6945 | /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ | |
6946 | #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 | |
6947 | /* Identifies the number of PFs on the device. */ | |
6948 | #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 | |
6949 | #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 | |
6950 | ||
6951 | ||
6952 | /***********************************/ | |
6953 | /* MC_CMD_SET_PF_COUNT | |
6954 | * Set number of PFs on the device. | |
6955 | */ | |
6956 | #define MC_CMD_SET_PF_COUNT 0xb7 | |
6957 | ||
6958 | /* MC_CMD_SET_PF_COUNT_IN msgrequest */ | |
6959 | #define MC_CMD_SET_PF_COUNT_IN_LEN 4 | |
6960 | /* New number of PFs on the device. */ | |
6961 | #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 | |
6962 | ||
6963 | /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ | |
6964 | #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 | |
6965 | ||
6966 | ||
6967 | /***********************************/ | |
6968 | /* MC_CMD_GET_PORT_ASSIGNMENT | |
6969 | * Get port assignment for current PCI function. | |
6970 | */ | |
6971 | #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 | |
6972 | ||
75122ec8 SS |
6973 | #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
6974 | ||
f2b0befd BH |
6975 | /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ |
6976 | #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 | |
6977 | ||
6978 | /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ | |
6979 | #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 | |
6980 | /* Identifies the port assignment for this function. */ | |
6981 | #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 | |
6982 | ||
6983 | ||
6984 | /***********************************/ | |
6985 | /* MC_CMD_SET_PORT_ASSIGNMENT | |
6986 | * Set port assignment for current PCI function. | |
6987 | */ | |
6988 | #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 | |
6989 | ||
75122ec8 SS |
6990 | #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
6991 | ||
f2b0befd BH |
6992 | /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ |
6993 | #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 | |
6994 | /* Identifies the port assignment for this function. */ | |
6995 | #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 | |
6996 | ||
6997 | /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ | |
6998 | #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 | |
6999 | ||
7000 | ||
7001 | /***********************************/ | |
7002 | /* MC_CMD_ALLOC_VIS | |
7003 | * Allocate VIs for current PCI function. | |
7004 | */ | |
7005 | #define MC_CMD_ALLOC_VIS 0x8b | |
7006 | ||
75122ec8 SS |
7007 | #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7008 | ||
f2b0befd BH |
7009 | /* MC_CMD_ALLOC_VIS_IN msgrequest */ |
7010 | #define MC_CMD_ALLOC_VIS_IN_LEN 8 | |
7011 | /* The minimum number of VIs that is acceptable */ | |
7012 | #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 | |
7013 | /* The maximum number of VIs that would be useful */ | |
7014 | #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 | |
7015 | ||
a9196bb0 EC |
7016 | /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. |
7017 | * Use extended version in new code. | |
7018 | */ | |
f2b0befd BH |
7019 | #define MC_CMD_ALLOC_VIS_OUT_LEN 8 |
7020 | /* The number of VIs allocated on this function */ | |
7021 | #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 | |
7022 | /* The base absolute VI number allocated to this function. Required to | |
7023 | * correctly interpret wakeup events. | |
7024 | */ | |
7025 | #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 | |
7026 | ||
a9196bb0 EC |
7027 | /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ |
7028 | #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 | |
7029 | /* The number of VIs allocated on this function */ | |
7030 | #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 | |
7031 | /* The base absolute VI number allocated to this function. Required to | |
7032 | * correctly interpret wakeup events. | |
7033 | */ | |
7034 | #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 | |
7035 | /* Function's port vi_shift value (always 0 on Huntington) */ | |
7036 | #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 | |
7037 | ||
f2b0befd BH |
7038 | |
7039 | /***********************************/ | |
7040 | /* MC_CMD_FREE_VIS | |
7041 | * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, | |
7042 | * but not freed. | |
7043 | */ | |
7044 | #define MC_CMD_FREE_VIS 0x8c | |
7045 | ||
75122ec8 SS |
7046 | #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7047 | ||
f2b0befd BH |
7048 | /* MC_CMD_FREE_VIS_IN msgrequest */ |
7049 | #define MC_CMD_FREE_VIS_IN_LEN 0 | |
7050 | ||
7051 | /* MC_CMD_FREE_VIS_OUT msgresponse */ | |
7052 | #define MC_CMD_FREE_VIS_OUT_LEN 0 | |
7053 | ||
7054 | ||
7055 | /***********************************/ | |
7056 | /* MC_CMD_GET_SRIOV_CFG | |
7057 | * Get SRIOV config for this PF. | |
7058 | */ | |
7059 | #define MC_CMD_GET_SRIOV_CFG 0xba | |
7060 | ||
75122ec8 SS |
7061 | #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7062 | ||
f2b0befd BH |
7063 | /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ |
7064 | #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 | |
7065 | ||
7066 | /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ | |
7067 | #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 | |
7068 | /* Number of VFs currently enabled. */ | |
7069 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 | |
7070 | /* Max number of VFs before sriov stride and offset may need to be changed. */ | |
7071 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 | |
7072 | #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 | |
7073 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 | |
7074 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 | |
7075 | /* RID offset of first VF from PF. */ | |
7076 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 | |
7077 | /* RID offset of each subsequent VF from the previous. */ | |
7078 | #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 | |
7079 | ||
7080 | ||
7081 | /***********************************/ | |
7082 | /* MC_CMD_SET_SRIOV_CFG | |
7083 | * Set SRIOV config for this PF. | |
7084 | */ | |
7085 | #define MC_CMD_SET_SRIOV_CFG 0xbb | |
7086 | ||
75122ec8 SS |
7087 | #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7088 | ||
f2b0befd BH |
7089 | /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ |
7090 | #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 | |
7091 | /* Number of VFs currently enabled. */ | |
7092 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 | |
7093 | /* Max number of VFs before sriov stride and offset may need to be changed. */ | |
7094 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 | |
7095 | #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 | |
7096 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 | |
7097 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 | |
7098 | /* RID offset of first VF from PF, or 0 for no change, or | |
7099 | * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. | |
7100 | */ | |
7101 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 | |
7102 | /* RID offset of each subsequent VF from the previous, 0 for no change, or | |
7103 | * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. | |
7104 | */ | |
7105 | #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 | |
7106 | ||
7107 | /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ | |
7108 | #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 | |
7109 | ||
7110 | ||
7111 | /***********************************/ | |
7112 | /* MC_CMD_GET_VI_ALLOC_INFO | |
7113 | * Get information about number of VI's and base VI number allocated to this | |
7114 | * function. | |
7115 | */ | |
7116 | #define MC_CMD_GET_VI_ALLOC_INFO 0x8d | |
7117 | ||
75122ec8 SS |
7118 | #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7119 | ||
f2b0befd BH |
7120 | /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ |
7121 | #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 | |
7122 | ||
7123 | /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ | |
a9196bb0 | 7124 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 |
f2b0befd BH |
7125 | /* The number of VIs allocated on this function */ |
7126 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 | |
7127 | /* The base absolute VI number allocated to this function. Required to | |
7128 | * correctly interpret wakeup events. | |
7129 | */ | |
7130 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 | |
a9196bb0 EC |
7131 | /* Function's port vi_shift value (always 0 on Huntington) */ |
7132 | #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 | |
f2b0befd BH |
7133 | |
7134 | ||
7135 | /***********************************/ | |
7136 | /* MC_CMD_DUMP_VI_STATE | |
7137 | * For CmdClient use. Dump pertinent information on a specific absolute VI. | |
7138 | */ | |
7139 | #define MC_CMD_DUMP_VI_STATE 0x8e | |
7140 | ||
75122ec8 SS |
7141 | #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7142 | ||
f2b0befd BH |
7143 | /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ |
7144 | #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 | |
7145 | /* The VI number to query. */ | |
7146 | #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 | |
7147 | ||
7148 | /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ | |
7149 | #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 | |
7150 | /* The PF part of the function owning this VI. */ | |
7151 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 | |
7152 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 | |
7153 | /* The VF part of the function owning this VI. */ | |
7154 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 | |
7155 | #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 | |
7156 | /* Base of VIs allocated to this function. */ | |
7157 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 | |
7158 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 | |
7159 | /* Count of VIs allocated to the owner function. */ | |
7160 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 | |
7161 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 | |
7162 | /* Base interrupt vector allocated to this function. */ | |
7163 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 | |
7164 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 | |
7165 | /* Number of interrupt vectors allocated to this function. */ | |
7166 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 | |
7167 | #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 | |
7168 | /* Raw evq ptr table data. */ | |
7169 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 | |
7170 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 | |
7171 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 | |
7172 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 | |
7173 | /* Raw evq timer table data. */ | |
7174 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 | |
7175 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 | |
7176 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 | |
7177 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 | |
7178 | /* Combined metadata field. */ | |
7179 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 | |
7180 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 | |
7181 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 | |
7182 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 | |
7183 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 | |
7184 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 | |
7185 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 | |
7186 | /* TXDPCPU raw table data for queue. */ | |
7187 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 | |
7188 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 | |
7189 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 | |
7190 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 | |
7191 | /* TXDPCPU raw table data for queue. */ | |
7192 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 | |
7193 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 | |
7194 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 | |
7195 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 | |
7196 | /* TXDPCPU raw table data for queue. */ | |
7197 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 | |
7198 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 | |
7199 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 | |
7200 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 | |
7201 | /* Combined metadata field. */ | |
7202 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 | |
7203 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 | |
7204 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 | |
7205 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 | |
7206 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 | |
7207 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 | |
7208 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 | |
7209 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 | |
7210 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 | |
7211 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 | |
7212 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 | |
7213 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 | |
7214 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 | |
7215 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 | |
7216 | /* RXDPCPU raw table data for queue. */ | |
7217 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 | |
7218 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 | |
7219 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 | |
7220 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 | |
7221 | /* RXDPCPU raw table data for queue. */ | |
7222 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 | |
7223 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 | |
7224 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 | |
7225 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 | |
7226 | /* Reserved, currently 0. */ | |
7227 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 | |
7228 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 | |
7229 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 | |
7230 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 | |
7231 | /* Combined metadata field. */ | |
7232 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 | |
7233 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 | |
7234 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 | |
7235 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 | |
7236 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 | |
7237 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 | |
7238 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 | |
7239 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 | |
7240 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 | |
7241 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 | |
7242 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 | |
7243 | #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 | |
7244 | ||
7245 | ||
7246 | /***********************************/ | |
7247 | /* MC_CMD_ALLOC_PIOBUF | |
7248 | * Allocate a push I/O buffer for later use with a tx queue. | |
7249 | */ | |
7250 | #define MC_CMD_ALLOC_PIOBUF 0x8f | |
7251 | ||
75122ec8 SS |
7252 | #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
7253 | ||
f2b0befd BH |
7254 | /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ |
7255 | #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 | |
7256 | ||
7257 | /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ | |
7258 | #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 | |
7259 | /* Handle for allocated push I/O buffer. */ | |
7260 | #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 | |
7261 | ||
7262 | ||
7263 | /***********************************/ | |
7264 | /* MC_CMD_FREE_PIOBUF | |
7265 | * Free a push I/O buffer. | |
7266 | */ | |
7267 | #define MC_CMD_FREE_PIOBUF 0x90 | |
7268 | ||
75122ec8 SS |
7269 | #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
7270 | ||
f2b0befd BH |
7271 | /* MC_CMD_FREE_PIOBUF_IN msgrequest */ |
7272 | #define MC_CMD_FREE_PIOBUF_IN_LEN 4 | |
7273 | /* Handle for allocated push I/O buffer. */ | |
7274 | #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 | |
7275 | ||
7276 | /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ | |
7277 | #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 | |
7278 | ||
7279 | ||
7280 | /***********************************/ | |
7281 | /* MC_CMD_GET_VI_TLP_PROCESSING | |
7282 | * Get TLP steering and ordering information for a VI. | |
7283 | */ | |
7284 | #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 | |
7285 | ||
75122ec8 SS |
7286 | #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7287 | ||
f2b0befd BH |
7288 | /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ |
7289 | #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 | |
7290 | /* VI number to get information for. */ | |
7291 | #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 | |
7292 | ||
7293 | /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ | |
7294 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 | |
7295 | /* Transaction processing steering hint 1 for use with the Rx Queue. */ | |
7296 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 | |
7297 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 | |
7298 | /* Transaction processing steering hint 2 for use with the Ev Queue. */ | |
7299 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 | |
7300 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 | |
7301 | /* Use Relaxed ordering model for TLPs on this VI. */ | |
7302 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 | |
7303 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 | |
7304 | /* Use ID based ordering for TLPs on this VI. */ | |
7305 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 | |
7306 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 | |
7307 | /* Set no snoop bit for TLPs on this VI. */ | |
7308 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 | |
7309 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 | |
7310 | /* Enable TPH for TLPs on this VI. */ | |
7311 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 | |
7312 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 | |
7313 | #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 | |
7314 | ||
7315 | ||
7316 | /***********************************/ | |
7317 | /* MC_CMD_SET_VI_TLP_PROCESSING | |
7318 | * Set TLP steering and ordering information for a VI. | |
7319 | */ | |
7320 | #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 | |
7321 | ||
75122ec8 SS |
7322 | #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
7323 | ||
f2b0befd BH |
7324 | /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ |
7325 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 | |
7326 | /* VI number to set information for. */ | |
7327 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 | |
7328 | /* Transaction processing steering hint 1 for use with the Rx Queue. */ | |
7329 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 | |
7330 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 | |
7331 | /* Transaction processing steering hint 2 for use with the Ev Queue. */ | |
7332 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 | |
7333 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 | |
7334 | /* Use Relaxed ordering model for TLPs on this VI. */ | |
7335 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 | |
7336 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 | |
7337 | /* Use ID based ordering for TLPs on this VI. */ | |
7338 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 | |
7339 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 | |
7340 | /* Set the no snoop bit for TLPs on this VI. */ | |
7341 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 | |
7342 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 | |
7343 | /* Enable TPH for TLPs on this VI. */ | |
7344 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 | |
7345 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 | |
7346 | #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 | |
7347 | ||
7348 | /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ | |
7349 | #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 | |
7350 | ||
7351 | ||
7352 | /***********************************/ | |
7353 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS | |
7354 | * Get global PCIe steering and transaction processing configuration. | |
7355 | */ | |
7356 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc | |
7357 | ||
75122ec8 SS |
7358 | #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7359 | ||
f2b0befd BH |
7360 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ |
7361 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 | |
7362 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 | |
7363 | /* enum: MISC. */ | |
7364 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 | |
7365 | /* enum: IDO. */ | |
7366 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 | |
7367 | /* enum: RO. */ | |
7368 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 | |
7369 | /* enum: TPH Type. */ | |
7370 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 | |
7371 | ||
7372 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ | |
7373 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 | |
7374 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 | |
7375 | /* Enum values, see field(s): */ | |
7376 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ | |
7377 | /* Amalgamated TLP info word. */ | |
7378 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 | |
7379 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 | |
7380 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 | |
7381 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 | |
7382 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 | |
7383 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 | |
7384 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 | |
7385 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 | |
7386 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 | |
7387 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 | |
7388 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 | |
7389 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 | |
7390 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 | |
7391 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 | |
7392 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 | |
7393 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 | |
7394 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 | |
7395 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 | |
7396 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 | |
7397 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 | |
7398 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 | |
7399 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 | |
7400 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 | |
7401 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 | |
7402 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 | |
7403 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 | |
7404 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 | |
7405 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 | |
7406 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 | |
7407 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 | |
7408 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 | |
7409 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 | |
7410 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 | |
7411 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 | |
7412 | #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 | |
7413 | ||
7414 | ||
7415 | /***********************************/ | |
7416 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS | |
7417 | * Set global PCIe steering and transaction processing configuration. | |
7418 | */ | |
7419 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd | |
7420 | ||
75122ec8 SS |
7421 | #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7422 | ||
f2b0befd BH |
7423 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ |
7424 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 | |
7425 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 | |
7426 | /* Enum values, see field(s): */ | |
7427 | /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ | |
7428 | /* Amalgamated TLP info word. */ | |
7429 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 | |
7430 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 | |
7431 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 | |
7432 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 | |
7433 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 | |
7434 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 | |
7435 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 | |
7436 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 | |
7437 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 | |
7438 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 | |
7439 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 | |
7440 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 | |
7441 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 | |
7442 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 | |
7443 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 | |
7444 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 | |
7445 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 | |
7446 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 | |
7447 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 | |
7448 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 | |
7449 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 | |
7450 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 | |
7451 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 | |
7452 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 | |
7453 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 | |
7454 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 | |
7455 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 | |
7456 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 | |
7457 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 | |
7458 | ||
7459 | /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ | |
7460 | #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 | |
7461 | ||
7462 | ||
7463 | /***********************************/ | |
7464 | /* MC_CMD_SATELLITE_DOWNLOAD | |
7465 | * Download a new set of images to the satellite CPUs from the host. | |
7466 | */ | |
7467 | #define MC_CMD_SATELLITE_DOWNLOAD 0x91 | |
7468 | ||
75122ec8 SS |
7469 | #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
7470 | ||
f2b0befd BH |
7471 | /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs |
7472 | * are subtle, and so downloads must proceed in a number of phases. | |
7473 | * | |
7474 | * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. | |
7475 | * | |
7476 | * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download | |
7477 | * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should | |
7478 | * be a checksum (a simple 32-bit sum) of the transferred data. An individual | |
7479 | * download may be aborted using CHUNK_ID_ABORT. | |
7480 | * | |
7481 | * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), | |
7482 | * similar to PHASE_IMEMS. | |
7483 | * | |
7484 | * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. | |
7485 | * | |
7486 | * After any error (a requested abort is not considered to be an error) the | |
7487 | * sequence must be restarted from PHASE_RESET. | |
7488 | */ | |
7489 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 | |
7490 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 | |
7491 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) | |
7492 | /* Download phase. (Note: the IDLE phase is used internally and is never valid | |
7493 | * in a command from the host.) | |
7494 | */ | |
7495 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 | |
7496 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ | |
7497 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ | |
7498 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ | |
7499 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ | |
7500 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ | |
7501 | /* Target for download. (These match the blob numbers defined in | |
7502 | * mc_flash_layout.h.) | |
7503 | */ | |
7504 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 | |
7505 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7506 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 | |
7507 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7508 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 | |
7509 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7510 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 | |
7511 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7512 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 | |
7513 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7514 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 | |
7515 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7516 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 | |
7517 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7518 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 | |
7519 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7520 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 | |
7521 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7522 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 | |
7523 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7524 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 | |
7525 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7526 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa | |
7527 | /* enum: Valid in phase 2 (PHASE_IMEMS) only */ | |
7528 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb | |
7529 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
7530 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc | |
7531 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
7532 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd | |
7533 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
7534 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe | |
7535 | /* enum: Valid in phase 3 (PHASE_VECTORS) only */ | |
7536 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf | |
7537 | /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ | |
7538 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff | |
7539 | /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ | |
7540 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 | |
7541 | /* enum: Last chunk, containing checksum rather than data */ | |
7542 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff | |
7543 | /* enum: Abort download of this item */ | |
7544 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe | |
7545 | /* Length of this chunk in bytes */ | |
7546 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 | |
7547 | /* Data for this chunk */ | |
7548 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 | |
7549 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 | |
7550 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 | |
7551 | #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 | |
7552 | ||
7553 | /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ | |
7554 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 | |
7555 | /* Same as MC_CMD_ERR field, but included as 0 in success cases */ | |
7556 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 | |
7557 | /* Extra status information */ | |
7558 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 | |
7559 | /* enum: Code download OK, completed. */ | |
7560 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 | |
7561 | /* enum: Code download aborted as requested. */ | |
7562 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 | |
7563 | /* enum: Code download OK so far, send next chunk. */ | |
7564 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 | |
7565 | /* enum: Download phases out of sequence */ | |
7566 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 | |
7567 | /* enum: Bad target for this phase */ | |
7568 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 | |
7569 | /* enum: Chunk ID out of sequence */ | |
7570 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 | |
7571 | /* enum: Chunk length zero or too large */ | |
7572 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 | |
7573 | /* enum: Checksum was incorrect */ | |
7574 | #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 | |
7575 | ||
7576 | ||
7577 | /***********************************/ | |
7578 | /* MC_CMD_GET_CAPABILITIES | |
7579 | * Get device capabilities. | |
7580 | * | |
7581 | * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to | |
7582 | * reference inherent device capabilities as opposed to current NVRAM config. | |
7583 | */ | |
7584 | #define MC_CMD_GET_CAPABILITIES 0xbe | |
7585 | ||
75122ec8 | 7586 | #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
a9196bb0 | 7587 | |
f2b0befd BH |
7588 | /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ |
7589 | #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 | |
7590 | ||
7591 | /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ | |
7592 | #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 | |
7593 | /* First word of flags. */ | |
7594 | #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 | |
23e202b4 EC |
7595 | #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 |
7596 | #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 | |
7597 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 | |
7598 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 | |
7599 | #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 | |
7600 | #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 | |
7601 | #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 | |
7602 | #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 | |
7603 | #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 | |
7604 | #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 | |
7605 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 | |
7606 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 | |
7607 | #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 | |
7608 | #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 | |
7609 | #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 | |
7610 | #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 | |
7611 | #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 | |
7612 | #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 | |
a9196bb0 EC |
7613 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 |
7614 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 | |
7615 | #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 | |
7616 | #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 | |
7617 | #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 | |
7618 | #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 | |
7619 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 | |
7620 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 | |
7621 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 | |
7622 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 | |
7623 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 | |
7624 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 | |
7625 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 | |
7626 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 | |
f2b0befd BH |
7627 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 |
7628 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 | |
7629 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 | |
7630 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 | |
7631 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 | |
7632 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 | |
7633 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 | |
7634 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 | |
7635 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 | |
7636 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 | |
7637 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 | |
7638 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 | |
7639 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 | |
7640 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 | |
7641 | #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 | |
7642 | #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 | |
2ca10a75 MS |
7643 | #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 |
7644 | #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 | |
a9196bb0 EC |
7645 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 |
7646 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 | |
7647 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 | |
7648 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 | |
d94619cd DP |
7649 | #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 |
7650 | #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 | |
a9196bb0 EC |
7651 | #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 |
7652 | #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 | |
f2b0befd BH |
7653 | /* RxDPCPU firmware id. */ |
7654 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 | |
7655 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 | |
7656 | /* enum: Standard RXDP firmware */ | |
7657 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 | |
7658 | /* enum: Low latency RXDP firmware */ | |
7659 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 | |
a9196bb0 EC |
7660 | /* enum: Packed stream RXDP firmware */ |
7661 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 | |
7662 | /* enum: BIST RXDP firmware */ | |
7663 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a | |
f2b0befd BH |
7664 | /* enum: RXDP Test firmware image 1 */ |
7665 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 | |
7666 | /* enum: RXDP Test firmware image 2 */ | |
7667 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 | |
7668 | /* enum: RXDP Test firmware image 3 */ | |
7669 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 | |
7670 | /* enum: RXDP Test firmware image 4 */ | |
7671 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 | |
7672 | /* enum: RXDP Test firmware image 5 */ | |
7673 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 | |
7674 | /* enum: RXDP Test firmware image 6 */ | |
7675 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 | |
7676 | /* enum: RXDP Test firmware image 7 */ | |
7677 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 | |
7678 | /* enum: RXDP Test firmware image 8 */ | |
7679 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 | |
23e202b4 EC |
7680 | /* enum: RXDP Test firmware image 9 */ |
7681 | #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b | |
f2b0befd BH |
7682 | /* TxDPCPU firmware id. */ |
7683 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 | |
7684 | #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 | |
7685 | /* enum: Standard TXDP firmware */ | |
7686 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 | |
7687 | /* enum: Low latency TXDP firmware */ | |
7688 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 | |
a9196bb0 EC |
7689 | /* enum: High packet rate TXDP firmware */ |
7690 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 | |
7691 | /* enum: BIST TXDP firmware */ | |
7692 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d | |
f2b0befd BH |
7693 | /* enum: TXDP Test firmware image 1 */ |
7694 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 | |
7695 | /* enum: TXDP Test firmware image 2 */ | |
7696 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 | |
23e202b4 EC |
7697 | /* enum: TXDP CSR bus test firmware */ |
7698 | #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 | |
f2b0befd BH |
7699 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 |
7700 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 | |
7701 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 | |
7702 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 | |
7703 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 | |
7704 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 | |
a9196bb0 EC |
7705 | /* enum: reserved value - do not use (may indicate alternative interpretation |
7706 | * of REV field in future) | |
7707 | */ | |
7708 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 | |
7709 | /* enum: Trivial RX PD firmware for early Huntington development (Huntington | |
7710 | * development only) | |
7711 | */ | |
7712 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 | |
7713 | /* enum: RX PD firmware with approximately Siena-compatible behaviour | |
7714 | * (Huntington development only) | |
7715 | */ | |
7716 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 | |
7717 | /* enum: Virtual switching (full feature) RX PD production firmware */ | |
7718 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 | |
7719 | /* enum: siena_compat variant RX PD firmware using PM rather than MAC | |
7720 | * (Huntington development only) | |
7721 | */ | |
7722 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 | |
7723 | /* enum: Low latency RX PD production firmware */ | |
7724 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 | |
7725 | /* enum: Packed stream RX PD production firmware */ | |
7726 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 | |
7727 | /* enum: RX PD firmware handling layer 2 only for high packet rate performance | |
7728 | * tests (Medford development only) | |
7729 | */ | |
7730 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 | |
7731 | /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ | |
7732 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe | |
7733 | /* enum: RX PD firmware parsing but not filtering network overlay tunnel | |
7734 | * encapsulations (Medford development only) | |
7735 | */ | |
7736 | #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf | |
f2b0befd BH |
7737 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 |
7738 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 | |
7739 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 | |
7740 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 | |
7741 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 | |
7742 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 | |
a9196bb0 EC |
7743 | /* enum: reserved value - do not use (may indicate alternative interpretation |
7744 | * of REV field in future) | |
7745 | */ | |
7746 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 | |
7747 | /* enum: Trivial TX PD firmware for early Huntington development (Huntington | |
7748 | * development only) | |
7749 | */ | |
7750 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 | |
7751 | /* enum: TX PD firmware with approximately Siena-compatible behaviour | |
7752 | * (Huntington development only) | |
7753 | */ | |
7754 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 | |
7755 | /* enum: Virtual switching (full feature) TX PD production firmware */ | |
7756 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 | |
7757 | /* enum: siena_compat variant TX PD firmware using PM rather than MAC | |
7758 | * (Huntington development only) | |
7759 | */ | |
7760 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 | |
f2b0befd | 7761 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ |
a9196bb0 EC |
7762 | /* enum: TX PD firmware handling layer 2 only for high packet rate performance |
7763 | * tests (Medford development only) | |
7764 | */ | |
7765 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 | |
7766 | /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ | |
7767 | #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe | |
f2b0befd BH |
7768 | /* Hardware capabilities of NIC */ |
7769 | #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 | |
7770 | /* Licensed capabilities */ | |
7771 | #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 | |
7772 | ||
23e202b4 EC |
7773 | /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ |
7774 | #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 | |
7775 | ||
7776 | /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ | |
7777 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 | |
7778 | /* First word of flags. */ | |
7779 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 | |
7780 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 | |
7781 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 | |
7782 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 | |
7783 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 | |
7784 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 | |
7785 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 | |
7786 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 | |
7787 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 | |
7788 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 | |
7789 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 | |
7790 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 | |
7791 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 | |
7792 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 | |
7793 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 | |
7794 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 | |
7795 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 | |
7796 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 | |
7797 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 | |
7798 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 | |
7799 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 | |
7800 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 | |
7801 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 | |
7802 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 | |
7803 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 | |
7804 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 | |
7805 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 | |
7806 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 | |
7807 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 | |
7808 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 | |
7809 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 | |
7810 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 | |
7811 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 | |
7812 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 | |
7813 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 | |
7814 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 | |
7815 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 | |
7816 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 | |
7817 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 | |
7818 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 | |
7819 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 | |
7820 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 | |
7821 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 | |
7822 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 | |
7823 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 | |
7824 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 | |
7825 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 | |
7826 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 | |
7827 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 | |
7828 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 | |
7829 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 | |
7830 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 | |
7831 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 | |
7832 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 | |
7833 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 | |
7834 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 | |
7835 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 | |
7836 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 | |
7837 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 | |
7838 | /* RxDPCPU firmware id. */ | |
7839 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 | |
7840 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 | |
7841 | /* enum: Standard RXDP firmware */ | |
7842 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 | |
7843 | /* enum: Low latency RXDP firmware */ | |
7844 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 | |
7845 | /* enum: Packed stream RXDP firmware */ | |
7846 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 | |
7847 | /* enum: BIST RXDP firmware */ | |
7848 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a | |
7849 | /* enum: RXDP Test firmware image 1 */ | |
7850 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 | |
7851 | /* enum: RXDP Test firmware image 2 */ | |
7852 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 | |
7853 | /* enum: RXDP Test firmware image 3 */ | |
7854 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 | |
7855 | /* enum: RXDP Test firmware image 4 */ | |
7856 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 | |
7857 | /* enum: RXDP Test firmware image 5 */ | |
7858 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 | |
7859 | /* enum: RXDP Test firmware image 6 */ | |
7860 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 | |
7861 | /* enum: RXDP Test firmware image 7 */ | |
7862 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 | |
7863 | /* enum: RXDP Test firmware image 8 */ | |
7864 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 | |
7865 | /* enum: RXDP Test firmware image 9 */ | |
7866 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b | |
7867 | /* TxDPCPU firmware id. */ | |
7868 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 | |
7869 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 | |
7870 | /* enum: Standard TXDP firmware */ | |
7871 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 | |
7872 | /* enum: Low latency TXDP firmware */ | |
7873 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 | |
7874 | /* enum: High packet rate TXDP firmware */ | |
7875 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 | |
7876 | /* enum: BIST TXDP firmware */ | |
7877 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d | |
7878 | /* enum: TXDP Test firmware image 1 */ | |
7879 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 | |
7880 | /* enum: TXDP Test firmware image 2 */ | |
7881 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 | |
7882 | /* enum: TXDP CSR bus test firmware */ | |
7883 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 | |
7884 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 | |
7885 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 | |
7886 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 | |
7887 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 | |
7888 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 | |
7889 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 | |
7890 | /* enum: reserved value - do not use (may indicate alternative interpretation | |
7891 | * of REV field in future) | |
7892 | */ | |
7893 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 | |
7894 | /* enum: Trivial RX PD firmware for early Huntington development (Huntington | |
7895 | * development only) | |
7896 | */ | |
7897 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 | |
7898 | /* enum: RX PD firmware with approximately Siena-compatible behaviour | |
7899 | * (Huntington development only) | |
7900 | */ | |
7901 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 | |
7902 | /* enum: Virtual switching (full feature) RX PD production firmware */ | |
7903 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 | |
7904 | /* enum: siena_compat variant RX PD firmware using PM rather than MAC | |
7905 | * (Huntington development only) | |
7906 | */ | |
7907 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 | |
7908 | /* enum: Low latency RX PD production firmware */ | |
7909 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 | |
7910 | /* enum: Packed stream RX PD production firmware */ | |
7911 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 | |
7912 | /* enum: RX PD firmware handling layer 2 only for high packet rate performance | |
7913 | * tests (Medford development only) | |
7914 | */ | |
7915 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 | |
7916 | /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ | |
7917 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe | |
7918 | /* enum: RX PD firmware parsing but not filtering network overlay tunnel | |
7919 | * encapsulations (Medford development only) | |
7920 | */ | |
7921 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf | |
7922 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 | |
7923 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 | |
7924 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 | |
7925 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 | |
7926 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 | |
7927 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 | |
7928 | /* enum: reserved value - do not use (may indicate alternative interpretation | |
7929 | * of REV field in future) | |
7930 | */ | |
7931 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 | |
7932 | /* enum: Trivial TX PD firmware for early Huntington development (Huntington | |
7933 | * development only) | |
7934 | */ | |
7935 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 | |
7936 | /* enum: TX PD firmware with approximately Siena-compatible behaviour | |
7937 | * (Huntington development only) | |
7938 | */ | |
7939 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 | |
7940 | /* enum: Virtual switching (full feature) TX PD production firmware */ | |
7941 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 | |
7942 | /* enum: siena_compat variant TX PD firmware using PM rather than MAC | |
7943 | * (Huntington development only) | |
7944 | */ | |
7945 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 | |
7946 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ | |
7947 | /* enum: TX PD firmware handling layer 2 only for high packet rate performance | |
7948 | * tests (Medford development only) | |
7949 | */ | |
7950 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 | |
7951 | /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ | |
7952 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe | |
7953 | /* Hardware capabilities of NIC */ | |
7954 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 | |
7955 | /* Licensed capabilities */ | |
7956 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 | |
7957 | /* Second word of flags. Not present on older firmware (check the length). */ | |
7958 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 | |
7959 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 | |
7960 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 | |
7961 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 | |
7962 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 | |
7963 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 | |
7964 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 | |
7965 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 | |
7966 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 | |
7967 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 | |
7968 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 | |
d29e33d6 BK |
7969 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 |
7970 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 | |
7971 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 | |
7972 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 | |
7973 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 | |
7974 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 | |
7975 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 | |
7976 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 | |
7977 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 | |
7978 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 | |
7979 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 | |
7980 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 | |
7981 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 | |
7982 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 | |
23e202b4 EC |
7983 | /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present |
7984 | * on older firmware (check the length). | |
7985 | */ | |
7986 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 | |
7987 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 | |
7988 | /* One byte per PF containing the number of the external port assigned to this | |
7989 | * PF, indexed by PF number. Special values indicate that a PF is either not | |
7990 | * present or not assigned. | |
7991 | */ | |
7992 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 | |
7993 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 | |
7994 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 | |
7995 | /* enum: The caller is not permitted to access information on this PF. */ | |
7996 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff | |
7997 | /* enum: PF does not exist. */ | |
7998 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe | |
7999 | /* enum: PF does exist but is not assigned to any external port. */ | |
8000 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd | |
8001 | /* enum: This value indicates that PF is assigned, but it cannot be expressed | |
8002 | * in this field. It is intended for a possible future situation where a more | |
8003 | * complex scheme of PFs to ports mapping is being used. The future driver | |
8004 | * should look for a new field supporting the new scheme. The current/old | |
8005 | * driver should treat this value as PF_NOT_ASSIGNED. | |
8006 | */ | |
8007 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc | |
8008 | /* One byte per PF containing the number of its VFs, indexed by PF number. A | |
8009 | * special value indicates that a PF is not present. | |
8010 | */ | |
8011 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 | |
8012 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 | |
8013 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 | |
8014 | /* enum: The caller is not permitted to access information on this PF. */ | |
8015 | /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ | |
8016 | /* enum: PF does not exist. */ | |
8017 | /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ | |
8018 | /* Number of VIs available for each external port */ | |
8019 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 | |
8020 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 | |
8021 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 | |
8022 | /* Size of RX descriptor cache expressed as binary logarithm The actual size | |
8023 | * equals (2 ^ RX_DESC_CACHE_SIZE) | |
8024 | */ | |
8025 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 | |
8026 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 | |
8027 | /* Size of TX descriptor cache expressed as binary logarithm The actual size | |
8028 | * equals (2 ^ TX_DESC_CACHE_SIZE) | |
8029 | */ | |
8030 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 | |
8031 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 | |
8032 | /* Total number of available PIO buffers */ | |
8033 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 | |
8034 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 | |
8035 | /* Size of a single PIO buffer */ | |
8036 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 | |
8037 | #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 | |
8038 | ||
d29e33d6 BK |
8039 | /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ |
8040 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 73 | |
8041 | /* First word of flags. */ | |
8042 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 | |
8043 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 | |
8044 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 | |
8045 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 | |
8046 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 | |
8047 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 | |
8048 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 | |
8049 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 | |
8050 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 | |
8051 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 | |
8052 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 | |
8053 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 | |
8054 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 | |
8055 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 | |
8056 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 | |
8057 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 | |
8058 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 | |
8059 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 | |
8060 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 | |
8061 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 | |
8062 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 | |
8063 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 | |
8064 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 | |
8065 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 | |
8066 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 | |
8067 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 | |
8068 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 | |
8069 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 | |
8070 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 | |
8071 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 | |
8072 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 | |
8073 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 | |
8074 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 | |
8075 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 | |
8076 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 | |
8077 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 | |
8078 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 | |
8079 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 | |
8080 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 | |
8081 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 | |
8082 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 | |
8083 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 | |
8084 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 | |
8085 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 | |
8086 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 | |
8087 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 | |
8088 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 | |
8089 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 | |
8090 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 | |
8091 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 | |
8092 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 | |
8093 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 | |
8094 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 | |
8095 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 | |
8096 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 | |
8097 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 | |
8098 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 | |
8099 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 | |
8100 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 | |
8101 | /* RxDPCPU firmware id. */ | |
8102 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 | |
8103 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 | |
8104 | /* enum: Standard RXDP firmware */ | |
8105 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 | |
8106 | /* enum: Low latency RXDP firmware */ | |
8107 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 | |
8108 | /* enum: Packed stream RXDP firmware */ | |
8109 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 | |
8110 | /* enum: BIST RXDP firmware */ | |
8111 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a | |
8112 | /* enum: RXDP Test firmware image 1 */ | |
8113 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 | |
8114 | /* enum: RXDP Test firmware image 2 */ | |
8115 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 | |
8116 | /* enum: RXDP Test firmware image 3 */ | |
8117 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 | |
8118 | /* enum: RXDP Test firmware image 4 */ | |
8119 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 | |
8120 | /* enum: RXDP Test firmware image 5 */ | |
8121 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 | |
8122 | /* enum: RXDP Test firmware image 6 */ | |
8123 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 | |
8124 | /* enum: RXDP Test firmware image 7 */ | |
8125 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 | |
8126 | /* enum: RXDP Test firmware image 8 */ | |
8127 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 | |
8128 | /* enum: RXDP Test firmware image 9 */ | |
8129 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b | |
8130 | /* TxDPCPU firmware id. */ | |
8131 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 | |
8132 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 | |
8133 | /* enum: Standard TXDP firmware */ | |
8134 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 | |
8135 | /* enum: Low latency TXDP firmware */ | |
8136 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 | |
8137 | /* enum: High packet rate TXDP firmware */ | |
8138 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 | |
8139 | /* enum: BIST TXDP firmware */ | |
8140 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d | |
8141 | /* enum: TXDP Test firmware image 1 */ | |
8142 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 | |
8143 | /* enum: TXDP Test firmware image 2 */ | |
8144 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 | |
8145 | /* enum: TXDP CSR bus test firmware */ | |
8146 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 | |
8147 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 | |
8148 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 | |
8149 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 | |
8150 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 | |
8151 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 | |
8152 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 | |
8153 | /* enum: reserved value - do not use (may indicate alternative interpretation | |
8154 | * of REV field in future) | |
8155 | */ | |
8156 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 | |
8157 | /* enum: Trivial RX PD firmware for early Huntington development (Huntington | |
8158 | * development only) | |
8159 | */ | |
8160 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 | |
8161 | /* enum: RX PD firmware with approximately Siena-compatible behaviour | |
8162 | * (Huntington development only) | |
8163 | */ | |
8164 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 | |
8165 | /* enum: Virtual switching (full feature) RX PD production firmware */ | |
8166 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 | |
8167 | /* enum: siena_compat variant RX PD firmware using PM rather than MAC | |
8168 | * (Huntington development only) | |
8169 | */ | |
8170 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 | |
8171 | /* enum: Low latency RX PD production firmware */ | |
8172 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 | |
8173 | /* enum: Packed stream RX PD production firmware */ | |
8174 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 | |
8175 | /* enum: RX PD firmware handling layer 2 only for high packet rate performance | |
8176 | * tests (Medford development only) | |
8177 | */ | |
8178 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 | |
8179 | /* enum: Rules engine RX PD production firmware */ | |
8180 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 | |
8181 | /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ | |
8182 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe | |
8183 | /* enum: RX PD firmware parsing but not filtering network overlay tunnel | |
8184 | * encapsulations (Medford development only) | |
8185 | */ | |
8186 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf | |
8187 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 | |
8188 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 | |
8189 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 | |
8190 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 | |
8191 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 | |
8192 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 | |
8193 | /* enum: reserved value - do not use (may indicate alternative interpretation | |
8194 | * of REV field in future) | |
8195 | */ | |
8196 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 | |
8197 | /* enum: Trivial TX PD firmware for early Huntington development (Huntington | |
8198 | * development only) | |
8199 | */ | |
8200 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 | |
8201 | /* enum: TX PD firmware with approximately Siena-compatible behaviour | |
8202 | * (Huntington development only) | |
8203 | */ | |
8204 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 | |
8205 | /* enum: Virtual switching (full feature) TX PD production firmware */ | |
8206 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 | |
8207 | /* enum: siena_compat variant TX PD firmware using PM rather than MAC | |
8208 | * (Huntington development only) | |
8209 | */ | |
8210 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 | |
8211 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ | |
8212 | /* enum: TX PD firmware handling layer 2 only for high packet rate performance | |
8213 | * tests (Medford development only) | |
8214 | */ | |
8215 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 | |
8216 | /* enum: Rules engine TX PD production firmware */ | |
8217 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 | |
8218 | /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ | |
8219 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe | |
8220 | /* Hardware capabilities of NIC */ | |
8221 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 | |
8222 | /* Licensed capabilities */ | |
8223 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 | |
8224 | /* Second word of flags. Not present on older firmware (check the length). */ | |
8225 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 | |
8226 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 | |
8227 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 | |
8228 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 | |
8229 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 | |
8230 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 | |
8231 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 | |
8232 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 | |
8233 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 | |
8234 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 | |
8235 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 | |
8236 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 | |
8237 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 | |
8238 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 | |
8239 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 | |
8240 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 | |
8241 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 | |
8242 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 | |
8243 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 | |
8244 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 | |
8245 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 | |
8246 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 | |
8247 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 | |
8248 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 | |
8249 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 | |
8250 | /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present | |
8251 | * on older firmware (check the length). | |
8252 | */ | |
8253 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 | |
8254 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 | |
8255 | /* One byte per PF containing the number of the external port assigned to this | |
8256 | * PF, indexed by PF number. Special values indicate that a PF is either not | |
8257 | * present or not assigned. | |
8258 | */ | |
8259 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 | |
8260 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 | |
8261 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 | |
8262 | /* enum: The caller is not permitted to access information on this PF. */ | |
8263 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff | |
8264 | /* enum: PF does not exist. */ | |
8265 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe | |
8266 | /* enum: PF does exist but is not assigned to any external port. */ | |
8267 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd | |
8268 | /* enum: This value indicates that PF is assigned, but it cannot be expressed | |
8269 | * in this field. It is intended for a possible future situation where a more | |
8270 | * complex scheme of PFs to ports mapping is being used. The future driver | |
8271 | * should look for a new field supporting the new scheme. The current/old | |
8272 | * driver should treat this value as PF_NOT_ASSIGNED. | |
8273 | */ | |
8274 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc | |
8275 | /* One byte per PF containing the number of its VFs, indexed by PF number. A | |
8276 | * special value indicates that a PF is not present. | |
8277 | */ | |
8278 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 | |
8279 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 | |
8280 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 | |
8281 | /* enum: The caller is not permitted to access information on this PF. */ | |
8282 | /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ | |
8283 | /* enum: PF does not exist. */ | |
8284 | /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ | |
8285 | /* Number of VIs available for each external port */ | |
8286 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 | |
8287 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 | |
8288 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 | |
8289 | /* Size of RX descriptor cache expressed as binary logarithm The actual size | |
8290 | * equals (2 ^ RX_DESC_CACHE_SIZE) | |
8291 | */ | |
8292 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 | |
8293 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 | |
8294 | /* Size of TX descriptor cache expressed as binary logarithm The actual size | |
8295 | * equals (2 ^ TX_DESC_CACHE_SIZE) | |
8296 | */ | |
8297 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 | |
8298 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 | |
8299 | /* Total number of available PIO buffers */ | |
8300 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 | |
8301 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 | |
8302 | /* Size of a single PIO buffer */ | |
8303 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 | |
8304 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 | |
8305 | /* On chips later than Medford the amount of address space assigned to each VI | |
8306 | * is configurable. This is a global setting that the driver must query to | |
8307 | * discover the VI to address mapping. Cut-through PIO (CTPIO) in not available | |
8308 | * with 8k VI windows. | |
8309 | */ | |
8310 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 | |
8311 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 | |
8312 | /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. | |
8313 | * CTPIO is not mapped. | |
8314 | */ | |
8315 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 | |
8316 | /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ | |
8317 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 | |
8318 | /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ | |
8319 | #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 | |
8320 | ||
f2b0befd BH |
8321 | |
8322 | /***********************************/ | |
8323 | /* MC_CMD_V2_EXTN | |
8324 | * Encapsulation for a v2 extended command | |
8325 | */ | |
8326 | #define MC_CMD_V2_EXTN 0x7f | |
8327 | ||
8328 | /* MC_CMD_V2_EXTN_IN msgrequest */ | |
8329 | #define MC_CMD_V2_EXTN_IN_LEN 4 | |
8330 | /* the extended command number */ | |
8331 | #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 | |
8332 | #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 | |
8333 | #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 | |
8334 | #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 | |
8335 | /* the actual length of the encapsulated command (which is not in the v1 | |
8336 | * header) | |
8337 | */ | |
8338 | #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 | |
8339 | #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 | |
8340 | #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 | |
8341 | #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 | |
8342 | ||
8343 | ||
8344 | /***********************************/ | |
8345 | /* MC_CMD_TCM_BUCKET_ALLOC | |
8346 | * Allocate a pacer bucket (for qau rp or a snapper test) | |
8347 | */ | |
8348 | #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 | |
8349 | ||
75122ec8 SS |
8350 | #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8351 | ||
f2b0befd BH |
8352 | /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ |
8353 | #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 | |
8354 | ||
8355 | /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ | |
8356 | #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 | |
8357 | /* the bucket id */ | |
8358 | #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 | |
8359 | ||
8360 | ||
8361 | /***********************************/ | |
8362 | /* MC_CMD_TCM_BUCKET_FREE | |
8363 | * Free a pacer bucket | |
8364 | */ | |
8365 | #define MC_CMD_TCM_BUCKET_FREE 0xb3 | |
8366 | ||
75122ec8 SS |
8367 | #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8368 | ||
f2b0befd BH |
8369 | /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ |
8370 | #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 | |
8371 | /* the bucket id */ | |
8372 | #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 | |
8373 | ||
8374 | /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ | |
8375 | #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 | |
8376 | ||
8377 | ||
8378 | /***********************************/ | |
8379 | /* MC_CMD_TCM_BUCKET_INIT | |
8380 | * Initialise pacer bucket with a given rate | |
8381 | */ | |
8382 | #define MC_CMD_TCM_BUCKET_INIT 0xb4 | |
8383 | ||
75122ec8 SS |
8384 | #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8385 | ||
f2b0befd BH |
8386 | /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ |
8387 | #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 | |
8388 | /* the bucket id */ | |
8389 | #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 | |
8390 | /* the rate in mbps */ | |
8391 | #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 | |
8392 | ||
a9196bb0 EC |
8393 | /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ |
8394 | #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 | |
8395 | /* the bucket id */ | |
8396 | #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 | |
8397 | /* the rate in mbps */ | |
8398 | #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 | |
8399 | /* the desired maximum fill level */ | |
8400 | #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 | |
8401 | ||
f2b0befd BH |
8402 | /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ |
8403 | #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 | |
8404 | ||
8405 | ||
8406 | /***********************************/ | |
8407 | /* MC_CMD_TCM_TXQ_INIT | |
8408 | * Initialise txq in pacer with given options or set options | |
8409 | */ | |
8410 | #define MC_CMD_TCM_TXQ_INIT 0xb5 | |
8411 | ||
75122ec8 SS |
8412 | #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8413 | ||
f2b0befd BH |
8414 | /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ |
8415 | #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 | |
8416 | /* the txq id */ | |
8417 | #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 | |
8418 | /* the static priority associated with the txq */ | |
8419 | #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 | |
a9196bb0 | 8420 | /* bitmask of the priority queues this txq is inserted into when inserted. */ |
f2b0befd | 8421 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 |
a9196bb0 EC |
8422 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 |
8423 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 | |
8424 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 | |
8425 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 | |
8426 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 | |
8427 | #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 | |
f2b0befd BH |
8428 | /* the reaction point (RP) bucket */ |
8429 | #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 | |
8430 | /* an already reserved bucket (typically set to bucket associated with outer | |
8431 | * vswitch) | |
8432 | */ | |
8433 | #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 | |
8434 | /* an already reserved bucket (typically set to bucket associated with inner | |
8435 | * vswitch) | |
8436 | */ | |
8437 | #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 | |
8438 | /* the min bucket (typically for ETS/minimum bandwidth) */ | |
8439 | #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 | |
8440 | ||
a9196bb0 EC |
8441 | /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ |
8442 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 | |
8443 | /* the txq id */ | |
8444 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 | |
8445 | /* the static priority associated with the txq */ | |
8446 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 | |
8447 | /* bitmask of the priority queues this txq is inserted into when inserted. */ | |
8448 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 | |
8449 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 | |
8450 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 | |
8451 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 | |
8452 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 | |
8453 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 | |
8454 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 | |
8455 | /* the reaction point (RP) bucket */ | |
8456 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 | |
8457 | /* an already reserved bucket (typically set to bucket associated with outer | |
8458 | * vswitch) | |
8459 | */ | |
8460 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 | |
8461 | /* an already reserved bucket (typically set to bucket associated with inner | |
8462 | * vswitch) | |
8463 | */ | |
8464 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 | |
8465 | /* the min bucket (typically for ETS/minimum bandwidth) */ | |
8466 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 | |
8467 | /* the static priority associated with the txq */ | |
8468 | #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 | |
8469 | ||
f2b0befd BH |
8470 | /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ |
8471 | #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 | |
8472 | ||
8473 | ||
8474 | /***********************************/ | |
8475 | /* MC_CMD_LINK_PIOBUF | |
8476 | * Link a push I/O buffer to a TxQ | |
8477 | */ | |
8478 | #define MC_CMD_LINK_PIOBUF 0x92 | |
8479 | ||
75122ec8 SS |
8480 | #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
8481 | ||
f2b0befd BH |
8482 | /* MC_CMD_LINK_PIOBUF_IN msgrequest */ |
8483 | #define MC_CMD_LINK_PIOBUF_IN_LEN 8 | |
8484 | /* Handle for allocated push I/O buffer. */ | |
8485 | #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 | |
8486 | /* Function Local Instance (VI) number. */ | |
8487 | #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 | |
8488 | ||
8489 | /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ | |
8490 | #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 | |
8491 | ||
8492 | ||
8493 | /***********************************/ | |
8494 | /* MC_CMD_UNLINK_PIOBUF | |
8495 | * Unlink a push I/O buffer from a TxQ | |
8496 | */ | |
8497 | #define MC_CMD_UNLINK_PIOBUF 0x93 | |
8498 | ||
75122ec8 SS |
8499 | #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
8500 | ||
f2b0befd BH |
8501 | /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ |
8502 | #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 | |
8503 | /* Function Local Instance (VI) number. */ | |
8504 | #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 | |
8505 | ||
8506 | /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ | |
8507 | #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 | |
8508 | ||
8509 | ||
8510 | /***********************************/ | |
8511 | /* MC_CMD_VSWITCH_ALLOC | |
8512 | * allocate and initialise a v-switch. | |
8513 | */ | |
8514 | #define MC_CMD_VSWITCH_ALLOC 0x94 | |
8515 | ||
75122ec8 SS |
8516 | #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8517 | ||
f2b0befd BH |
8518 | /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ |
8519 | #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 | |
8520 | /* The port to connect to the v-switch's upstream port. */ | |
8521 | #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
8522 | /* The type of v-switch to create. */ | |
8523 | #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 | |
8524 | /* enum: VLAN */ | |
8525 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 | |
8526 | /* enum: VEB */ | |
8527 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 | |
a9196bb0 | 8528 | /* enum: VEPA (obsolete) */ |
f2b0befd | 8529 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 |
a9196bb0 EC |
8530 | /* enum: MUX */ |
8531 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 | |
8532 | /* enum: Snapper specific; semantics TBD */ | |
8533 | #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 | |
f2b0befd BH |
8534 | /* Flags controlling v-port creation */ |
8535 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 | |
8536 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 | |
8537 | #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 | |
a9196bb0 EC |
8538 | /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, |
8539 | * this must be one or greated, and the attached v-ports must have exactly this | |
8540 | * number of tags. For other v-switch types, this must be zero of greater, and | |
8541 | * is an upper limit on the number of VLAN tags for attached v-ports. An error | |
8542 | * will be returned if existing configuration means we can't support attached | |
8543 | * v-ports with this number of tags. | |
8544 | */ | |
f2b0befd BH |
8545 | #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 |
8546 | ||
8547 | /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ | |
8548 | #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 | |
8549 | ||
8550 | ||
8551 | /***********************************/ | |
8552 | /* MC_CMD_VSWITCH_FREE | |
8553 | * de-allocate a v-switch. | |
8554 | */ | |
8555 | #define MC_CMD_VSWITCH_FREE 0x95 | |
8556 | ||
75122ec8 SS |
8557 | #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8558 | ||
f2b0befd BH |
8559 | /* MC_CMD_VSWITCH_FREE_IN msgrequest */ |
8560 | #define MC_CMD_VSWITCH_FREE_IN_LEN 4 | |
8561 | /* The port to which the v-switch is connected. */ | |
8562 | #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 | |
8563 | ||
8564 | /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ | |
8565 | #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 | |
8566 | ||
8567 | ||
23e202b4 EC |
8568 | /***********************************/ |
8569 | /* MC_CMD_VSWITCH_QUERY | |
8570 | * read some config of v-switch. For now this command is an empty placeholder. | |
8571 | * It may be used to check if a v-switch is connected to a given EVB port (if | |
8572 | * not, then the command returns ENOENT). | |
8573 | */ | |
8574 | #define MC_CMD_VSWITCH_QUERY 0x63 | |
8575 | ||
8576 | #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
8577 | ||
8578 | /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ | |
8579 | #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 | |
8580 | /* The port to which the v-switch is connected. */ | |
8581 | #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 | |
8582 | ||
8583 | /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ | |
8584 | #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 | |
8585 | ||
8586 | ||
f2b0befd BH |
8587 | /***********************************/ |
8588 | /* MC_CMD_VPORT_ALLOC | |
8589 | * allocate a v-port. | |
8590 | */ | |
8591 | #define MC_CMD_VPORT_ALLOC 0x96 | |
8592 | ||
75122ec8 SS |
8593 | #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8594 | ||
f2b0befd BH |
8595 | /* MC_CMD_VPORT_ALLOC_IN msgrequest */ |
8596 | #define MC_CMD_VPORT_ALLOC_IN_LEN 20 | |
8597 | /* The port to which the v-switch is connected. */ | |
8598 | #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
8599 | /* The type of the new v-port. */ | |
8600 | #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 | |
8601 | /* enum: VLAN (obsolete) */ | |
8602 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 | |
8603 | /* enum: VEB (obsolete) */ | |
8604 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 | |
8605 | /* enum: VEPA (obsolete) */ | |
8606 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 | |
8607 | /* enum: A normal v-port receives packets which match a specified MAC and/or | |
8608 | * VLAN. | |
8609 | */ | |
8610 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 | |
8611 | /* enum: An expansion v-port packets traffic which don't match any other | |
8612 | * v-port. | |
8613 | */ | |
8614 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 | |
8615 | /* enum: An test v-port receives packets which match any filters installed by | |
8616 | * its downstream components. | |
8617 | */ | |
8618 | #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 | |
8619 | /* Flags controlling v-port creation */ | |
8620 | #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 | |
8621 | #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 | |
8622 | #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 | |
23e202b4 EC |
8623 | #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 |
8624 | #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 | |
a9196bb0 EC |
8625 | /* The number of VLAN tags to insert/remove. An error will be returned if |
8626 | * incompatible with the number of VLAN tags specified for the upstream | |
8627 | * v-switch. | |
8628 | */ | |
f2b0befd BH |
8629 | #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 |
8630 | /* The actual VLAN tags to insert/remove */ | |
8631 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 | |
8632 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 | |
8633 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 | |
8634 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 | |
8635 | #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 | |
8636 | ||
8637 | /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ | |
8638 | #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 | |
8639 | /* The handle of the new v-port */ | |
8640 | #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 | |
8641 | ||
8642 | ||
8643 | /***********************************/ | |
8644 | /* MC_CMD_VPORT_FREE | |
8645 | * de-allocate a v-port. | |
8646 | */ | |
8647 | #define MC_CMD_VPORT_FREE 0x97 | |
8648 | ||
75122ec8 SS |
8649 | #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8650 | ||
f2b0befd BH |
8651 | /* MC_CMD_VPORT_FREE_IN msgrequest */ |
8652 | #define MC_CMD_VPORT_FREE_IN_LEN 4 | |
8653 | /* The handle of the v-port */ | |
8654 | #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 | |
8655 | ||
8656 | /* MC_CMD_VPORT_FREE_OUT msgresponse */ | |
8657 | #define MC_CMD_VPORT_FREE_OUT_LEN 0 | |
8658 | ||
8659 | ||
8660 | /***********************************/ | |
8661 | /* MC_CMD_VADAPTOR_ALLOC | |
8662 | * allocate a v-adaptor. | |
8663 | */ | |
8664 | #define MC_CMD_VADAPTOR_ALLOC 0x98 | |
8665 | ||
75122ec8 SS |
8666 | #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8667 | ||
f2b0befd | 8668 | /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ |
af6a074d | 8669 | #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 |
f2b0befd BH |
8670 | /* The port to connect to the v-adaptor's port. */ |
8671 | #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
8672 | /* Flags controlling v-adaptor creation */ | |
8673 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 | |
8674 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 | |
8675 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 | |
23e202b4 EC |
8676 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 |
8677 | #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 | |
f2b0befd BH |
8678 | /* The number of VLAN tags to strip on receive */ |
8679 | #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 | |
af6a074d SS |
8680 | /* The number of VLAN tags to transparently insert/remove. */ |
8681 | #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 | |
8682 | /* The actual VLAN tags to insert/remove */ | |
8683 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 | |
8684 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 | |
8685 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 | |
8686 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 | |
8687 | #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 | |
8688 | /* The MAC address to assign to this v-adaptor */ | |
8689 | #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 | |
8690 | #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 | |
8691 | /* enum: Derive the MAC address from the upstream port */ | |
8692 | #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 | |
f2b0befd BH |
8693 | |
8694 | /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ | |
8695 | #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 | |
8696 | ||
8697 | ||
8698 | /***********************************/ | |
8699 | /* MC_CMD_VADAPTOR_FREE | |
8700 | * de-allocate a v-adaptor. | |
8701 | */ | |
8702 | #define MC_CMD_VADAPTOR_FREE 0x99 | |
8703 | ||
75122ec8 SS |
8704 | #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8705 | ||
f2b0befd BH |
8706 | /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ |
8707 | #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 | |
8708 | /* The port to which the v-adaptor is connected. */ | |
8709 | #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 | |
8710 | ||
8711 | /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ | |
8712 | #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 | |
8713 | ||
8714 | ||
910c8789 SS |
8715 | /***********************************/ |
8716 | /* MC_CMD_VADAPTOR_SET_MAC | |
8717 | * assign a new MAC address to a v-adaptor. | |
8718 | */ | |
8719 | #define MC_CMD_VADAPTOR_SET_MAC 0x5d | |
8720 | ||
8721 | #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
8722 | ||
8723 | /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ | |
8724 | #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 | |
8725 | /* The port to which the v-adaptor is connected. */ | |
8726 | #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 | |
8727 | /* The new MAC address to assign to this v-adaptor */ | |
8728 | #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 | |
8729 | #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 | |
8730 | ||
8731 | /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ | |
8732 | #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 | |
8733 | ||
8734 | ||
8735 | /***********************************/ | |
8736 | /* MC_CMD_VADAPTOR_GET_MAC | |
8737 | * read the MAC address assigned to a v-adaptor. | |
8738 | */ | |
8739 | #define MC_CMD_VADAPTOR_GET_MAC 0x5e | |
8740 | ||
8741 | #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
8742 | ||
8743 | /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ | |
8744 | #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 | |
8745 | /* The port to which the v-adaptor is connected. */ | |
8746 | #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 | |
8747 | ||
8748 | /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ | |
8749 | #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 | |
8750 | /* The MAC address assigned to this v-adaptor */ | |
8751 | #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 | |
8752 | #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 | |
8753 | ||
8754 | ||
23e202b4 EC |
8755 | /***********************************/ |
8756 | /* MC_CMD_VADAPTOR_QUERY | |
8757 | * read some config of v-adaptor. | |
8758 | */ | |
8759 | #define MC_CMD_VADAPTOR_QUERY 0x61 | |
8760 | ||
8761 | #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
8762 | ||
8763 | /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ | |
8764 | #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 | |
8765 | /* The port to which the v-adaptor is connected. */ | |
8766 | #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 | |
8767 | ||
8768 | /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ | |
8769 | #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 | |
8770 | /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ | |
8771 | #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 | |
8772 | /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ | |
8773 | #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 | |
8774 | /* The number of VLAN tags that may still be added */ | |
8775 | #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 | |
8776 | ||
8777 | ||
f2b0befd BH |
8778 | /***********************************/ |
8779 | /* MC_CMD_EVB_PORT_ASSIGN | |
8780 | * assign a port to a PCI function. | |
8781 | */ | |
8782 | #define MC_CMD_EVB_PORT_ASSIGN 0x9a | |
8783 | ||
75122ec8 SS |
8784 | #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8785 | ||
f2b0befd BH |
8786 | /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ |
8787 | #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 | |
8788 | /* The port to assign. */ | |
8789 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 | |
8790 | /* The target function to modify. */ | |
8791 | #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 | |
8792 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 | |
8793 | #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 | |
8794 | #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 | |
8795 | #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 | |
8796 | ||
8797 | /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ | |
8798 | #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 | |
8799 | ||
8800 | ||
8801 | /***********************************/ | |
8802 | /* MC_CMD_RDWR_A64_REGIONS | |
8803 | * Assign the 64 bit region addresses. | |
8804 | */ | |
8805 | #define MC_CMD_RDWR_A64_REGIONS 0x9b | |
8806 | ||
75122ec8 SS |
8807 | #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
8808 | ||
f2b0befd BH |
8809 | /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ |
8810 | #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 | |
8811 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 | |
8812 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 | |
8813 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 | |
8814 | #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 | |
8815 | /* Write enable bits 0-3, set to write, clear to read. */ | |
8816 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 | |
8817 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 | |
8818 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 | |
8819 | #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 | |
8820 | ||
8821 | /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included | |
8822 | * regardless of state of write bits in the request. | |
8823 | */ | |
8824 | #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 | |
8825 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 | |
8826 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 | |
8827 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 | |
8828 | #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 | |
8829 | ||
8830 | ||
8831 | /***********************************/ | |
8832 | /* MC_CMD_ONLOAD_STACK_ALLOC | |
8833 | * Allocate an Onload stack ID. | |
8834 | */ | |
8835 | #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c | |
8836 | ||
75122ec8 SS |
8837 | #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
8838 | ||
f2b0befd BH |
8839 | /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ |
8840 | #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 | |
8841 | /* The handle of the owning upstream port */ | |
8842 | #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
8843 | ||
8844 | /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ | |
8845 | #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 | |
8846 | /* The handle of the new Onload stack */ | |
8847 | #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 | |
8848 | ||
8849 | ||
8850 | /***********************************/ | |
8851 | /* MC_CMD_ONLOAD_STACK_FREE | |
8852 | * Free an Onload stack ID. | |
8853 | */ | |
8854 | #define MC_CMD_ONLOAD_STACK_FREE 0x9d | |
8855 | ||
75122ec8 SS |
8856 | #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD |
8857 | ||
f2b0befd BH |
8858 | /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ |
8859 | #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 | |
8860 | /* The handle of the Onload stack */ | |
8861 | #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 | |
8862 | ||
8863 | /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ | |
8864 | #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 | |
8865 | ||
8866 | ||
8867 | /***********************************/ | |
8868 | /* MC_CMD_RSS_CONTEXT_ALLOC | |
8869 | * Allocate an RSS context. | |
8870 | */ | |
8871 | #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e | |
8872 | ||
75122ec8 SS |
8873 | #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8874 | ||
f2b0befd BH |
8875 | /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ |
8876 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 | |
8877 | /* The handle of the owning upstream port */ | |
8878 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
8879 | /* The type of context to allocate */ | |
8880 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 | |
8881 | /* enum: Allocate a context for exclusive use. The key and indirection table | |
8882 | * must be explicitly configured. | |
8883 | */ | |
8884 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 | |
8885 | /* enum: Allocate a context for shared use; this will spread across a range of | |
8886 | * queues, but the key and indirection table are pre-configured and may not be | |
8887 | * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. | |
8888 | */ | |
8889 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 | |
8890 | /* Number of queues spanned by this context, in the range 1-64; valid offsets | |
8891 | * in the indirection table will be in the range 0 to NUM_QUEUES-1. | |
8892 | */ | |
8893 | #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 | |
8894 | ||
8895 | /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ | |
8896 | #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 | |
a9196bb0 EC |
8897 | /* The handle of the new RSS context. This should be considered opaque to the |
8898 | * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid | |
8899 | * handle. | |
8900 | */ | |
f2b0befd | 8901 | #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 |
a9196bb0 EC |
8902 | /* enum: guaranteed invalid RSS context handle value */ |
8903 | #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff | |
f2b0befd BH |
8904 | |
8905 | ||
8906 | /***********************************/ | |
8907 | /* MC_CMD_RSS_CONTEXT_FREE | |
8908 | * Free an RSS context. | |
8909 | */ | |
8910 | #define MC_CMD_RSS_CONTEXT_FREE 0x9f | |
8911 | ||
75122ec8 SS |
8912 | #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8913 | ||
f2b0befd BH |
8914 | /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ |
8915 | #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 | |
8916 | /* The handle of the RSS context */ | |
8917 | #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 | |
8918 | ||
8919 | /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ | |
8920 | #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 | |
8921 | ||
8922 | ||
8923 | /***********************************/ | |
8924 | /* MC_CMD_RSS_CONTEXT_SET_KEY | |
8925 | * Set the Toeplitz hash key for an RSS context. | |
8926 | */ | |
8927 | #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 | |
8928 | ||
75122ec8 SS |
8929 | #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8930 | ||
f2b0befd BH |
8931 | /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ |
8932 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 | |
8933 | /* The handle of the RSS context */ | |
8934 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 | |
8935 | /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ | |
8936 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 | |
8937 | #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 | |
8938 | ||
8939 | /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ | |
8940 | #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 | |
8941 | ||
8942 | ||
8943 | /***********************************/ | |
8944 | /* MC_CMD_RSS_CONTEXT_GET_KEY | |
8945 | * Get the Toeplitz hash key for an RSS context. | |
8946 | */ | |
8947 | #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 | |
8948 | ||
75122ec8 SS |
8949 | #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8950 | ||
f2b0befd BH |
8951 | /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ |
8952 | #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 | |
8953 | /* The handle of the RSS context */ | |
8954 | #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 | |
8955 | ||
8956 | /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ | |
8957 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 | |
8958 | /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ | |
8959 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 | |
8960 | #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 | |
8961 | ||
8962 | ||
8963 | /***********************************/ | |
8964 | /* MC_CMD_RSS_CONTEXT_SET_TABLE | |
8965 | * Set the indirection table for an RSS context. | |
8966 | */ | |
8967 | #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 | |
8968 | ||
75122ec8 SS |
8969 | #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8970 | ||
f2b0befd BH |
8971 | /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ |
8972 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 | |
8973 | /* The handle of the RSS context */ | |
8974 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 | |
8975 | /* The 128-byte indirection table (1 byte per entry) */ | |
8976 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 | |
8977 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 | |
8978 | ||
8979 | /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ | |
8980 | #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 | |
8981 | ||
8982 | ||
8983 | /***********************************/ | |
8984 | /* MC_CMD_RSS_CONTEXT_GET_TABLE | |
8985 | * Get the indirection table for an RSS context. | |
8986 | */ | |
8987 | #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 | |
8988 | ||
75122ec8 SS |
8989 | #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
8990 | ||
f2b0befd BH |
8991 | /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ |
8992 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 | |
8993 | /* The handle of the RSS context */ | |
8994 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 | |
8995 | ||
8996 | /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ | |
8997 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 | |
8998 | /* The 128-byte indirection table (1 byte per entry) */ | |
8999 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 | |
9000 | #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 | |
9001 | ||
9002 | ||
9003 | /***********************************/ | |
9004 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS | |
9005 | * Set various control flags for an RSS context. | |
9006 | */ | |
9007 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 | |
9008 | ||
75122ec8 SS |
9009 | #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9010 | ||
f2b0befd BH |
9011 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ |
9012 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 | |
9013 | /* The handle of the RSS context */ | |
9014 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 | |
23e202b4 EC |
9015 | /* Hash control flags. The _EN bits are always supported, but new modes are |
9016 | * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: | |
9017 | * in this case, the MODE fields may be set to non-zero values, and will take | |
9018 | * effect regardless of the settings of the _EN flags. See the RSS_MODE | |
9019 | * structure for the meaning of the mode bits. Drivers must check the | |
9020 | * capability before trying to set any _MODE fields, as older firmware will | |
9021 | * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In | |
9022 | * the case where all the _MODE flags are zero, the _EN flags take effect, | |
9023 | * providing backward compatibility for existing drivers. (Setting all _MODE | |
9024 | * *and* all _EN flags to zero is valid, to disable RSS spreading for that | |
9025 | * particular packet type.) | |
a9196bb0 | 9026 | */ |
f2b0befd BH |
9027 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 |
9028 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 | |
9029 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 | |
9030 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 | |
9031 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 | |
9032 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 | |
9033 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 | |
9034 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 | |
9035 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 | |
a9196bb0 EC |
9036 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 |
9037 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 | |
9038 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 | |
9039 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 | |
9040 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 | |
9041 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 | |
9042 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 | |
9043 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 | |
9044 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 | |
9045 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 | |
9046 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 | |
9047 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 | |
9048 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 | |
9049 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 | |
f2b0befd BH |
9050 | |
9051 | /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ | |
9052 | #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 | |
9053 | ||
9054 | ||
9055 | /***********************************/ | |
9056 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS | |
9057 | * Get various control flags for an RSS context. | |
9058 | */ | |
9059 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 | |
9060 | ||
75122ec8 SS |
9061 | #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9062 | ||
f2b0befd BH |
9063 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ |
9064 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 | |
9065 | /* The handle of the RSS context */ | |
9066 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 | |
9067 | ||
9068 | /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ | |
9069 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 | |
23e202b4 EC |
9070 | /* Hash control flags. If all _MODE bits are zero (which will always be true |
9071 | * for older firmware which does not report the ADDITIONAL_RSS_MODES | |
9072 | * capability), the _EN bits report the state. If any _MODE bits are non-zero | |
9073 | * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) | |
9074 | * then the _EN bits should be disregarded, although the _MODE flags are | |
9075 | * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS | |
9076 | * context and in the case where the _EN flags were used in the SET. This | |
9077 | * provides backward compatibility: old drivers will not be attempting to | |
9078 | * derive any meaning from the _MODE bits (and can never set them to any value | |
9079 | * not representable by the _EN bits); new drivers can always determine the | |
9080 | * mode by looking only at the _MODE bits; the value returned by a GET can | |
9081 | * always be used for a SET regardless of old/new driver vs. old/new firmware. | |
a9196bb0 | 9082 | */ |
f2b0befd BH |
9083 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 |
9084 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 | |
9085 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 | |
9086 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 | |
9087 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 | |
9088 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 | |
9089 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 | |
9090 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 | |
9091 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 | |
a9196bb0 EC |
9092 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 |
9093 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 | |
9094 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 | |
9095 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 | |
9096 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 | |
9097 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 | |
9098 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 | |
9099 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 | |
9100 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 | |
9101 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 | |
9102 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 | |
9103 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 | |
9104 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 | |
9105 | #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 | |
f2b0befd BH |
9106 | |
9107 | ||
9108 | /***********************************/ | |
9109 | /* MC_CMD_DOT1P_MAPPING_ALLOC | |
9110 | * Allocate a .1p mapping. | |
9111 | */ | |
9112 | #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 | |
9113 | ||
75122ec8 SS |
9114 | #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9115 | ||
f2b0befd BH |
9116 | /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ |
9117 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 | |
9118 | /* The handle of the owning upstream port */ | |
9119 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 | |
9120 | /* Number of queues spanned by this mapping, in the range 1-64; valid fixed | |
9121 | * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and | |
9122 | * referenced RSS contexts must span no more than this number. | |
9123 | */ | |
9124 | #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 | |
9125 | ||
9126 | /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ | |
9127 | #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 | |
a9196bb0 EC |
9128 | /* The handle of the new .1p mapping. This should be considered opaque to the |
9129 | * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid | |
9130 | * handle. | |
9131 | */ | |
f2b0befd | 9132 | #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 |
a9196bb0 EC |
9133 | /* enum: guaranteed invalid .1p mapping handle value */ |
9134 | #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff | |
f2b0befd BH |
9135 | |
9136 | ||
9137 | /***********************************/ | |
9138 | /* MC_CMD_DOT1P_MAPPING_FREE | |
9139 | * Free a .1p mapping. | |
9140 | */ | |
9141 | #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 | |
9142 | ||
75122ec8 SS |
9143 | #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9144 | ||
f2b0befd BH |
9145 | /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ |
9146 | #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 | |
9147 | /* The handle of the .1p mapping */ | |
9148 | #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 | |
9149 | ||
9150 | /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ | |
9151 | #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 | |
9152 | ||
9153 | ||
9154 | /***********************************/ | |
9155 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE | |
9156 | * Set the mapping table for a .1p mapping. | |
9157 | */ | |
9158 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 | |
9159 | ||
75122ec8 SS |
9160 | #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9161 | ||
f2b0befd BH |
9162 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ |
9163 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 | |
9164 | /* The handle of the .1p mapping */ | |
9165 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 | |
9166 | /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context | |
9167 | * handle) | |
9168 | */ | |
9169 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 | |
9170 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 | |
9171 | ||
9172 | /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ | |
9173 | #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 | |
9174 | ||
9175 | ||
9176 | /***********************************/ | |
9177 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE | |
9178 | * Get the mapping table for a .1p mapping. | |
9179 | */ | |
9180 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 | |
9181 | ||
75122ec8 SS |
9182 | #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9183 | ||
f2b0befd BH |
9184 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ |
9185 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 | |
9186 | /* The handle of the .1p mapping */ | |
9187 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 | |
9188 | ||
9189 | /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ | |
9190 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 | |
9191 | /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context | |
9192 | * handle) | |
9193 | */ | |
9194 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 | |
9195 | #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 | |
9196 | ||
9197 | ||
9198 | /***********************************/ | |
9199 | /* MC_CMD_GET_VECTOR_CFG | |
9200 | * Get Interrupt Vector config for this PF. | |
9201 | */ | |
9202 | #define MC_CMD_GET_VECTOR_CFG 0xbf | |
9203 | ||
75122ec8 SS |
9204 | #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9205 | ||
f2b0befd BH |
9206 | /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ |
9207 | #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 | |
9208 | ||
9209 | /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ | |
9210 | #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 | |
9211 | /* Base absolute interrupt vector number. */ | |
9212 | #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 | |
9213 | /* Number of interrupt vectors allocate to this PF. */ | |
9214 | #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 | |
9215 | /* Number of interrupt vectors to allocate per VF. */ | |
9216 | #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 | |
9217 | ||
9218 | ||
9219 | /***********************************/ | |
9220 | /* MC_CMD_SET_VECTOR_CFG | |
9221 | * Set Interrupt Vector config for this PF. | |
9222 | */ | |
9223 | #define MC_CMD_SET_VECTOR_CFG 0xc0 | |
9224 | ||
75122ec8 SS |
9225 | #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9226 | ||
f2b0befd BH |
9227 | /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ |
9228 | #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 | |
9229 | /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to | |
9230 | * let the system find a suitable base. | |
9231 | */ | |
9232 | #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 | |
9233 | /* Number of interrupt vectors allocate to this PF. */ | |
9234 | #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 | |
9235 | /* Number of interrupt vectors to allocate per VF. */ | |
9236 | #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 | |
9237 | ||
9238 | /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ | |
9239 | #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 | |
9240 | ||
9241 | ||
9242 | /***********************************/ | |
a9196bb0 EC |
9243 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS |
9244 | * Add a MAC address to a v-port | |
f2b0befd | 9245 | */ |
a9196bb0 | 9246 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 |
f2b0befd | 9247 | |
a9196bb0 | 9248 | #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
f2b0befd | 9249 | |
a9196bb0 EC |
9250 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ |
9251 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 | |
9252 | /* The handle of the v-port */ | |
9253 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 | |
9254 | /* MAC address to add */ | |
9255 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 | |
9256 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 | |
f2b0befd | 9257 | |
a9196bb0 EC |
9258 | /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ |
9259 | #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 | |
f2b0befd BH |
9260 | |
9261 | ||
9262 | /***********************************/ | |
a9196bb0 EC |
9263 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS |
9264 | * Delete a MAC address from a v-port | |
f2b0befd | 9265 | */ |
a9196bb0 | 9266 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 |
f2b0befd | 9267 | |
a9196bb0 | 9268 | #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
75122ec8 | 9269 | |
f2b0befd BH |
9270 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ |
9271 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 | |
9272 | /* The handle of the v-port */ | |
9273 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 | |
9274 | /* MAC address to add */ | |
9275 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 | |
9276 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 | |
9277 | ||
9278 | /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ | |
9279 | #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 | |
9280 | ||
9281 | ||
9282 | /***********************************/ | |
9283 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES | |
9284 | * Delete a MAC address from a v-port | |
9285 | */ | |
9286 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa | |
9287 | ||
75122ec8 SS |
9288 | #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9289 | ||
f2b0befd BH |
9290 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ |
9291 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 | |
9292 | /* The handle of the v-port */ | |
9293 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 | |
9294 | ||
9295 | /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ | |
9296 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 | |
9297 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 | |
9298 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) | |
9299 | /* The number of MAC addresses returned */ | |
9300 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 | |
9301 | /* Array of MAC addresses */ | |
9302 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 | |
9303 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 | |
9304 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 | |
9305 | #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 | |
9306 | ||
9307 | ||
23e202b4 EC |
9308 | /***********************************/ |
9309 | /* MC_CMD_VPORT_RECONFIGURE | |
9310 | * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port | |
9311 | * has already been passed to another function (v-port's user), then that | |
9312 | * function will be reset before applying the changes. | |
9313 | */ | |
9314 | #define MC_CMD_VPORT_RECONFIGURE 0xeb | |
9315 | ||
9316 | #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
9317 | ||
9318 | /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ | |
9319 | #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 | |
9320 | /* The handle of the v-port */ | |
9321 | #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 | |
9322 | /* Flags requesting what should be changed. */ | |
9323 | #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 | |
9324 | #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 | |
9325 | #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 | |
9326 | #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 | |
9327 | #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 | |
9328 | /* The number of VLAN tags to insert/remove. An error will be returned if | |
9329 | * incompatible with the number of VLAN tags specified for the upstream | |
9330 | * v-switch. | |
9331 | */ | |
9332 | #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 | |
9333 | /* The actual VLAN tags to insert/remove */ | |
9334 | #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 | |
9335 | #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 | |
9336 | #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 | |
9337 | #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 | |
9338 | #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 | |
9339 | /* The number of MAC addresses to add */ | |
9340 | #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 | |
9341 | /* MAC addresses to add */ | |
9342 | #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 | |
9343 | #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 | |
9344 | #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 | |
9345 | ||
9346 | /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ | |
9347 | #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 | |
9348 | #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 | |
9349 | #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 | |
9350 | #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 | |
9351 | ||
9352 | ||
9353 | /***********************************/ | |
9354 | /* MC_CMD_EVB_PORT_QUERY | |
9355 | * read some config of v-port. | |
9356 | */ | |
9357 | #define MC_CMD_EVB_PORT_QUERY 0x62 | |
9358 | ||
9359 | #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
9360 | ||
9361 | /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ | |
9362 | #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 | |
9363 | /* The handle of the v-port */ | |
9364 | #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 | |
9365 | ||
9366 | /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ | |
9367 | #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 | |
9368 | /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ | |
9369 | #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 | |
9370 | /* The number of VLAN tags that may be used on a v-adaptor connected to this | |
9371 | * EVB port. | |
9372 | */ | |
9373 | #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 | |
9374 | ||
9375 | ||
f2b0befd BH |
9376 | /***********************************/ |
9377 | /* MC_CMD_DUMP_BUFTBL_ENTRIES | |
9378 | * Dump buffer table entries, mainly for command client debug use. Dumps | |
9379 | * absolute entries, and does not use chunk handles. All entries must be in | |
9380 | * range, and used for q page mapping, Although the latter restriction may be | |
9381 | * lifted in future. | |
9382 | */ | |
9383 | #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab | |
9384 | ||
75122ec8 SS |
9385 | #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9386 | ||
f2b0befd BH |
9387 | /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ |
9388 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 | |
9389 | /* Index of the first buffer table entry. */ | |
9390 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 | |
9391 | /* Number of buffer table entries to dump. */ | |
9392 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 | |
9393 | ||
9394 | /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ | |
9395 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 | |
9396 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 | |
9397 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) | |
a9196bb0 | 9398 | /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ |
f2b0befd BH |
9399 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 |
9400 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 | |
9401 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 | |
9402 | #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 | |
9403 | ||
9404 | ||
9405 | /***********************************/ | |
9406 | /* MC_CMD_SET_RXDP_CONFIG | |
9407 | * Set global RXDP configuration settings | |
9408 | */ | |
9409 | #define MC_CMD_SET_RXDP_CONFIG 0xc1 | |
9410 | ||
75122ec8 SS |
9411 | #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9412 | ||
f2b0befd BH |
9413 | /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ |
9414 | #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 | |
9415 | #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 | |
9416 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 | |
9417 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 | |
23e202b4 EC |
9418 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 |
9419 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 | |
9420 | /* enum: pad to 64 bytes */ | |
9421 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 | |
9422 | /* enum: pad to 128 bytes (Medford only) */ | |
9423 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 | |
9424 | /* enum: pad to 256 bytes (Medford only) */ | |
9425 | #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 | |
f2b0befd BH |
9426 | |
9427 | /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ | |
9428 | #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 | |
9429 | ||
9430 | ||
9431 | /***********************************/ | |
9432 | /* MC_CMD_GET_RXDP_CONFIG | |
9433 | * Get global RXDP configuration settings | |
9434 | */ | |
9435 | #define MC_CMD_GET_RXDP_CONFIG 0xc2 | |
9436 | ||
d29e33d6 | 9437 | #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
75122ec8 | 9438 | |
f2b0befd BH |
9439 | /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ |
9440 | #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 | |
9441 | ||
9442 | /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ | |
9443 | #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 | |
9444 | #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 | |
9445 | #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 | |
9446 | #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 | |
23e202b4 EC |
9447 | #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 |
9448 | #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 | |
9449 | /* Enum values, see field(s): */ | |
9450 | /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ | |
f2b0befd BH |
9451 | |
9452 | ||
f2b0befd BH |
9453 | /***********************************/ |
9454 | /* MC_CMD_GET_CLOCK | |
9455 | * Return the system and PDCPU clock frequencies. | |
9456 | */ | |
9457 | #define MC_CMD_GET_CLOCK 0xac | |
9458 | ||
75122ec8 SS |
9459 | #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9460 | ||
f2b0befd BH |
9461 | /* MC_CMD_GET_CLOCK_IN msgrequest */ |
9462 | #define MC_CMD_GET_CLOCK_IN_LEN 0 | |
9463 | ||
9464 | /* MC_CMD_GET_CLOCK_OUT msgresponse */ | |
9465 | #define MC_CMD_GET_CLOCK_OUT_LEN 8 | |
9466 | /* System frequency, MHz */ | |
9467 | #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 | |
9468 | /* DPCPU frequency, MHz */ | |
9469 | #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 | |
9470 | ||
9471 | ||
9472 | /***********************************/ | |
9473 | /* MC_CMD_SET_CLOCK | |
9474 | * Control the system and DPCPU clock frequencies. Changes are lost reboot. | |
9475 | */ | |
9476 | #define MC_CMD_SET_CLOCK 0xad | |
9477 | ||
75122ec8 SS |
9478 | #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9479 | ||
f2b0befd | 9480 | /* MC_CMD_SET_CLOCK_IN msgrequest */ |
a9196bb0 EC |
9481 | #define MC_CMD_SET_CLOCK_IN_LEN 28 |
9482 | /* Requested frequency in MHz for system clock domain */ | |
f2b0befd | 9483 | #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 |
a9196bb0 EC |
9484 | /* enum: Leave the system clock domain frequency unchanged */ |
9485 | #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 | |
9486 | /* Requested frequency in MHz for inter-core clock domain */ | |
f2b0befd | 9487 | #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 |
a9196bb0 EC |
9488 | /* enum: Leave the inter-core clock domain frequency unchanged */ |
9489 | #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 | |
9490 | /* Requested frequency in MHz for DPCPU clock domain */ | |
f2b0befd | 9491 | #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 |
a9196bb0 EC |
9492 | /* enum: Leave the DPCPU clock domain frequency unchanged */ |
9493 | #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 | |
9494 | /* Requested frequency in MHz for PCS clock domain */ | |
9495 | #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 | |
9496 | /* enum: Leave the PCS clock domain frequency unchanged */ | |
9497 | #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 | |
9498 | /* Requested frequency in MHz for MC clock domain */ | |
9499 | #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 | |
9500 | /* enum: Leave the MC clock domain frequency unchanged */ | |
9501 | #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 | |
9502 | /* Requested frequency in MHz for rmon clock domain */ | |
9503 | #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 | |
9504 | /* enum: Leave the rmon clock domain frequency unchanged */ | |
9505 | #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 | |
9506 | /* Requested frequency in MHz for vswitch clock domain */ | |
9507 | #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 | |
9508 | /* enum: Leave the vswitch clock domain frequency unchanged */ | |
9509 | #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 | |
f2b0befd BH |
9510 | |
9511 | /* MC_CMD_SET_CLOCK_OUT msgresponse */ | |
a9196bb0 | 9512 | #define MC_CMD_SET_CLOCK_OUT_LEN 28 |
f2b0befd BH |
9513 | /* Resulting system frequency in MHz */ |
9514 | #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 | |
a9196bb0 EC |
9515 | /* enum: The system clock domain doesn't exist */ |
9516 | #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 | |
f2b0befd BH |
9517 | /* Resulting inter-core frequency in MHz */ |
9518 | #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 | |
a9196bb0 EC |
9519 | /* enum: The inter-core clock domain doesn't exist / isn't used */ |
9520 | #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 | |
f2b0befd BH |
9521 | /* Resulting DPCPU frequency in MHz */ |
9522 | #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 | |
a9196bb0 EC |
9523 | /* enum: The dpcpu clock domain doesn't exist */ |
9524 | #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 | |
9525 | /* Resulting PCS frequency in MHz */ | |
9526 | #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 | |
9527 | /* enum: The PCS clock domain doesn't exist / isn't controlled */ | |
9528 | #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 | |
9529 | /* Resulting MC frequency in MHz */ | |
9530 | #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 | |
9531 | /* enum: The MC clock domain doesn't exist / isn't controlled */ | |
9532 | #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 | |
9533 | /* Resulting rmon frequency in MHz */ | |
9534 | #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 | |
9535 | /* enum: The rmon clock domain doesn't exist / isn't controlled */ | |
9536 | #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 | |
9537 | /* Resulting vswitch frequency in MHz */ | |
9538 | #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 | |
9539 | /* enum: The vswitch clock domain doesn't exist / isn't controlled */ | |
9540 | #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 | |
f2b0befd BH |
9541 | |
9542 | ||
9543 | /***********************************/ | |
9544 | /* MC_CMD_DPCPU_RPC | |
9545 | * Send an arbitrary DPCPU message. | |
9546 | */ | |
9547 | #define MC_CMD_DPCPU_RPC 0xae | |
9548 | ||
75122ec8 SS |
9549 | #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9550 | ||
f2b0befd BH |
9551 | /* MC_CMD_DPCPU_RPC_IN msgrequest */ |
9552 | #define MC_CMD_DPCPU_RPC_IN_LEN 36 | |
9553 | #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 | |
a9196bb0 EC |
9554 | /* enum: RxDPCPU0 */ |
9555 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 | |
f2b0befd BH |
9556 | /* enum: TxDPCPU0 */ |
9557 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 | |
9558 | /* enum: TxDPCPU1 */ | |
9559 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 | |
a9196bb0 EC |
9560 | /* enum: RxDPCPU1 (Medford only) */ |
9561 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 | |
9562 | /* enum: RxDPCPU (will be for the calling function; for now, just an alias of | |
9563 | * DPCPU_RX0) | |
9564 | */ | |
9565 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 | |
9566 | /* enum: TxDPCPU (will be for the calling function; for now, just an alias of | |
9567 | * DPCPU_TX0) | |
9568 | */ | |
9569 | #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 | |
f2b0befd BH |
9570 | /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be |
9571 | * initialised to zero | |
9572 | */ | |
9573 | #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 | |
9574 | #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 | |
9575 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 | |
9576 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 | |
9577 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ | |
9578 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ | |
9579 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ | |
9580 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ | |
9581 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ | |
9582 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ | |
9583 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ | |
9584 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ | |
9585 | #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ | |
9586 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 | |
9587 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 | |
9588 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 | |
9589 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 | |
9590 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 | |
9591 | #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 | |
9592 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 | |
9593 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 | |
9594 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 | |
9595 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 | |
9596 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ | |
9597 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ | |
9598 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ | |
9599 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ | |
9600 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ | |
9601 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 | |
9602 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 | |
9603 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 | |
9604 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 | |
9605 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 | |
9606 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 | |
9607 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 | |
9608 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 | |
9609 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ | |
9610 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ | |
9611 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ | |
9612 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 | |
9613 | #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 | |
9614 | #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 | |
9615 | #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 | |
9616 | /* Register data to write. Only valid in write/write-read. */ | |
9617 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 | |
9618 | /* Register address. */ | |
9619 | #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 | |
9620 | ||
9621 | /* MC_CMD_DPCPU_RPC_OUT msgresponse */ | |
9622 | #define MC_CMD_DPCPU_RPC_OUT_LEN 36 | |
9623 | #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 | |
9624 | /* DATA */ | |
9625 | #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 | |
9626 | #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 | |
9627 | #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 | |
9628 | #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 | |
9629 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 | |
9630 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 | |
9631 | #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 | |
9632 | #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 | |
9633 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 | |
9634 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 | |
9635 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 | |
9636 | #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 | |
9637 | ||
9638 | ||
9639 | /***********************************/ | |
9640 | /* MC_CMD_TRIGGER_INTERRUPT | |
9641 | * Trigger an interrupt by prodding the BIU. | |
9642 | */ | |
9643 | #define MC_CMD_TRIGGER_INTERRUPT 0xe3 | |
9644 | ||
75122ec8 SS |
9645 | #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9646 | ||
f2b0befd BH |
9647 | /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ |
9648 | #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 | |
9649 | /* Interrupt level relative to base for function. */ | |
9650 | #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 | |
9651 | ||
9652 | /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ | |
9653 | #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 | |
9654 | ||
9655 | ||
a9196bb0 EC |
9656 | /***********************************/ |
9657 | /* MC_CMD_SHMBOOT_OP | |
9658 | * Special operations to support (for now) shmboot. | |
9659 | */ | |
9660 | #define MC_CMD_SHMBOOT_OP 0xe6 | |
9661 | ||
9662 | #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
9663 | ||
9664 | /* MC_CMD_SHMBOOT_OP_IN msgrequest */ | |
9665 | #define MC_CMD_SHMBOOT_OP_IN_LEN 4 | |
9666 | /* Identifies the operation to perform */ | |
9667 | #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 | |
9668 | /* enum: Copy slave_data section to the slave core. (Greenport only) */ | |
9669 | #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 | |
9670 | ||
9671 | /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ | |
9672 | #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 | |
9673 | ||
9674 | ||
512bb06c BH |
9675 | /***********************************/ |
9676 | /* MC_CMD_CAP_BLK_READ | |
9677 | * Read multiple 64bit words from capture block memory | |
9678 | */ | |
9679 | #define MC_CMD_CAP_BLK_READ 0xe7 | |
9680 | ||
75122ec8 SS |
9681 | #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9682 | ||
512bb06c BH |
9683 | /* MC_CMD_CAP_BLK_READ_IN msgrequest */ |
9684 | #define MC_CMD_CAP_BLK_READ_IN_LEN 12 | |
9685 | #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 | |
9686 | #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 | |
9687 | #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 | |
9688 | ||
9689 | /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ | |
9690 | #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 | |
9691 | #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 | |
9692 | #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) | |
9693 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 | |
9694 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 | |
9695 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 | |
9696 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 | |
9697 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 | |
9698 | #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 | |
9699 | ||
9700 | ||
f2b0befd BH |
9701 | /***********************************/ |
9702 | /* MC_CMD_DUMP_DO | |
9703 | * Take a dump of the DUT state | |
9704 | */ | |
9705 | #define MC_CMD_DUMP_DO 0xe8 | |
9706 | ||
75122ec8 SS |
9707 | #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9708 | ||
f2b0befd BH |
9709 | /* MC_CMD_DUMP_DO_IN msgrequest */ |
9710 | #define MC_CMD_DUMP_DO_IN_LEN 52 | |
9711 | #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 | |
9712 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 | |
9713 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ | |
9714 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ | |
9715 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 | |
9716 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ | |
9717 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ | |
9718 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ | |
9719 | #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ | |
9720 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 | |
9721 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 | |
9722 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 | |
9723 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 | |
9724 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 | |
9725 | #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ | |
9726 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 | |
9727 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 | |
9728 | #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ | |
9729 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 | |
512bb06c BH |
9730 | /* enum: The uart port this command was received over (if using a uart |
9731 | * transport) | |
9732 | */ | |
9733 | #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff | |
f2b0befd BH |
9734 | #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 |
9735 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 | |
9736 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ | |
9737 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ | |
9738 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 | |
9739 | /* Enum values, see field(s): */ | |
9740 | /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
9741 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 | |
9742 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 | |
9743 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 | |
9744 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 | |
9745 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 | |
9746 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 | |
9747 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 | |
9748 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 | |
9749 | #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 | |
9750 | ||
9751 | /* MC_CMD_DUMP_DO_OUT msgresponse */ | |
9752 | #define MC_CMD_DUMP_DO_OUT_LEN 4 | |
9753 | #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 | |
9754 | ||
9755 | ||
9756 | /***********************************/ | |
9757 | /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED | |
9758 | * Configure unsolicited dumps | |
9759 | */ | |
9760 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 | |
9761 | ||
75122ec8 SS |
9762 | #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9763 | ||
f2b0befd BH |
9764 | /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ |
9765 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 | |
9766 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 | |
9767 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 | |
9768 | /* Enum values, see field(s): */ | |
9769 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ | |
9770 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 | |
9771 | /* Enum values, see field(s): */ | |
9772 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
9773 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 | |
9774 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 | |
9775 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 | |
9776 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 | |
9777 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 | |
9778 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 | |
9779 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 | |
9780 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 | |
9781 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 | |
9782 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 | |
9783 | /* Enum values, see field(s): */ | |
9784 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ | |
9785 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 | |
9786 | /* Enum values, see field(s): */ | |
9787 | /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ | |
9788 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 | |
9789 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 | |
9790 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 | |
9791 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 | |
9792 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 | |
9793 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 | |
9794 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 | |
9795 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 | |
9796 | #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 | |
9797 | ||
9798 | ||
9799 | /***********************************/ | |
9800 | /* MC_CMD_SET_PSU | |
9801 | * Adjusts power supply parameters. This is a warranty-voiding operation. | |
9802 | * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if | |
9803 | * the parameter is out of range. | |
9804 | */ | |
9805 | #define MC_CMD_SET_PSU 0xea | |
9806 | ||
75122ec8 SS |
9807 | #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9808 | ||
f2b0befd BH |
9809 | /* MC_CMD_SET_PSU_IN msgrequest */ |
9810 | #define MC_CMD_SET_PSU_IN_LEN 12 | |
9811 | #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 | |
9812 | #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ | |
9813 | #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 | |
9814 | #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ | |
9815 | #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ | |
9816 | /* desired value, eg voltage in mV */ | |
9817 | #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 | |
9818 | ||
9819 | /* MC_CMD_SET_PSU_OUT msgresponse */ | |
9820 | #define MC_CMD_SET_PSU_OUT_LEN 0 | |
9821 | ||
9822 | ||
9823 | /***********************************/ | |
9824 | /* MC_CMD_GET_FUNCTION_INFO | |
9825 | * Get function information. PF and VF number. | |
9826 | */ | |
9827 | #define MC_CMD_GET_FUNCTION_INFO 0xec | |
9828 | ||
75122ec8 SS |
9829 | #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9830 | ||
f2b0befd BH |
9831 | /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ |
9832 | #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 | |
9833 | ||
9834 | /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ | |
9835 | #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 | |
9836 | #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 | |
9837 | #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 | |
9838 | ||
9839 | ||
9840 | /***********************************/ | |
9841 | /* MC_CMD_ENABLE_OFFLINE_BIST | |
9842 | * Enters offline BIST mode. All queues are torn down, chip enters quiescent | |
9843 | * mode, calling function gets exclusive MCDI ownership. The only way out is | |
9844 | * reboot. | |
9845 | */ | |
9846 | #define MC_CMD_ENABLE_OFFLINE_BIST 0xed | |
9847 | ||
75122ec8 SS |
9848 | #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9849 | ||
f2b0befd BH |
9850 | /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ |
9851 | #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 | |
9852 | ||
9853 | /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ | |
9854 | #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 | |
9855 | ||
9856 | ||
9857 | /***********************************/ | |
512bb06c BH |
9858 | /* MC_CMD_UART_SEND_DATA |
9859 | * Send checksummed[sic] block of data over the uart. Response is a placeholder | |
9860 | * should we wish to make this reliable; currently requests are fire-and- | |
9861 | * forget. | |
9862 | */ | |
9863 | #define MC_CMD_UART_SEND_DATA 0xee | |
9864 | ||
75122ec8 SS |
9865 | #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9866 | ||
512bb06c BH |
9867 | /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ |
9868 | #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 | |
9869 | #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 | |
9870 | #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) | |
9871 | /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ | |
9872 | #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 | |
9873 | /* Offset at which to write the data */ | |
9874 | #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 | |
9875 | /* Length of data */ | |
9876 | #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 | |
9877 | /* Reserved for future use */ | |
9878 | #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 | |
9879 | #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 | |
9880 | #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 | |
9881 | #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 | |
9882 | #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 | |
9883 | ||
9884 | /* MC_CMD_UART_SEND_DATA_IN msgresponse */ | |
9885 | #define MC_CMD_UART_SEND_DATA_IN_LEN 0 | |
9886 | ||
9887 | ||
9888 | /***********************************/ | |
9889 | /* MC_CMD_UART_RECV_DATA | |
9890 | * Request checksummed[sic] block of data over the uart. Only a placeholder, | |
9891 | * subject to change and not currently implemented. | |
9892 | */ | |
9893 | #define MC_CMD_UART_RECV_DATA 0xef | |
9894 | ||
75122ec8 SS |
9895 | #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
9896 | ||
512bb06c BH |
9897 | /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ |
9898 | #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 | |
9899 | /* CRC32 over OFFSET, LENGTH, RESERVED */ | |
9900 | #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 | |
9901 | /* Offset from which to read the data */ | |
9902 | #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 | |
9903 | /* Length of data */ | |
9904 | #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 | |
9905 | /* Reserved for future use */ | |
9906 | #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 | |
9907 | ||
9908 | /* MC_CMD_UART_RECV_DATA_IN msgresponse */ | |
9909 | #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 | |
9910 | #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 | |
9911 | #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) | |
9912 | /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ | |
9913 | #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 | |
9914 | /* Offset at which to write the data */ | |
9915 | #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 | |
9916 | /* Length of data */ | |
9917 | #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 | |
9918 | /* Reserved for future use */ | |
9919 | #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 | |
9920 | #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 | |
9921 | #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 | |
9922 | #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 | |
9923 | #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 | |
f2b0befd BH |
9924 | |
9925 | ||
9926 | /***********************************/ | |
9927 | /* MC_CMD_READ_FUSES | |
9928 | * Read data programmed into the device One-Time-Programmable (OTP) Fuses | |
9929 | */ | |
9930 | #define MC_CMD_READ_FUSES 0xf0 | |
9931 | ||
75122ec8 SS |
9932 | #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9933 | ||
f2b0befd BH |
9934 | /* MC_CMD_READ_FUSES_IN msgrequest */ |
9935 | #define MC_CMD_READ_FUSES_IN_LEN 8 | |
9936 | /* Offset in OTP to read */ | |
9937 | #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 | |
9938 | /* Length of data to read in bytes */ | |
9939 | #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 | |
9940 | ||
9941 | /* MC_CMD_READ_FUSES_OUT msgresponse */ | |
9942 | #define MC_CMD_READ_FUSES_OUT_LENMIN 4 | |
9943 | #define MC_CMD_READ_FUSES_OUT_LENMAX 252 | |
9944 | #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) | |
9945 | /* Length of returned OTP data in bytes */ | |
9946 | #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 | |
9947 | /* Returned data */ | |
9948 | #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 | |
9949 | #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 | |
9950 | #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 | |
9951 | #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 | |
9952 | ||
9953 | ||
9954 | /***********************************/ | |
9955 | /* MC_CMD_KR_TUNE | |
9956 | * Get or set KR Serdes RXEQ and TX Driver settings | |
9957 | */ | |
9958 | #define MC_CMD_KR_TUNE 0xf1 | |
9959 | ||
75122ec8 SS |
9960 | #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
9961 | ||
f2b0befd BH |
9962 | /* MC_CMD_KR_TUNE_IN msgrequest */ |
9963 | #define MC_CMD_KR_TUNE_IN_LENMIN 4 | |
9964 | #define MC_CMD_KR_TUNE_IN_LENMAX 252 | |
9965 | #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) | |
9966 | /* Requested operation */ | |
9967 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 | |
9968 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 | |
9969 | /* enum: Get current RXEQ settings */ | |
9970 | #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 | |
9971 | /* enum: Override RXEQ settings */ | |
9972 | #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 | |
9973 | /* enum: Get current TX Driver settings */ | |
9974 | #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 | |
9975 | /* enum: Override TX Driver settings */ | |
9976 | #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 | |
9977 | /* enum: Force KR Serdes reset / recalibration */ | |
9978 | #define MC_CMD_KR_TUNE_IN_RECAL 0x4 | |
512bb06c BH |
9979 | /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid |
9980 | * signal. | |
9981 | */ | |
9982 | #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 | |
9983 | /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The | |
9984 | * caller should call this command repeatedly after starting eye plot, until no | |
9985 | * more data is returned. | |
9986 | */ | |
9987 | #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 | |
a9196bb0 EC |
9988 | /* enum: Read Figure Of Merit (eye quality, higher is better). */ |
9989 | #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 | |
f2b0befd BH |
9990 | /* Align the arguments to 32 bits */ |
9991 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 | |
9992 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 | |
9993 | /* Arguments specific to the operation */ | |
9994 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 | |
9995 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 | |
9996 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 | |
9997 | #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 | |
9998 | ||
9999 | /* MC_CMD_KR_TUNE_OUT msgresponse */ | |
10000 | #define MC_CMD_KR_TUNE_OUT_LEN 0 | |
10001 | ||
10002 | /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ | |
10003 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 | |
10004 | /* Requested operation */ | |
10005 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 | |
10006 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 | |
10007 | /* Align the arguments to 32 bits */ | |
10008 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 | |
10009 | #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 | |
10010 | ||
10011 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ | |
10012 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 | |
10013 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 | |
10014 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
10015 | /* RXEQ Parameter */ | |
10016 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 | |
10017 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 | |
10018 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 | |
10019 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 | |
10020 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 | |
10021 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
23e202b4 | 10022 | /* enum: Attenuation (0-15, Huntington) */ |
f2b0befd | 10023 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 |
23e202b4 | 10024 | /* enum: CTLE Boost (0-15, Huntington) */ |
f2b0befd | 10025 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 |
23e202b4 EC |
10026 | /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max |
10027 | * positive, Medford - 0-31) | |
a9196bb0 | 10028 | */ |
f2b0befd | 10029 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 |
23e202b4 EC |
10030 | /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max |
10031 | * positive, Medford - 0-31) | |
a9196bb0 | 10032 | */ |
f2b0befd | 10033 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 |
23e202b4 EC |
10034 | /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max |
10035 | * positive, Medford - 0-16) | |
a9196bb0 | 10036 | */ |
f2b0befd | 10037 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 |
23e202b4 EC |
10038 | /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max |
10039 | * positive, Medford - 0-16) | |
a9196bb0 | 10040 | */ |
f2b0befd | 10041 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 |
23e202b4 EC |
10042 | /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max |
10043 | * positive, Medford - 0-16) | |
a9196bb0 | 10044 | */ |
f2b0befd | 10045 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 |
23e202b4 | 10046 | /* enum: Edge DFE DLEV (0-128 for Medford) */ |
a9196bb0 | 10047 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 |
23e202b4 EC |
10048 | /* enum: Variable Gain Amplifier (0-15, Medford) */ |
10049 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 | |
10050 | /* enum: CTLE EQ Capacitor (0-15, Medford) */ | |
10051 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 | |
10052 | /* enum: CTLE EQ Resistor (0-7, Medford) */ | |
10053 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa | |
f2b0befd BH |
10054 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 |
10055 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 | |
10056 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ | |
10057 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ | |
10058 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ | |
10059 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ | |
10060 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ | |
10061 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 | |
10062 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 | |
10063 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 | |
10064 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 | |
10065 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 | |
10066 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 | |
10067 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 | |
10068 | #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
10069 | ||
10070 | /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ | |
10071 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 | |
10072 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 | |
10073 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) | |
10074 | /* Requested operation */ | |
10075 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 | |
10076 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 | |
10077 | /* Align the arguments to 32 bits */ | |
10078 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 | |
10079 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 | |
10080 | /* RXEQ Parameter */ | |
10081 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 | |
10082 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 | |
10083 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 | |
10084 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 | |
10085 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 | |
10086 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 | |
10087 | /* Enum values, see field(s): */ | |
10088 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ | |
10089 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 | |
10090 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 | |
10091 | /* Enum values, see field(s): */ | |
10092 | /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ | |
10093 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 | |
10094 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 | |
10095 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 | |
10096 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 | |
10097 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 | |
10098 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 | |
10099 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 | |
10100 | #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 | |
10101 | ||
10102 | /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ | |
10103 | #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 | |
10104 | ||
512bb06c BH |
10105 | /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ |
10106 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 | |
10107 | /* Requested operation */ | |
10108 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 | |
10109 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 | |
10110 | /* Align the arguments to 32 bits */ | |
10111 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 | |
10112 | #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 | |
10113 | ||
10114 | /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ | |
10115 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 | |
10116 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 | |
10117 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
10118 | /* TXEQ Parameter */ | |
10119 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 | |
10120 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 | |
10121 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 | |
10122 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 | |
10123 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 | |
10124 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
23e202b4 | 10125 | /* enum: TX Amplitude (Huntington, Medford) */ |
512bb06c | 10126 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 |
23e202b4 | 10127 | /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ |
512bb06c BH |
10128 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 |
10129 | /* enum: De-Emphasis Tap1 Fine */ | |
10130 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 | |
23e202b4 | 10131 | /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ |
512bb06c | 10132 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 |
23e202b4 | 10133 | /* enum: De-Emphasis Tap2 Fine (Huntington) */ |
512bb06c | 10134 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 |
23e202b4 | 10135 | /* enum: Pre-Emphasis Magnitude (Huntington) */ |
512bb06c | 10136 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 |
23e202b4 | 10137 | /* enum: Pre-Emphasis Fine (Huntington) */ |
512bb06c | 10138 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 |
23e202b4 | 10139 | /* enum: TX Slew Rate Coarse control (Huntington) */ |
512bb06c | 10140 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 |
23e202b4 | 10141 | /* enum: TX Slew Rate Fine control (Huntington) */ |
512bb06c | 10142 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 |
23e202b4 | 10143 | /* enum: TX Termination Impedance control (Huntington) */ |
a9196bb0 | 10144 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 |
23e202b4 EC |
10145 | /* enum: TX Amplitude Fine control (Medford) */ |
10146 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa | |
10147 | /* enum: Pre-shoot Tap (Medford) */ | |
10148 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb | |
10149 | /* enum: De-emphasis Tap (Medford) */ | |
10150 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc | |
512bb06c BH |
10151 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 |
10152 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 | |
10153 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ | |
10154 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ | |
10155 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ | |
10156 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ | |
10157 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ | |
10158 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 | |
10159 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 | |
10160 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 | |
10161 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 | |
10162 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 | |
10163 | #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 | |
10164 | ||
10165 | /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ | |
10166 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 | |
10167 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 | |
10168 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) | |
10169 | /* Requested operation */ | |
10170 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 | |
10171 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 | |
10172 | /* Align the arguments to 32 bits */ | |
10173 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 | |
10174 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 | |
10175 | /* TXEQ Parameter */ | |
10176 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 | |
10177 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 | |
10178 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 | |
10179 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 | |
10180 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 | |
10181 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 | |
10182 | /* Enum values, see field(s): */ | |
10183 | /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ | |
10184 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 | |
10185 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 | |
10186 | /* Enum values, see field(s): */ | |
10187 | /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ | |
10188 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 | |
10189 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 | |
10190 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 | |
10191 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 | |
10192 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 | |
10193 | #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 | |
10194 | ||
10195 | /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ | |
10196 | #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 | |
10197 | ||
f2b0befd BH |
10198 | /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ |
10199 | #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 | |
10200 | /* Requested operation */ | |
10201 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 | |
10202 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 | |
10203 | /* Align the arguments to 32 bits */ | |
10204 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 | |
10205 | #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 | |
10206 | ||
10207 | /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ | |
10208 | #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 | |
10209 | ||
512bb06c BH |
10210 | /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ |
10211 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 | |
10212 | /* Requested operation */ | |
10213 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 | |
10214 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 | |
10215 | /* Align the arguments to 32 bits */ | |
10216 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 | |
10217 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 | |
10218 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 | |
10219 | ||
10220 | /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ | |
10221 | #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 | |
10222 | ||
10223 | /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ | |
10224 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 | |
10225 | /* Requested operation */ | |
10226 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 | |
10227 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 | |
10228 | /* Align the arguments to 32 bits */ | |
10229 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 | |
10230 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 | |
10231 | ||
10232 | /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ | |
10233 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 | |
10234 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 | |
10235 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) | |
10236 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 | |
10237 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 | |
10238 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 | |
10239 | #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 | |
10240 | ||
a9196bb0 EC |
10241 | /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ |
10242 | #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 | |
10243 | /* Requested operation */ | |
10244 | #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 | |
10245 | #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 | |
10246 | /* Align the arguments to 32 bits */ | |
10247 | #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 | |
10248 | #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 | |
10249 | #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 | |
10250 | ||
10251 | /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ | |
10252 | #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 | |
10253 | #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 | |
10254 | ||
f2b0befd BH |
10255 | |
10256 | /***********************************/ | |
10257 | /* MC_CMD_PCIE_TUNE | |
10258 | * Get or set PCIE Serdes RXEQ and TX Driver settings | |
10259 | */ | |
10260 | #define MC_CMD_PCIE_TUNE 0xf2 | |
10261 | ||
75122ec8 SS |
10262 | #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
10263 | ||
f2b0befd BH |
10264 | /* MC_CMD_PCIE_TUNE_IN msgrequest */ |
10265 | #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 | |
10266 | #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 | |
10267 | #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) | |
10268 | /* Requested operation */ | |
10269 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 | |
10270 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 | |
10271 | /* enum: Get current RXEQ settings */ | |
10272 | #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 | |
10273 | /* enum: Override RXEQ settings */ | |
10274 | #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 | |
10275 | /* enum: Get current TX Driver settings */ | |
10276 | #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 | |
10277 | /* enum: Override TX Driver settings */ | |
10278 | #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 | |
512bb06c BH |
10279 | /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ |
10280 | #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 | |
10281 | /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The | |
10282 | * caller should call this command repeatedly after starting eye plot, until no | |
10283 | * more data is returned. | |
10284 | */ | |
10285 | #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 | |
f2b0befd BH |
10286 | /* Align the arguments to 32 bits */ |
10287 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 | |
10288 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 | |
10289 | /* Arguments specific to the operation */ | |
10290 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 | |
10291 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 | |
10292 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 | |
10293 | #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 | |
10294 | ||
10295 | /* MC_CMD_PCIE_TUNE_OUT msgresponse */ | |
10296 | #define MC_CMD_PCIE_TUNE_OUT_LEN 0 | |
10297 | ||
10298 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ | |
10299 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 | |
10300 | /* Requested operation */ | |
10301 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 | |
10302 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 | |
10303 | /* Align the arguments to 32 bits */ | |
10304 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 | |
10305 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 | |
10306 | ||
10307 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ | |
10308 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 | |
10309 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 | |
10310 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
10311 | /* RXEQ Parameter */ | |
10312 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 | |
10313 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 | |
10314 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 | |
10315 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 | |
10316 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 | |
10317 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
10318 | /* enum: Attenuation (0-15) */ | |
10319 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 | |
10320 | /* enum: CTLE Boost (0-15) */ | |
10321 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 | |
10322 | /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ | |
10323 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 | |
10324 | /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ | |
10325 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 | |
10326 | /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ | |
10327 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 | |
10328 | /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ | |
10329 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 | |
10330 | /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ | |
10331 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 | |
23e202b4 EC |
10332 | /* enum: DFE DLev */ |
10333 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 | |
10334 | /* enum: Figure of Merit */ | |
10335 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 | |
10336 | /* enum: CTLE EQ Capacitor (HF Gain) */ | |
10337 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 | |
10338 | /* enum: CTLE EQ Resistor (DC Gain) */ | |
10339 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa | |
f2b0befd | 10340 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 |
23e202b4 | 10341 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 |
f2b0befd BH |
10342 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ |
10343 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ | |
10344 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ | |
10345 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ | |
10346 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ | |
10347 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ | |
10348 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ | |
10349 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ | |
23e202b4 EC |
10350 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ |
10351 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ | |
10352 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ | |
10353 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ | |
10354 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ | |
10355 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ | |
10356 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ | |
10357 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ | |
10358 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ | |
10359 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 | |
10360 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 | |
10361 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 | |
10362 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 | |
f2b0befd BH |
10363 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 |
10364 | #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
10365 | ||
23e202b4 EC |
10366 | /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ |
10367 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 | |
10368 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 | |
10369 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) | |
10370 | /* Requested operation */ | |
10371 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 | |
10372 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 | |
10373 | /* Align the arguments to 32 bits */ | |
10374 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 | |
10375 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 | |
10376 | /* RXEQ Parameter */ | |
10377 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 | |
10378 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 | |
10379 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 | |
10380 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 | |
10381 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 | |
10382 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 | |
10383 | /* Enum values, see field(s): */ | |
10384 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ | |
10385 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 | |
10386 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 | |
10387 | /* Enum values, see field(s): */ | |
10388 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ | |
10389 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 | |
10390 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 | |
10391 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 | |
10392 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 | |
10393 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 | |
10394 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 | |
10395 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 | |
10396 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 | |
10397 | ||
10398 | /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ | |
10399 | #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 | |
10400 | ||
f2b0befd BH |
10401 | /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ |
10402 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 | |
10403 | /* Requested operation */ | |
10404 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 | |
10405 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 | |
10406 | /* Align the arguments to 32 bits */ | |
10407 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 | |
10408 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 | |
10409 | ||
10410 | /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ | |
10411 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 | |
10412 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 | |
10413 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) | |
10414 | /* RXEQ Parameter */ | |
10415 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 | |
10416 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 | |
10417 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 | |
10418 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 | |
10419 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 | |
10420 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 | |
10421 | /* enum: TxMargin (PIPE) */ | |
10422 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 | |
10423 | /* enum: TxSwing (PIPE) */ | |
10424 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 | |
10425 | /* enum: De-emphasis coefficient C(-1) (PIPE) */ | |
10426 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 | |
10427 | /* enum: De-emphasis coefficient C(0) (PIPE) */ | |
10428 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 | |
10429 | /* enum: De-emphasis coefficient C(+1) (PIPE) */ | |
10430 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 | |
10431 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 | |
10432 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 | |
10433 | /* Enum values, see field(s): */ | |
10434 | /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ | |
10435 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 | |
10436 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 | |
10437 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 | |
10438 | #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 | |
10439 | ||
512bb06c BH |
10440 | /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ |
10441 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 | |
10442 | /* Requested operation */ | |
10443 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 | |
10444 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 | |
10445 | /* Align the arguments to 32 bits */ | |
10446 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 | |
10447 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 | |
10448 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 | |
10449 | ||
10450 | /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ | |
10451 | #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 | |
10452 | ||
10453 | /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ | |
10454 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 | |
10455 | /* Requested operation */ | |
10456 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 | |
10457 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 | |
10458 | /* Align the arguments to 32 bits */ | |
10459 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 | |
10460 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 | |
10461 | ||
10462 | /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ | |
10463 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 | |
10464 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 | |
10465 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) | |
10466 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 | |
10467 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 | |
10468 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 | |
10469 | #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 | |
10470 | ||
f2b0befd BH |
10471 | |
10472 | /***********************************/ | |
10473 | /* MC_CMD_LICENSING | |
10474 | * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition | |
23e202b4 | 10475 | * - not used for V3 licensing |
f2b0befd BH |
10476 | */ |
10477 | #define MC_CMD_LICENSING 0xf3 | |
10478 | ||
75122ec8 SS |
10479 | #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
10480 | ||
f2b0befd BH |
10481 | /* MC_CMD_LICENSING_IN msgrequest */ |
10482 | #define MC_CMD_LICENSING_IN_LEN 4 | |
10483 | /* identifies the type of operation requested */ | |
10484 | #define MC_CMD_LICENSING_IN_OP_OFST 0 | |
10485 | /* enum: re-read and apply licenses after a license key partition update; note | |
10486 | * that this operation returns a zero-length response | |
10487 | */ | |
10488 | #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 | |
10489 | /* enum: report counts of installed licenses */ | |
10490 | #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 | |
10491 | ||
10492 | /* MC_CMD_LICENSING_OUT msgresponse */ | |
10493 | #define MC_CMD_LICENSING_OUT_LEN 28 | |
10494 | /* count of application keys which are valid */ | |
10495 | #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 | |
10496 | /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with | |
10497 | * MC_CMD_FC_OP_LICENSE) | |
10498 | */ | |
10499 | #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 | |
10500 | /* count of application keys which are invalid due to being blacklisted */ | |
10501 | #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 | |
10502 | /* count of application keys which are invalid due to being unverifiable */ | |
10503 | #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 | |
10504 | /* count of application keys which are invalid due to being for the wrong node | |
10505 | */ | |
10506 | #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 | |
10507 | /* licensing state (for diagnostics; the exact meaning of the bits in this | |
10508 | * field are private to the firmware) | |
10509 | */ | |
10510 | #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 | |
10511 | /* licensing subsystem self-test report (for manftest) */ | |
10512 | #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 | |
10513 | /* enum: licensing subsystem self-test failed */ | |
10514 | #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 | |
10515 | /* enum: licensing subsystem self-test passed */ | |
10516 | #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 | |
10517 | ||
10518 | ||
23e202b4 EC |
10519 | /***********************************/ |
10520 | /* MC_CMD_LICENSING_V3 | |
10521 | * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition | |
10522 | * - V3 licensing (Medford) | |
10523 | */ | |
10524 | #define MC_CMD_LICENSING_V3 0xd0 | |
10525 | ||
10526 | #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
10527 | ||
10528 | /* MC_CMD_LICENSING_V3_IN msgrequest */ | |
10529 | #define MC_CMD_LICENSING_V3_IN_LEN 4 | |
10530 | /* identifies the type of operation requested */ | |
10531 | #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 | |
10532 | /* enum: re-read and apply licenses after a license key partition update; note | |
10533 | * that this operation returns a zero-length response | |
10534 | */ | |
10535 | #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 | |
d29e33d6 BK |
10536 | /* enum: report counts of installed licenses Returns EAGAIN if license |
10537 | * processing (updating) has been started but not yet completed. | |
10538 | */ | |
23e202b4 EC |
10539 | #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 |
10540 | ||
10541 | /* MC_CMD_LICENSING_V3_OUT msgresponse */ | |
10542 | #define MC_CMD_LICENSING_V3_OUT_LEN 88 | |
10543 | /* count of keys which are valid */ | |
10544 | #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 | |
10545 | /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with | |
10546 | * MC_CMD_FC_OP_LICENSE) | |
10547 | */ | |
10548 | #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 | |
10549 | /* count of keys which are invalid due to being unverifiable */ | |
10550 | #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 | |
10551 | /* count of keys which are invalid due to being for the wrong node */ | |
10552 | #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 | |
10553 | /* licensing state (for diagnostics; the exact meaning of the bits in this | |
10554 | * field are private to the firmware) | |
10555 | */ | |
10556 | #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 | |
10557 | /* licensing subsystem self-test report (for manftest) */ | |
10558 | #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 | |
10559 | /* enum: licensing subsystem self-test failed */ | |
10560 | #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 | |
10561 | /* enum: licensing subsystem self-test passed */ | |
10562 | #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 | |
10563 | /* bitmask of licensed applications */ | |
10564 | #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 | |
10565 | #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 | |
10566 | #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 | |
10567 | #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 | |
10568 | /* reserved for future use */ | |
10569 | #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 | |
10570 | #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 | |
10571 | /* bitmask of licensed features */ | |
10572 | #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 | |
10573 | #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 | |
10574 | #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 | |
10575 | #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 | |
10576 | /* reserved for future use */ | |
10577 | #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 | |
10578 | #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 | |
10579 | ||
10580 | ||
10581 | /***********************************/ | |
10582 | /* MC_CMD_LICENSING_GET_ID_V3 | |
10583 | * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license | |
10584 | * partition - V3 licensing (Medford) | |
10585 | */ | |
10586 | #define MC_CMD_LICENSING_GET_ID_V3 0xd1 | |
10587 | ||
10588 | #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
10589 | ||
10590 | /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ | |
10591 | #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 | |
10592 | ||
10593 | /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ | |
10594 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 | |
10595 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 | |
10596 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) | |
10597 | /* type of license (eg 3) */ | |
10598 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 | |
10599 | /* length of the license ID (in bytes) */ | |
10600 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 | |
10601 | /* the unique license ID of the adapter */ | |
10602 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 | |
10603 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 | |
10604 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 | |
10605 | #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 | |
10606 | ||
10607 | ||
f2b0befd BH |
10608 | /***********************************/ |
10609 | /* MC_CMD_MC2MC_PROXY | |
10610 | * Execute an arbitrary MCDI command on the slave MC of a dual-core device. | |
10611 | * This will fail on a single-core system. | |
10612 | */ | |
10613 | #define MC_CMD_MC2MC_PROXY 0xf4 | |
05a9320f | 10614 | |
75122ec8 SS |
10615 | #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
10616 | ||
512bb06c BH |
10617 | /* MC_CMD_MC2MC_PROXY_IN msgrequest */ |
10618 | #define MC_CMD_MC2MC_PROXY_IN_LEN 0 | |
10619 | ||
10620 | /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ | |
10621 | #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 | |
10622 | ||
10623 | ||
10624 | /***********************************/ | |
10625 | /* MC_CMD_GET_LICENSED_APP_STATE | |
10626 | * Query the state of an individual licensed application. (Note that the actual | |
10627 | * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation | |
23e202b4 | 10628 | * or a reboot of the MC.) Not used for V3 licensing |
512bb06c BH |
10629 | */ |
10630 | #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 | |
10631 | ||
75122ec8 SS |
10632 | #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
10633 | ||
512bb06c BH |
10634 | /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ |
10635 | #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 | |
10636 | /* application ID to query (LICENSED_APP_ID_xxx) */ | |
10637 | #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 | |
10638 | ||
10639 | /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ | |
10640 | #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 | |
10641 | /* state of this application */ | |
10642 | #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 | |
10643 | /* enum: no (or invalid) license is present for the application */ | |
10644 | #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 | |
10645 | /* enum: a valid license is present for the application */ | |
10646 | #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 | |
10647 | ||
10648 | ||
23e202b4 EC |
10649 | /***********************************/ |
10650 | /* MC_CMD_GET_LICENSED_V3_APP_STATE | |
10651 | * Query the state of an individual licensed application. (Note that the actual | |
10652 | * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE | |
10653 | * operation or a reboot of the MC.) Used for V3 licensing (Medford) | |
10654 | */ | |
10655 | #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 | |
10656 | ||
10657 | #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
10658 | ||
10659 | /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ | |
10660 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 | |
10661 | /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit | |
10662 | * mask | |
10663 | */ | |
10664 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 | |
10665 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 | |
10666 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 | |
10667 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 | |
10668 | ||
10669 | /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ | |
10670 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 | |
10671 | /* state of this application */ | |
10672 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 | |
10673 | /* enum: no (or invalid) license is present for the application */ | |
10674 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 | |
10675 | /* enum: a valid license is present for the application */ | |
10676 | #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 | |
10677 | ||
10678 | ||
10679 | /***********************************/ | |
10680 | /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES | |
10681 | * Query the state of an one or more licensed features. (Note that the actual | |
10682 | * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE | |
10683 | * operation or a reboot of the MC.) Used for V3 licensing (Medford) | |
10684 | */ | |
10685 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 | |
10686 | ||
10687 | #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
10688 | ||
10689 | /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ | |
10690 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 | |
10691 | /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or | |
10692 | * more bits set | |
10693 | */ | |
10694 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 | |
10695 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 | |
10696 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 | |
10697 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 | |
10698 | ||
10699 | /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ | |
10700 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 | |
10701 | /* states of these features - bit set for licensed, clear for not licensed */ | |
10702 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 | |
10703 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 | |
10704 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 | |
10705 | #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 | |
10706 | ||
10707 | ||
512bb06c BH |
10708 | /***********************************/ |
10709 | /* MC_CMD_LICENSED_APP_OP | |
23e202b4 EC |
10710 | * Perform an action for an individual licensed application - not used for V3 |
10711 | * licensing. | |
512bb06c BH |
10712 | */ |
10713 | #define MC_CMD_LICENSED_APP_OP 0xf6 | |
10714 | ||
75122ec8 SS |
10715 | #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL |
10716 | ||
512bb06c BH |
10717 | /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ |
10718 | #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 | |
10719 | #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 | |
10720 | #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) | |
10721 | /* application ID */ | |
10722 | #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 | |
10723 | /* the type of operation requested */ | |
10724 | #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 | |
10725 | /* enum: validate application */ | |
10726 | #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 | |
a9196bb0 EC |
10727 | /* enum: mask application */ |
10728 | #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 | |
512bb06c BH |
10729 | /* arguments specific to this particular operation */ |
10730 | #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 | |
10731 | #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 | |
10732 | #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 | |
10733 | #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 | |
10734 | ||
10735 | /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ | |
10736 | #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 | |
10737 | #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 | |
10738 | #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) | |
10739 | /* result specific to this particular operation */ | |
10740 | #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 | |
10741 | #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 | |
10742 | #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 | |
10743 | #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 | |
10744 | ||
10745 | /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ | |
10746 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 | |
10747 | /* application ID */ | |
10748 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 | |
10749 | /* the type of operation requested */ | |
10750 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 | |
10751 | /* validation challenge */ | |
10752 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 | |
10753 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 | |
10754 | ||
10755 | /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ | |
10756 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 | |
10757 | /* feature expiry (time_t) */ | |
10758 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 | |
10759 | /* validation response */ | |
10760 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 | |
10761 | #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 | |
10762 | ||
a9196bb0 EC |
10763 | /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ |
10764 | #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 | |
10765 | /* application ID */ | |
10766 | #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 | |
10767 | /* the type of operation requested */ | |
10768 | #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 | |
10769 | /* flag */ | |
10770 | #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 | |
10771 | ||
10772 | /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ | |
10773 | #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 | |
10774 | ||
512bb06c | 10775 | |
23e202b4 EC |
10776 | /***********************************/ |
10777 | /* MC_CMD_LICENSED_V3_VALIDATE_APP | |
10778 | * Perform validation for an individual licensed application - V3 licensing | |
10779 | * (Medford) | |
10780 | */ | |
10781 | #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 | |
10782 | ||
10783 | #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
10784 | ||
10785 | /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ | |
10786 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 72 | |
10787 | /* application ID expressed as a single bit mask */ | |
10788 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 0 | |
10789 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 | |
10790 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 0 | |
10791 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 4 | |
10792 | /* challenge for validation */ | |
10793 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 8 | |
10794 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 64 | |
10795 | ||
10796 | /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ | |
10797 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 72 | |
10798 | /* application expiry time */ | |
10799 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 0 | |
10800 | /* application expiry units */ | |
10801 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 4 | |
10802 | /* enum: expiry units are accounting units */ | |
10803 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 | |
10804 | /* enum: expiry units are calendar days */ | |
10805 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 | |
10806 | /* validation response to challenge */ | |
10807 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 8 | |
10808 | #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 64 | |
10809 | ||
10810 | ||
10811 | /***********************************/ | |
10812 | /* MC_CMD_LICENSED_V3_MASK_FEATURES | |
10813 | * Mask features - V3 licensing (Medford) | |
10814 | */ | |
10815 | #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 | |
10816 | ||
10817 | #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
10818 | ||
10819 | /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ | |
10820 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 | |
10821 | /* mask to be applied to features to be changed */ | |
10822 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 | |
10823 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 | |
10824 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 | |
10825 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 | |
10826 | /* whether to turn on or turn off the masked features */ | |
10827 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 | |
10828 | /* enum: turn the features off */ | |
10829 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 | |
10830 | /* enum: turn the features back on */ | |
10831 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 | |
10832 | ||
10833 | /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ | |
10834 | #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 | |
10835 | ||
10836 | ||
512bb06c BH |
10837 | /***********************************/ |
10838 | /* MC_CMD_SET_PORT_SNIFF_CONFIG | |
a9196bb0 | 10839 | * Configure RX port sniffing for the physical port associated with the calling |
512bb06c BH |
10840 | * function. Only a privileged function may change the port sniffing |
10841 | * configuration. A copy of all traffic delivered to the host (non-promiscuous | |
10842 | * mode) or all traffic arriving at the port (promiscuous mode) may be | |
10843 | * delivered to a specific queue, or a set of queues with RSS. | |
10844 | */ | |
10845 | #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 | |
10846 | ||
75122ec8 SS |
10847 | #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
10848 | ||
512bb06c BH |
10849 | /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ |
10850 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 | |
10851 | /* configuration flags */ | |
10852 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 | |
10853 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 | |
10854 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 | |
10855 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 | |
10856 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 | |
10857 | /* receive queue handle (for RSS mode, this is the base queue) */ | |
10858 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 | |
10859 | /* receive mode */ | |
10860 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 | |
10861 | /* enum: receive to just the specified queue */ | |
10862 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 | |
10863 | /* enum: receive to multiple queues using RSS context */ | |
10864 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 | |
10865 | /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note | |
10866 | * that these handles should be considered opaque to the host, although a value | |
10867 | * of 0xFFFFFFFF is guaranteed never to be a valid handle. | |
10868 | */ | |
10869 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 | |
10870 | ||
10871 | /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ | |
10872 | #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 | |
10873 | ||
10874 | ||
10875 | /***********************************/ | |
10876 | /* MC_CMD_GET_PORT_SNIFF_CONFIG | |
a9196bb0 | 10877 | * Obtain the current RX port sniffing configuration for the physical port |
512bb06c BH |
10878 | * associated with the calling function. Only a privileged function may read |
10879 | * the configuration. | |
10880 | */ | |
10881 | #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 | |
10882 | ||
75122ec8 SS |
10883 | #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN |
10884 | ||
512bb06c BH |
10885 | /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ |
10886 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 | |
10887 | ||
10888 | /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ | |
10889 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 | |
10890 | /* configuration flags */ | |
10891 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 | |
10892 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 | |
10893 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 | |
10894 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 | |
10895 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 | |
10896 | /* receiving queue handle (for RSS mode, this is the base queue) */ | |
10897 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 | |
10898 | /* receive mode */ | |
10899 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 | |
10900 | /* enum: receiving to just the specified queue */ | |
10901 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 | |
10902 | /* enum: receiving to multiple queues using RSS context */ | |
10903 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 | |
10904 | /* RSS context (for RX_MODE_RSS) */ | |
10905 | #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 | |
10906 | ||
5297a98d | 10907 | |
a9196bb0 EC |
10908 | /***********************************/ |
10909 | /* MC_CMD_SET_PARSER_DISP_CONFIG | |
10910 | * Change configuration related to the parser-dispatcher subsystem. | |
10911 | */ | |
10912 | #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 | |
10913 | ||
10914 | #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
10915 | ||
10916 | /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ | |
10917 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 | |
10918 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 | |
10919 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) | |
10920 | /* the type of configuration setting to change */ | |
10921 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 | |
10922 | /* enum: Per-TXQ enable for multicast UDP destination lookup for possible | |
10923 | * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) | |
10924 | */ | |
10925 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 | |
10926 | /* enum: Per-v-adaptor enable for suppression of self-transmissions on the | |
10927 | * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single | |
10928 | * boolean.) | |
10929 | */ | |
10930 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 | |
10931 | /* handle for the entity to update: queue handle, EVB port ID, etc. depending | |
10932 | * on the type of configuration setting being changed | |
10933 | */ | |
10934 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 | |
10935 | /* new value: the details depend on the type of configuration setting being | |
10936 | * changed | |
10937 | */ | |
10938 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 | |
10939 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 | |
10940 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 | |
10941 | #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 | |
10942 | ||
10943 | /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ | |
10944 | #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 | |
10945 | ||
10946 | ||
10947 | /***********************************/ | |
10948 | /* MC_CMD_GET_PARSER_DISP_CONFIG | |
10949 | * Read configuration related to the parser-dispatcher subsystem. | |
10950 | */ | |
10951 | #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa | |
10952 | ||
10953 | #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
10954 | ||
10955 | /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ | |
10956 | #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 | |
10957 | /* the type of configuration setting to read */ | |
10958 | #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 | |
10959 | /* Enum values, see field(s): */ | |
10960 | /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ | |
10961 | /* handle for the entity to query: queue handle, EVB port ID, etc. depending on | |
10962 | * the type of configuration setting being read | |
10963 | */ | |
10964 | #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 | |
10965 | ||
10966 | /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ | |
10967 | #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 | |
10968 | #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 | |
10969 | #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) | |
10970 | /* current value: the details depend on the type of configuration setting being | |
10971 | * read | |
10972 | */ | |
10973 | #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 | |
10974 | #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 | |
10975 | #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 | |
10976 | #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 | |
10977 | ||
10978 | ||
10979 | /***********************************/ | |
10980 | /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG | |
10981 | * Configure TX port sniffing for the physical port associated with the calling | |
10982 | * function. Only a privileged function may change the port sniffing | |
10983 | * configuration. A copy of all traffic transmitted through the port may be | |
10984 | * delivered to a specific queue, or a set of queues with RSS. Note that these | |
10985 | * packets are delivered with transmit timestamps in the packet prefix, not | |
10986 | * receive timestamps, so it is likely that the queue(s) will need to be | |
10987 | * dedicated as TX sniff receivers. | |
10988 | */ | |
10989 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb | |
10990 | ||
10991 | #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
10992 | ||
10993 | /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ | |
10994 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 | |
10995 | /* configuration flags */ | |
10996 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 | |
10997 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 | |
10998 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 | |
10999 | /* receive queue handle (for RSS mode, this is the base queue) */ | |
11000 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 | |
11001 | /* receive mode */ | |
11002 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 | |
11003 | /* enum: receive to just the specified queue */ | |
11004 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 | |
11005 | /* enum: receive to multiple queues using RSS context */ | |
11006 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 | |
11007 | /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note | |
11008 | * that these handles should be considered opaque to the host, although a value | |
11009 | * of 0xFFFFFFFF is guaranteed never to be a valid handle. | |
11010 | */ | |
11011 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 | |
11012 | ||
11013 | /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ | |
11014 | #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 | |
11015 | ||
11016 | ||
11017 | /***********************************/ | |
11018 | /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG | |
11019 | * Obtain the current TX port sniffing configuration for the physical port | |
11020 | * associated with the calling function. Only a privileged function may read | |
11021 | * the configuration. | |
11022 | */ | |
11023 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc | |
11024 | ||
11025 | #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11026 | ||
11027 | /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ | |
11028 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 | |
11029 | ||
11030 | /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ | |
11031 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 | |
11032 | /* configuration flags */ | |
11033 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 | |
11034 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 | |
11035 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 | |
11036 | /* receiving queue handle (for RSS mode, this is the base queue) */ | |
11037 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 | |
11038 | /* receive mode */ | |
11039 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 | |
11040 | /* enum: receiving to just the specified queue */ | |
11041 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 | |
11042 | /* enum: receiving to multiple queues using RSS context */ | |
11043 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 | |
11044 | /* RSS context (for RX_MODE_RSS) */ | |
11045 | #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 | |
11046 | ||
11047 | ||
11048 | /***********************************/ | |
11049 | /* MC_CMD_RMON_STATS_RX_ERRORS | |
11050 | * Per queue rx error stats. | |
11051 | */ | |
11052 | #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe | |
11053 | ||
11054 | #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
11055 | ||
11056 | /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ | |
11057 | #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 | |
11058 | /* The rx queue to get stats for. */ | |
11059 | #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 | |
11060 | #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 | |
11061 | #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 | |
11062 | #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 | |
11063 | ||
11064 | /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ | |
11065 | #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 | |
11066 | #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 | |
11067 | #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 | |
11068 | #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 | |
11069 | #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 | |
11070 | ||
11071 | ||
11072 | /***********************************/ | |
11073 | /* MC_CMD_GET_PCIE_RESOURCE_INFO | |
11074 | * Find out about available PCIE resources | |
11075 | */ | |
11076 | #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd | |
11077 | ||
11078 | /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ | |
11079 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 | |
11080 | ||
11081 | /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ | |
11082 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 | |
11083 | /* The maximum number of PFs the device can expose */ | |
11084 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 | |
11085 | /* The maximum number of VFs the device can expose in total */ | |
11086 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 | |
11087 | /* The maximum number of MSI-X vectors the device can provide in total */ | |
11088 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 | |
11089 | /* the number of MSI-X vectors the device will allocate by default to each PF | |
11090 | */ | |
11091 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 | |
11092 | /* the number of MSI-X vectors the device will allocate by default to each VF | |
11093 | */ | |
11094 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 | |
11095 | /* the maximum number of MSI-X vectors the device can allocate to any one PF */ | |
11096 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 | |
11097 | /* the maximum number of MSI-X vectors the device can allocate to any one VF */ | |
11098 | #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 | |
11099 | ||
11100 | ||
11101 | /***********************************/ | |
11102 | /* MC_CMD_GET_PORT_MODES | |
11103 | * Find out about available port modes | |
11104 | */ | |
11105 | #define MC_CMD_GET_PORT_MODES 0xff | |
11106 | ||
11107 | #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
11108 | ||
11109 | /* MC_CMD_GET_PORT_MODES_IN msgrequest */ | |
11110 | #define MC_CMD_GET_PORT_MODES_IN_LEN 0 | |
11111 | ||
11112 | /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ | |
11113 | #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 | |
11114 | /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ | |
11115 | #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 | |
11116 | /* Default (canonical) board mode */ | |
11117 | #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 | |
11118 | /* Current board mode */ | |
11119 | #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 | |
11120 | ||
11121 | ||
11122 | /***********************************/ | |
11123 | /* MC_CMD_READ_ATB | |
11124 | * Sample voltages on the ATB | |
11125 | */ | |
11126 | #define MC_CMD_READ_ATB 0x100 | |
11127 | ||
11128 | #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11129 | ||
11130 | /* MC_CMD_READ_ATB_IN msgrequest */ | |
11131 | #define MC_CMD_READ_ATB_IN_LEN 16 | |
11132 | #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 | |
11133 | #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ | |
11134 | #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ | |
11135 | #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ | |
11136 | #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 | |
11137 | #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 | |
11138 | #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 | |
11139 | ||
11140 | /* MC_CMD_READ_ATB_OUT msgresponse */ | |
11141 | #define MC_CMD_READ_ATB_OUT_LEN 4 | |
11142 | #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 | |
11143 | ||
11144 | ||
11145 | /***********************************/ | |
11146 | /* MC_CMD_GET_WORKAROUNDS | |
11147 | * Read the list of all implemented and all currently enabled workarounds. The | |
11148 | * enums here must correspond with those in MC_CMD_WORKAROUND. | |
11149 | */ | |
11150 | #define MC_CMD_GET_WORKAROUNDS 0x59 | |
11151 | ||
11152 | #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
11153 | ||
11154 | /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ | |
11155 | #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 | |
11156 | /* Each workaround is represented by a single bit according to the enums below. | |
11157 | */ | |
11158 | #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 | |
11159 | #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 | |
11160 | /* enum: Bug 17230 work around. */ | |
11161 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 | |
11162 | /* enum: Bug 35388 work around (unsafe EVQ writes). */ | |
11163 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 | |
11164 | /* enum: Bug35017 workaround (A64 tables must be identity map) */ | |
11165 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 | |
11166 | /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ | |
11167 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 | |
11168 | /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution | |
11169 | * - before adding code that queries this workaround, remember that there's | |
11170 | * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, | |
11171 | * and will hence (incorrectly) report that the bug doesn't exist. | |
11172 | */ | |
11173 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 | |
11174 | /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ | |
11175 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 | |
d29e33d6 BK |
11176 | /* enum: Bug 61265 work around (broken EVQ TMR writes). */ |
11177 | #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 | |
a9196bb0 EC |
11178 | |
11179 | ||
11180 | /***********************************/ | |
11181 | /* MC_CMD_PRIVILEGE_MASK | |
11182 | * Read/set privileges of an arbitrary PCIe function | |
11183 | */ | |
11184 | #define MC_CMD_PRIVILEGE_MASK 0x5a | |
11185 | ||
11186 | #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
11187 | ||
11188 | /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ | |
11189 | #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 | |
11190 | /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF | |
11191 | * 1,3 = 0x00030001 | |
11192 | */ | |
11193 | #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 | |
11194 | #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 | |
11195 | #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 | |
11196 | #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 | |
11197 | #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 | |
11198 | #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ | |
11199 | /* New privilege mask to be set. The mask will only be changed if the MSB is | |
11200 | * set to 1. | |
11201 | */ | |
11202 | #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 | |
11203 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ | |
11204 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ | |
11205 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ | |
11206 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ | |
11207 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ | |
23e202b4 EC |
11208 | /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ |
11209 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 | |
a9196bb0 EC |
11210 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ |
11211 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ | |
11212 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ | |
11213 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ | |
11214 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ | |
23e202b4 EC |
11215 | /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC |
11216 | * adress. | |
11217 | */ | |
11218 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 | |
11219 | /* enum: Privilege that allows a Function to change the MAC address configured | |
11220 | * in its associated vAdapter/vPort. | |
11221 | */ | |
11222 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 | |
11223 | /* enum: Privilege that allows a Function to install filters that specify VLANs | |
11224 | * that are not in the permit list for the associated vPort. This privilege is | |
11225 | * primarily to support ESX where vPorts are created that restrict traffic to | |
11226 | * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. | |
11227 | */ | |
11228 | #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 | |
a9196bb0 EC |
11229 | /* enum: Set this bit to indicate that a new privilege mask is to be set, |
11230 | * otherwise the command will only read the existing mask. | |
11231 | */ | |
11232 | #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 | |
11233 | ||
11234 | /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ | |
11235 | #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 | |
11236 | /* For an admin function, always all the privileges are reported. */ | |
11237 | #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 | |
11238 | ||
11239 | ||
11240 | /***********************************/ | |
11241 | /* MC_CMD_LINK_STATE_MODE | |
11242 | * Read/set link state mode of a VF | |
11243 | */ | |
11244 | #define MC_CMD_LINK_STATE_MODE 0x5c | |
11245 | ||
11246 | #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
11247 | ||
11248 | /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ | |
11249 | #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 | |
11250 | /* The target function to have its link state mode read or set, must be a VF | |
11251 | * e.g. VF 1,3 = 0x00030001 | |
11252 | */ | |
11253 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 | |
11254 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 | |
11255 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 | |
11256 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 | |
11257 | #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 | |
11258 | /* New link state mode to be set */ | |
11259 | #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 | |
11260 | #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ | |
11261 | #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ | |
11262 | #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ | |
11263 | /* enum: Use this value to just read the existing setting without modifying it. | |
11264 | */ | |
11265 | #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff | |
11266 | ||
11267 | /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ | |
11268 | #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 | |
11269 | #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 | |
11270 | ||
11271 | ||
11272 | /***********************************/ | |
11273 | /* MC_CMD_GET_SNAPSHOT_LENGTH | |
11274 | * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH | |
11275 | * parameter to MC_CMD_INIT_RXQ. | |
11276 | */ | |
11277 | #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 | |
11278 | ||
11279 | #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
11280 | ||
11281 | /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ | |
11282 | #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 | |
11283 | ||
11284 | /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ | |
11285 | #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 | |
11286 | /* Minimum acceptable snapshot length. */ | |
11287 | #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 | |
11288 | /* Maximum acceptable snapshot length. */ | |
11289 | #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 | |
11290 | ||
11291 | ||
11292 | /***********************************/ | |
11293 | /* MC_CMD_FUSE_DIAGS | |
11294 | * Additional fuse diagnostics | |
11295 | */ | |
11296 | #define MC_CMD_FUSE_DIAGS 0x102 | |
11297 | ||
11298 | #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11299 | ||
11300 | /* MC_CMD_FUSE_DIAGS_IN msgrequest */ | |
11301 | #define MC_CMD_FUSE_DIAGS_IN_LEN 0 | |
11302 | ||
11303 | /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ | |
11304 | #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 | |
11305 | /* Total number of mismatched bits between pairs in area 0 */ | |
11306 | #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 | |
11307 | /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ | |
11308 | #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 | |
11309 | /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ | |
11310 | #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 | |
11311 | /* Checksum of data after logical OR of pairs in area 0 */ | |
11312 | #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 | |
11313 | /* Total number of mismatched bits between pairs in area 1 */ | |
11314 | #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 | |
11315 | /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ | |
11316 | #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 | |
11317 | /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ | |
11318 | #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 | |
11319 | /* Checksum of data after logical OR of pairs in area 1 */ | |
11320 | #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 | |
11321 | /* Total number of mismatched bits between pairs in area 2 */ | |
11322 | #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 | |
11323 | /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ | |
11324 | #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 | |
11325 | /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ | |
11326 | #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 | |
11327 | /* Checksum of data after logical OR of pairs in area 2 */ | |
11328 | #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 | |
11329 | ||
11330 | ||
11331 | /***********************************/ | |
11332 | /* MC_CMD_PRIVILEGE_MODIFY | |
11333 | * Modify the privileges of a set of PCIe functions. Note that this operation | |
11334 | * only effects non-admin functions unless the admin privilege itself is | |
11335 | * included in one of the masks provided. | |
11336 | */ | |
11337 | #define MC_CMD_PRIVILEGE_MODIFY 0x60 | |
11338 | ||
11339 | #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11340 | ||
11341 | /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ | |
11342 | #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 | |
11343 | /* The groups of functions to have their privilege masks modified. */ | |
11344 | #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 | |
11345 | #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ | |
11346 | #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ | |
11347 | #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ | |
11348 | #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ | |
11349 | #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ | |
11350 | #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ | |
11351 | /* For VFS_OF_PF specify the PF, for ONE specify the target function */ | |
11352 | #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 | |
11353 | #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 | |
11354 | #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 | |
11355 | #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 | |
11356 | #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 | |
11357 | /* Privileges to be added to the target functions. For privilege definitions | |
11358 | * refer to the command MC_CMD_PRIVILEGE_MASK | |
11359 | */ | |
11360 | #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 | |
11361 | /* Privileges to be removed from the target functions. For privilege | |
11362 | * definitions refer to the command MC_CMD_PRIVILEGE_MASK | |
11363 | */ | |
11364 | #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 | |
11365 | ||
11366 | /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ | |
11367 | #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 | |
11368 | ||
11369 | ||
11370 | /***********************************/ | |
11371 | /* MC_CMD_XPM_READ_BYTES | |
11372 | * Read XPM memory | |
11373 | */ | |
11374 | #define MC_CMD_XPM_READ_BYTES 0x103 | |
11375 | ||
11376 | #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11377 | ||
11378 | /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ | |
11379 | #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 | |
11380 | /* Start address (byte) */ | |
11381 | #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 | |
11382 | /* Count (bytes) */ | |
11383 | #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 | |
11384 | ||
11385 | /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ | |
11386 | #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 | |
11387 | #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 | |
11388 | #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) | |
11389 | /* Data */ | |
11390 | #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 | |
11391 | #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 | |
11392 | #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 | |
11393 | #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 | |
11394 | ||
11395 | ||
11396 | /***********************************/ | |
11397 | /* MC_CMD_XPM_WRITE_BYTES | |
11398 | * Write XPM memory | |
11399 | */ | |
11400 | #define MC_CMD_XPM_WRITE_BYTES 0x104 | |
11401 | ||
11402 | #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11403 | ||
11404 | /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ | |
11405 | #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 | |
11406 | #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 | |
11407 | #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) | |
11408 | /* Start address (byte) */ | |
11409 | #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 | |
11410 | /* Count (bytes) */ | |
11411 | #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 | |
11412 | /* Data */ | |
11413 | #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 | |
11414 | #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 | |
11415 | #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 | |
11416 | #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 | |
11417 | ||
11418 | /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ | |
11419 | #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 | |
11420 | ||
11421 | ||
11422 | /***********************************/ | |
11423 | /* MC_CMD_XPM_READ_SECTOR | |
11424 | * Read XPM sector | |
11425 | */ | |
11426 | #define MC_CMD_XPM_READ_SECTOR 0x105 | |
11427 | ||
11428 | #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11429 | ||
11430 | /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ | |
11431 | #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 | |
11432 | /* Sector index */ | |
11433 | #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 | |
11434 | /* Sector size */ | |
11435 | #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 | |
11436 | ||
11437 | /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ | |
11438 | #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 | |
11439 | #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 | |
11440 | #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) | |
11441 | /* Sector type */ | |
11442 | #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 | |
11443 | #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ | |
11444 | #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ | |
11445 | #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ | |
11446 | #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ | |
11447 | /* Sector data */ | |
11448 | #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 | |
11449 | #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 | |
11450 | #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 | |
11451 | #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 | |
11452 | ||
11453 | ||
11454 | /***********************************/ | |
11455 | /* MC_CMD_XPM_WRITE_SECTOR | |
11456 | * Write XPM sector | |
11457 | */ | |
11458 | #define MC_CMD_XPM_WRITE_SECTOR 0x106 | |
11459 | ||
11460 | #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11461 | ||
11462 | /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ | |
11463 | #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 | |
11464 | #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 | |
11465 | #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) | |
11466 | /* If writing fails due to an uncorrectable error, try up to RETRIES following | |
11467 | * sectors (or until no more space available). If 0, only one write attempt is | |
11468 | * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair | |
11469 | * mechanism. | |
11470 | */ | |
11471 | #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 | |
11472 | #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 | |
11473 | #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 | |
11474 | #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 | |
11475 | /* Sector type */ | |
11476 | #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 | |
11477 | /* Enum values, see field(s): */ | |
23e202b4 | 11478 | /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ |
a9196bb0 EC |
11479 | /* Sector size */ |
11480 | #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 | |
11481 | /* Sector data */ | |
11482 | #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 | |
11483 | #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 | |
11484 | #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 | |
11485 | #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 | |
11486 | ||
11487 | /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ | |
11488 | #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 | |
11489 | /* New sector index */ | |
11490 | #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 | |
11491 | ||
11492 | ||
11493 | /***********************************/ | |
11494 | /* MC_CMD_XPM_INVALIDATE_SECTOR | |
11495 | * Invalidate XPM sector | |
11496 | */ | |
11497 | #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 | |
11498 | ||
11499 | #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11500 | ||
11501 | /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ | |
11502 | #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 | |
11503 | /* Sector index */ | |
11504 | #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 | |
11505 | ||
11506 | /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ | |
11507 | #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 | |
11508 | ||
11509 | ||
11510 | /***********************************/ | |
11511 | /* MC_CMD_XPM_BLANK_CHECK | |
11512 | * Blank-check XPM memory and report bad locations | |
11513 | */ | |
11514 | #define MC_CMD_XPM_BLANK_CHECK 0x108 | |
11515 | ||
11516 | #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11517 | ||
11518 | /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ | |
11519 | #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 | |
11520 | /* Start address (byte) */ | |
11521 | #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 | |
11522 | /* Count (bytes) */ | |
11523 | #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 | |
11524 | ||
11525 | /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ | |
11526 | #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 | |
11527 | #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 | |
11528 | #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) | |
11529 | /* Total number of bad (non-blank) locations */ | |
11530 | #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 | |
11531 | /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit | |
11532 | * into MCDI response) | |
11533 | */ | |
11534 | #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 | |
11535 | #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 | |
11536 | #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 | |
11537 | #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 | |
11538 | ||
11539 | ||
11540 | /***********************************/ | |
11541 | /* MC_CMD_XPM_REPAIR | |
11542 | * Blank-check and repair XPM memory | |
11543 | */ | |
11544 | #define MC_CMD_XPM_REPAIR 0x109 | |
11545 | ||
11546 | #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11547 | ||
11548 | /* MC_CMD_XPM_REPAIR_IN msgrequest */ | |
11549 | #define MC_CMD_XPM_REPAIR_IN_LEN 8 | |
11550 | /* Start address (byte) */ | |
11551 | #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 | |
11552 | /* Count (bytes) */ | |
11553 | #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 | |
11554 | ||
11555 | /* MC_CMD_XPM_REPAIR_OUT msgresponse */ | |
11556 | #define MC_CMD_XPM_REPAIR_OUT_LEN 0 | |
11557 | ||
11558 | ||
11559 | /***********************************/ | |
11560 | /* MC_CMD_XPM_DECODER_TEST | |
11561 | * Test XPM memory address decoders for gross manufacturing defects. Can only | |
11562 | * be performed on an unprogrammed part. | |
11563 | */ | |
11564 | #define MC_CMD_XPM_DECODER_TEST 0x10a | |
11565 | ||
11566 | #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11567 | ||
11568 | /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ | |
11569 | #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 | |
11570 | ||
11571 | /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ | |
11572 | #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 | |
11573 | ||
11574 | ||
11575 | /***********************************/ | |
11576 | /* MC_CMD_XPM_WRITE_TEST | |
11577 | * XPM memory write test. Test XPM write logic for gross manufacturing defects | |
11578 | * by writing to a dedicated test row. There are 16 locations in the test row | |
11579 | * and the test can only be performed on locations that have not been | |
11580 | * previously used (i.e. can be run at most 16 times). The test will pick the | |
11581 | * first available location to use, or fail with ENOSPC if none left. | |
11582 | */ | |
11583 | #define MC_CMD_XPM_WRITE_TEST 0x10b | |
11584 | ||
11585 | #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11586 | ||
11587 | /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ | |
11588 | #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 | |
11589 | ||
11590 | /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ | |
11591 | #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 | |
11592 | ||
11593 | ||
23e202b4 EC |
11594 | /***********************************/ |
11595 | /* MC_CMD_EXEC_SIGNED | |
11596 | * Check the CMAC of the contents of IMEM and DMEM against the value supplied | |
11597 | * and if correct begin execution from the start of IMEM. The caller supplies a | |
11598 | * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC | |
11599 | * computation runs from the start of IMEM, and from the start of DMEM + 16k, | |
11600 | * to match flash booting. The command will respond with EINVAL if the CMAC | |
11601 | * does match, otherwise it will respond with success before it jumps to IMEM. | |
11602 | */ | |
11603 | #define MC_CMD_EXEC_SIGNED 0x10c | |
11604 | ||
11605 | #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11606 | ||
11607 | /* MC_CMD_EXEC_SIGNED_IN msgrequest */ | |
11608 | #define MC_CMD_EXEC_SIGNED_IN_LEN 28 | |
11609 | /* the length of code to include in the CMAC */ | |
11610 | #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 | |
11611 | /* the length of date to include in the CMAC */ | |
11612 | #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 | |
11613 | /* the XPM sector containing the key to use */ | |
11614 | #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 | |
11615 | /* the expected CMAC value */ | |
11616 | #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 | |
11617 | #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 | |
11618 | ||
11619 | /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ | |
11620 | #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 | |
11621 | ||
11622 | ||
11623 | /***********************************/ | |
11624 | /* MC_CMD_PREPARE_SIGNED | |
11625 | * Prepare to upload a signed image. This will scrub the specified length of | |
11626 | * the data region, which must be at least as large as the DATALEN supplied to | |
11627 | * MC_CMD_EXEC_SIGNED. | |
11628 | */ | |
11629 | #define MC_CMD_PREPARE_SIGNED 0x10d | |
11630 | ||
11631 | #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11632 | ||
11633 | /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ | |
11634 | #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 | |
11635 | /* the length of data area to clear */ | |
11636 | #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 | |
11637 | ||
11638 | /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ | |
11639 | #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 | |
11640 | ||
11641 | ||
11642 | /***********************************/ | |
11643 | /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS | |
11644 | * Configure UDP ports for tunnel encapsulation hardware acceleration. The | |
11645 | * parser-dispatcher will attempt to parse traffic on these ports as tunnel | |
11646 | * encapsulation PDUs and filter them using the tunnel encapsulation filter | |
11647 | * chain rather than the standard filter chain. Note that this command can | |
11648 | * cause all functions to see a reset. (Available on Medford only.) | |
11649 | */ | |
11650 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 | |
11651 | ||
11652 | #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11653 | ||
11654 | /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ | |
11655 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 | |
11656 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 | |
11657 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) | |
11658 | /* Flags */ | |
11659 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 | |
11660 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 | |
11661 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 | |
11662 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 | |
11663 | /* The number of entries in the ENTRIES array */ | |
11664 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 | |
11665 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 | |
11666 | /* Entries defining the UDP port to protocol mapping, each laid out as a | |
11667 | * TUNNEL_ENCAP_UDP_PORT_ENTRY | |
11668 | */ | |
11669 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 | |
11670 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 | |
11671 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 | |
11672 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 | |
11673 | ||
11674 | /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ | |
11675 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 | |
11676 | /* Flags */ | |
11677 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 | |
11678 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 | |
11679 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 | |
11680 | #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 | |
11681 | ||
11682 | ||
11683 | /***********************************/ | |
11684 | /* MC_CMD_RX_BALANCING | |
11685 | * Configure a port upconverter to distribute the packets on both RX engines. | |
11686 | * Packets are distributed based on a table with the destination vFIFO. The | |
11687 | * index of the table is a hash of source and destination of IPV4 and VLAN | |
11688 | * priority. | |
11689 | */ | |
11690 | #define MC_CMD_RX_BALANCING 0x118 | |
11691 | ||
11692 | #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN | |
11693 | ||
11694 | /* MC_CMD_RX_BALANCING_IN msgrequest */ | |
d29e33d6 | 11695 | #define MC_CMD_RX_BALANCING_IN_LEN 16 |
23e202b4 EC |
11696 | /* The RX port whose upconverter table will be modified */ |
11697 | #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 | |
23e202b4 | 11698 | /* The VLAN priority associated to the table index and vFIFO */ |
d29e33d6 | 11699 | #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 |
23e202b4 | 11700 | /* The resulting bit of SRC^DST for indexing the table */ |
d29e33d6 | 11701 | #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 |
23e202b4 | 11702 | /* The RX engine to which the vFIFO in the table entry will point to */ |
d29e33d6 | 11703 | #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 |
23e202b4 EC |
11704 | |
11705 | /* MC_CMD_RX_BALANCING_OUT msgresponse */ | |
11706 | #define MC_CMD_RX_BALANCING_OUT_LEN 0 | |
11707 | ||
d29e33d6 BK |
11708 | /***********************************/ |
11709 | /* MC_CMD_SET_EVQ_TMR | |
11710 | * Update the timer load, timer reload and timer mode values for a given EVQ. | |
11711 | * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will | |
11712 | * be rounded up to the granularity supported by the hardware, then truncated | |
11713 | * to the range supported by the hardware. The resulting value after the | |
11714 | * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS | |
11715 | * and TMR_RELOAD_ACT_NS). | |
11716 | */ | |
11717 | #define MC_CMD_SET_EVQ_TMR 0x120 | |
11718 | ||
11719 | #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
11720 | ||
11721 | /* MC_CMD_SET_EVQ_TMR_IN msgrequest */ | |
11722 | #define MC_CMD_SET_EVQ_TMR_IN_LEN 16 | |
11723 | /* Function-relative queue instance */ | |
11724 | #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 | |
11725 | /* Requested value for timer load (in nanoseconds) */ | |
11726 | #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 | |
11727 | /* Requested value for timer reload (in nanoseconds) */ | |
11728 | #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 | |
11729 | /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ | |
11730 | #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 | |
11731 | #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ | |
11732 | #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ | |
11733 | #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ | |
11734 | #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ | |
11735 | ||
11736 | /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ | |
11737 | #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 | |
11738 | /* Actual value for timer load (in nanoseconds) */ | |
11739 | #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 | |
11740 | /* Actual value for timer reload (in nanoseconds) */ | |
11741 | #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 | |
11742 | ||
11743 | ||
11744 | /***********************************/ | |
11745 | /* MC_CMD_GET_EVQ_TMR_PROPERTIES | |
11746 | * Query properties about the event queue timers. | |
11747 | */ | |
11748 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 | |
11749 | ||
11750 | #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL | |
11751 | ||
11752 | /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ | |
11753 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 | |
11754 | ||
11755 | /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ | |
11756 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 | |
11757 | /* Reserved for future use. */ | |
11758 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 | |
11759 | /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in | |
11760 | * nanoseconds) for each increment of the timer load/reload count. The | |
11761 | * requested duration of a timer is this value multiplied by the timer | |
11762 | * load/reload count. | |
11763 | */ | |
11764 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 | |
11765 | /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value | |
11766 | * allowed for timer load/reload counts. | |
11767 | */ | |
11768 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 | |
11769 | /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a | |
11770 | * multiple of this step size will be rounded in an implementation defined | |
11771 | * manner. | |
11772 | */ | |
11773 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 | |
11774 | /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only | |
11775 | * meaningful if MC_CMD_SET_EVQ_TMR is implemented. | |
11776 | */ | |
11777 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 | |
11778 | /* Timer durations requested via MCDI that are not a multiple of this step size | |
11779 | * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. | |
11780 | */ | |
11781 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 | |
11782 | /* For timers updated using the bug35388 workaround, this is the time interval | |
11783 | * (in nanoseconds) for each increment of the timer load/reload count. The | |
11784 | * requested duration of a timer is this value multiplied by the timer | |
11785 | * load/reload count. This field is only meaningful if the bug35388 workaround | |
11786 | * is enabled. | |
11787 | */ | |
11788 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 | |
11789 | /* For timers updated using the bug35388 workaround, this is the maximum value | |
11790 | * allowed for timer load/reload counts. This field is only meaningful if the | |
11791 | * bug35388 workaround is enabled. | |
11792 | */ | |
11793 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 | |
11794 | /* For timers updated using the bug35388 workaround, timer load/reload counts | |
11795 | * not a multiple of this step size will be rounded in an implementation | |
11796 | * defined manner. This field is only meaningful if the bug35388 workaround is | |
11797 | * enabled. | |
11798 | */ | |
11799 | #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 | |
23e202b4 | 11800 | |
f0d37f42 | 11801 | #endif /* MCDI_PCOL_H */ |