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Merge remote-tracking branch 'mmc-uh/next'
[deliverable/linux.git] / drivers / net / ethernet / sfc / siena.c
CommitLineData
afd4aea0 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
afd4aea0 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2006-2013 Solarflare Communications Inc.
afd4aea0
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
5a0e3ad6 15#include <linux/slab.h>
d614cfbc 16#include <linux/random.h>
afd4aea0
BH		 17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
8b8a95a1 21#include "farch_regs.h"
afd4aea0
BH		 22#include "io.h"
23#include "phy.h"
24#include "workarounds.h"
25#include "mcdi.h"
26#include "mcdi_pcol.h"
d4f2cecc 27#include "selftest.h"
7fa8d547 28#include "siena_sriov.h"
afd4aea0
BH		 29
30/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32static void siena_init_wol(struct efx_nic *efx);
33
34
35static void siena_push_irq_moderation(struct efx_channel *channel)
36{
539de7c5 37 struct efx_nic *efx = channel->efx;
afd4aea0
BH		 38 efx_dword_t timer_cmd;
39
539de7c5
BK		 40 if (channel->irq_moderation_us) {
41 unsigned int ticks;
42
43 ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us);
afd4aea0
BH		 44 EFX_POPULATE_DWORD_2(timer_cmd,
45 FRF_CZ_TC_TIMER_MODE,
46 FFE_CZ_TIMER_MODE_INT_HLDOFF,
47 FRF_CZ_TC_TIMER_VAL,
539de7c5
BK		 48 ticks - 1);
49 } else {
afd4aea0
BH		 50 EFX_POPULATE_DWORD_2(timer_cmd,
51 FRF_CZ_TC_TIMER_MODE,
52 FFE_CZ_TIMER_MODE_DIS,
53 FRF_CZ_TC_TIMER_VAL, 0);
539de7c5 54 }
afd4aea0
BH		 55 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
56 channel->channel);
57}
58
d5e8cc6c
BH		 59void siena_prepare_flush(struct efx_nic *efx)
60{
61 if (efx->fc_disable++ == 0)
62 efx_mcdi_set_mac(efx);
63}
64
65void siena_finish_flush(struct efx_nic *efx)
66{
67 if (--efx->fc_disable == 0)
68 efx_mcdi_set_mac(efx);
69}
70
86094f7f 71static const struct efx_farch_register_test siena_register_tests[] = {
afd4aea0 72 { FR_AZ_ADR_REGION,
4cddca54 73 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
afd4aea0
BH		 74 { FR_CZ_USR_EV_CFG,
75 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
76 { FR_AZ_RX_CFG,
77 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
78 { FR_AZ_TX_CFG,
79 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
80 { FR_AZ_TX_RESERVED,
81 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
82 { FR_AZ_SRM_TX_DC_CFG,
83 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
84 { FR_AZ_RX_DC_CFG,
85 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
86 { FR_AZ_RX_DC_PF_WM,
87 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
88 { FR_BZ_DP_CTRL,
89 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
90 { FR_BZ_RX_RSS_TKEY,
91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
92 { FR_CZ_RX_RSS_IPV6_REG1,
93 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
94 { FR_CZ_RX_RSS_IPV6_REG2,
95 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
96 { FR_CZ_RX_RSS_IPV6_REG3,
97 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
98};
99
d4f2cecc 100static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
afd4aea0 101{
ef492f11 102 enum reset_type reset_method = RESET_TYPE_ALL;
d4f2cecc
BH		 103 int rc, rc2;
104
105 efx_reset_down(efx, reset_method);
106
107 /* Reset the chip immediately so that it is completely
108 * quiescent regardless of what any VF driver does.
109 */
6bff861d 110 rc = efx_mcdi_reset(efx, reset_method);
d4f2cecc
BH		 111 if (rc)
112 goto out;
113
114 tests->registers =
86094f7f
BH		 115 efx_farch_test_registers(efx, siena_register_tests,
116 ARRAY_SIZE(siena_register_tests))
d4f2cecc
BH		 117 ? -1 : 1;
118
6bff861d 119 rc = efx_mcdi_reset(efx, reset_method);
d4f2cecc
BH		 120out:
121 rc2 = efx_reset_up(efx, reset_method, rc == 0);
122 return rc ? rc : rc2;
afd4aea0
BH		 123}
124
9ec06595
DP		 125/**************************************************************************
126 *
127 * PTP
128 *
129 **************************************************************************
130 */
131
132static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
133{
134 _efx_writed(efx, cpu_to_le32(host_time),
135 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
136}
137
138static int siena_ptp_set_ts_config(struct efx_nic *efx,
139 struct hwtstamp_config *init)
140{
141 int rc;
142
143 switch (init->rx_filter) {
144 case HWTSTAMP_FILTER_NONE:
145 /* if TX timestamping is still requested then leave PTP on */
146 return efx_ptp_change_mode(efx,
147 init->tx_type != HWTSTAMP_TX_OFF,
148 efx_ptp_get_mode(efx));
149 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
150 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
151 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
152 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
153 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
154 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
155 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
156 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
157 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
158 rc = efx_ptp_change_mode(efx, true,
159 MC_CMD_PTP_MODE_V2_ENHANCED);
160 /* bug 33070 - old versions of the firmware do not support the
161 * improved UUID filtering option. Similarly old versions of the
162 * application do not expect it to be enabled. If the firmware
163 * does not accept the enhanced mode, fall back to the standard
164 * PTP v2 UUID filtering. */
165 if (rc != 0)
166 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
167 return rc;
168 default:
169 return -ERANGE;
170 }
171}
172
afd4aea0
BH		 173/**************************************************************************
174 *
175 * Device reset
176 *
177 **************************************************************************
178 */
179
0e2a9c7c
BH		 180static int siena_map_reset_flags(u32 *flags)
181{
182 enum {
183 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
184 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
185 ETH_RESET_PHY),
186 SIENA_RESET_MC = (SIENA_RESET_PORT |
187 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
188 };
189
190 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
191 *flags &= ~SIENA_RESET_MC;
192 return RESET_TYPE_WORLD;
193 }
194
195 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
196 *flags &= ~SIENA_RESET_PORT;
197 return RESET_TYPE_ALL;
198 }
199
200 /* no invisible reset implemented */
201
202 return -EINVAL;
203}
204
626950db
AR		 205#ifdef CONFIG_EEH
206/* When a PCI device is isolated from the bus, a subsequent MMIO read is
207 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
208 * was written to minimise MMIO read (for latency) then a periodic call to check
209 * the EEH status of the device is required so that device recovery can happen
210 * in a timely fashion.
211 */
212static void siena_monitor(struct efx_nic *efx)
213{
12a89dba 214 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
626950db
AR		 215
216 eeh_dev_check_failure(eehdev);
217}
218#endif
219
afd4aea0
BH		 220static int siena_probe_nvconfig(struct efx_nic *efx)
221{
cc180b69
BH		 222 u32 caps = 0;
223 int rc;
224
225 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
226
227 efx->timer_quantum_ns =
228 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
229 3072 : 6144; /* 768 cycles */
d95e329a
BK		 230 efx->timer_max_ns = efx->type->timer_period_max *
231 efx->timer_quantum_ns;
232
cc180b69 233 return rc;
afd4aea0
BH		 234}
235
c15eed22 236static int siena_dimension_resources(struct efx_nic *efx)
28e47c49
BH		 237{
238 /* Each port has a small block of internal SRAM dedicated to
239 * the buffer table and descriptor caches. In theory we can
240 * map both blocks to one port, but we don't.
241 */
86094f7f 242 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
c15eed22 243 return 0;
28e47c49
BH		 244}
245
b105798f
BH		 246static unsigned int siena_mem_map_size(struct efx_nic *efx)
247{
248 return FR_CZ_MC_TREG_SMEM +
249 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
250}
251
afd4aea0
BH		 252static int siena_probe_nic(struct efx_nic *efx)
253{
254 struct siena_nic_data *nic_data;
d42a8f46 255 efx_oword_t reg;
afd4aea0
BH		 256 int rc;
257
258 /* Allocate storage for hardware specific data */
259 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
260 if (!nic_data)
261 return -ENOMEM;
2dc313ec 262 nic_data->efx = efx;
afd4aea0
BH		 263 efx->nic_data = nic_data;
264
86094f7f 265 if (efx_farch_fpga_ver(efx) != 0) {
62776d03
BH		 266 netif_err(efx, probe, efx->net_dev,
267 "Siena FPGA not supported\n");
afd4aea0
BH		 268 rc = -ENODEV;
269 goto fail1;
270 }
271
b105798f 272 efx->max_channels = EFX_MAX_CHANNELS;
b0fbdae1 273 efx->max_tx_channels = EFX_MAX_CHANNELS;
b105798f 274
d42a8f46 275 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
6602041b 276 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
d42a8f46 277
f073dde0 278 rc = efx_mcdi_init(efx);
afd4aea0 279 if (rc)
86c432ca 280 goto fail1;
afd4aea0 281
afd4aea0 282 /* Now we can reset the NIC */
6bff861d 283 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
afd4aea0 284 if (rc) {
62776d03 285 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
afd4aea0
BH		 286 goto fail3;
287 }
288
289 siena_init_wol(efx);
290
291 /* Allocate memory for INT_KER */
0d19a540
BH		 292 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
293 GFP_KERNEL);
afd4aea0
BH		 294 if (rc)
295 goto fail4;
296 BUG_ON(efx->irq_status.dma_addr & 0x0f);
297
62776d03
BH		 298 netif_dbg(efx, probe, efx->net_dev,
299 "INT_KER at %llx (virt %p phys %llx)\n",
300 (unsigned long long)efx->irq_status.dma_addr,
301 efx->irq_status.addr,
302 (unsigned long long)virt_to_phys(efx->irq_status.addr));
afd4aea0
BH		 303
304 /* Read in the non-volatile configuration */
305 rc = siena_probe_nvconfig(efx);
306 if (rc == -EINVAL) {
62776d03
BH		 307 netif_err(efx, probe, efx->net_dev,
308 "NVRAM is invalid therefore using defaults\n");
afd4aea0
BH		 309 efx->phy_type = PHY_TYPE_NONE;
310 efx->mdio.prtad = MDIO_PRTAD_NONE;
311 } else if (rc) {
312 goto fail5;
313 }
314
55c5e0f8
BH		 315 rc = efx_mcdi_mon_probe(efx);
316 if (rc)
317 goto fail5;
318
7fa8d547 319#ifdef CONFIG_SFC_SRIOV
327c685e 320 efx_siena_sriov_probe(efx);
7fa8d547 321#endif
ac36baf8 322 efx_ptp_defer_probe_with_channel(efx);
cd2d5b52 323
afd4aea0
BH		 324 return 0;
325
326fail5:
327 efx_nic_free_buffer(efx, &efx->irq_status);
328fail4:
329fail3:
f3ad5003 330 efx_mcdi_fini(efx);
afd4aea0
BH		 331fail1:
332 kfree(efx->nic_data);
333 return rc;
334}
335
267c0157
JC		 336static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
337 const u32 *rx_indir_table)
d43050c0
AR		 338{
339 efx_oword_t temp;
340
341 /* Set hash key for IPv4 */
342 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
343 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
344
345 /* Enable IPv6 RSS */
346 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
347 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
348 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
349 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
350 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
351 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
352 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
353 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
354 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
355 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
356 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
357 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
358
267c0157
JC		 359 memcpy(efx->rx_indir_table, rx_indir_table,
360 sizeof(efx->rx_indir_table));
d43050c0 361 efx_farch_rx_push_indir_table(efx);
267c0157
JC		 362
363 return 0;
d43050c0
AR		 364}
365
afd4aea0
BH		 366/* This call performs hardware-specific global initialisation, such as
367 * defining the descriptor cache sizes and number of RSS channels.
368 * It does not set up any buffers, descriptor rings or event queues.
369 */
370static int siena_init_nic(struct efx_nic *efx)
371{
372 efx_oword_t temp;
373 int rc;
374
375 /* Recover from a failed assertion post-reset */
376 rc = efx_mcdi_handle_assertion(efx);
377 if (rc)
378 return rc;
379
380 /* Squash TX of packets of 16 bytes or less */
381 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
382 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
383 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
384
385 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
386 * descriptors (which is bad).
387 */
388 efx_reado(efx, &temp, FR_AZ_TX_CFG);
389 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
390 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
391 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
392
393 efx_reado(efx, &temp, FR_AZ_RX_CFG);
394 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
395 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
477e54eb
BH		 396 /* Enable hash insertion. This is broken for the 'Falcon' hash
397 * if IPv6 hashing is also enabled, so also select Toeplitz
398 * TCP/IPv4 and IPv4 hashes. */
399 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
400 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
401 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
85740cdf
BH		 402 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
403 EFX_RX_USR_BUF_SIZE >> 5);
afd4aea0
BH		 404 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
405
267c0157 406 siena_rx_push_rss_config(efx, false, efx->rx_indir_table);
d614cfbc 407
afd4aea0
BH		 408 /* Enable event logging */
409 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
410 if (rc)
411 return rc;
412
413 /* Set destination of both TX and RX Flush events */
414 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
415 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
416
417 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
418 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
419
86094f7f 420 efx_farch_init_common(efx);
afd4aea0
BH		 421 return 0;
422}
423
424static void siena_remove_nic(struct efx_nic *efx)
425{
55c5e0f8
BH		 426 efx_mcdi_mon_remove(efx);
427
afd4aea0
BH		 428 efx_nic_free_buffer(efx, &efx->irq_status);
429
6bff861d 430 efx_mcdi_reset(efx, RESET_TYPE_ALL);
afd4aea0 431
4c75b43a 432 efx_mcdi_fini(efx);
afd4aea0
BH		 433
434 /* Tear down the private nic state */
86c432ca 435 kfree(efx->nic_data);
afd4aea0
BH		 436 efx->nic_data = NULL;
437}
438
cd0ecc9a
BH		 439#define SIENA_DMA_STAT(ext_name, mcdi_name) \
440 [SIENA_STAT_ ## ext_name] = \
441 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
442#define SIENA_OTHER_STAT(ext_name) \
443 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 444#define GENERIC_SW_STAT(ext_name) \
445 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
cd0ecc9a
BH		 446
447static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
448 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
449 SIENA_OTHER_STAT(tx_good_bytes),
450 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
451 SIENA_DMA_STAT(tx_packets, TX_PKTS),
452 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
453 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
454 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
455 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
456 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
457 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
458 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
459 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
460 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
461 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
462 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
463 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
464 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
465 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
466 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
467 SIENA_OTHER_STAT(tx_collision),
468 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
469 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
470 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
471 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
472 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
473 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
474 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
475 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
476 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
477 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
478 SIENA_OTHER_STAT(rx_good_bytes),
479 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
480 SIENA_DMA_STAT(rx_packets, RX_PKTS),
481 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
482 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
483 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
484 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
485 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
486 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
487 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
488 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
489 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
490 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
491 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
492 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
493 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
494 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
495 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
496 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
497 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
498 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
499 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
500 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
501 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
502 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
503 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
504 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
e4d112e4
EC		 505 GENERIC_SW_STAT(rx_nodesc_trunc),
506 GENERIC_SW_STAT(rx_noskb_drops),
cd0ecc9a
BH		 507};
508static const unsigned long siena_stat_mask[] = {
509 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
510};
511
512static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
513{
514 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
515 siena_stat_mask, names);
516}
517
afd4aea0
BH		 518static int siena_try_update_nic_stats(struct efx_nic *efx)
519{
cd0ecc9a
BH		 520 struct siena_nic_data *nic_data = efx->nic_data;
521 u64 *stats = nic_data->stats;
a659b2a9 522 __le64 *dma_stats;
a659b2a9 523 __le64 generation_start, generation_end;
afd4aea0 524
43d620c8 525 dma_stats = efx->stats_buffer.addr;
afd4aea0
BH		 526
527 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
43f775b2 528 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
afd4aea0
BH		 529 return 0;
530 rmb();
cd0ecc9a
BH		 531 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
532 stats, efx->stats_buffer.addr, false);
afd4aea0
BH		 533 rmb();
534 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
535 if (generation_end != generation_start)
536 return -EAGAIN;
537
cd0ecc9a 538 /* Update derived statistics */
f8f3b5ae
JC		 539 efx_nic_fix_nodesc_drop_stat(efx,
540 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
cd0ecc9a
BH		 541 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
542 stats[SIENA_STAT_tx_bytes] -
543 stats[SIENA_STAT_tx_bad_bytes]);
544 stats[SIENA_STAT_tx_collision] =
545 stats[SIENA_STAT_tx_single_collision] +
546 stats[SIENA_STAT_tx_multiple_collision] +
547 stats[SIENA_STAT_tx_excessive_collision] +
548 stats[SIENA_STAT_tx_late_collision];
549 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
550 stats[SIENA_STAT_rx_bytes] -
551 stats[SIENA_STAT_rx_bad_bytes]);
e4d112e4 552 efx_update_sw_stats(efx, stats);
afd4aea0
BH		 553 return 0;
554}
555
cd0ecc9a
BH		 556static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
557 struct rtnl_link_stats64 *core_stats)
afd4aea0 558{
cd0ecc9a
BH		 559 struct siena_nic_data *nic_data = efx->nic_data;
560 u64 *stats = nic_data->stats;
aabc5649
BH		 561 int retry;
562
563 /* If we're unlucky enough to read statistics wduring the DMA, wait
564 * up to 10ms for it to finish (typically takes <500us) */
565 for (retry = 0; retry < 100; ++retry) {
566 if (siena_try_update_nic_stats(efx) == 0)
cd0ecc9a 567 break;
aabc5649
BH		 568 udelay(100);
569 }
570
cd0ecc9a
BH		 571 if (full_stats)
572 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
573
574 if (core_stats) {
575 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
576 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
577 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
578 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
e4d112e4
EC		 579 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
580 stats[GENERIC_STAT_rx_nodesc_trunc] +
581 stats[GENERIC_STAT_rx_noskb_drops];
cd0ecc9a
BH		 582 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
583 core_stats->collisions = stats[SIENA_STAT_tx_collision];
584 core_stats->rx_length_errors =
585 stats[SIENA_STAT_rx_gtjumbo] +
586 stats[SIENA_STAT_rx_length_error];
587 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
588 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
589 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
590 core_stats->tx_window_errors =
591 stats[SIENA_STAT_tx_late_collision];
592
593 core_stats->rx_errors = (core_stats->rx_length_errors +
594 core_stats->rx_crc_errors +
595 core_stats->rx_frame_errors +
596 stats[SIENA_STAT_rx_symbol_error]);
597 core_stats->tx_errors = (core_stats->tx_window_errors +
598 stats[SIENA_STAT_tx_bad]);
599 }
600
601 return SIENA_STAT_COUNT;
afd4aea0
BH		 602}
603
319ec644
BH		 604static int siena_mac_reconfigure(struct efx_nic *efx)
605{
606 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
607 int rc;
608
609 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
610 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
611 sizeof(efx->multicast_hash));
612
964e6135
BH		 613 efx_farch_filter_sync_rx_mode(efx);
614
319ec644
BH		 615 WARN_ON(!mutex_is_locked(&efx->mac_lock));
616
617 rc = efx_mcdi_set_mac(efx);
618 if (rc != 0)
619 return rc;
620
621 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
622 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
623 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
624 inbuf, sizeof(inbuf), NULL, 0, NULL);
625}
626
afd4aea0
BH		 627/**************************************************************************
628 *
629 * Wake on LAN
630 *
631 **************************************************************************
632 */
633
634static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
635{
636 struct siena_nic_data *nic_data = efx->nic_data;
637
638 wol->supported = WAKE_MAGIC;
639 if (nic_data->wol_filter_id != -1)
640 wol->wolopts = WAKE_MAGIC;
641 else
642 wol->wolopts = 0;
643 memset(&wol->sopass, 0, sizeof(wol->sopass));
644}
645
646
647static int siena_set_wol(struct efx_nic *efx, u32 type)
648{
649 struct siena_nic_data *nic_data = efx->nic_data;
650 int rc;
651
652 if (type & ~WAKE_MAGIC)
653 return -EINVAL;
654
655 if (type & WAKE_MAGIC) {
656 if (nic_data->wol_filter_id != -1)
657 efx_mcdi_wol_filter_remove(efx,
658 nic_data->wol_filter_id);
02ebc268 659 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
afd4aea0
BH		 660 &nic_data->wol_filter_id);
661 if (rc)
662 goto fail;
663
664 pci_wake_from_d3(efx->pci_dev, true);
665 } else {
666 rc = efx_mcdi_wol_filter_reset(efx);
667 nic_data->wol_filter_id = -1;
668 pci_wake_from_d3(efx->pci_dev, false);
669 if (rc)
670 goto fail;
671 }
672
673 return 0;
674 fail:
62776d03
BH		 675 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
676 __func__, type, rc);
afd4aea0
BH		 677 return rc;
678}
679
680
681static void siena_init_wol(struct efx_nic *efx)
682{
683 struct siena_nic_data *nic_data = efx->nic_data;
684 int rc;
685
686 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
687
688 if (rc != 0) {
689 /* If it failed, attempt to get into a synchronised
690 * state with MC by resetting any set WoL filters */
691 efx_mcdi_wol_filter_reset(efx);
692 nic_data->wol_filter_id = -1;
693 } else if (nic_data->wol_filter_id != -1) {
694 pci_wake_from_d3(efx->pci_dev, true);
695 }
696}
697
f3ad5003
BH		 698/**************************************************************************
699 *
700 * MCDI
701 *
702 **************************************************************************
703 */
704
705#define MCDI_PDU(efx) \
706 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
707#define MCDI_DOORBELL(efx) \
708 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
709#define MCDI_STATUS(efx) \
710 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
711
712static void siena_mcdi_request(struct efx_nic *efx,
713 const efx_dword_t *hdr, size_t hdr_len,
714 const efx_dword_t *sdu, size_t sdu_len)
715{
716 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
717 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
718 unsigned int i;
719 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
720
721 EFX_BUG_ON_PARANOID(hdr_len != 4);
722
723 efx_writed(efx, hdr, pdu);
724
725 for (i = 0; i < inlen_dw; i++)
726 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
727
728 /* Ensure the request is written out before the doorbell */
729 wmb();
730
731 /* ring the doorbell with a distinctive value */
732 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
733}
734
735static bool siena_mcdi_poll_response(struct efx_nic *efx)
736{
737 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
738 efx_dword_t hdr;
739
740 efx_readd(efx, &hdr, pdu);
741
742 /* All 1's indicates that shared memory is in reset (and is
743 * not a valid hdr). Wait for it to come out reset before
744 * completing the command
745 */
746 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
747 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
748}
749
750static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
751 size_t offset, size_t outlen)
752{
753 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
754 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
755 int i;
756
757 for (i = 0; i < outlen_dw; i++)
758 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
759}
760
761static int siena_mcdi_poll_reboot(struct efx_nic *efx)
762{
cd0ecc9a 763 struct siena_nic_data *nic_data = efx->nic_data;
f3ad5003
BH		 764 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
765 efx_dword_t reg;
766 u32 value;
767
768 efx_readd(efx, &reg, addr);
769 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
770
771 if (value == 0)
772 return 0;
773
774 EFX_ZERO_DWORD(reg);
775 efx_writed(efx, &reg, addr);
776
cd0ecc9a
BH		 777 /* MAC statistics have been cleared on the NIC; clear the local
778 * copies that we update with efx_update_diff_stat().
779 */
780 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
781 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
782
f3ad5003
BH		 783 if (value == MC_STATUS_DWORD_ASSERT)
784 return -EINTR;
785 else
786 return -EIO;
787}
afd4aea0 788
45a3fd55
BH		 789/**************************************************************************
790 *
791 * MTD
792 *
793 **************************************************************************
794 */
795
796#ifdef CONFIG_SFC_MTD
797
798struct siena_nvram_type_info {
799 int port;
800 const char *name;
801};
802
803static const struct siena_nvram_type_info siena_nvram_types[] = {
804 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
805 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
806 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
807 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
808 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
809 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
810 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
811 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
812 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
813 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
814 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
815 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
816 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
817};
818
819static int siena_mtd_probe_partition(struct efx_nic *efx,
820 struct efx_mcdi_mtd_partition *part,
821 unsigned int type)
822{
823 const struct siena_nvram_type_info *info;
824 size_t size, erase_size;
825 bool protected;
826 int rc;
827
828 if (type >= ARRAY_SIZE(siena_nvram_types) ||
829 siena_nvram_types[type].name == NULL)
830 return -ENODEV;
831
832 info = &siena_nvram_types[type];
833
834 if (info->port != efx_port_num(efx))
835 return -ENODEV;
836
837 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
838 if (rc)
839 return rc;
840 if (protected)
841 return -ENODEV; /* hide it */
842
843 part->nvram_type = type;
844 part->common.dev_type_name = "Siena NVRAM manager";
845 part->common.type_name = info->name;
846
847 part->common.mtd.type = MTD_NORFLASH;
848 part->common.mtd.flags = MTD_CAP_NORFLASH;
849 part->common.mtd.size = size;
850 part->common.mtd.erasesize = erase_size;
851
852 return 0;
853}
854
855static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
856 struct efx_mcdi_mtd_partition *parts,
857 size_t n_parts)
858{
859 uint16_t fw_subtype_list[
860 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
861 size_t i;
862 int rc;
863
864 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
865 if (rc)
866 return rc;
867
868 for (i = 0; i < n_parts; i++)
869 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
870
871 return 0;
872}
873
874static int siena_mtd_probe(struct efx_nic *efx)
875{
876 struct efx_mcdi_mtd_partition *parts;
877 u32 nvram_types;
878 unsigned int type;
879 size_t n_parts;
880 int rc;
881
882 ASSERT_RTNL();
883
884 rc = efx_mcdi_nvram_types(efx, &nvram_types);
885 if (rc)
886 return rc;
887
888 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
889 if (!parts)
890 return -ENOMEM;
891
892 type = 0;
893 n_parts = 0;
894
895 while (nvram_types != 0) {
896 if (nvram_types & 1) {
897 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
898 type);
899 if (rc == 0)
900 n_parts++;
901 else if (rc != -ENODEV)
902 goto fail;
903 }
904 type++;
905 nvram_types >>= 1;
906 }
907
908 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
909 if (rc)
910 goto fail;
911
912 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
913fail:
914 if (rc)
915 kfree(parts);
916 return rc;
917}
918
919#endif /* CONFIG_SFC_MTD */
920
afd4aea0
BH		 921/**************************************************************************
922 *
923 * Revision-dependent attributes used by efx.c and nic.c
924 *
925 **************************************************************************
926 */
927
6c8c2513 928const struct efx_nic_type siena_a0_nic_type = {
6f7f8aa6 929 .is_vf = false,
02246a7f 930 .mem_bar = EFX_MEM_BAR,
b105798f 931 .mem_map_size = siena_mem_map_size,
afd4aea0
BH		 932 .probe = siena_probe_nic,
933 .remove = siena_remove_nic,
934 .init = siena_init_nic,
28e47c49 935 .dimension_resources = siena_dimension_resources,
afd4aea0 936 .fini = efx_port_dummy_op_void,
626950db
AR		 937#ifdef CONFIG_EEH
938 .monitor = siena_monitor,
939#else
afd4aea0 940 .monitor = NULL,
626950db 941#endif
6bff861d 942 .map_reset_reason = efx_mcdi_map_reset_reason,
0e2a9c7c 943 .map_reset_flags = siena_map_reset_flags,
6bff861d 944 .reset = efx_mcdi_reset,
43f775b2
BH		 945 .probe_port = efx_mcdi_port_probe,
946 .remove_port = efx_mcdi_port_remove,
e42c3d85 947 .fini_dmaq = efx_farch_fini_dmaq,
d5e8cc6c
BH		 948 .prepare_flush = siena_prepare_flush,
949 .finish_flush = siena_finish_flush,
e283546c
EC		 950 .prepare_flr = efx_port_dummy_op_void,
951 .finish_flr = efx_farch_finish_flr,
cd0ecc9a 952 .describe_stats = siena_describe_nic_stats,
afd4aea0 953 .update_stats = siena_update_nic_stats,
43f775b2 954 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 955 .pull_stats = efx_mcdi_mac_pull_stats,
43f775b2 956 .stop_stats = efx_mcdi_mac_stop_stats,
afd4aea0
BH		 957 .set_id_led = efx_mcdi_set_id_led,
958 .push_irq_moderation = siena_push_irq_moderation,
319ec644 959 .reconfigure_mac = siena_mac_reconfigure,
710b208d 960 .check_mac_fault = efx_mcdi_mac_check_fault,
43f775b2 961 .reconfigure_port = efx_mcdi_port_reconfigure,
afd4aea0
BH		 962 .get_wol = siena_get_wol,
963 .set_wol = siena_set_wol,
964 .resume_wol = siena_init_wol,
d4f2cecc 965 .test_chip = siena_test_chip,
2e803407 966 .test_nvram = efx_mcdi_nvram_test_all,
f3ad5003
BH		 967 .mcdi_request = siena_mcdi_request,
968 .mcdi_poll_response = siena_mcdi_poll_response,
969 .mcdi_read_response = siena_mcdi_read_response,
970 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
86094f7f
BH		 971 .irq_enable_master = efx_farch_irq_enable_master,
972 .irq_test_generate = efx_farch_irq_test_generate,
973 .irq_disable_non_ev = efx_farch_irq_disable_master,
974 .irq_handle_msi = efx_farch_msi_interrupt,
975 .irq_handle_legacy = efx_farch_legacy_interrupt,
976 .tx_probe = efx_farch_tx_probe,
977 .tx_init = efx_farch_tx_init,
978 .tx_remove = efx_farch_tx_remove,
979 .tx_write = efx_farch_tx_write,
d43050c0 980 .rx_push_rss_config = siena_rx_push_rss_config,
86094f7f
BH		 981 .rx_probe = efx_farch_rx_probe,
982 .rx_init = efx_farch_rx_init,
983 .rx_remove = efx_farch_rx_remove,
984 .rx_write = efx_farch_rx_write,
985 .rx_defer_refill = efx_farch_rx_defer_refill,
986 .ev_probe = efx_farch_ev_probe,
987 .ev_init = efx_farch_ev_init,
988 .ev_fini = efx_farch_ev_fini,
989 .ev_remove = efx_farch_ev_remove,
990 .ev_process = efx_farch_ev_process,
991 .ev_read_ack = efx_farch_ev_read_ack,
992 .ev_test_generate = efx_farch_ev_test_generate,
add72477
BH		 993 .filter_table_probe = efx_farch_filter_table_probe,
994 .filter_table_restore = efx_farch_filter_table_restore,
995 .filter_table_remove = efx_farch_filter_table_remove,
996 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
997 .filter_insert = efx_farch_filter_insert,
998 .filter_remove_safe = efx_farch_filter_remove_safe,
999 .filter_get_safe = efx_farch_filter_get_safe,
1000 .filter_clear_rx = efx_farch_filter_clear_rx,
1001 .filter_count_rx_used = efx_farch_filter_count_rx_used,
1002 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
1003 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
1004#ifdef CONFIG_RFS_ACCEL
1005 .filter_rfs_insert = efx_farch_filter_rfs_insert,
1006 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
1007#endif
45a3fd55
BH		 1008#ifdef CONFIG_SFC_MTD
1009 .mtd_probe = siena_mtd_probe,
1010 .mtd_rename = efx_mcdi_mtd_rename,
1011 .mtd_read = efx_mcdi_mtd_read,
1012 .mtd_erase = efx_mcdi_mtd_erase,
1013 .mtd_write = efx_mcdi_mtd_write,
1014 .mtd_sync = efx_mcdi_mtd_sync,
1015#endif
977a5d5d 1016 .ptp_write_host_time = siena_ptp_write_host_time,
9ec06595 1017 .ptp_set_ts_config = siena_ptp_set_ts_config,
7fa8d547 1018#ifdef CONFIG_SFC_SRIOV
834e23dd 1019 .sriov_configure = efx_siena_sriov_configure,
d98a4ffe
SS		 1020 .sriov_init = efx_siena_sriov_init,
1021 .sriov_fini = efx_siena_sriov_fini,
d98a4ffe
SS		 1022 .sriov_wanted = efx_siena_sriov_wanted,
1023 .sriov_reset = efx_siena_sriov_reset,
7fa8d547
SS		 1024 .sriov_flr = efx_siena_sriov_flr,
1025 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1026 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1027 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1028 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
6d8aaaf6
DP		 1029 .vswitching_probe = efx_port_dummy_op_int,
1030 .vswitching_restore = efx_port_dummy_op_int,
1031 .vswitching_remove = efx_port_dummy_op_void,
910c8789 1032 .set_mac_address = efx_siena_sriov_mac_address_changed,
7fa8d547 1033#endif
afd4aea0
BH		 1034
1035 .revision = EFX_REV_SIENA_A0,
afd4aea0
BH		 1036 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1037 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1038 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1039 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1040 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1041 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
43a3739d
JC		 1042 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1043 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
afd4aea0 1044 .rx_buffer_padding = 0,
85740cdf 1045 .can_rx_scatter = true,
afd4aea0 1046 .max_interrupt_mode = EFX_INT_MODE_MSIX,
cc180b69 1047 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
39c9cf07 1048 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b4187e42 1049 NETIF_F_RXHASH | NETIF_F_NTUPLE),
df2cd8af 1050 .mcdi_max_ver = 1,
add72477 1051 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
9ec06595
DP		 1052 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1053 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
7415991e 1054 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
afd4aea0 1055};
Linux kernel - Deliverables
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