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[deliverable/linux.git] / drivers / net / ethernet / smsc / smc91x.h
CommitLineData
1da177e4
LT		 1/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
0ab75ae8 21 . along with this program; if not, see <http://www.gnu.org/licenses/>.
1da177e4
LT		 22 .
23 . Information contained in this file was obtained from the LAN91C111
24 . manual from SMC. To get a copy, if you really want one, you can find
25 . information under www.smsc.com.
26 .
27 . Authors
28 . Erik Stahlman <erik@vt.edu>
29 . Daris A Nevil <dnevil@snmc.com>
2f82af08 30 . Nicolas Pitre <nico@fluxnic.net>
1da177e4
LT		 31 .
32 ---------------------------------------------------------------------------*/
33#ifndef _SMC91X_H_
34#define _SMC91X_H_
35
d24c8f24 36#include <linux/dmaengine.h>
3e947943 37#include <linux/smc91x.h>
1da177e4 38
2fb04fdf
RK		 39/*
40 * Any 16-bit access is performed with two 8-bit accesses if the hardware
41 * can't do it directly. Most registers are 16-bit so those are mandatory.
42 */
43#define SMC_outw_b(x, a, r) \
44 do { \
45 unsigned int __val16 = (x); \
46 unsigned int __reg = (r); \
47 SMC_outb(__val16, a, __reg); \
48 SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
49 } while (0)
50
51#define SMC_inw_b(a, r) \
52 ({ \
53 unsigned int __val16; \
54 unsigned int __reg = r; \
55 __val16 = SMC_inb(a, __reg); \
56 __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
57 __val16; \
58 })
59
1da177e4
LT		 60/*
61 * Define your architecture specific bus configuration parameters here.
62 */
63
b70661c7 64#if defined(CONFIG_ARM)
1da177e4 65
38fd6c38
EM		 66#include <asm/mach-types.h>
67
68/* Now the bus width is specified in the platform data
69 * pretend here to support all I/O access types
70 */
71#define SMC_CAN_USE_8BIT 1
1da177e4 72#define SMC_CAN_USE_16BIT 1
38fd6c38 73#define SMC_CAN_USE_32BIT 1
1da177e4
LT		 74#define SMC_NOWAIT 1
75
3aed74cd 76#define SMC_IO_SHIFT (lp->io_shift)
1da177e4 77
38fd6c38 78#define SMC_inb(a, r) readb((a) + (r))
2fb04fdf
RK		 79#define SMC_inw(a, r) \
80 ({ \
81 unsigned int __smc_r = r; \
82 SMC_16BIT(lp) ? readw((a) + __smc_r) : \
83 SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) : \
84 ({ BUG(); 0; }); \
85 })
86
38fd6c38
EM		 87#define SMC_inl(a, r) readl((a) + (r))
88#define SMC_outb(v, a, r) writeb(v, (a) + (r))
2fb04fdf
RK		 89#define SMC_outw(v, a, r) \
90 do { \
91 unsigned int __v = v, __smc_r = r; \
92 if (SMC_16BIT(lp)) \
93 __SMC_outw(__v, a, __smc_r); \
94 else if (SMC_8BIT(lp)) \
95 SMC_outw_b(__v, a, __smc_r); \
96 else \
97 BUG(); \
98 } while (0)
99
38fd6c38 100#define SMC_outl(v, a, r) writel(v, (a) + (r))
2fb04fdf
RK		 101#define SMC_insb(a, r, p, l) readsb((a) + (r), p, l)
102#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, l)
1da177e4
LT		 103#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
104#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
38fd6c38
EM		 105#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
106#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
e7b3dc7e 107#define SMC_IRQ_FLAGS (-1) /* from resource */
1da177e4 108
38fd6c38 109/* We actually can't write halfwords properly if not word aligned */
2fb04fdf 110static inline void __SMC_outw(u16 val, void __iomem *ioaddr, int reg)
38fd6c38 111{
b70661c7
AB		 112 if ((machine_is_mainstone() || machine_is_stargate2() ||
113 machine_is_pxa_idp()) && reg & 2) {
1da177e4
LT		 114 unsigned int v = val << 16;
115 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
116 writel(v, ioaddr + (reg & ~2));
117 } else {
118 writew(val, ioaddr + reg);
119 }
120}
121
1da177e4
LT		 122#elif defined(CONFIG_SH_SH4202_MICRODEV)
123
124#define SMC_CAN_USE_8BIT 0
125#define SMC_CAN_USE_16BIT 1
126#define SMC_CAN_USE_32BIT 0
127
128#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
129#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
130#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
131#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
132#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
133#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
134#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
135#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
136#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
137#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
138
9ded96f2 139#define SMC_IRQ_FLAGS (0)
1da177e4 140
1da177e4
LT		 141#elif defined(CONFIG_M32R)
142
143#define SMC_CAN_USE_8BIT 0
144#define SMC_CAN_USE_16BIT 1
145#define SMC_CAN_USE_32BIT 0
146
59dc76a4 147#define SMC_inb(a, r) inb(((u32)a) + (r))
f3ac9fbf
HT		 148#define SMC_inw(a, r) inw(((u32)a) + (r))
149#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
150#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
151#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
152#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
1da177e4 153
9ded96f2 154#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 155
156#define RPC_LSA_DEFAULT RPC_LED_TX_RX
157#define RPC_LSB_DEFAULT RPC_LED_100_10
158
b920de1b
DH		 159#elif defined(CONFIG_MN10300)
160
161/*
162 * MN10300/AM33 configuration
163 */
164
2f2a2132 165#include <unit/smc91111.h>
b920de1b 166
6321b54a
MS		 167#elif defined(CONFIG_ATARI)
168
169#define SMC_CAN_USE_8BIT 1
170#define SMC_CAN_USE_16BIT 1
171#define SMC_CAN_USE_32BIT 1
172#define SMC_NOWAIT 1
173
174#define SMC_inb(a, r) readb((a) + (r))
175#define SMC_inw(a, r) readw((a) + (r))
176#define SMC_inl(a, r) readl((a) + (r))
177#define SMC_outb(v, a, r) writeb(v, (a) + (r))
178#define SMC_outw(v, a, r) writew(v, (a) + (r))
179#define SMC_outl(v, a, r) writel(v, (a) + (r))
180#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
181#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
182#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
183#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
184
185#define RPC_LSA_DEFAULT RPC_LED_100_10
186#define RPC_LSB_DEFAULT RPC_LED_TX_RX
187
717ea4b3
GU		 188#elif defined(CONFIG_COLDFIRE)
189
190#define SMC_CAN_USE_8BIT 0
191#define SMC_CAN_USE_16BIT 1
192#define SMC_CAN_USE_32BIT 0
193#define SMC_NOWAIT 1
194
195static inline void mcf_insw(void *a, unsigned char *p, int l)
196{
197 u16 *wp = (u16 *) p;
198 while (l-- > 0)
199 *wp++ = readw(a);
200}
201
202static inline void mcf_outsw(void *a, unsigned char *p, int l)
203{
204 u16 *wp = (u16 *) p;
205 while (l-- > 0)
206 writew(*wp++, a);
207}
208
209#define SMC_inw(a, r) _swapw(readw((a) + (r)))
210#define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
211#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
212#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
213
cf68ca1e 214#define SMC_IRQ_FLAGS 0
717ea4b3 215
f147d0b3
YS		 216#elif defined(CONFIG_H8300)
217#define SMC_CAN_USE_8BIT 1
218#define SMC_CAN_USE_16BIT 0
219#define SMC_CAN_USE_32BIT 0
220#define SMC_NOWAIT 0
221
222#define SMC_inb(a, r) ioread8((a) + (r))
223#define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
224#define SMC_insb(a, r, p, l) ioread8_rep((a) + (r), p, l)
225#define SMC_outsb(a, r, p, l) iowrite8_rep((a) + (r), p, l)
226
1da177e4
LT		 227#else
228
b920de1b
DH		 229/*
230 * Default configuration
231 */
232
1da177e4
LT		 233#define SMC_CAN_USE_8BIT 1
234#define SMC_CAN_USE_16BIT 1
235#define SMC_CAN_USE_32BIT 1
236#define SMC_NOWAIT 1
237
d1c5ea33
MD		 238#define SMC_IO_SHIFT (lp->io_shift)
239
4ba73aa1
WD		 240#define SMC_inb(a, r) ioread8((a) + (r))
241#define SMC_inw(a, r) ioread16((a) + (r))
242#define SMC_inl(a, r) ioread32((a) + (r))
243#define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
244#define SMC_outw(v, a, r) iowrite16(v, (a) + (r))
245#define SMC_outl(v, a, r) iowrite32(v, (a) + (r))
246#define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l)
247#define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l)
248#define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l)
249#define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l)
1da177e4
LT		 250
251#define RPC_LSA_DEFAULT RPC_LED_100_10
252#define RPC_LSB_DEFAULT RPC_LED_TX_RX
253
254#endif
255
073ac8fd
RK		 256
257/* store this information for the driver.. */
258struct smc_local {
259 /*
260 * If I have to wait until memory is available to send a
261 * packet, I will store the skbuff here, until I get the
262 * desired memory. Then, I'll send it out and free it.
263 */
264 struct sk_buff *pending_tx_skb;
265 struct tasklet_struct tx_task;
266
7d2911c4
TL		 267 struct gpio_desc *power_gpio;
268 struct gpio_desc *reset_gpio;
269
073ac8fd
RK		 270 /* version/revision of the SMC91x chip */
271 int version;
272
273 /* Contains the current active transmission mode */
274 int tcr_cur_mode;
275
276 /* Contains the current active receive mode */
277 int rcr_cur_mode;
278
279 /* Contains the current active receive/phy mode */
280 int rpc_cur_mode;
281 int ctl_rfduplx;
282 int ctl_rspeed;
283
284 u32 msg_enable;
285 u32 phy_type;
286 struct mii_if_info mii;
287
288 /* work queue */
289 struct work_struct phy_configure;
290 struct net_device *dev;
291 int work_pending;
292
293 spinlock_t lock;
294
52256c0e 295#ifdef CONFIG_ARCH_PXA
073ac8fd
RK		 296 /* DMA needs the physical address of the chip */
297 u_long physaddr;
298 struct device *device;
299#endif
d24c8f24 300 struct dma_chan *dma_chan;
073ac8fd
RK		 301 void __iomem *base;
302 void __iomem *datacs;
3e947943 303
15919886
EM		 304 /* the low address lines on some platforms aren't connected... */
305 int io_shift;
306
3e947943 307 struct smc91x_platdata cfg;
073ac8fd
RK		 308};
309
fa6d3be0
EM		 310#define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
311#define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
312#define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
073ac8fd 313
52256c0e 314#ifdef CONFIG_ARCH_PXA
1da177e4
LT		 315/*
316 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
317 * always happening in irq context so no need to worry about races. TX is
318 * different and probably not worth it for that reason, and not as critical
319 * as RX which can overrun memory and lose packets.
320 */
321#include <linux/dma-mapping.h>
d24c8f24 322#include <linux/dma/pxa-dma.h>
1da177e4
LT		 323
324#ifdef SMC_insl
325#undef SMC_insl
326#define SMC_insl(a, r, p, l) \
073ac8fd 327 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
d24c8f24
RJ		 328static inline void
329smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)
330{
331 dma_addr_t dmabuf;
332 struct dma_async_tx_descriptor *tx;
333 dma_cookie_t cookie;
334 enum dma_status status;
335 struct dma_tx_state state;
336
337 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
338 tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,
339 DMA_DEV_TO_MEM, 0);
340 if (tx) {
341 cookie = dmaengine_submit(tx);
342 dma_async_issue_pending(lp->dma_chan);
343 do {
344 status = dmaengine_tx_status(lp->dma_chan, cookie,
345 &state);
346 cpu_relax();
347 } while (status != DMA_COMPLETE && status != DMA_ERROR &&
348 state.residue);
349 dmaengine_terminate_all(lp->dma_chan);
350 }
351 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
352}
353
1da177e4 354static inline void
073ac8fd 355smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
1da177e4
LT		 356 u_char *buf, int len)
357{
d24c8f24
RJ		 358 struct dma_slave_config config;
359 int ret;
1da177e4
LT		 360
361 /* fallback if no DMA available */
d24c8f24 362 if (!lp->dma_chan) {
1da177e4
LT		 363 readsl(ioaddr + reg, buf, len);
364 return;
365 }
366
367 /* 64 bit alignment is required for memory to memory DMA */
368 if ((long)buf & 4) {
369 *((u32 *)buf) = SMC_inl(ioaddr, reg);
370 buf += 4;
371 len--;
372 }
373
d24c8f24
RJ		 374 memset(&config, 0, sizeof(config));
375 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
376 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
377 config.src_addr = lp->physaddr + reg;
378 config.dst_addr = lp->physaddr + reg;
379 config.src_maxburst = 32;
380 config.dst_maxburst = 32;
381 ret = dmaengine_slave_config(lp->dma_chan, &config);
382 if (ret) {
383 dev_err(lp->device, "dma channel configuration failed: %d\n",
384 ret);
385 return;
386 }
387
1da177e4 388 len *= 4;
d24c8f24 389 smc_pxa_dma_inpump(lp, buf, len);
1da177e4
LT		 390}
391#endif
392
393#ifdef SMC_insw
394#undef SMC_insw
395#define SMC_insw(a, r, p, l) \
073ac8fd 396 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
1da177e4 397static inline void
073ac8fd 398smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
1da177e4
LT		 399 u_char *buf, int len)
400{
d24c8f24
RJ		 401 struct dma_slave_config config;
402 int ret;
1da177e4
LT		 403
404 /* fallback if no DMA available */
d24c8f24 405 if (!lp->dma_chan) {
1da177e4
LT		 406 readsw(ioaddr + reg, buf, len);
407 return;
408 }
409
410 /* 64 bit alignment is required for memory to memory DMA */
411 while ((long)buf & 6) {
412 *((u16 *)buf) = SMC_inw(ioaddr, reg);
413 buf += 2;
414 len--;
415 }
416
d24c8f24
RJ		 417 memset(&config, 0, sizeof(config));
418 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
419 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
420 config.src_addr = lp->physaddr + reg;
421 config.dst_addr = lp->physaddr + reg;
422 config.src_maxburst = 32;
423 config.dst_maxburst = 32;
424 ret = dmaengine_slave_config(lp->dma_chan, &config);
425 if (ret) {
426 dev_err(lp->device, "dma channel configuration failed: %d\n",
427 ret);
428 return;
429 }
430
1da177e4 431 len *= 2;
d24c8f24 432 smc_pxa_dma_inpump(lp, buf, len);
1da177e4
LT		 433}
434#endif
435
52256c0e 436#endif /* CONFIG_ARCH_PXA */
1da177e4
LT		 437
438
09779c6d
NP		 439/*
440 * Everything a particular hardware setup needs should have been defined
441 * at this point. Add stubs for the undefined cases, mainly to avoid
442 * compilation warnings since they'll be optimized away, or to prevent buggy
443 * use of them.
444 */
445
446#if ! SMC_CAN_USE_32BIT
447#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
448#define SMC_outl(x, ioaddr, reg) BUG()
449#define SMC_insl(a, r, p, l) BUG()
450#define SMC_outsl(a, r, p, l) BUG()
451#endif
452
453#if !defined(SMC_insl) || !defined(SMC_outsl)
454#define SMC_insl(a, r, p, l) BUG()
455#define SMC_outsl(a, r, p, l) BUG()
456#endif
457
458#if ! SMC_CAN_USE_16BIT
459
2fb04fdf
RK		 460#define SMC_outw(x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg)
461#define SMC_inw(ioaddr, reg) SMC_inw_b(ioaddr, reg)
09779c6d
NP		 462#define SMC_insw(a, r, p, l) BUG()
463#define SMC_outsw(a, r, p, l) BUG()
464
465#endif
466
467#if !defined(SMC_insw) || !defined(SMC_outsw)
468#define SMC_insw(a, r, p, l) BUG()
469#define SMC_outsw(a, r, p, l) BUG()
470#endif
471
472#if ! SMC_CAN_USE_8BIT
daa7ee8d 473#undef SMC_inb
09779c6d 474#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
daa7ee8d 475#undef SMC_outb
09779c6d
NP		 476#define SMC_outb(x, ioaddr, reg) BUG()
477#define SMC_insb(a, r, p, l) BUG()
478#define SMC_outsb(a, r, p, l) BUG()
479#endif
480
481#if !defined(SMC_insb) || !defined(SMC_outsb)
482#define SMC_insb(a, r, p, l) BUG()
483#define SMC_outsb(a, r, p, l) BUG()
484#endif
485
486#ifndef SMC_CAN_USE_DATACS
487#define SMC_CAN_USE_DATACS 0
488#endif
489
1da177e4
LT		 490#ifndef SMC_IO_SHIFT
491#define SMC_IO_SHIFT 0
492#endif
09779c6d
NP		 493
494#ifndef SMC_IRQ_FLAGS
1fb9df5d 495#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
09779c6d
NP		 496#endif
497
498#ifndef SMC_INTERRUPT_PREAMBLE
499#define SMC_INTERRUPT_PREAMBLE
500#endif
501
502
503/* Because of bank switching, the LAN91x uses only 16 I/O ports */
1da177e4
LT		 504#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
505#define SMC_DATA_EXTENT (4)
506
507/*
508 . Bank Select Register:
509 .
510 . yyyy yyyy 0000 00xx
511 . xx = bank number
512 . yyyy yyyy = 0x33, for identification purposes.
513*/
514#define BANK_SELECT (14 << SMC_IO_SHIFT)
515
516
517// Transmit Control Register
518/* BANK 0 */
cfdfa865 519#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
1da177e4
LT		 520#define TCR_ENABLE 0x0001 // When 1 we can transmit
521#define TCR_LOOP 0x0002 // Controls output pin LBK
522#define TCR_FORCOL 0x0004 // When 1 will force a collision
523#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
524#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
525#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
526#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
527#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
528#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
529#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
530
531#define TCR_CLEAR 0 /* do NOTHING */
532/* the default settings for the TCR register : */
533#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
534
535
536// EPH Status Register
537/* BANK 0 */
cfdfa865 538#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
1da177e4
LT		 539#define ES_TX_SUC 0x0001 // Last TX was successful
540#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
541#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
542#define ES_LTX_MULT 0x0008 // Last tx was a multicast
543#define ES_16COL 0x0010 // 16 Collisions Reached
544#define ES_SQET 0x0020 // Signal Quality Error Test
545#define ES_LTXBRD 0x0040 // Last tx was a broadcast
546#define ES_TXDEFR 0x0080 // Transmit Deferred
547#define ES_LATCOL 0x0200 // Late collision detected on last tx
548#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
549#define ES_EXC_DEF 0x0800 // Excessive Deferral
550#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
551#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
552#define ES_TXUNRN 0x8000 // Tx Underrun
553
554
555// Receive Control Register
556/* BANK 0 */
cfdfa865 557#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
1da177e4
LT		 558#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
559#define RCR_PRMS 0x0002 // Enable promiscuous mode
560#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
561#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
562#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
563#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
564#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
565#define RCR_SOFTRST 0x8000 // resets the chip
566
567/* the normal settings for the RCR register : */
568#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
569#define RCR_CLEAR 0x0 // set it to a base state
570
571
572// Counter Register
573/* BANK 0 */
cfdfa865 574#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
1da177e4
LT		 575
576
577// Memory Information Register
578/* BANK 0 */
cfdfa865 579#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
1da177e4
LT		 580
581
582// Receive/Phy Control Register
583/* BANK 0 */
cfdfa865 584#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
1da177e4
LT		 585#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
586#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
587#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
588#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
589#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
1da177e4
LT		 590
591#ifndef RPC_LSA_DEFAULT
592#define RPC_LSA_DEFAULT RPC_LED_100
593#endif
594#ifndef RPC_LSB_DEFAULT
595#define RPC_LSB_DEFAULT RPC_LED_FD
596#endif
597
b0dbcf51 598#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
1da177e4
LT		 599
600
601/* Bank 0 0x0C is reserved */
602
603// Bank Select Register
604/* All Banks */
605#define BSR_REG 0x000E
606
607
608// Configuration Reg
609/* BANK 1 */
cfdfa865 610#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
1da177e4
LT		 611#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
612#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
613#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
614#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
615
616// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
617#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
618
619
620// Base Address Register
621/* BANK 1 */
cfdfa865 622#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
1da177e4
LT		 623
624
625// Individual Address Registers
626/* BANK 1 */
cfdfa865
MD		 627#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
628#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
629#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
1da177e4
LT		 630
631
632// General Purpose Register
633/* BANK 1 */
cfdfa865 634#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
1da177e4
LT		 635
636
637// Control Register
638/* BANK 1 */
cfdfa865 639#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
1da177e4
LT		 640#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
641#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
642#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
643#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
644#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
645#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
646#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
647#define CTL_STORE 0x0001 // When set stores registers into EEPROM
648
649
650// MMU Command Register
651/* BANK 2 */
cfdfa865 652#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
1da177e4
LT		 653#define MC_BUSY 1 // When 1 the last release has not completed
654#define MC_NOP (0<<5) // No Op
655#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
656#define MC_RESET (2<<5) // Reset MMU to initial state
657#define MC_REMOVE (3<<5) // Remove the current rx packet
658#define MC_RELEASE (4<<5) // Remove and release the current rx packet
659#define MC_FREEPKT (5<<5) // Release packet in PNR register
660#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
661#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
662
663
664// Packet Number Register
665/* BANK 2 */
cfdfa865 666#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
1da177e4
LT		 667
668
669// Allocation Result Register
670/* BANK 2 */
cfdfa865 671#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
1da177e4
LT		 672#define AR_FAILED 0x80 // Alocation Failed
673
674
675// TX FIFO Ports Register
676/* BANK 2 */
cfdfa865 677#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
1da177e4
LT		 678#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
679
680// RX FIFO Ports Register
681/* BANK 2 */
cfdfa865 682#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
1da177e4
LT		 683#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
684
cfdfa865 685#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
1da177e4
LT		 686
687// Pointer Register
688/* BANK 2 */
cfdfa865 689#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
1da177e4
LT		 690#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
691#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
692#define PTR_READ 0x2000 // When 1 the operation is a read
693
694
695// Data Register
696/* BANK 2 */
cfdfa865 697#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
1da177e4
LT		 698
699
700// Interrupt Status/Acknowledge Register
701/* BANK 2 */
cfdfa865 702#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
1da177e4
LT		 703
704
705// Interrupt Mask Register
706/* BANK 2 */
cfdfa865 707#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
1da177e4
LT		 708#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
709#define IM_ERCV_INT 0x40 // Early Receive Interrupt
710#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
711#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
712#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
713#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
714#define IM_TX_INT 0x02 // Transmit Interrupt
715#define IM_RCV_INT 0x01 // Receive Interrupt
716
717
718// Multicast Table Registers
719/* BANK 3 */
cfdfa865
MD		 720#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
721#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
722#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
723#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
1da177e4
LT		 724
725
726// Management Interface Register (MII)
727/* BANK 3 */
cfdfa865 728#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
1da177e4
LT		 729#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
730#define MII_MDOE 0x0008 // MII Output Enable
731#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
732#define MII_MDI 0x0002 // MII Input, pin MDI
733#define MII_MDO 0x0001 // MII Output, pin MDO
734
735
736// Revision Register
737/* BANK 3 */
738/* ( hi: chip id low: rev # ) */
cfdfa865 739#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
1da177e4
LT		 740
741
742// Early RCV Register
743/* BANK 3 */
744/* this is NOT on SMC9192 */
cfdfa865 745#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
1da177e4
LT		 746#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
747#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
748
749
750// External Register
751/* BANK 7 */
cfdfa865 752#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
1da177e4
LT		 753
754
755#define CHIP_9192 3
756#define CHIP_9194 4
757#define CHIP_9195 5
758#define CHIP_9196 6
759#define CHIP_91100 7
760#define CHIP_91100FD 8
761#define CHIP_91111FD 9
762
763static const char * chip_ids[ 16 ] = {
764 NULL, NULL, NULL,
765 /* 3 */ "SMC91C90/91C92",
766 /* 4 */ "SMC91C94",
767 /* 5 */ "SMC91C95",
768 /* 6 */ "SMC91C96",
769 /* 7 */ "SMC91C100",
770 /* 8 */ "SMC91C100FD",
771 /* 9 */ "SMC91C11xFD",
772 NULL, NULL, NULL,
773 NULL, NULL, NULL};
774
775
1da177e4
LT		 776/*
777 . Receive status bits
778*/
779#define RS_ALGNERR 0x8000
780#define RS_BRODCAST 0x4000
781#define RS_BADCRC 0x2000
782#define RS_ODDFRAME 0x1000
783#define RS_TOOLONG 0x0800
784#define RS_TOOSHORT 0x0400
785#define RS_MULTICAST 0x0001
786#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
787
788
789/*
790 * PHY IDs
791 * LAN83C183 == LAN91C111 Internal PHY
792 */
793#define PHY_LAN83C183 0x0016f840
794#define PHY_LAN83C180 0x02821c50
795
796/*
797 * PHY Register Addresses (LAN91C111 Internal PHY)
798 *
799 * Generic PHY registers can be found in <linux/mii.h>
800 *
801 * These phy registers are specific to our on-board phy.
802 */
803
804// PHY Configuration Register 1
805#define PHY_CFG1_REG 0x10
806#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
807#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
808#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
809#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
810#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
811#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
812#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
813#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
814#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
815#define PHY_CFG1_TLVL_MASK 0x003C
816#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
817
818
819// PHY Configuration Register 2
820#define PHY_CFG2_REG 0x11
821#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
822#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
823#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
824#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
825
826// PHY Status Output (and Interrupt status) Register
827#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
828#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
829#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
830#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
831#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
832#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
833#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
834#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
835#define PHY_INT_JAB 0x0100 // 1=Jabber detected
836#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
837#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
838
839// PHY Interrupt/Status Mask Register
840#define PHY_MASK_REG 0x13 // Interrupt Mask
841// Uses the same bit definitions as PHY_INT_REG
842
843
844/*
845 * SMC91C96 ethernet config and status registers.
846 * These are in the "attribute" space.
847 */
848#define ECOR 0x8000
849#define ECOR_RESET 0x80
850#define ECOR_LEVEL_IRQ 0x40
851#define ECOR_WR_ATTRIB 0x04
852#define ECOR_ENABLE 0x01
853
854#define ECSR 0x8002
855#define ECSR_IOIS8 0x20
856#define ECSR_PWRDWN 0x04
857#define ECSR_INT 0x02
858
859#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
860
861
862/*
863 * Macros to abstract register access according to the data bus
864 * capabilities. Please use those and not the in/out primitives.
865 * Note: the following macros do *not* select the bank -- this must
866 * be done separately as needed in the main code. The SMC_REG() macro
867 * only uses the bank argument for debugging purposes (when enabled).
09779c6d
NP		 868 *
869 * Note: despite inline functions being safer, everything leading to this
870 * should preferably be macros to let BUG() display the line number in
871 * the core source code since we're interested in the top call site
872 * not in any inline function location.
1da177e4
LT		 873 */
874
875#if SMC_DEBUG > 0
cfdfa865 876#define SMC_REG(lp, reg, bank) \
1da177e4 877 ({ \
cfdfa865 878 int __b = SMC_CURRENT_BANK(lp); \
1da177e4 879 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
6389aa45
BB		 880 pr_err("%s: bank reg screwed (0x%04x)\n", \
881 CARDNAME, __b); \
1da177e4
LT		 882 BUG(); \
883 } \
884 reg<<SMC_IO_SHIFT; \
885 })
886#else
cfdfa865 887#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1da177e4
LT		 888#endif
889
09779c6d
NP		 890/*
891 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
892 * aligned to a 32 bit boundary. I tell you that does exist!
893 * Fortunately the affected register accesses can be easily worked around
25985edc 894 * since we can write zeroes to the preceding 16 bits without adverse
09779c6d
NP		 895 * effects and use a 32-bit access.
896 *
897 * Enforce it on any 32-bit capable setup for now.
898 */
3e947943 899#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
09779c6d 900
cfdfa865 901#define SMC_GET_PN(lp) \
3e947943 902 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
cfdfa865 903 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
09779c6d 904
cfdfa865 905#define SMC_SET_PN(lp, x) \
09779c6d 906 do { \
3e947943 907 if (SMC_MUST_ALIGN_WRITE(lp)) \
cfdfa865 908 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
3e947943 909 else if (SMC_8BIT(lp)) \
cfdfa865 910 SMC_outb(x, ioaddr, PN_REG(lp)); \
09779c6d 911 else \
cfdfa865 912 SMC_outw(x, ioaddr, PN_REG(lp)); \
09779c6d
NP		 913 } while (0)
914
cfdfa865 915#define SMC_GET_AR(lp) \
3e947943 916 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
cfdfa865 917 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
09779c6d 918
cfdfa865 919#define SMC_GET_TXFIFO(lp) \
3e947943 920 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
cfdfa865 921 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
09779c6d 922
cfdfa865 923#define SMC_GET_RXFIFO(lp) \
3e947943 924 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
cfdfa865 925 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
09779c6d 926
cfdfa865 927#define SMC_GET_INT(lp) \
3e947943 928 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
cfdfa865 929 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
09779c6d 930
cfdfa865 931#define SMC_ACK_INT(lp, x) \
1da177e4 932 do { \
3e947943 933 if (SMC_8BIT(lp)) \
cfdfa865 934 SMC_outb(x, ioaddr, INT_REG(lp)); \
09779c6d
NP		 935 else { \
936 unsigned long __flags; \
937 int __mask; \
938 local_irq_save(__flags); \
cfdfa865
MD		 939 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
940 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
09779c6d
NP		 941 local_irq_restore(__flags); \
942 } \
943 } while (0)
944
cfdfa865 945#define SMC_GET_INT_MASK(lp) \
3e947943 946 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
cfdfa865 947 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
09779c6d 948
cfdfa865 949#define SMC_SET_INT_MASK(lp, x) \
09779c6d 950 do { \
3e947943 951 if (SMC_8BIT(lp)) \
cfdfa865 952 SMC_outb(x, ioaddr, IM_REG(lp)); \
09779c6d 953 else \
cfdfa865 954 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
09779c6d
NP		 955 } while (0)
956
cfdfa865 957#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
09779c6d 958
cfdfa865 959#define SMC_SELECT_BANK(lp, x) \
09779c6d 960 do { \
3e947943 961 if (SMC_MUST_ALIGN_WRITE(lp)) \
09779c6d
NP		 962 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
963 else \
964 SMC_outw(x, ioaddr, BANK_SELECT); \
965 } while (0)
966
cfdfa865 967#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
09779c6d 968
cfdfa865 969#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
09779c6d 970
cfdfa865 971#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
09779c6d 972
cfdfa865 973#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
09779c6d 974
cfdfa865 975#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
09779c6d 976
cfdfa865 977#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
09779c6d 978
cfdfa865 979#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
09779c6d 980
cfdfa865 981#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
09779c6d 982
357fe2c6
VS		 983#define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
984
985#define SMC_SET_GP(lp, x) \
986 do { \
987 if (SMC_MUST_ALIGN_WRITE(lp)) \
988 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
989 else \
990 SMC_outw(x, ioaddr, GP_REG(lp)); \
991 } while (0)
992
cfdfa865 993#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
09779c6d 994
cfdfa865 995#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
09779c6d 996
cfdfa865 997#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
09779c6d 998
cfdfa865 999#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
09779c6d 1000
cfdfa865 1001#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
09779c6d 1002
cfdfa865 1003#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
09779c6d 1004
cfdfa865 1005#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
09779c6d 1006
cfdfa865 1007#define SMC_SET_PTR(lp, x) \
09779c6d 1008 do { \
3e947943 1009 if (SMC_MUST_ALIGN_WRITE(lp)) \
cfdfa865 1010 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
09779c6d 1011 else \
cfdfa865 1012 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1da177e4 1013 } while (0)
1da177e4 1014
cfdfa865 1015#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
09779c6d 1016
cfdfa865 1017#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
09779c6d 1018
cfdfa865 1019#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
09779c6d 1020
cfdfa865 1021#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
09779c6d 1022
cfdfa865 1023#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
09779c6d 1024
cfdfa865 1025#define SMC_SET_RPC(lp, x) \
09779c6d 1026 do { \
3e947943 1027 if (SMC_MUST_ALIGN_WRITE(lp)) \
cfdfa865 1028 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
09779c6d 1029 else \
cfdfa865 1030 SMC_outw(x, ioaddr, RPC_REG(lp)); \
09779c6d
NP		 1031 } while (0)
1032
cfdfa865 1033#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
09779c6d 1034
cfdfa865 1035#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1da177e4
LT		 1036
1037#ifndef SMC_GET_MAC_ADDR
cfdfa865 1038#define SMC_GET_MAC_ADDR(lp, addr) \
1da177e4
LT		 1039 do { \
1040 unsigned int __v; \
cfdfa865 1041 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1da177e4 1042 addr[0] = __v; addr[1] = __v >> 8; \
cfdfa865 1043 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1da177e4 1044 addr[2] = __v; addr[3] = __v >> 8; \
cfdfa865 1045 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1da177e4
LT		 1046 addr[4] = __v; addr[5] = __v >> 8; \
1047 } while (0)
1048#endif
1049
cfdfa865 1050#define SMC_SET_MAC_ADDR(lp, addr) \
1da177e4 1051 do { \
cfdfa865
MD		 1052 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1053 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1054 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1da177e4
LT		 1055 } while (0)
1056
cfdfa865 1057#define SMC_SET_MCAST(lp, x) \
1da177e4
LT		 1058 do { \
1059 const unsigned char *mt = (x); \
cfdfa865
MD		 1060 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1061 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1062 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1063 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1da177e4
LT		 1064 } while (0)
1065
cfdfa865 1066#define SMC_PUT_PKT_HDR(lp, status, length) \
1da177e4 1067 do { \
3e947943 1068 if (SMC_32BIT(lp)) \
cfdfa865
MD		 1069 SMC_outl((status) | (length)<<16, ioaddr, \
1070 DATA_REG(lp)); \
09779c6d 1071 else { \
cfdfa865
MD		 1072 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1073 SMC_outw(length, ioaddr, DATA_REG(lp)); \
09779c6d 1074 } \
1da177e4 1075 } while (0)
1da177e4 1076
cfdfa865 1077#define SMC_GET_PKT_HDR(lp, status, length) \
1da177e4 1078 do { \
3e947943 1079 if (SMC_32BIT(lp)) { \
cfdfa865 1080 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
09779c6d
NP		 1081 (status) = __val & 0xffff; \
1082 (length) = __val >> 16; \
1083 } else { \
cfdfa865
MD		 1084 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1085 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1da177e4
LT		 1086 } \
1087 } while (0)
1da177e4 1088
cfdfa865 1089#define SMC_PUSH_DATA(lp, p, l) \
1da177e4 1090 do { \
3e947943 1091 if (SMC_32BIT(lp)) { \
09779c6d
NP		 1092 void *__ptr = (p); \
1093 int __len = (l); \
fbd81976 1094 void __iomem *__ioaddr = ioaddr; \
09779c6d
NP		 1095 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1096 __len -= 2; \
e9e4ea74 1097 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
09779c6d
NP		 1098 __ptr += 2; \
1099 } \
1100 if (SMC_CAN_USE_DATACS && lp->datacs) \
1101 __ioaddr = lp->datacs; \
cfdfa865 1102 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
09779c6d
NP		 1103 if (__len & 2) { \
1104 __ptr += (__len & ~3); \
e9e4ea74 1105 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
09779c6d 1106 } \
3e947943 1107 } else if (SMC_16BIT(lp)) \
cfdfa865 1108 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
3e947943 1109 else if (SMC_8BIT(lp)) \
cfdfa865 1110 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1da177e4 1111 } while (0)
1da177e4 1112
cfdfa865 1113#define SMC_PULL_DATA(lp, p, l) \
09779c6d 1114 do { \
3e947943 1115 if (SMC_32BIT(lp)) { \
09779c6d
NP		 1116 void *__ptr = (p); \
1117 int __len = (l); \
fbd81976 1118 void __iomem *__ioaddr = ioaddr; \
09779c6d
NP		 1119 if ((unsigned long)__ptr & 2) { \
1120 /* \
1121 * We want 32bit alignment here. \
1122 * Since some buses perform a full \
1123 * 32bit fetch even for 16bit data \
1124 * we can't use SMC_inw() here. \
1125 * Back both source (on-chip) and \
1126 * destination pointers of 2 bytes. \
1127 * This is possible since the call to \
1128 * SMC_GET_PKT_HDR() already advanced \
1129 * the source pointer of 4 bytes, and \
1130 * the skb_reserve(skb, 2) advanced \
1131 * the destination pointer of 2 bytes. \
1132 */ \
1133 __ptr -= 2; \
1134 __len += 2; \
cfdfa865
MD		 1135 SMC_SET_PTR(lp, \
1136 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
09779c6d
NP		 1137 } \
1138 if (SMC_CAN_USE_DATACS && lp->datacs) \
1139 __ioaddr = lp->datacs; \
1da177e4 1140 __len += 2; \
cfdfa865 1141 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
3e947943 1142 } else if (SMC_16BIT(lp)) \
cfdfa865 1143 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
3e947943 1144 else if (SMC_8BIT(lp)) \
cfdfa865 1145 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
09779c6d 1146 } while (0)
1da177e4
LT		 1147
1148#endif /* _SMC91X_H_ */
Linux kernel - Deliverables
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