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Merge remote-tracking branch 'vfio/next'
[deliverable/linux.git] / drivers / net / ethernet / tehuti / tehuti.c
CommitLineData
1a348ccc
AG		 1/*
2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/*
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
b595076a 15 * There are 2 types of RX communication channels between driver and NIC.
1a348ccc
AG		 16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25 *
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
30 * RXD Fifo.
31 *
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
41 *
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
51 *
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
62 *
63 */
64
865a21a5
JP		 65#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66
1a348ccc 67#include "tehuti.h"
1a348ccc 68
9baa3c34 69static const struct pci_device_id bdx_pci_tbl[] = {
a355d865 70 { PCI_VDEVICE(TEHUTI, 0x3009), },
71 { PCI_VDEVICE(TEHUTI, 0x3010), },
72 { PCI_VDEVICE(TEHUTI, 0x3014), },
73 { 0 }
1a348ccc
AG		 74};
75
76MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
77
78/* Definitions needed by ISR or NAPI functions */
79static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
80static void bdx_tx_cleanup(struct bdx_priv *priv);
81static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
82
83/* Definitions needed by FW loading */
84static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
85
86/* Definitions needed by hw_start */
87static int bdx_tx_init(struct bdx_priv *priv);
88static int bdx_rx_init(struct bdx_priv *priv);
89
90/* Definitions needed by bdx_close */
91static void bdx_rx_free(struct bdx_priv *priv);
92static void bdx_tx_free(struct bdx_priv *priv);
93
94/* Definitions needed by bdx_probe */
c061b18d 95static void bdx_set_ethtool_ops(struct net_device *netdev);
1a348ccc
AG		 96
97/*************************************************************************
98 * Print Info *
99 *************************************************************************/
100
101static void print_hw_id(struct pci_dev *pdev)
102{
103 struct pci_nic *nic = pci_get_drvdata(pdev);
104 u16 pci_link_status = 0;
105 u16 pci_ctrl = 0;
106
107 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
108 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
109
865a21a5
JP		 110 pr_info("%s%s\n", BDX_NIC_NAME,
111 nic->port_num == 1 ? "" : ", 2-Port");
112 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
113 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
114 readl(nic->regs + FPGA_SEED),
115 GET_LINK_STATUS_LANES(pci_link_status),
116 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
1a348ccc
AG		 117}
118
119static void print_fw_id(struct pci_nic *nic)
120{
865a21a5 121 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
1a348ccc
AG		 122}
123
124static void print_eth_id(struct net_device *ndev)
125{
865a21a5
JP		 126 netdev_info(ndev, "%s, Port %c\n",
127 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
1a348ccc
AG		 128
129}
130
131/*************************************************************************
132 * Code *
133 *************************************************************************/
134
135#define bdx_enable_interrupts(priv) \
136 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
137#define bdx_disable_interrupts(priv) \
138 do { WRITE_REG(priv, regIMR, 0); } while (0)
139
49ce9c2c
BH		 140/**
141 * bdx_fifo_init - create TX/RX descriptor fifo for host-NIC communication.
142 * @priv: NIC private structure
143 * @f: fifo to initialize
144 * @fsz_type: fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
145 * @reg_XXX: offsets of registers relative to base address
146 *
1a348ccc
AG		 147 * 1K extra space is allocated at the end of the fifo to simplify
148 * processing of descriptors that wraps around fifo's end
1a348ccc
AG		 149 *
150 * Returns 0 on success, negative value on failure
151 *
152 */
153static int
154bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
155 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
156{
157 u16 memsz = FIFO_SIZE * (1 << fsz_type);
158
159 memset(f, 0, sizeof(struct fifo));
160 /* pci_alloc_consistent gives us 4k-aligned memory */
161 f->va = pci_alloc_consistent(priv->pdev,
162 memsz + FIFO_EXTRA_SPACE, &f->da);
163 if (!f->va) {
865a21a5 164 pr_err("pci_alloc_consistent failed\n");
1a348ccc
AG		 165 RET(-ENOMEM);
166 }
167 f->reg_CFG0 = reg_CFG0;
168 f->reg_CFG1 = reg_CFG1;
169 f->reg_RPTR = reg_RPTR;
170 f->reg_WPTR = reg_WPTR;
171 f->rptr = 0;
172 f->wptr = 0;
173 f->memsz = memsz;
174 f->size_mask = memsz - 1;
175 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
176 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
177
178 RET(0);
179}
180
49ce9c2c
BH		 181/**
182 * bdx_fifo_free - free all resources used by fifo
183 * @priv: NIC private structure
184 * @f: fifo to release
1a348ccc
AG		 185 */
186static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
187{
188 ENTER;
189 if (f->va) {
190 pci_free_consistent(priv->pdev,
191 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
192 f->va = NULL;
193 }
194 RET();
195}
196
49ce9c2c 197/**
1a348ccc 198 * bdx_link_changed - notifies OS about hw link state.
49ce9c2c 199 * @priv: hw adapter structure
1a348ccc
AG		 200 */
201static void bdx_link_changed(struct bdx_priv *priv)
202{
203 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
204
205 if (!link) {
206 if (netif_carrier_ok(priv->ndev)) {
207 netif_stop_queue(priv->ndev);
208 netif_carrier_off(priv->ndev);
865a21a5 209 netdev_err(priv->ndev, "Link Down\n");
1a348ccc
AG		 210 }
211 } else {
212 if (!netif_carrier_ok(priv->ndev)) {
213 netif_wake_queue(priv->ndev);
214 netif_carrier_on(priv->ndev);
865a21a5 215 netdev_err(priv->ndev, "Link Up\n");
1a348ccc
AG		 216 }
217 }
218}
219
220static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
221{
222 if (isr & IR_RX_FREE_0) {
223 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
224 DBG("RX_FREE_0\n");
225 }
226
227 if (isr & IR_LNKCHG0)
228 bdx_link_changed(priv);
229
230 if (isr & IR_PCIE_LINK)
865a21a5 231 netdev_err(priv->ndev, "PCI-E Link Fault\n");
1a348ccc
AG		 232
233 if (isr & IR_PCIE_TOUT)
865a21a5 234 netdev_err(priv->ndev, "PCI-E Time Out\n");
1a348ccc
AG		 235
236}
237
49ce9c2c
BH		 238/**
239 * bdx_isr_napi - Interrupt Service Routine for Bordeaux NIC
240 * @irq: interrupt number
241 * @dev: network device
1a348ccc
AG		 242 *
243 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
244 *
245 * It reads ISR register to know interrupt reasons, and proceed them one by one.
246 * Reasons of interest are:
247 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
248 * RX_FREE - number of free Rx buffers in RXF fifo gets low
249 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
250 */
251
252static irqreturn_t bdx_isr_napi(int irq, void *dev)
253{
254 struct net_device *ndev = dev;
8f15ea42 255 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 256 u32 isr;
257
258 ENTER;
259 isr = (READ_REG(priv, regISR) & IR_RUN);
260 if (unlikely(!isr)) {
261 bdx_enable_interrupts(priv);
262 return IRQ_NONE; /* Not our interrupt */
263 }
264
265 if (isr & IR_EXTRA)
266 bdx_isr_extra(priv, isr);
267
268 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
288379f0
BH		 269 if (likely(napi_schedule_prep(&priv->napi))) {
270 __napi_schedule(&priv->napi);
1a348ccc
AG		 271 RET(IRQ_HANDLED);
272 } else {
273 /* NOTE: we get here if intr has slipped into window
274 * between these lines in bdx_poll:
275 * bdx_enable_interrupts(priv);
276 * return 0;
277 * currently intrs are disabled (since we read ISR),
278 * and we have failed to register next poll.
279 * so we read the regs to trigger chip
280 * and allow further interupts. */
281 READ_REG(priv, regTXF_WPTR_0);
282 READ_REG(priv, regRXD_WPTR_0);
283 }
284 }
285
286 bdx_enable_interrupts(priv);
287 RET(IRQ_HANDLED);
288}
289
290static int bdx_poll(struct napi_struct *napi, int budget)
291{
292 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
1a348ccc
AG		 293 int work_done;
294
295 ENTER;
296 bdx_tx_cleanup(priv);
297 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
298 if ((work_done < budget) ||
299 (priv->napi_stop++ >= 30)) {
300 DBG("rx poll is done. backing to isr-driven\n");
301
302 /* from time to time we exit to let NAPI layer release
303 * device lock and allow waiting tasks (eg rmmod) to advance) */
304 priv->napi_stop = 0;
305
288379f0 306 napi_complete(napi);
1a348ccc
AG		 307 bdx_enable_interrupts(priv);
308 }
309 return work_done;
310}
311
49ce9c2c
BH		 312/**
313 * bdx_fw_load - loads firmware to NIC
314 * @priv: NIC private structure
315 *
1a348ccc
AG		 316 * Firmware is loaded via TXD fifo, so it must be initialized first.
317 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
318 * can have few of them). So all drivers use semaphore register to choose one
319 * that will actually load FW to NIC.
320 */
321
322static int bdx_fw_load(struct bdx_priv *priv)
323{
06e1f9ff 324 const struct firmware *fw = NULL;
1a348ccc 325 int master, i;
06e1f9ff 326 int rc;
1a348ccc
AG		 327
328 ENTER;
329 master = READ_REG(priv, regINIT_SEMAPHORE);
330 if (!READ_REG(priv, regINIT_STATUS) && master) {
46814e08 331 rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev);
06e1f9ff
BH		 332 if (rc)
333 goto out;
334 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
1a348ccc
AG		 335 mdelay(100);
336 }
337 for (i = 0; i < 200; i++) {
06e1f9ff
BH		 338 if (READ_REG(priv, regINIT_STATUS)) {
339 rc = 0;
340 goto out;
341 }
1a348ccc
AG		 342 mdelay(2);
343 }
06e1f9ff
BH		 344 rc = -EIO;
345out:
1a348ccc
AG		 346 if (master)
347 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
53c0ad52
JJ		 348
349 release_firmware(fw);
1a348ccc 350
06e1f9ff 351 if (rc) {
865a21a5 352 netdev_err(priv->ndev, "firmware loading failed\n");
06e1f9ff
BH		 353 if (rc == -EIO)
354 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
355 READ_REG(priv, regVPC),
356 READ_REG(priv, regVIC),
357 READ_REG(priv, regINIT_STATUS), i);
358 RET(rc);
1a348ccc
AG		 359 } else {
360 DBG("%s: firmware loading success\n", priv->ndev->name);
361 RET(0);
362 }
363}
364
365static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
366{
367 u32 val;
368
369 ENTER;
370 DBG("mac0=%x mac1=%x mac2=%x\n",
371 READ_REG(priv, regUNC_MAC0_A),
372 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
373
374 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
375 WRITE_REG(priv, regUNC_MAC2_A, val);
376 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
377 WRITE_REG(priv, regUNC_MAC1_A, val);
378 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
379 WRITE_REG(priv, regUNC_MAC0_A, val);
380
381 DBG("mac0=%x mac1=%x mac2=%x\n",
382 READ_REG(priv, regUNC_MAC0_A),
383 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
384 RET();
385}
386
49ce9c2c
BH		 387/**
388 * bdx_hw_start - inits registers and starts HW's Rx and Tx engines
389 * @priv: NIC private structure
1a348ccc
AG		 390 */
391static int bdx_hw_start(struct bdx_priv *priv)
392{
393 int rc = -EIO;
394 struct net_device *ndev = priv->ndev;
395
396 ENTER;
397 bdx_link_changed(priv);
398
399 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
400 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
401 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
402 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
403 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
404 WRITE_REG(priv, regRX_FULLNESS, 0);
405 WRITE_REG(priv, regTX_FULLNESS, 0);
406 WRITE_REG(priv, regCTRLST,
407 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
408
409 WRITE_REG(priv, regVGLB, 0);
410 WRITE_REG(priv, regMAX_FRAME_A,
411 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
412
413 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
414 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
415 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
416
417 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
418 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
419
420 /* Enable timer interrupt once in 2 secs. */
421 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
422 bdx_restore_mac(priv->ndev, priv);
423
424 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
425 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
426
249658d5 427#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
cb001a1f
JP		 428
429 rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
430 ndev->name, ndev);
431 if (rc)
1a348ccc
AG		 432 goto err_irq;
433 bdx_enable_interrupts(priv);
434
435 RET(0);
436
437err_irq:
438 RET(rc);
439}
440
441static void bdx_hw_stop(struct bdx_priv *priv)
442{
443 ENTER;
444 bdx_disable_interrupts(priv);
445 free_irq(priv->pdev->irq, priv->ndev);
446
447 netif_carrier_off(priv->ndev);
448 netif_stop_queue(priv->ndev);
449
450 RET();
451}
452
453static int bdx_hw_reset_direct(void __iomem *regs)
454{
455 u32 val, i;
456 ENTER;
457
458 /* reset sequences: read, write 1, read, write 0 */
459 val = readl(regs + regCLKPLL);
460 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
461 udelay(50);
462 val = readl(regs + regCLKPLL);
463 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
464
465 /* check that the PLLs are locked and reset ended */
466 for (i = 0; i < 70; i++, mdelay(10))
467 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
468 /* do any PCI-E read transaction */
469 readl(regs + regRXD_CFG0_0);
470 return 0;
471 }
865a21a5 472 pr_err("HW reset failed\n");
1a348ccc
AG		 473 return 1; /* failure */
474}
475
476static int bdx_hw_reset(struct bdx_priv *priv)
477{
478 u32 val, i;
479 ENTER;
480
481 if (priv->port == 0) {
482 /* reset sequences: read, write 1, read, write 0 */
483 val = READ_REG(priv, regCLKPLL);
484 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
485 udelay(50);
486 val = READ_REG(priv, regCLKPLL);
487 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
488 }
489 /* check that the PLLs are locked and reset ended */
490 for (i = 0; i < 70; i++, mdelay(10))
491 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
492 /* do any PCI-E read transaction */
493 READ_REG(priv, regRXD_CFG0_0);
494 return 0;
495 }
865a21a5 496 pr_err("HW reset failed\n");
1a348ccc
AG		 497 return 1; /* failure */
498}
499
500static int bdx_sw_reset(struct bdx_priv *priv)
501{
502 int i;
503
504 ENTER;
505 /* 1. load MAC (obsolete) */
506 /* 2. disable Rx (and Tx) */
507 WRITE_REG(priv, regGMAC_RXF_A, 0);
508 mdelay(100);
509 /* 3. disable port */
510 WRITE_REG(priv, regDIS_PORT, 1);
511 /* 4. disable queue */
512 WRITE_REG(priv, regDIS_QU, 1);
513 /* 5. wait until hw is disabled */
514 for (i = 0; i < 50; i++) {
515 if (READ_REG(priv, regRST_PORT) & 1)
516 break;
517 mdelay(10);
518 }
519 if (i == 50)
865a21a5 520 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
1a348ccc
AG		 521
522 /* 6. disable intrs */
523 WRITE_REG(priv, regRDINTCM0, 0);
524 WRITE_REG(priv, regTDINTCM0, 0);
525 WRITE_REG(priv, regIMR, 0);
526 READ_REG(priv, regISR);
527
528 /* 7. reset queue */
529 WRITE_REG(priv, regRST_QU, 1);
530 /* 8. reset port */
531 WRITE_REG(priv, regRST_PORT, 1);
532 /* 9. zero all read and write pointers */
533 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
534 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
535 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
536 WRITE_REG(priv, i, 0);
537 /* 10. unseet port disable */
538 WRITE_REG(priv, regDIS_PORT, 0);
539 /* 11. unset queue disable */
540 WRITE_REG(priv, regDIS_QU, 0);
541 /* 12. unset queue reset */
542 WRITE_REG(priv, regRST_QU, 0);
543 /* 13. unset port reset */
544 WRITE_REG(priv, regRST_PORT, 0);
545 /* 14. enable Rx */
546 /* skiped. will be done later */
547 /* 15. save MAC (obsolete) */
548 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
549 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
550
551 RET(0);
552}
553
554/* bdx_reset - performs right type of reset depending on hw type */
555static int bdx_reset(struct bdx_priv *priv)
556{
557 ENTER;
558 RET((priv->pdev->device == 0x3009)
559 ? bdx_hw_reset(priv)
560 : bdx_sw_reset(priv));
561}
562
563/**
564 * bdx_close - Disables a network interface
565 * @netdev: network interface device structure
566 *
567 * Returns 0, this is not allowed to fail
568 *
569 * The close entry point is called when an interface is de-activated
570 * by the OS. The hardware is still under the drivers control, but
571 * needs to be disabled. A global MAC reset is issued to stop the
572 * hardware, and all transmit and receive resources are freed.
573 **/
574static int bdx_close(struct net_device *ndev)
575{
576 struct bdx_priv *priv = NULL;
577
578 ENTER;
8f15ea42 579 priv = netdev_priv(ndev);
1a348ccc
AG		 580
581 napi_disable(&priv->napi);
582
583 bdx_reset(priv);
584 bdx_hw_stop(priv);
585 bdx_rx_free(priv);
586 bdx_tx_free(priv);
587 RET(0);
588}
589
590/**
591 * bdx_open - Called when a network interface is made active
592 * @netdev: network interface device structure
593 *
594 * Returns 0 on success, negative value on failure
595 *
596 * The open entry point is called when a network interface is made
597 * active by the system (IFF_UP). At this point all resources needed
598 * for transmit and receive operations are allocated, the interrupt
599 * handler is registered with the OS, the watchdog timer is started,
600 * and the stack is notified that the interface is ready.
601 **/
602static int bdx_open(struct net_device *ndev)
603{
604 struct bdx_priv *priv;
605 int rc;
606
607 ENTER;
8f15ea42 608 priv = netdev_priv(ndev);
1a348ccc
AG		 609 bdx_reset(priv);
610 if (netif_running(ndev))
611 netif_stop_queue(priv->ndev);
612
cb001a1f
JP		 613 if ((rc = bdx_tx_init(priv)) ||
614 (rc = bdx_rx_init(priv)) ||
615 (rc = bdx_fw_load(priv)))
1a348ccc
AG		 616 goto err;
617
618 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
619
cb001a1f
JP		 620 rc = bdx_hw_start(priv);
621 if (rc)
1a348ccc
AG		 622 goto err;
623
624 napi_enable(&priv->napi);
625
626 print_fw_id(priv->nic);
627
628 RET(0);
629
630err:
631 bdx_close(ndev);
632 RET(rc);
633}
634
6131a260
FR		 635static int bdx_range_check(struct bdx_priv *priv, u32 offset)
636{
637 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
638 -EINVAL : 0;
639}
640
1a348ccc
AG		 641static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
642{
8f15ea42 643 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 644 u32 data[3];
645 int error;
646
647 ENTER;
648
649 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
650 if (cmd != SIOCDEVPRIVATE) {
651 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
652 if (error) {
25985edc 653 pr_err("can't copy from user\n");
d2338070 654 RET(-EFAULT);
1a348ccc
AG		 655 }
656 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
657 }
658
62035542 659 if (!capable(CAP_SYS_RAWIO))
f946dffe
JG		 660 return -EPERM;
661
1a348ccc
AG		 662 switch (data[0]) {
663
664 case BDX_OP_READ:
6131a260
FR		 665 error = bdx_range_check(priv, data[1]);
666 if (error < 0)
667 return error;
1a348ccc
AG		 668 data[2] = READ_REG(priv, data[1]);
669 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
670 data[2]);
671 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
672 if (error)
d2338070 673 RET(-EFAULT);
1a348ccc
AG		 674 break;
675
676 case BDX_OP_WRITE:
6131a260
FR		 677 error = bdx_range_check(priv, data[1]);
678 if (error < 0)
679 return error;
1a348ccc
AG		 680 WRITE_REG(priv, data[1], data[2]);
681 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
682 break;
683
684 default:
685 RET(-EOPNOTSUPP);
686 }
687 return 0;
688}
689
690static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
691{
692 ENTER;
693 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
694 RET(bdx_ioctl_priv(ndev, ifr, cmd));
695 else
696 RET(-EOPNOTSUPP);
697}
698
49ce9c2c 699/**
1a348ccc 700 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
49ce9c2c
BH		 701 * @ndev: network device
702 * @vid: VLAN vid
703 * @op: add or kill operation
704 *
705 * Passes VLAN filter table to hardware
1a348ccc
AG		 706 */
707static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
708{
8f15ea42 709 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 710 u32 reg, bit, val;
711
712 ENTER;
713 DBG2("vid=%d value=%d\n", (int)vid, enable);
714 if (unlikely(vid >= 4096)) {
865a21a5 715 pr_err("invalid VID: %u (> 4096)\n", vid);
1a348ccc
AG		 716 RET();
717 }
718 reg = regVLAN_0 + (vid / 32) * 4;
719 bit = 1 << vid % 32;
720 val = READ_REG(priv, reg);
721 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
722 if (enable)
723 val |= bit;
724 else
725 val &= ~bit;
726 DBG2("new val %x\n", val);
727 WRITE_REG(priv, reg, val);
728 RET();
729}
730
49ce9c2c 731/**
1a348ccc 732 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
49ce9c2c
BH		 733 * @ndev: network device
734 * @vid: VLAN vid to add
1a348ccc 735 */
80d5c368 736static int bdx_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
1a348ccc
AG		 737{
738 __bdx_vlan_rx_vid(ndev, vid, 1);
8e586137 739 return 0;
1a348ccc
AG		 740}
741
49ce9c2c 742/**
1a348ccc 743 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
49ce9c2c
BH		 744 * @ndev: network device
745 * @vid: VLAN vid to kill
1a348ccc 746 */
80d5c368 747static int bdx_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
1a348ccc
AG		 748{
749 __bdx_vlan_rx_vid(ndev, vid, 0);
8e586137 750 return 0;
1a348ccc
AG		 751}
752
1a348ccc
AG		 753/**
754 * bdx_change_mtu - Change the Maximum Transfer Unit
755 * @netdev: network interface device structure
756 * @new_mtu: new value for maximum frame size
757 *
758 * Returns 0 on success, negative on failure
759 */
760static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
761{
1a348ccc
AG		 762 ENTER;
763
764 if (new_mtu == ndev->mtu)
765 RET(0);
766
767 /* enforce minimum frame size */
768 if (new_mtu < ETH_ZLEN) {
865a21a5
JP		 769 netdev_err(ndev, "mtu %d is less then minimal %d\n",
770 new_mtu, ETH_ZLEN);
1a348ccc
AG		 771 RET(-EINVAL);
772 }
773
774 ndev->mtu = new_mtu;
775 if (netif_running(ndev)) {
776 bdx_close(ndev);
777 bdx_open(ndev);
778 }
779 RET(0);
780}
781
782static void bdx_setmulti(struct net_device *ndev)
783{
8f15ea42 784 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 785
786 u32 rxf_val =
787 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
788 int i;
789
790 ENTER;
791 /* IMF - imperfect (hash) rx multicat filter */
792 /* PMF - perfect rx multicat filter */
793
794 /* FIXME: RXE(OFF) */
795 if (ndev->flags & IFF_PROMISC) {
796 rxf_val |= GMAC_RX_FILTER_PRM;
797 } else if (ndev->flags & IFF_ALLMULTI) {
798 /* set IMF to accept all multicast frmaes */
799 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
800 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
4cd24eaf 801 } else if (!netdev_mc_empty(ndev)) {
1a348ccc 802 u8 hash;
22bedad3 803 struct netdev_hw_addr *ha;
1a348ccc
AG		 804 u32 reg, val;
805
806 /* set IMF to deny all multicast frames */
807 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
808 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
809 /* set PMF to deny all multicast frames */
810 for (i = 0; i < MAC_MCST_NUM; i++) {
811 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
812 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
813 }
814
815 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
b595076a 816 /* TBD: sort addresses and write them in ascending order
1a348ccc
AG		 817 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
818 * multicast frames throu IMF */
1a348ccc 819 /* accept the rest of addresses throu IMF */
22bedad3 820 netdev_for_each_mc_addr(ha, ndev) {
1a348ccc
AG		 821 hash = 0;
822 for (i = 0; i < ETH_ALEN; i++)
22bedad3 823 hash ^= ha->addr[i];
1a348ccc
AG		 824 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
825 val = READ_REG(priv, reg);
826 val |= (1 << (hash % 32));
827 WRITE_REG(priv, reg, val);
828 }
829
830 } else {
4cd24eaf 831 DBG("only own mac %d\n", netdev_mc_count(ndev));
1a348ccc
AG		 832 rxf_val |= GMAC_RX_FILTER_AB;
833 }
834 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
835 /* enable RX */
836 /* FIXME: RXE(ON) */
837 RET();
838}
839
840static int bdx_set_mac(struct net_device *ndev, void *p)
841{
8f15ea42 842 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 843 struct sockaddr *addr = p;
844
845 ENTER;
846 /*
847 if (netif_running(dev))
848 return -EBUSY
849 */
850 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
851 bdx_restore_mac(ndev, priv);
852 RET(0);
853}
854
855static int bdx_read_mac(struct bdx_priv *priv)
856{
857 u16 macAddress[3], i;
858 ENTER;
859
860 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
861 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
862 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
863 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
864 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
865 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
866 for (i = 0; i < 3; i++) {
867 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
868 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
869 }
870 RET(0);
871}
872
873static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
874{
875 u64 val;
876
877 val = READ_REG(priv, reg);
878 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
879 return val;
880}
881
882/*Do the statistics-update work*/
883static void bdx_update_stats(struct bdx_priv *priv)
884{
885 struct bdx_stats *stats = &priv->hw_stats;
886 u64 *stats_vector = (u64 *) stats;
887 int i;
888 int addr;
889
890 /*Fill HW structure */
891 addr = 0x7200;
892 /*First 12 statistics - 0x7200 - 0x72B0 */
893 for (i = 0; i < 12; i++) {
894 stats_vector[i] = bdx_read_l2stat(priv, addr);
895 addr += 0x10;
896 }
897 BDX_ASSERT(addr != 0x72C0);
898 /* 0x72C0-0x72E0 RSRV */
899 addr = 0x72F0;
900 for (; i < 16; i++) {
901 stats_vector[i] = bdx_read_l2stat(priv, addr);
902 addr += 0x10;
903 }
904 BDX_ASSERT(addr != 0x7330);
905 /* 0x7330-0x7360 RSRV */
906 addr = 0x7370;
907 for (; i < 19; i++) {
908 stats_vector[i] = bdx_read_l2stat(priv, addr);
909 addr += 0x10;
910 }
911 BDX_ASSERT(addr != 0x73A0);
912 /* 0x73A0-0x73B0 RSRV */
913 addr = 0x73C0;
914 for (; i < 23; i++) {
915 stats_vector[i] = bdx_read_l2stat(priv, addr);
916 addr += 0x10;
917 }
918 BDX_ASSERT(addr != 0x7400);
919 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
920}
921
1a348ccc
AG		 922static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
923 u16 rxd_vlan);
924static void print_rxfd(struct rxf_desc *rxfd);
925
926/*************************************************************************
927 * Rx DB *
928 *************************************************************************/
929
930static void bdx_rxdb_destroy(struct rxdb *db)
931{
c0feed87 932 vfree(db);
1a348ccc
AG		 933}
934
935static struct rxdb *bdx_rxdb_create(int nelem)
936{
937 struct rxdb *db;
938 int i;
939
940 db = vmalloc(sizeof(struct rxdb)
941 + (nelem * sizeof(int))
942 + (nelem * sizeof(struct rx_map)));
943 if (likely(db != NULL)) {
944 db->stack = (int *)(db + 1);
945 db->elems = (void *)(db->stack + nelem);
946 db->nelem = nelem;
947 db->top = nelem;
948 for (i = 0; i < nelem; i++)
949 db->stack[i] = nelem - i - 1; /* to make first allocs
950 close to db struct*/
951 }
952
953 return db;
954}
955
956static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
957{
958 BDX_ASSERT(db->top <= 0);
959 return db->stack[--(db->top)];
960}
961
962static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
963{
964 BDX_ASSERT((n < 0) || (n >= db->nelem));
965 return db->elems + n;
966}
967
968static inline int bdx_rxdb_available(struct rxdb *db)
969{
970 return db->top;
971}
972
973static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
974{
975 BDX_ASSERT((n >= db->nelem) || (n < 0));
976 db->stack[(db->top)++] = n;
977}
978
979/*************************************************************************
980 * Rx Init *
981 *************************************************************************/
982
49ce9c2c
BH		 983/**
984 * bdx_rx_init - initialize RX all related HW and SW resources
985 * @priv: NIC private structure
1a348ccc
AG		 986 *
987 * Returns 0 on success, negative value on failure
988 *
989 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
990 * skb for rx. It assumes that Rx is desabled in HW
991 * funcs are grouped for better cache usage
992 *
025dfdaf 993 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
1a348ccc 994 * filled and packets will be dropped by nic without getting into host or
25985edc 995 * cousing interrupt. Anyway, in that condition, host has no chance to process
1a348ccc
AG		 996 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
997 */
998
999/* TBD: ensure proper packet size */
1000
1001static int bdx_rx_init(struct bdx_priv *priv)
1002{
1003 ENTER;
ddfce6bb 1004
1a348ccc
AG		 1005 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
1006 regRXD_CFG0_0, regRXD_CFG1_0,
1007 regRXD_RPTR_0, regRXD_WPTR_0))
1008 goto err_mem;
1009 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1010 regRXF_CFG0_0, regRXF_CFG1_0,
1011 regRXF_RPTR_0, regRXF_WPTR_0))
1012 goto err_mem;
cb001a1f
JP		 1013 priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1014 sizeof(struct rxf_desc));
1015 if (!priv->rxdb)
1a348ccc
AG		 1016 goto err_mem;
1017
1018 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1019 return 0;
1020
1021err_mem:
865a21a5 1022 netdev_err(priv->ndev, "Rx init failed\n");
1a348ccc
AG		 1023 return -ENOMEM;
1024}
1025
49ce9c2c
BH		 1026/**
1027 * bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1028 * @priv: NIC private structure
1029 * @f: RXF fifo
1a348ccc
AG		 1030 */
1031static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1032{
1033 struct rx_map *dm;
1034 struct rxdb *db = priv->rxdb;
1035 u16 i;
1036
1037 ENTER;
1038 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1039 db->nelem - bdx_rxdb_available(db));
1040 while (bdx_rxdb_available(db) > 0) {
1041 i = bdx_rxdb_alloc_elem(db);
1042 dm = bdx_rxdb_addr_elem(db, i);
1043 dm->dma = 0;
1044 }
1045 for (i = 0; i < db->nelem; i++) {
1046 dm = bdx_rxdb_addr_elem(db, i);
1047 if (dm->dma) {
1048 pci_unmap_single(priv->pdev,
1049 dm->dma, f->m.pktsz,
1050 PCI_DMA_FROMDEVICE);
1051 dev_kfree_skb(dm->skb);
1052 }
1053 }
1054}
1055
49ce9c2c
BH		 1056/**
1057 * bdx_rx_free - release all Rx resources
1058 * @priv: NIC private structure
1059 *
1a348ccc
AG		 1060 * It assumes that Rx is desabled in HW
1061 */
1062static void bdx_rx_free(struct bdx_priv *priv)
1063{
1064 ENTER;
1065 if (priv->rxdb) {
1066 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1067 bdx_rxdb_destroy(priv->rxdb);
1068 priv->rxdb = NULL;
1069 }
1070 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1071 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1072
1073 RET();
1074}
1075
1076/*************************************************************************
1077 * Rx Engine *
1078 *************************************************************************/
1079
49ce9c2c
BH		 1080/**
1081 * bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1082 * @priv: nic's private structure
1083 * @f: RXF fifo that needs skbs
1084 *
1a348ccc
AG		 1085 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1086 * skb's virtual and physical addresses are stored in skb db.
1087 * To calculate free space, func uses cached values of RPTR and WPTR
1088 * When needed, it also updates RPTR and WPTR.
1089 */
1090
1091/* TBD: do not update WPTR if no desc were written */
1092
1093static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1094{
1095 struct sk_buff *skb;
1096 struct rxf_desc *rxfd;
1097 struct rx_map *dm;
1098 int dno, delta, idx;
1099 struct rxdb *db = priv->rxdb;
1100
1101 ENTER;
1102 dno = bdx_rxdb_available(db) - 1;
1103 while (dno > 0) {
dae2e9f4 1104 skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN);
720a43ef 1105 if (!skb)
1a348ccc 1106 break;
720a43ef 1107
1a348ccc
AG		 1108 skb_reserve(skb, NET_IP_ALIGN);
1109
1110 idx = bdx_rxdb_alloc_elem(db);
1111 dm = bdx_rxdb_addr_elem(db, idx);
1112 dm->dma = pci_map_single(priv->pdev,
1113 skb->data, f->m.pktsz,
1114 PCI_DMA_FROMDEVICE);
1115 dm->skb = skb;
1116 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1117 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1118 rxfd->va_lo = idx;
1119 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1120 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1121 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1122 print_rxfd(rxfd);
1123
1124 f->m.wptr += sizeof(struct rxf_desc);
1125 delta = f->m.wptr - f->m.memsz;
1126 if (unlikely(delta >= 0)) {
1127 f->m.wptr = delta;
1128 if (delta > 0) {
1129 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1130 DBG("wrapped descriptor\n");
1131 }
1132 }
1133 dno--;
1134 }
1135 /*TBD: to do - delayed rxf wptr like in txd */
1136 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1137 RET();
1138}
1139
1140static inline void
1141NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1142 struct sk_buff *skb)
1143{
1144 ENTER;
312cd513
JP		 1145 DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1));
1146 if (GET_RXD_VTAG(rxd_val1)) {
1147 DBG("%s: vlan rcv vlan '%x' vtag '%x'\n",
1a348ccc
AG		 1148 priv->ndev->name,
1149 GET_RXD_VLAN_ID(rxd_vlan),
312cd513 1150 GET_RXD_VTAG(rxd_val1));
86a9bad3 1151 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), GET_RXD_VLAN_TCI(rxd_vlan));
1a348ccc 1152 }
312cd513 1153 netif_receive_skb(skb);
1a348ccc
AG		 1154}
1155
1156static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1157{
1158 struct rxf_desc *rxfd;
1159 struct rx_map *dm;
1160 struct rxf_fifo *f;
1161 struct rxdb *db;
1162 struct sk_buff *skb;
1163 int delta;
1164
1165 ENTER;
1166 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1167 f = &priv->rxf_fifo0;
1168 db = priv->rxdb;
1169 DBG("db=%p f=%p\n", db, f);
1170 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1171 DBG("dm=%p\n", dm);
1172 skb = dm->skb;
1173 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1174 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1175 rxfd->va_lo = rxdd->va_lo;
1176 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1177 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1178 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1179 print_rxfd(rxfd);
1180
1181 f->m.wptr += sizeof(struct rxf_desc);
1182 delta = f->m.wptr - f->m.memsz;
1183 if (unlikely(delta >= 0)) {
1184 f->m.wptr = delta;
1185 if (delta > 0) {
1186 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1187 DBG("wrapped descriptor\n");
1188 }
1189 }
1190 RET();
1191}
1192
49ce9c2c
BH		 1193/**
1194 * bdx_rx_receive - receives full packets from RXD fifo and pass them to OS
25985edc 1195 * NOTE: a special treatment is given to non-continuous descriptors
1a348ccc
AG		 1196 * that start near the end, wraps around and continue at the beginning. a second
1197 * part is copied right after the first, and then descriptor is interpreted as
1198 * normal. fifo has an extra space to allow such operations
49ce9c2c
BH		 1199 * @priv: nic's private structure
1200 * @f: RXF fifo that needs skbs
1201 * @budget: maximum number of packets to receive
1a348ccc
AG		 1202 */
1203
1204/* TBD: replace memcpy func call by explicite inline asm */
1205
1206static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1207{
0add79e3 1208 struct net_device *ndev = priv->ndev;
1a348ccc
AG		 1209 struct sk_buff *skb, *skb2;
1210 struct rxd_desc *rxdd;
1211 struct rx_map *dm;
1212 struct rxf_fifo *rxf_fifo;
1213 int tmp_len, size;
1214 int done = 0;
1215 int max_done = BDX_MAX_RX_DONE;
1216 struct rxdb *db = NULL;
1217 /* Unmarshalled descriptor - copy of descriptor in host order */
1218 u32 rxd_val1;
1219 u16 len;
1220 u16 rxd_vlan;
1221
1222 ENTER;
1223 max_done = budget;
1224
1a348ccc
AG		 1225 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1226
1227 size = f->m.wptr - f->m.rptr;
1228 if (size < 0)
1229 size = f->m.memsz + size; /* size is negative :-) */
1230
1231 while (size > 0) {
1232
1233 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1234 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1235
1236 len = CPU_CHIP_SWAP16(rxdd->len);
1237
1238 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1239
1240 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1241
1242 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1243 BDX_ASSERT(tmp_len <= 0);
1244 size -= tmp_len;
1245 if (size < 0) /* test for partially arrived descriptor */
1246 break;
1247
1248 f->m.rptr += tmp_len;
1249
1250 tmp_len = f->m.rptr - f->m.memsz;
1251 if (unlikely(tmp_len >= 0)) {
1252 f->m.rptr = tmp_len;
1253 if (tmp_len > 0) {
1254 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1255 f->m.rptr, tmp_len);
1256 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1257 }
1258 }
1259
1260 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1261 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
0add79e3 1262 ndev->stats.rx_errors++;
1a348ccc
AG		 1263 bdx_recycle_skb(priv, rxdd);
1264 continue;
1265 }
1266
1267 rxf_fifo = &priv->rxf_fifo0;
1268 db = priv->rxdb;
1269 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1270 skb = dm->skb;
1271
1272 if (len < BDX_COPYBREAK &&
dae2e9f4 1273 (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) {
1a348ccc
AG		 1274 skb_reserve(skb2, NET_IP_ALIGN);
1275 /*skb_put(skb2, len); */
1276 pci_dma_sync_single_for_cpu(priv->pdev,
1277 dm->dma, rxf_fifo->m.pktsz,
1278 PCI_DMA_FROMDEVICE);
1279 memcpy(skb2->data, skb->data, len);
1280 bdx_recycle_skb(priv, rxdd);
1281 skb = skb2;
1282 } else {
1283 pci_unmap_single(priv->pdev,
1284 dm->dma, rxf_fifo->m.pktsz,
1285 PCI_DMA_FROMDEVICE);
1286 bdx_rxdb_free_elem(db, rxdd->va_lo);
1287 }
1288
0add79e3 1289 ndev->stats.rx_bytes += len;
1a348ccc
AG		 1290
1291 skb_put(skb, len);
0add79e3 1292 skb->protocol = eth_type_trans(skb, ndev);
1a348ccc
AG		 1293
1294 /* Non-IP packets aren't checksum-offloaded */
1295 if (GET_RXD_PKT_ID(rxd_val1) == 0)
bc8acf2c
ED		 1296 skb_checksum_none_assert(skb);
1297 else
1298 skb->ip_summed = CHECKSUM_UNNECESSARY;
1a348ccc
AG		 1299
1300 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1301
1302 if (++done >= max_done)
1303 break;
1304 }
1305
0add79e3 1306 ndev->stats.rx_packets += done;
1a348ccc
AG		 1307
1308 /* FIXME: do smth to minimize pci accesses */
1309 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1310
1311 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1312
1313 RET(done);
1314}
1315
1316/*************************************************************************
1317 * Debug / Temprorary Code *
1318 *************************************************************************/
1319static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1320 u16 rxd_vlan)
1321{
865a21a5 1322 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1a348ccc
AG		 1323 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1324 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1325 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1326 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1327 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1328 rxdd->va_hi);
1329}
1330
1331static void print_rxfd(struct rxf_desc *rxfd)
1332{
fd9071ec 1333 DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n"
1a348ccc
AG		 1334 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1335 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1336}
1337
1338/*
1339 * TX HW/SW interaction overview
1340 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
b595076a 1341 * There are 2 types of TX communication channels between driver and NIC.
1a348ccc
AG		 1342 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1343 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1344 *
1345 * Currently NIC supports TSO, checksuming and gather DMA
1346 * UFO and IP fragmentation is on the way
1347 *
1348 * RX SW Data Structures
1349 * ~~~~~~~~~~~~~~~~~~~~~
1350 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1351 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1352 * acknowledges sent by TXF descriptors.
1353 * Implemented as cyclic buffer.
1354 * fifo - keeps info about fifo's size and location, relevant HW registers,
1355 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1356 * Implemented as simple struct.
1357 *
1358 * TX SW Execution Flow
1359 * ~~~~~~~~~~~~~~~~~~~~
1360 * OS calls driver's hard_xmit method with packet to sent.
1361 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1362 * by updating TXD WPTR.
1363 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1364 * To prevent TXD fifo overflow without reading HW registers every time,
1365 * SW deploys "tx level" technique.
1366 * Upon strart up, tx level is initialized to TXD fifo length.
1367 * For every sent packet, SW gets its TXD descriptor sizei
1368 * (from precalculated array) and substructs it from tx level.
1369 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1370 * original TXD descriptor from txdb and adds it to tx level.
1371 * When Tx level drops under some predefined treshhold, the driver
1372 * stops the TX queue. When TX level rises above that level,
1373 * the tx queue is enabled again.
1374 *
1375 * This technique avoids eccessive reading of RPTR and WPTR registers.
1376 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1377 */
1378
1379/*************************************************************************
1380 * Tx DB *
1381 *************************************************************************/
1382static inline int bdx_tx_db_size(struct txdb *db)
1383{
1384 int taken = db->wptr - db->rptr;
1385 if (taken < 0)
1386 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1387
1388 return db->size - taken;
1389}
1390
49ce9c2c
BH		 1391/**
1392 * __bdx_tx_db_ptr_next - helper function, increment read/write pointer + wrap
1393 * @db: tx data base
1394 * @pptr: read or write pointer
1a348ccc
AG		 1395 */
1396static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1397{
1398 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1399
1400 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1401 *pptr != db->wptr); /* or write pointer */
1402
1403 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1404 *pptr >= db->end); /* in range */
1405
1406 ++*pptr;
1407 if (unlikely(*pptr == db->end))
1408 *pptr = db->start;
1409}
1410
49ce9c2c
BH		 1411/**
1412 * bdx_tx_db_inc_rptr - increment read pointer
1413 * @db: tx data base
1a348ccc
AG		 1414 */
1415static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1416{
1417 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1418 __bdx_tx_db_ptr_next(db, &db->rptr);
1419}
1420
49ce9c2c
BH		 1421/**
1422 * bdx_tx_db_inc_wptr - increment write pointer
1423 * @db: tx data base
1a348ccc
AG		 1424 */
1425static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1426{
1427 __bdx_tx_db_ptr_next(db, &db->wptr);
1428 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1429 a result of write */
1430}
1431
49ce9c2c
BH		 1432/**
1433 * bdx_tx_db_init - creates and initializes tx db
1434 * @d: tx data base
1435 * @sz_type: size of tx fifo
1436 *
1a348ccc
AG		 1437 * Returns 0 on success, error code otherwise
1438 */
1439static int bdx_tx_db_init(struct txdb *d, int sz_type)
1440{
1441 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1442
1443 d->start = vmalloc(memsz);
1444 if (!d->start)
1445 return -ENOMEM;
1446
1447 /*
1448 * In order to differentiate between db is empty and db is full
1449 * states at least one element should always be empty in order to
1450 * avoid rptr == wptr which means db is empty
1451 */
1452 d->size = memsz / sizeof(struct tx_map) - 1;
1453 d->end = d->start + d->size + 1; /* just after last element */
1454
1455 /* all dbs are created equally empty */
1456 d->rptr = d->start;
1457 d->wptr = d->start;
1458
1459 return 0;
1460}
1461
49ce9c2c
BH		 1462/**
1463 * bdx_tx_db_close - closes tx db and frees all memory
1464 * @d: tx data base
1a348ccc
AG		 1465 */
1466static void bdx_tx_db_close(struct txdb *d)
1467{
1468 BDX_ASSERT(d == NULL);
1469
c0feed87
F		 1470 vfree(d->start);
1471 d->start = NULL;
1a348ccc
AG		 1472}
1473
1474/*************************************************************************
1475 * Tx Engine *
1476 *************************************************************************/
1477
1478/* sizes of tx desc (including padding if needed) as function
1479 * of skb's frag number */
1480static struct {
1481 u16 bytes;
1482 u16 qwords; /* qword = 64 bit */
1483} txd_sizes[MAX_SKB_FRAGS + 1];
1484
49ce9c2c
BH		 1485/**
1486 * bdx_tx_map_skb - creates and stores dma mappings for skb's data blocks
1487 * @priv: NIC private structure
1488 * @skb: socket buffer to map
1489 * @txdd: TX descriptor to use
1a348ccc
AG		 1490 *
1491 * It makes dma mappings for skb's data blocks and writes them to PBL of
1492 * new tx descriptor. It also stores them in the tx db, so they could be
1493 * unmaped after data was sent. It is reponsibility of a caller to make
1494 * sure that there is enough space in the tx db. Last element holds pointer
1495 * to skb itself and marked with zero length
1496 */
1497static inline void
1498bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1499 struct txd_desc *txdd)
1500{
1501 struct txdb *db = &priv->txdb;
1502 struct pbl *pbl = &txdd->pbl[0];
1503 int nr_frags = skb_shinfo(skb)->nr_frags;
1504 int i;
1505
e743d313 1506 db->wptr->len = skb_headlen(skb);
1a348ccc
AG		 1507 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1508 db->wptr->len, PCI_DMA_TODEVICE);
1509 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1510 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1511 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1512 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1513 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1514 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1515 bdx_tx_db_inc_wptr(db);
1516
1517 for (i = 0; i < nr_frags; i++) {
9e903e08 1518 const struct skb_frag_struct *frag;
1a348ccc
AG		 1519
1520 frag = &skb_shinfo(skb)->frags[i];
9e903e08 1521 db->wptr->len = skb_frag_size(frag);
e4811086 1522 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
9e903e08 1523 0, skb_frag_size(frag),
5d6bcdfe 1524 DMA_TO_DEVICE);
1a348ccc
AG		 1525
1526 pbl++;
1527 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1528 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1529 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1530 bdx_tx_db_inc_wptr(db);
1531 }
1532
1533 /* add skb clean up info. */
1534 db->wptr->len = -txd_sizes[nr_frags].bytes;
1535 db->wptr->addr.skb = skb;
1536 bdx_tx_db_inc_wptr(db);
1537}
1538
1539/* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1540 * number of frags is used as index to fetch correct descriptors size,
1541 * instead of calculating it each time */
1542static void __init init_txd_sizes(void)
1543{
1544 int i, lwords;
1545
1546 /* 7 - is number of lwords in txd with one phys buffer
1547 * 3 - is number of lwords used for every additional phys buffer */
1548 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1549 lwords = 7 + (i * 3);
1550 if (lwords & 1)
1551 lwords++; /* pad it with 1 lword */
1552 txd_sizes[i].qwords = lwords >> 1;
1553 txd_sizes[i].bytes = lwords << 2;
1554 }
1555}
1556
1557/* bdx_tx_init - initialize all Tx related stuff.
1558 * Namely, TXD and TXF fifos, database etc */
1559static int bdx_tx_init(struct bdx_priv *priv)
1560{
1561 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1562 regTXD_CFG0_0,
1563 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1564 goto err_mem;
1565 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1566 regTXF_CFG0_0,
1567 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1568 goto err_mem;
1569
1570 /* The TX db has to keep mappings for all packets sent (on TxD)
1571 * and not yet reclaimed (on TxF) */
1572 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1573 goto err_mem;
1574
1575 priv->tx_level = BDX_MAX_TX_LEVEL;
1576#ifdef BDX_DELAY_WPTR
1577 priv->tx_update_mark = priv->tx_level - 1024;
1578#endif
1579 return 0;
1580
1581err_mem:
865a21a5 1582 netdev_err(priv->ndev, "Tx init failed\n");
1a348ccc
AG		 1583 return -ENOMEM;
1584}
1585
49ce9c2c 1586/**
25985edc 1587 * bdx_tx_space - calculates available space in TX fifo
49ce9c2c
BH		 1588 * @priv: NIC private structure
1589 *
25985edc 1590 * Returns available space in TX fifo in bytes
1a348ccc
AG		 1591 */
1592static inline int bdx_tx_space(struct bdx_priv *priv)
1593{
1594 struct txd_fifo *f = &priv->txd_fifo0;
1595 int fsize;
1596
1597 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1598 fsize = f->m.rptr - f->m.wptr;
1599 if (fsize <= 0)
1600 fsize = f->m.memsz + fsize;
249658d5 1601 return fsize;
1a348ccc
AG		 1602}
1603
49ce9c2c
BH		 1604/**
1605 * bdx_tx_transmit - send packet to NIC
1606 * @skb: packet to send
1607 * @ndev: network device assigned to NIC
1a348ccc
AG		 1608 * Return codes:
1609 * o NETDEV_TX_OK everything ok.
1610 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1611 * Usually a bug, means queue start/stop flow control is broken in
1612 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1a348ccc 1613 */
61357325
SH		 1614static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1615 struct net_device *ndev)
1a348ccc 1616{
8f15ea42 1617 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 1618 struct txd_fifo *f = &priv->txd_fifo0;
1619 int txd_checksum = 7; /* full checksum */
1620 int txd_lgsnd = 0;
1621 int txd_vlan_id = 0;
1622 int txd_vtag = 0;
1623 int txd_mss = 0;
1624
1625 int nr_frags = skb_shinfo(skb)->nr_frags;
1626 struct txd_desc *txdd;
1627 int len;
1628 unsigned long flags;
1629
1630 ENTER;
1631 local_irq_save(flags);
a6086a89 1632 spin_lock(&priv->tx_lock);
1a348ccc
AG		 1633
1634 /* build tx descriptor */
1635 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1636 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1637 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1638 txd_checksum = 0;
1639
1640 if (skb_shinfo(skb)->gso_size) {
1641 txd_mss = skb_shinfo(skb)->gso_size;
1642 txd_lgsnd = 1;
1643 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1644 txd_mss);
1645 }
1646
df8a39de 1647 if (skb_vlan_tag_present(skb)) {
1a348ccc 1648 /*Cut VLAN ID to 12 bits */
df8a39de 1649 txd_vlan_id = skb_vlan_tag_get(skb) & BITS_MASK(12);
1a348ccc
AG		 1650 txd_vtag = 1;
1651 }
1652
1653 txdd->length = CPU_CHIP_SWAP16(skb->len);
1654 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1655 txdd->txd_val1 =
1656 CPU_CHIP_SWAP32(TXD_W1_VAL
1657 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1658 txd_lgsnd, txd_vlan_id));
1659 DBG("=== TxD desc =====================\n");
1660 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1661 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1662
1663 bdx_tx_map_skb(priv, skb, txdd);
1664
1665 /* increment TXD write pointer. In case of
1666 fifo wrapping copy reminder of the descriptor
1667 to the beginning */
1668 f->m.wptr += txd_sizes[nr_frags].bytes;
1669 len = f->m.wptr - f->m.memsz;
1670 if (unlikely(len >= 0)) {
1671 f->m.wptr = len;
1672 if (len > 0) {
1673 BDX_ASSERT(len > f->m.memsz);
1674 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1675 }
1676 }
1677 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1678
1679 priv->tx_level -= txd_sizes[nr_frags].bytes;
1680 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1681#ifdef BDX_DELAY_WPTR
1682 if (priv->tx_level > priv->tx_update_mark) {
1683 /* Force memory writes to complete before letting h/w
1684 know there are new descriptors to fetch.
1685 (might be needed on platforms like IA64)
1686 wmb(); */
1687 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1688 } else {
1689 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1690 priv->tx_noupd = 0;
1691 WRITE_REG(priv, f->m.reg_WPTR,
1692 f->m.wptr & TXF_WPTR_WR_PTR);
1693 }
1694 }
1695#else
1696 /* Force memory writes to complete before letting h/w
1697 know there are new descriptors to fetch.
1698 (might be needed on platforms like IA64)
1699 wmb(); */
1700 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1701
1702#endif
28679751 1703#ifdef BDX_LLTX
860e9538 1704 netif_trans_update(ndev); /* NETIF_F_LLTX driver :( */
28679751 1705#endif
0add79e3
TK		 1706 ndev->stats.tx_packets++;
1707 ndev->stats.tx_bytes += skb->len;
1a348ccc
AG		 1708
1709 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1710 DBG("%s: %s: TX Q STOP level %d\n",
1711 BDX_DRV_NAME, ndev->name, priv->tx_level);
1712 netif_stop_queue(ndev);
1713 }
1714
1715 spin_unlock_irqrestore(&priv->tx_lock, flags);
1716 return NETDEV_TX_OK;
1717}
1718
49ce9c2c
BH		 1719/**
1720 * bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1721 * @priv: bdx adapter
1722 *
1a348ccc
AG		 1723 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1724 * that those packets were sent
1725 */
1726static void bdx_tx_cleanup(struct bdx_priv *priv)
1727{
1728 struct txf_fifo *f = &priv->txf_fifo0;
1729 struct txdb *db = &priv->txdb;
1730 int tx_level = 0;
1731
1732 ENTER;
1733 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1734 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1735
1736 while (f->m.wptr != f->m.rptr) {
1737 f->m.rptr += BDX_TXF_DESC_SZ;
1738 f->m.rptr &= f->m.size_mask;
1739
1740 /* unmap all the fragments */
1741 /* first has to come tx_maps containing dma */
1742 BDX_ASSERT(db->rptr->len == 0);
1743 do {
1744 BDX_ASSERT(db->rptr->addr.dma == 0);
1745 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1746 db->rptr->len, PCI_DMA_TODEVICE);
1747 bdx_tx_db_inc_rptr(db);
1748 } while (db->rptr->len > 0);
1749 tx_level -= db->rptr->len; /* '-' koz len is negative */
1750
1751 /* now should come skb pointer - free it */
1a348ccc
AG		 1752 dev_kfree_skb_irq(db->rptr->addr.skb);
1753 bdx_tx_db_inc_rptr(db);
1754 }
1755
1756 /* let h/w know which TXF descriptors were cleaned */
1757 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1758 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1759
1760 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
88bfe6ea 1761 * we resume the transmission and use tx_lock to synchronize with xmit.*/
1a348ccc
AG		 1762 spin_lock(&priv->tx_lock);
1763 priv->tx_level += tx_level;
1764 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1765#ifdef BDX_DELAY_WPTR
1766 if (priv->tx_noupd) {
1767 priv->tx_noupd = 0;
1768 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1769 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1770 }
1771#endif
1772
8e95a202
JP		 1773 if (unlikely(netif_queue_stopped(priv->ndev) &&
1774 netif_carrier_ok(priv->ndev) &&
1775 (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1a348ccc
AG		 1776 DBG("%s: %s: TX Q WAKE level %d\n",
1777 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1778 netif_wake_queue(priv->ndev);
1779 }
1780 spin_unlock(&priv->tx_lock);
1781}
1782
49ce9c2c
BH		 1783/**
1784 * bdx_tx_free_skbs - frees all skbs from TXD fifo.
1a348ccc
AG		 1785 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1786 */
1787static void bdx_tx_free_skbs(struct bdx_priv *priv)
1788{
1789 struct txdb *db = &priv->txdb;
1790
1791 ENTER;
1792 while (db->rptr != db->wptr) {
1793 if (likely(db->rptr->len))
1794 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1795 db->rptr->len, PCI_DMA_TODEVICE);
1796 else
1797 dev_kfree_skb(db->rptr->addr.skb);
1798 bdx_tx_db_inc_rptr(db);
1799 }
1800 RET();
1801}
1802
1803/* bdx_tx_free - frees all Tx resources */
1804static void bdx_tx_free(struct bdx_priv *priv)
1805{
1806 ENTER;
1807 bdx_tx_free_skbs(priv);
1808 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1809 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1810 bdx_tx_db_close(&priv->txdb);
1811}
1812
49ce9c2c
BH		 1813/**
1814 * bdx_tx_push_desc - push descriptor to TxD fifo
1815 * @priv: NIC private structure
1816 * @data: desc's data
1817 * @size: desc's size
1a348ccc
AG		 1818 *
1819 * Pushes desc to TxD fifo and overlaps it if needed.
1820 * NOTE: this func does not check for available space. this is responsibility
025dfdaf 1821 * of the caller. Neither does it check that data size is smaller than
1a348ccc
AG		 1822 * fifo size.
1823 */
1824static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1825{
1826 struct txd_fifo *f = &priv->txd_fifo0;
1827 int i = f->m.memsz - f->m.wptr;
1828
1829 if (size == 0)
1830 return;
1831
1832 if (i > size) {
1833 memcpy(f->m.va + f->m.wptr, data, size);
1834 f->m.wptr += size;
1835 } else {
1836 memcpy(f->m.va + f->m.wptr, data, i);
1837 f->m.wptr = size - i;
1838 memcpy(f->m.va, data + i, f->m.wptr);
1839 }
1840 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1841}
1842
49ce9c2c
BH		 1843/**
1844 * bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1845 * @priv: NIC private structure
1846 * @data: desc's data
1847 * @size: desc's size
1a348ccc 1848 *
3ad2f3fb 1849 * NOTE: this func does check for available space and, if necessary, waits for
1a348ccc
AG		 1850 * NIC to read existing data before writing new one.
1851 */
1852static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1853{
1854 int timer = 0;
1855 ENTER;
1856
1857 while (size > 0) {
1858 /* we substruct 8 because when fifo is full rptr == wptr
1859 which also means that fifo is empty, we can understand
1860 the difference, but could hw do the same ??? :) */
1861 int avail = bdx_tx_space(priv) - 8;
1862 if (avail <= 0) {
1863 if (timer++ > 300) { /* prevent endless loop */
1864 DBG("timeout while writing desc to TxD fifo\n");
1865 break;
1866 }
1867 udelay(50); /* give hw a chance to clean fifo */
1868 continue;
1869 }
df7641af 1870 avail = min(avail, size);
1a348ccc
AG		 1871 DBG("about to push %d bytes starting %p size %d\n", avail,
1872 data, size);
1873 bdx_tx_push_desc(priv, data, avail);
1874 size -= avail;
1875 data += avail;
1876 }
1877 RET();
1878}
1879
2f30b1f6 1880static const struct net_device_ops bdx_netdev_ops = {
312cd513 1881 .ndo_open = bdx_open,
2f30b1f6
SH		 1882 .ndo_stop = bdx_close,
1883 .ndo_start_xmit = bdx_tx_transmit,
1884 .ndo_validate_addr = eth_validate_addr,
1885 .ndo_do_ioctl = bdx_ioctl,
afc4b13d 1886 .ndo_set_rx_mode = bdx_setmulti,
2f30b1f6
SH		 1887 .ndo_change_mtu = bdx_change_mtu,
1888 .ndo_set_mac_address = bdx_set_mac,
2f30b1f6
SH		 1889 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
1890 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
1891};
1892
1a348ccc
AG		 1893/**
1894 * bdx_probe - Device Initialization Routine
1895 * @pdev: PCI device information struct
1896 * @ent: entry in bdx_pci_tbl
1897 *
1898 * Returns 0 on success, negative on failure
1899 *
1900 * bdx_probe initializes an adapter identified by a pci_dev structure.
1901 * The OS initialization, configuring of the adapter private structure,
1902 * and a hardware reset occur.
1903 *
1904 * functions and their order used as explained in
1905 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1906 *
1907 */
1908
1909/* TBD: netif_msg should be checked and implemented. I disable it for now */
17abe3e4 1910static int
1a348ccc
AG		 1911bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1912{
1913 struct net_device *ndev;
1914 struct bdx_priv *priv;
1915 int err, pci_using_dac, port;
1916 unsigned long pciaddr;
1917 u32 regionSize;
1918 struct pci_nic *nic;
1919
1920 ENTER;
1921
1922 nic = vmalloc(sizeof(*nic));
1923 if (!nic)
1924 RET(-ENOMEM);
1925
1926 /************** pci *****************/
cb001a1f
JP		 1927 err = pci_enable_device(pdev);
1928 if (err) /* it triggers interrupt, dunno why. */
1929 goto err_pci; /* it's not a problem though */
1a348ccc 1930
6a35528a
YH		 1931 if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) &&
1932 !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) {
1a348ccc
AG		 1933 pci_using_dac = 1;
1934 } else {
284901a9
YH		 1935 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1936 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
865a21a5 1937 pr_err("No usable DMA configuration, aborting\n");
1a348ccc
AG		 1938 goto err_dma;
1939 }
1940 pci_using_dac = 0;
1941 }
1942
cb001a1f
JP		 1943 err = pci_request_regions(pdev, BDX_DRV_NAME);
1944 if (err)
1a348ccc
AG		 1945 goto err_dma;
1946
1947 pci_set_master(pdev);
1948
1949 pciaddr = pci_resource_start(pdev, 0);
1950 if (!pciaddr) {
1951 err = -EIO;
865a21a5 1952 pr_err("no MMIO resource\n");
1a348ccc
AG		 1953 goto err_out_res;
1954 }
cb001a1f
JP		 1955 regionSize = pci_resource_len(pdev, 0);
1956 if (regionSize < BDX_REGS_SIZE) {
1a348ccc 1957 err = -EIO;
865a21a5 1958 pr_err("MMIO resource (%x) too small\n", regionSize);
1a348ccc
AG		 1959 goto err_out_res;
1960 }
1961
1962 nic->regs = ioremap(pciaddr, regionSize);
1963 if (!nic->regs) {
1964 err = -EIO;
865a21a5 1965 pr_err("ioremap failed\n");
1a348ccc
AG		 1966 goto err_out_res;
1967 }
1968
1969 if (pdev->irq < 2) {
1970 err = -EIO;
865a21a5 1971 pr_err("invalid irq (%d)\n", pdev->irq);
1a348ccc
AG		 1972 goto err_out_iomap;
1973 }
1974 pci_set_drvdata(pdev, nic);
1975
1976 if (pdev->device == 0x3014)
1977 nic->port_num = 2;
1978 else
1979 nic->port_num = 1;
1980
1981 print_hw_id(pdev);
1982
1983 bdx_hw_reset_direct(nic->regs);
1984
1985 nic->irq_type = IRQ_INTX;
1986#ifdef BDX_MSI
1987 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
cb001a1f
JP		 1988 err = pci_enable_msi(pdev);
1989 if (err)
d524d84b 1990 pr_err("Can't enable msi. error is %d\n", err);
1a348ccc
AG		 1991 else
1992 nic->irq_type = IRQ_MSI;
1993 } else
1994 DBG("HW does not support MSI\n");
1995#endif
1996
1997 /************** netdev **************/
1998 for (port = 0; port < nic->port_num; port++) {
cb001a1f
JP		 1999 ndev = alloc_etherdev(sizeof(struct bdx_priv));
2000 if (!ndev) {
1a348ccc 2001 err = -ENOMEM;
1a348ccc
AG		 2002 goto err_out_iomap;
2003 }
2004
2f30b1f6 2005 ndev->netdev_ops = &bdx_netdev_ops;
1a348ccc 2006 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1a348ccc 2007
c061b18d 2008 bdx_set_ethtool_ops(ndev); /* ethtool interface */
1a348ccc
AG		 2009
2010 /* these fields are used for info purposes only
2011 * so we can have them same for all ports of the board */
2012 ndev->if_port = port;
1a348ccc 2013 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
f646968f
PM		 2014 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2015 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXCSUM
1a348ccc 2016 ;
eea3250b 2017 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
f646968f 2018 NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX;
1a348ccc
AG		 2019
2020 if (pci_using_dac)
2021 ndev->features |= NETIF_F_HIGHDMA;
2022
2023 /************** priv ****************/
8f15ea42 2024 priv = nic->priv[port] = netdev_priv(ndev);
1a348ccc 2025
1a348ccc
AG		 2026 priv->pBdxRegs = nic->regs + port * 0x8000;
2027 priv->port = port;
2028 priv->pdev = pdev;
2029 priv->ndev = ndev;
2030 priv->nic = nic;
2031 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2032
2033 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2034
2035 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2036 DBG("HW statistics not supported\n");
2037 priv->stats_flag = 0;
2038 } else {
2039 priv->stats_flag = 1;
2040 }
2041
2042 /* Initialize fifo sizes. */
2043 priv->txd_size = 2;
2044 priv->txf_size = 2;
2045 priv->rxd_size = 2;
2046 priv->rxf_size = 3;
2047
2048 /* Initialize the initial coalescing registers. */
2049 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2050 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2051
2052 /* ndev->xmit_lock spinlock is not used.
2053 * Private priv->tx_lock is used for synchronization
2054 * between transmit and TX irq cleanup. In addition
2055 * set multicast list callback has to use priv->tx_lock.
2056 */
2057#ifdef BDX_LLTX
2058 ndev->features |= NETIF_F_LLTX;
2059#endif
2060 spin_lock_init(&priv->tx_lock);
2061
2062 /*bdx_hw_reset(priv); */
2063 if (bdx_read_mac(priv)) {
865a21a5 2064 pr_err("load MAC address failed\n");
1a348ccc
AG		 2065 goto err_out_iomap;
2066 }
2067 SET_NETDEV_DEV(ndev, &pdev->dev);
cb001a1f
JP		 2068 err = register_netdev(ndev);
2069 if (err) {
865a21a5 2070 pr_err("register_netdev failed\n");
1a348ccc
AG		 2071 goto err_out_free;
2072 }
2073 netif_carrier_off(ndev);
2074 netif_stop_queue(ndev);
2075
2076 print_eth_id(ndev);
2077 }
2078 RET(0);
2079
2080err_out_free:
2081 free_netdev(ndev);
2082err_out_iomap:
2083 iounmap(nic->regs);
2084err_out_res:
2085 pci_release_regions(pdev);
2086err_dma:
2087 pci_disable_device(pdev);
bc2618f7 2088err_pci:
1a348ccc
AG		 2089 vfree(nic);
2090
2091 RET(err);
2092}
2093
2094/****************** Ethtool interface *********************/
1a348ccc
AG		 2095/* get strings for statistics counters */
2096static const char
2097 bdx_stat_names[][ETH_GSTRING_LEN] = {
2098 "InUCast", /* 0x7200 */
2099 "InMCast", /* 0x7210 */
2100 "InBCast", /* 0x7220 */
2101 "InPkts", /* 0x7230 */
2102 "InErrors", /* 0x7240 */
2103 "InDropped", /* 0x7250 */
2104 "FrameTooLong", /* 0x7260 */
2105 "FrameSequenceErrors", /* 0x7270 */
2106 "InVLAN", /* 0x7280 */
2107 "InDroppedDFE", /* 0x7290 */
2108 "InDroppedIntFull", /* 0x72A0 */
2109 "InFrameAlignErrors", /* 0x72B0 */
2110
2111 /* 0x72C0-0x72E0 RSRV */
2112
2113 "OutUCast", /* 0x72F0 */
2114 "OutMCast", /* 0x7300 */
2115 "OutBCast", /* 0x7310 */
2116 "OutPkts", /* 0x7320 */
2117
2118 /* 0x7330-0x7360 RSRV */
2119
2120 "OutVLAN", /* 0x7370 */
2121 "InUCastOctects", /* 0x7380 */
2122 "OutUCastOctects", /* 0x7390 */
2123
2124 /* 0x73A0-0x73B0 RSRV */
2125
2126 "InBCastOctects", /* 0x73C0 */
2127 "OutBCastOctects", /* 0x73D0 */
2128 "InOctects", /* 0x73E0 */
2129 "OutOctects", /* 0x73F0 */
2130};
2131
2132/*
2133 * bdx_get_settings - get device-specific settings
2134 * @netdev
2135 * @ecmd
2136 */
2137static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2138{
2139 u32 rdintcm;
2140 u32 tdintcm;
8f15ea42 2141 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2142
2143 rdintcm = priv->rdintcm;
2144 tdintcm = priv->tdintcm;
2145
2146 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2147 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
70739497 2148 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1a348ccc
AG		 2149 ecmd->duplex = DUPLEX_FULL;
2150 ecmd->port = PORT_FIBRE;
2151 ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */
2152 ecmd->autoneg = AUTONEG_DISABLE;
2153
2154 /* PCK_TH measures in multiples of FIFO bytes
2155 We translate to packets */
2156 ecmd->maxtxpkt =
2157 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2158 ecmd->maxrxpkt =
2159 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2160
2161 return 0;
2162}
2163
2164/*
2165 * bdx_get_drvinfo - report driver information
2166 * @netdev
2167 * @drvinfo
2168 */
2169static void
2170bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2171{
8f15ea42 2172 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc 2173
7826d43f
JP		 2174 strlcpy(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2175 strlcpy(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2176 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2177 strlcpy(drvinfo->bus_info, pci_name(priv->pdev),
1a348ccc 2178 sizeof(drvinfo->bus_info));
1a348ccc
AG		 2179}
2180
1a348ccc
AG		 2181/*
2182 * bdx_get_coalesce - get interrupt coalescing parameters
2183 * @netdev
2184 * @ecoal
2185 */
2186static int
2187bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2188{
2189 u32 rdintcm;
2190 u32 tdintcm;
8f15ea42 2191 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2192
2193 rdintcm = priv->rdintcm;
2194 tdintcm = priv->tdintcm;
2195
2196 /* PCK_TH measures in multiples of FIFO bytes
2197 We translate to packets */
2198 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2199 ecoal->rx_max_coalesced_frames =
2200 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2201
2202 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2203 ecoal->tx_max_coalesced_frames =
2204 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2205
2206 /* adaptive parameters ignored */
2207 return 0;
2208}
2209
2210/*
2211 * bdx_set_coalesce - set interrupt coalescing parameters
2212 * @netdev
2213 * @ecoal
2214 */
2215static int
2216bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2217{
2218 u32 rdintcm;
2219 u32 tdintcm;
8f15ea42 2220 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2221 int rx_coal;
2222 int tx_coal;
2223 int rx_max_coal;
2224 int tx_max_coal;
2225
2226 /* Check for valid input */
2227 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2228 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2229 rx_max_coal = ecoal->rx_max_coalesced_frames;
2230 tx_max_coal = ecoal->tx_max_coalesced_frames;
2231
2232 /* Translate from packets to multiples of FIFO bytes */
2233 rx_max_coal =
2234 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2235 / PCK_TH_MULT);
2236 tx_max_coal =
2237 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2238 / PCK_TH_MULT);
2239
8e95a202
JP		 2240 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2241 (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
1a348ccc
AG		 2242 return -EINVAL;
2243
2244 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2245 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2246 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2247 tx_max_coal);
2248
2249 priv->rdintcm = rdintcm;
2250 priv->tdintcm = tdintcm;
2251
2252 WRITE_REG(priv, regRDINTCM0, rdintcm);
2253 WRITE_REG(priv, regTDINTCM0, tdintcm);
2254
2255 return 0;
2256}
2257
2258/* Convert RX fifo size to number of pending packets */
2259static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2260{
249658d5 2261 return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
1a348ccc
AG		 2262}
2263
2264/* Convert TX fifo size to number of pending packets */
2265static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2266{
249658d5 2267 return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
1a348ccc
AG		 2268}
2269
2270/*
2271 * bdx_get_ringparam - report ring sizes
2272 * @netdev
2273 * @ring
2274 */
2275static void
2276bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2277{
8f15ea42 2278 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2279
2280 /*max_pending - the maximum-sized FIFO we allow */
2281 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2282 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2283 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2284 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2285}
2286
2287/*
2288 * bdx_set_ringparam - set ring sizes
2289 * @netdev
2290 * @ring
2291 */
2292static int
2293bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2294{
8f15ea42 2295 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2296 int rx_size = 0;
2297 int tx_size = 0;
2298
2299 for (; rx_size < 4; rx_size++) {
2300 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2301 break;
2302 }
2303 if (rx_size == 4)
2304 rx_size = 3;
2305
2306 for (; tx_size < 4; tx_size++) {
2307 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2308 break;
2309 }
2310 if (tx_size == 4)
2311 tx_size = 3;
2312
2313 /*Is there anything to do? */
8e95a202
JP		 2314 if ((rx_size == priv->rxf_size) &&
2315 (tx_size == priv->txd_size))
1a348ccc
AG		 2316 return 0;
2317
2318 priv->rxf_size = rx_size;
2319 if (rx_size > 1)
2320 priv->rxd_size = rx_size - 1;
2321 else
2322 priv->rxd_size = rx_size;
2323
2324 priv->txf_size = priv->txd_size = tx_size;
2325
2326 if (netif_running(netdev)) {
2327 bdx_close(netdev);
2328 bdx_open(netdev);
2329 }
2330 return 0;
2331}
2332
2333/*
2334 * bdx_get_strings - return a set of strings that describe the requested objects
2335 * @netdev
2336 * @data
2337 */
2338static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2339{
2340 switch (stringset) {
1a348ccc
AG		 2341 case ETH_SS_STATS:
2342 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2343 break;
2344 }
2345}
2346
2347/*
1ddee09f 2348 * bdx_get_sset_count - return number of statistics or tests
1a348ccc
AG		 2349 * @netdev
2350 */
1ddee09f 2351static int bdx_get_sset_count(struct net_device *netdev, int stringset)
1a348ccc 2352{
8f15ea42 2353 struct bdx_priv *priv = netdev_priv(netdev);
1ddee09f
BH		 2354
2355 switch (stringset) {
2356 case ETH_SS_STATS:
2357 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2358 != sizeof(struct bdx_stats) / sizeof(u64));
249658d5 2359 return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0;
1ddee09f 2360 }
249658d5
JP		 2361
2362 return -EINVAL;
1a348ccc
AG		 2363}
2364
2365/*
2366 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2367 * @netdev
2368 * @stats
2369 * @data
2370 */
2371static void bdx_get_ethtool_stats(struct net_device *netdev,
2372 struct ethtool_stats *stats, u64 *data)
2373{
8f15ea42 2374 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2375
2376 if (priv->stats_flag) {
2377
2378 /* Update stats from HW */
2379 bdx_update_stats(priv);
2380
2381 /* Copy data to user buffer */
2382 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2383 }
2384}
2385
2386/*
c061b18d 2387 * bdx_set_ethtool_ops - ethtool interface implementation
1a348ccc
AG		 2388 * @netdev
2389 */
c061b18d 2390static void bdx_set_ethtool_ops(struct net_device *netdev)
1a348ccc 2391{
0fc0b732 2392 static const struct ethtool_ops bdx_ethtool_ops = {
1a348ccc
AG		 2393 .get_settings = bdx_get_settings,
2394 .get_drvinfo = bdx_get_drvinfo,
2395 .get_link = ethtool_op_get_link,
2396 .get_coalesce = bdx_get_coalesce,
2397 .set_coalesce = bdx_set_coalesce,
2398 .get_ringparam = bdx_get_ringparam,
2399 .set_ringparam = bdx_set_ringparam,
1a348ccc 2400 .get_strings = bdx_get_strings,
1ddee09f 2401 .get_sset_count = bdx_get_sset_count,
1a348ccc
AG		 2402 .get_ethtool_stats = bdx_get_ethtool_stats,
2403 };
2404
7ad24ea4 2405 netdev->ethtool_ops = &bdx_ethtool_ops;
1a348ccc
AG		 2406}
2407
2408/**
2409 * bdx_remove - Device Removal Routine
2410 * @pdev: PCI device information struct
2411 *
2412 * bdx_remove is called by the PCI subsystem to alert the driver
2413 * that it should release a PCI device. The could be caused by a
2414 * Hot-Plug event, or because the driver is going to be removed from
2415 * memory.
2416 **/
17abe3e4 2417static void bdx_remove(struct pci_dev *pdev)
1a348ccc
AG		 2418{
2419 struct pci_nic *nic = pci_get_drvdata(pdev);
2420 struct net_device *ndev;
2421 int port;
2422
2423 for (port = 0; port < nic->port_num; port++) {
2424 ndev = nic->priv[port]->ndev;
2425 unregister_netdev(ndev);
2426 free_netdev(ndev);
2427 }
2428
2429 /*bdx_hw_reset_direct(nic->regs); */
2430#ifdef BDX_MSI
2431 if (nic->irq_type == IRQ_MSI)
2432 pci_disable_msi(pdev);
2433#endif
2434
2435 iounmap(nic->regs);
2436 pci_release_regions(pdev);
2437 pci_disable_device(pdev);
1a348ccc
AG		 2438 vfree(nic);
2439
2440 RET();
2441}
2442
2443static struct pci_driver bdx_pci_driver = {
2444 .name = BDX_DRV_NAME,
2445 .id_table = bdx_pci_tbl,
2446 .probe = bdx_probe,
17abe3e4 2447 .remove = bdx_remove,
1a348ccc
AG		 2448};
2449
2450/*
2451 * print_driver_id - print parameters of the driver build
2452 */
2453static void __init print_driver_id(void)
2454{
865a21a5
JP		 2455 pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2456 pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
1a348ccc
AG		 2457}
2458
2459static int __init bdx_module_init(void)
2460{
2461 ENTER;
1a348ccc
AG		 2462 init_txd_sizes();
2463 print_driver_id();
2464 RET(pci_register_driver(&bdx_pci_driver));
2465}
2466
2467module_init(bdx_module_init);
2468
2469static void __exit bdx_module_exit(void)
2470{
2471 ENTER;
2472 pci_unregister_driver(&bdx_pci_driver);
2473 RET();
2474}
2475
2476module_exit(bdx_module_exit);
2477
2478MODULE_LICENSE("GPL");
2479MODULE_AUTHOR(DRIVER_AUTHOR);
2480MODULE_DESCRIPTION(BDX_DRV_DESC);
46814e08 2481MODULE_FIRMWARE("tehuti/bdx.bin");
Linux kernel - Deliverables
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