projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
127#define CPDMA_TX_PRIORITY_MAP 0x76543210
128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
d3bb9c58
M		 143#define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
df828598
M		 147static int debug_level;
148module_param(debug_level, int, 0);
149MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151static int ale_ageout = 10;
152module_param(ale_ageout, int, 0);
153MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156module_param(rx_packet_max, int, 0);
157MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
996a5c27 159struct cpsw_wr_regs {
df828598
M		 160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
ff5b8ef2
M		 168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
df828598
M		 177};
178
996a5c27 179struct cpsw_ss_regs {
df828598
M		 180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
bd357af2
RC		 185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
df828598
M		 193};
194
9750a3ad
RC		 195/* CPSW_PORT_V1 */
196#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205/* CPSW_PORT_V2 */
206#define CPSW2_CONTROL 0x00 /* Control Register */
207#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214/* CPSW_PORT_V1 and V2 */
215#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219/* CPSW_PORT_V2 only */
220#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229/* Bit definitions for the CPSW2_CONTROL register */
230#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 240#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 242#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
09c55372
GC		 248#define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 251
09c55372
GC		 252#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257#define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 265
266/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268#define TS_SEQ_ID_OFFSET_MASK (0x3f)
269#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270#define TS_MSG_TYPE_EN_MASK (0xffff)
271
272/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 274
2e5b38ab
RC		 275/* Bit definitions for the CPSW1_TS_CTL register */
276#define CPSW_V1_TS_RX_EN BIT(0)
277#define CPSW_V1_TS_TX_EN BIT(4)
278#define CPSW_V1_MSG_TYPE_OFS 16
279
280/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
df828598
M		 283struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
d9ba8f9e 286 u32 tx_in_ctl;
df828598
M		 287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291};
292
293struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304};
305
d9718546
M		 306struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342};
343
df828598 344struct cpsw_slave {
9750a3ad 345 void __iomem *regs;
df828598
M		 346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
d9ba8f9e
M		 351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
df828598
M		 354};
355
9750a3ad
RC		 356static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357{
358 return __raw_readl(slave->regs + offset);
359}
360
361static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362{
363 __raw_writel(val, slave->regs + offset);
364}
365
df828598
M		 366struct cpsw_priv {
367 spinlock_t lock;
368 struct platform_device *pdev;
369 struct net_device *ndev;
df637193 370 struct device_node *phy_node;
32a7432c
M		 371 struct napi_struct napi_rx;
372 struct napi_struct napi_tx;
df828598
M		 373 struct device *dev;
374 struct cpsw_platform_data data;
996a5c27
RC		 375 struct cpsw_ss_regs __iomem *regs;
376 struct cpsw_wr_regs __iomem *wr_regs;
d9718546 377 u8 __iomem *hw_stats;
df828598
M		 378 struct cpsw_host_regs __iomem *host_port_regs;
379 u32 msg_enable;
e90cfac6 380 u32 version;
ff5b8ef2
M		 381 u32 coal_intvl;
382 u32 bus_freq_mhz;
df828598
M		 383 int rx_packet_max;
384 int host_port;
385 struct clk *clk;
386 u8 mac_addr[ETH_ALEN];
387 struct cpsw_slave *slaves;
388 struct cpdma_ctlr *dma;
389 struct cpdma_chan *txch, *rxch;
390 struct cpsw_ale *ale;
1923d6e4
M		 391 bool rx_pause;
392 bool tx_pause;
7da11600
M		 393 bool quirk_irq;
394 bool rx_irq_disabled;
395 bool tx_irq_disabled;
df828598
M		 396 /* snapshot of IRQ numbers */
397 u32 irqs_table[4];
398 u32 num_irqs;
9232b16d 399 struct cpts *cpts;
d9ba8f9e 400 u32 emac_port;
df828598
M		 401};
402
d9718546
M		 403struct cpsw_stats {
404 char stat_string[ETH_GSTRING_LEN];
405 int type;
406 int sizeof_stat;
407 int stat_offset;
408};
409
410enum {
411 CPSW_STATS,
412 CPDMA_RX_STATS,
413 CPDMA_TX_STATS,
414};
415
416#define CPSW_STAT(m) CPSW_STATS, \
417 sizeof(((struct cpsw_hw_stats *)0)->m), \
418 offsetof(struct cpsw_hw_stats, m)
419#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
420 sizeof(((struct cpdma_chan_stats *)0)->m), \
421 offsetof(struct cpdma_chan_stats, m)
422#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
423 sizeof(((struct cpdma_chan_stats *)0)->m), \
424 offsetof(struct cpdma_chan_stats, m)
425
426static const struct cpsw_stats cpsw_gstrings_stats[] = {
427 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
428 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
429 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
430 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
431 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
432 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
433 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
434 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
435 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
436 { "Rx Fragments", CPSW_STAT(rxfragments) },
437 { "Rx Octets", CPSW_STAT(rxoctets) },
438 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
439 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
440 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
441 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
442 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
443 { "Collisions", CPSW_STAT(txcollisionframes) },
444 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
445 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
446 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
447 { "Late Collisions", CPSW_STAT(txlatecollisions) },
448 { "Tx Underrun", CPSW_STAT(txunderrun) },
449 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
450 { "Tx Octets", CPSW_STAT(txoctets) },
451 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
452 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
453 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
454 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
455 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
456 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
457 { "Net Octets", CPSW_STAT(netoctets) },
458 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
459 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
460 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
461 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
462 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
463 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
464 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
465 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
466 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
467 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
468 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
469 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
470 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
471 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
472 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
473 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
474 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
475 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
476 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
477 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
478 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
479 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
480 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
481 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
482 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
483 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
484 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
485 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
486 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
487};
488
489#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
490
df828598 491#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 492#define for_each_slave(priv, func, arg...) \
493 do { \
6e6ceaed
SS		 494 struct cpsw_slave *slave; \
495 int n; \
d9ba8f9e
M		 496 if (priv->data.dual_emac) \
497 (func)((priv)->slaves + priv->emac_port, ##arg);\
498 else \
6e6ceaed
SS		 499 for (n = (priv)->data.slaves, \
500 slave = (priv)->slaves; \
501 n; n--) \
502 (func)(slave++, ##arg); \
d9ba8f9e
M		 503 } while (0)
504#define cpsw_get_slave_ndev(priv, __slave_no__) \
1973db0d
M		 505 ((__slave_no__ < priv->data.slaves) ? \
506 priv->slaves[__slave_no__].ndev : NULL)
d9ba8f9e 507#define cpsw_get_slave_priv(priv, __slave_no__) \
1973db0d
M		 508 (((__slave_no__ < priv->data.slaves) && \
509 (priv->slaves[__slave_no__].ndev)) ? \
d9ba8f9e
M		 510 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
511
512#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
513 do { \
514 if (!priv->data.dual_emac) \
515 break; \
516 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
517 ndev = cpsw_get_slave_ndev(priv, 0); \
518 priv = netdev_priv(ndev); \
519 skb->dev = ndev; \
520 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
521 ndev = cpsw_get_slave_ndev(priv, 1); \
522 priv = netdev_priv(ndev); \
523 skb->dev = ndev; \
524 } \
df828598 525 } while (0)
d9ba8f9e
M		 526#define cpsw_add_mcast(priv, addr) \
527 do { \
528 if (priv->data.dual_emac) { \
529 struct cpsw_slave *slave = priv->slaves + \
530 priv->emac_port; \
531 int slave_port = cpsw_get_slave_port(priv, \
532 slave->slave_num); \
533 cpsw_ale_add_mcast(priv->ale, addr, \
534 1 << slave_port | 1 << priv->host_port, \
535 ALE_VLAN, slave->port_vlan, 0); \
536 } else { \
537 cpsw_ale_add_mcast(priv->ale, addr, \
538 ALE_ALL_PORTS << priv->host_port, \
539 0, 0, 0); \
540 } \
541 } while (0)
542
543static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
544{
545 if (priv->host_port == 0)
546 return slave_num + 1;
547 else
548 return slave_num;
549}
df828598 550
0cd8f9cc
M		 551static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
552{
553 struct cpsw_priv *priv = netdev_priv(ndev);
554 struct cpsw_ale *ale = priv->ale;
555 int i;
556
557 if (priv->data.dual_emac) {
558 bool flag = false;
559
560 /* Enabling promiscuous mode for one interface will be
561 * common for both the interface as the interface shares
562 * the same hardware resource.
563 */
0d961b3b 564 for (i = 0; i < priv->data.slaves; i++)
0cd8f9cc
M		 565 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
566 flag = true;
567
568 if (!enable && flag) {
569 enable = true;
570 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
571 }
572
573 if (enable) {
574 /* Enable Bypass */
575 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
576
577 dev_dbg(&ndev->dev, "promiscuity enabled\n");
578 } else {
579 /* Disable Bypass */
580 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
581 dev_dbg(&ndev->dev, "promiscuity disabled\n");
582 }
583 } else {
584 if (enable) {
585 unsigned long timeout = jiffies + HZ;
586
6f979eb3
LS		 587 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
588 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 589 cpsw_ale_control_set(ale, i,
590 ALE_PORT_NOLEARN, 1);
591 cpsw_ale_control_set(ale, i,
592 ALE_PORT_NO_SA_UPDATE, 1);
593 }
594
595 /* Clear All Untouched entries */
596 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
597 do {
598 cpu_relax();
599 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
600 break;
601 } while (time_after(timeout, jiffies));
602 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
603
604 /* Clear all mcast from ALE */
605 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
25906052 606 priv->host_port, -1);
0cd8f9cc
M		 607
608 /* Flood All Unicast Packets to Host port */
609 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
610 dev_dbg(&ndev->dev, "promiscuity enabled\n");
611 } else {
6f979eb3 612 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 613 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
614
6f979eb3
LS		 615 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
616 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 617 cpsw_ale_control_set(ale, i,
618 ALE_PORT_NOLEARN, 0);
619 cpsw_ale_control_set(ale, i,
620 ALE_PORT_NO_SA_UPDATE, 0);
621 }
622 dev_dbg(&ndev->dev, "promiscuity disabled\n");
623 }
624 }
625}
626
5c50a856
M		 627static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
628{
629 struct cpsw_priv *priv = netdev_priv(ndev);
25906052
M		 630 int vid;
631
632 if (priv->data.dual_emac)
633 vid = priv->slaves[priv->emac_port].port_vlan;
634 else
635 vid = priv->data.default_vlan;
5c50a856
M		 636
637 if (ndev->flags & IFF_PROMISC) {
638 /* Enable promiscuous mode */
0cd8f9cc 639 cpsw_set_promiscious(ndev, true);
1e5c4bc4 640 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
5c50a856 641 return;
0cd8f9cc
M		 642 } else {
643 /* Disable promiscuous mode */
644 cpsw_set_promiscious(ndev, false);
5c50a856
M		 645 }
646
1e5c4bc4
LS		 647 /* Restore allmulti on vlans if necessary */
648 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
649
5c50a856 650 /* Clear all mcast from ALE */
25906052
M		 651 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
652 vid);
5c50a856
M		 653
654 if (!netdev_mc_empty(ndev)) {
655 struct netdev_hw_addr *ha;
656
657 /* program multicast address list into ALE register */
658 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 659 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 660 }
661 }
662}
663
df828598
M		 664static void cpsw_intr_enable(struct cpsw_priv *priv)
665{
996a5c27
RC		 666 __raw_writel(0xFF, &priv->wr_regs->tx_en);
667 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 668
669 cpdma_ctlr_int_ctrl(priv->dma, true);
670 return;
671}
672
673static void cpsw_intr_disable(struct cpsw_priv *priv)
674{
996a5c27
RC		 675 __raw_writel(0, &priv->wr_regs->tx_en);
676 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 677
678 cpdma_ctlr_int_ctrl(priv->dma, false);
679 return;
680}
681
1a3b5056 682static void cpsw_tx_handler(void *token, int len, int status)
df828598
M		 683{
684 struct sk_buff *skb = token;
685 struct net_device *ndev = skb->dev;
686 struct cpsw_priv *priv = netdev_priv(ndev);
687
fae50823
M		 688 /* Check whether the queue is stopped due to stalled tx dma, if the
689 * queue is stopped then start the queue as we have free desc for tx
690 */
df828598 691 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 692 netif_wake_queue(ndev);
9232b16d 693 cpts_tx_timestamp(priv->cpts, skb);
8dc43ddc
TK		 694 ndev->stats.tx_packets++;
695 ndev->stats.tx_bytes += len;
df828598
M		 696 dev_kfree_skb_any(skb);
697}
698
1a3b5056 699static void cpsw_rx_handler(void *token, int len, int status)
df828598
M		 700{
701 struct sk_buff *skb = token;
b4727e69 702 struct sk_buff *new_skb;
df828598
M		 703 struct net_device *ndev = skb->dev;
704 struct cpsw_priv *priv = netdev_priv(ndev);
705 int ret = 0;
706
d9ba8f9e
M		 707 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
708
16e5c57d 709 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822
M		 710 bool ndev_status = false;
711 struct cpsw_slave *slave = priv->slaves;
712 int n;
713
714 if (priv->data.dual_emac) {
715 /* In dual emac mode check for all interfaces */
716 for (n = priv->data.slaves; n; n--, slave++)
717 if (netif_running(slave->ndev))
718 ndev_status = true;
719 }
720
721 if (ndev_status && (status >= 0)) {
722 /* The packet received is for the interface which
723 * is already down and the other interface is up
dbedd44e 724 * and running, instead of freeing which results
a0e2c822
M		 725 * in reducing of the number of rx descriptor in
726 * DMA engine, requeue skb back to cpdma.
727 */
728 new_skb = skb;
729 goto requeue;
730 }
731
b4727e69 732 /* the interface is going down, skbs are purged */
df828598
M		 733 dev_kfree_skb_any(skb);
734 return;
735 }
b4727e69
SS		 736
737 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
738 if (new_skb) {
df828598 739 skb_put(skb, len);
9232b16d 740 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 741 skb->protocol = eth_type_trans(skb, ndev);
742 netif_receive_skb(skb);
8dc43ddc
TK		 743 ndev->stats.rx_bytes += len;
744 ndev->stats.rx_packets++;
b4727e69 745 } else {
8dc43ddc 746 ndev->stats.rx_dropped++;
b4727e69 747 new_skb = skb;
df828598
M		 748 }
749
a0e2c822 750requeue:
b4727e69
SS		 751 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
752 skb_tailroom(new_skb), 0);
753 if (WARN_ON(ret < 0))
754 dev_kfree_skb_any(new_skb);
df828598
M		 755}
756
c03abd84 757static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598
M		 758{
759 struct cpsw_priv *priv = dev_id;
7ce67a38 760
32a7432c 761 writel(0, &priv->wr_regs->tx_en);
c03abd84 762 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
c03abd84 763
7da11600
M		 764 if (priv->quirk_irq) {
765 disable_irq_nosync(priv->irqs_table[1]);
766 priv->tx_irq_disabled = true;
767 }
768
32a7432c 769 napi_schedule(&priv->napi_tx);
c03abd84
FB		 770 return IRQ_HANDLED;
771}
772
773static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
774{
775 struct cpsw_priv *priv = dev_id;
776
777 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
870915fe 778 writel(0, &priv->wr_regs->rx_en);
fd51cf19 779
7da11600
M		 780 if (priv->quirk_irq) {
781 disable_irq_nosync(priv->irqs_table[0]);
782 priv->rx_irq_disabled = true;
783 }
784
32a7432c 785 napi_schedule(&priv->napi_rx);
d354eb85 786 return IRQ_HANDLED;
df828598
M		 787}
788
32a7432c
M		 789static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
790{
791 struct cpsw_priv *priv = napi_to_priv(napi_tx);
792 int num_tx;
793
794 num_tx = cpdma_chan_process(priv->txch, budget);
795 if (num_tx < budget) {
796 napi_complete(napi_tx);
797 writel(0xff, &priv->wr_regs->tx_en);
7da11600
M		 798 if (priv->quirk_irq && priv->tx_irq_disabled) {
799 priv->tx_irq_disabled = false;
800 enable_irq(priv->irqs_table[1]);
801 }
32a7432c
M		 802 }
803
804 if (num_tx)
805 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
806
807 return num_tx;
808}
809
810static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 811{
32a7432c 812 struct cpsw_priv *priv = napi_to_priv(napi_rx);
1e353cdd 813 int num_rx;
df828598 814
510a1e72 815 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 816 if (num_rx < budget) {
32a7432c 817 napi_complete(napi_rx);
870915fe 818 writel(0xff, &priv->wr_regs->rx_en);
7da11600
M		 819 if (priv->quirk_irq && priv->rx_irq_disabled) {
820 priv->rx_irq_disabled = false;
821 enable_irq(priv->irqs_table[0]);
822 }
df828598
M		 823 }
824
1e353cdd
M		 825 if (num_rx)
826 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
510a1e72 827
df828598
M		 828 return num_rx;
829}
830
831static inline void soft_reset(const char *module, void __iomem *reg)
832{
833 unsigned long timeout = jiffies + HZ;
834
835 __raw_writel(1, reg);
836 do {
837 cpu_relax();
838 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
839
840 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
841}
842
843#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
844 ((mac)[2] << 16) | ((mac)[3] << 24))
845#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
846
847static void cpsw_set_slave_mac(struct cpsw_slave *slave,
848 struct cpsw_priv *priv)
849{
9750a3ad
RC		 850 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
851 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 852}
853
854static void _cpsw_adjust_link(struct cpsw_slave *slave,
855 struct cpsw_priv *priv, bool *link)
856{
857 struct phy_device *phy = slave->phy;
858 u32 mac_control = 0;
859 u32 slave_port;
860
861 if (!phy)
862 return;
863
864 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
865
866 if (phy->link) {
867 mac_control = priv->data.mac_control;
868
869 /* enable forwarding */
870 cpsw_ale_control_set(priv->ale, slave_port,
871 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
872
873 if (phy->speed == 1000)
874 mac_control |= BIT(7); /* GIGABITEN */
875 if (phy->duplex)
876 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 877
878 /* set speed_in input in case RMII mode is used in 100Mbps */
879 if (phy->speed == 100)
880 mac_control |= BIT(15);
a81d8762
M		 881 else if (phy->speed == 10)
882 mac_control |= BIT(18); /* In Band mode */
342b7b74 883
1923d6e4
M		 884 if (priv->rx_pause)
885 mac_control |= BIT(3);
886
887 if (priv->tx_pause)
888 mac_control |= BIT(4);
889
df828598
M		 890 *link = true;
891 } else {
892 mac_control = 0;
893 /* disable forwarding */
894 cpsw_ale_control_set(priv->ale, slave_port,
895 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
896 }
897
898 if (mac_control != slave->mac_control) {
899 phy_print_status(phy);
900 __raw_writel(mac_control, &slave->sliver->mac_control);
901 }
902
903 slave->mac_control = mac_control;
904}
905
906static void cpsw_adjust_link(struct net_device *ndev)
907{
908 struct cpsw_priv *priv = netdev_priv(ndev);
909 bool link = false;
910
911 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
912
913 if (link) {
914 netif_carrier_on(ndev);
915 if (netif_running(ndev))
916 netif_wake_queue(ndev);
917 } else {
918 netif_carrier_off(ndev);
919 netif_stop_queue(ndev);
920 }
921}
922
ff5b8ef2
M		 923static int cpsw_get_coalesce(struct net_device *ndev,
924 struct ethtool_coalesce *coal)
925{
926 struct cpsw_priv *priv = netdev_priv(ndev);
927
928 coal->rx_coalesce_usecs = priv->coal_intvl;
929 return 0;
930}
931
932static int cpsw_set_coalesce(struct net_device *ndev,
933 struct ethtool_coalesce *coal)
934{
935 struct cpsw_priv *priv = netdev_priv(ndev);
936 u32 int_ctrl;
937 u32 num_interrupts = 0;
938 u32 prescale = 0;
939 u32 addnl_dvdr = 1;
940 u32 coal_intvl = 0;
941
ff5b8ef2
M		 942 coal_intvl = coal->rx_coalesce_usecs;
943
944 int_ctrl = readl(&priv->wr_regs->int_control);
945 prescale = priv->bus_freq_mhz * 4;
946
a84bc2a9
M		 947 if (!coal->rx_coalesce_usecs) {
948 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
949 goto update_return;
950 }
951
ff5b8ef2
M		 952 if (coal_intvl < CPSW_CMINTMIN_INTVL)
953 coal_intvl = CPSW_CMINTMIN_INTVL;
954
955 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
956 /* Interrupt pacer works with 4us Pulse, we can
957 * throttle further by dilating the 4us pulse.
958 */
959 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
960
961 if (addnl_dvdr > 1) {
962 prescale *= addnl_dvdr;
963 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
964 coal_intvl = (CPSW_CMINTMAX_INTVL
965 * addnl_dvdr);
966 } else {
967 addnl_dvdr = 1;
968 coal_intvl = CPSW_CMINTMAX_INTVL;
969 }
970 }
971
972 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
973 writel(num_interrupts, &priv->wr_regs->rx_imax);
974 writel(num_interrupts, &priv->wr_regs->tx_imax);
975
976 int_ctrl |= CPSW_INTPACEEN;
977 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
978 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 979
980update_return:
ff5b8ef2
M		 981 writel(int_ctrl, &priv->wr_regs->int_control);
982
983 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
984 if (priv->data.dual_emac) {
985 int i;
986
987 for (i = 0; i < priv->data.slaves; i++) {
988 priv = netdev_priv(priv->slaves[i].ndev);
989 priv->coal_intvl = coal_intvl;
990 }
991 } else {
992 priv->coal_intvl = coal_intvl;
993 }
994
995 return 0;
996}
997
d9718546
M		 998static int cpsw_get_sset_count(struct net_device *ndev, int sset)
999{
1000 switch (sset) {
1001 case ETH_SS_STATS:
1002 return CPSW_STATS_LEN;
1003 default:
1004 return -EOPNOTSUPP;
1005 }
1006}
1007
1008static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1009{
1010 u8 *p = data;
1011 int i;
1012
1013 switch (stringset) {
1014 case ETH_SS_STATS:
1015 for (i = 0; i < CPSW_STATS_LEN; i++) {
1016 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1017 ETH_GSTRING_LEN);
1018 p += ETH_GSTRING_LEN;
1019 }
1020 break;
1021 }
1022}
1023
1024static void cpsw_get_ethtool_stats(struct net_device *ndev,
1025 struct ethtool_stats *stats, u64 *data)
1026{
1027 struct cpsw_priv *priv = netdev_priv(ndev);
1028 struct cpdma_chan_stats rx_stats;
1029 struct cpdma_chan_stats tx_stats;
1030 u32 val;
1031 u8 *p;
1032 int i;
1033
1034 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1035 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1036 cpdma_chan_get_stats(priv->txch, &tx_stats);
1037
1038 for (i = 0; i < CPSW_STATS_LEN; i++) {
1039 switch (cpsw_gstrings_stats[i].type) {
1040 case CPSW_STATS:
1041 val = readl(priv->hw_stats +
1042 cpsw_gstrings_stats[i].stat_offset);
1043 data[i] = val;
1044 break;
1045
1046 case CPDMA_RX_STATS:
1047 p = (u8 *)&rx_stats +
1048 cpsw_gstrings_stats[i].stat_offset;
1049 data[i] = *(u32 *)p;
1050 break;
1051
1052 case CPDMA_TX_STATS:
1053 p = (u8 *)&tx_stats +
1054 cpsw_gstrings_stats[i].stat_offset;
1055 data[i] = *(u32 *)p;
1056 break;
1057 }
1058 }
1059}
1060
d9ba8f9e
M		 1061static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1062{
1063 u32 i;
1064 u32 usage_count = 0;
1065
1066 if (!priv->data.dual_emac)
1067 return 0;
1068
1069 for (i = 0; i < priv->data.slaves; i++)
1070 if (priv->slaves[i].open_stat)
1071 usage_count++;
1072
1073 return usage_count;
1074}
1075
1076static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1077 struct cpsw_priv *priv, struct sk_buff *skb)
1078{
1079 if (!priv->data.dual_emac)
1080 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1081 skb->len, 0);
d9ba8f9e
M		 1082
1083 if (ndev == cpsw_get_slave_ndev(priv, 0))
1084 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1085 skb->len, 1);
d9ba8f9e
M		 1086 else
1087 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1088 skb->len, 2);
d9ba8f9e
M		 1089}
1090
1091static inline void cpsw_add_dual_emac_def_ale_entries(
1092 struct cpsw_priv *priv, struct cpsw_slave *slave,
1093 u32 slave_port)
1094{
1095 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1096
1097 if (priv->version == CPSW_VERSION_1)
1098 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1099 else
1100 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1101 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1102 port_mask, port_mask, 0);
1103 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1104 port_mask, ALE_VLAN, slave->port_vlan, 0);
1105 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
56887149 1106 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1107}
1108
1e7a2e21 1109static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1110{
1111 char name[32];
df828598 1112
1e7a2e21 1113 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1114 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1115}
1116
1117static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1118{
1119 u32 slave_port;
1120
1121 soft_reset_slave(slave);
df828598
M		 1122
1123 /* setup priority mapping */
1124 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 1125
1126 switch (priv->version) {
1127 case CPSW_VERSION_1:
1128 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1129 break;
1130 case CPSW_VERSION_2:
c193f365 1131 case CPSW_VERSION_3:
926489be 1132 case CPSW_VERSION_4:
9750a3ad
RC		 1133 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1134 break;
1135 }
df828598
M		 1136
1137 /* setup max packet size, and mac address */
1138 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1139 cpsw_set_slave_mac(slave, priv);
1140
1141 slave->mac_control = 0; /* no link yet */
1142
1143 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1144
d9ba8f9e
M		 1145 if (priv->data.dual_emac)
1146 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1147 else
1148 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1149 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1150
df637193
AG		 1151 if (priv->phy_node)
1152 slave->phy = of_phy_connect(priv->ndev, priv->phy_node,
9e42f715
HS		 1153 &cpsw_adjust_link, 0, slave->data->phy_if);
1154 else
1155 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1156 &cpsw_adjust_link, slave->data->phy_if);
df828598
M		 1157 if (IS_ERR(slave->phy)) {
1158 dev_err(priv->dev, "phy %s not found on slave %d\n",
1159 slave->data->phy_id, slave->slave_num);
1160 slave->phy = NULL;
1161 } else {
2220943a
AL		 1162 phy_attached_info(slave->phy);
1163
df828598 1164 phy_start(slave->phy);
388367a5
M		 1165
1166 /* Configure GMII_SEL register */
1167 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1168 slave->slave_num);
df828598
M		 1169 }
1170}
1171
3b72c2fe
M		 1172static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1173{
1174 const int vlan = priv->data.default_vlan;
1175 const int port = priv->host_port;
1176 u32 reg;
1177 int i;
1e5c4bc4 1178 int unreg_mcast_mask;
3b72c2fe
M		 1179
1180 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1181 CPSW2_PORT_VLAN;
1182
1183 writel(vlan, &priv->host_port_regs->port_vlan);
1184
0237c110 1185 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1186 slave_write(priv->slaves + i, vlan, reg);
1187
1e5c4bc4
LS		 1188 if (priv->ndev->flags & IFF_ALLMULTI)
1189 unreg_mcast_mask = ALE_ALL_PORTS;
1190 else
1191 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1192
3b72c2fe
M		 1193 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1194 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1e5c4bc4 1195 unreg_mcast_mask << port);
3b72c2fe
M		 1196}
1197
df828598
M		 1198static void cpsw_init_host_port(struct cpsw_priv *priv)
1199{
3b72c2fe 1200 u32 control_reg;
d9ba8f9e 1201 u32 fifo_mode;
3b72c2fe 1202
df828598
M		 1203 /* soft reset the controller and initialize ale */
1204 soft_reset("cpsw", &priv->regs->soft_reset);
1205 cpsw_ale_start(priv->ale);
1206
1207 /* switch to vlan unaware mode */
3b72c2fe
M		 1208 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1209 CPSW_ALE_VLAN_AWARE);
1210 control_reg = readl(&priv->regs->control);
1211 control_reg |= CPSW_VLAN_AWARE;
1212 writel(control_reg, &priv->regs->control);
d9ba8f9e
M		 1213 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1214 CPSW_FIFO_NORMAL_MODE;
1215 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
df828598
M		 1216
1217 /* setup host port priority mapping */
1218 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1219 &priv->host_port_regs->cpdma_tx_pri_map);
1220 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1221
1222 cpsw_ale_control_set(priv->ale, priv->host_port,
1223 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1224
d9ba8f9e
M		 1225 if (!priv->data.dual_emac) {
1226 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1227 0, 0);
1228 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1229 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1230 }
df828598
M		 1231}
1232
aacebbf8
SS		 1233static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1234{
3995d265
SP		 1235 u32 slave_port;
1236
1237 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1238
aacebbf8
SS		 1239 if (!slave->phy)
1240 return;
1241 phy_stop(slave->phy);
1242 phy_disconnect(slave->phy);
1243 slave->phy = NULL;
3995d265
SP		 1244 cpsw_ale_control_set(priv->ale, slave_port,
1245 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
aacebbf8
SS		 1246}
1247
df828598
M		 1248static int cpsw_ndo_open(struct net_device *ndev)
1249{
1250 struct cpsw_priv *priv = netdev_priv(ndev);
1251 int i, ret;
1252 u32 reg;
1253
3fa88c51
GS		 1254 pm_runtime_get_sync(&priv->pdev->dev);
1255
d9ba8f9e
M		 1256 if (!cpsw_common_res_usage_state(priv))
1257 cpsw_intr_disable(priv);
df828598
M		 1258 netif_carrier_off(ndev);
1259
549985ee 1260 reg = priv->version;
df828598
M		 1261
1262 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1263 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1264 CPSW_RTL_VERSION(reg));
1265
1266 /* initialize host and slave ports */
d9ba8f9e
M		 1267 if (!cpsw_common_res_usage_state(priv))
1268 cpsw_init_host_port(priv);
df828598
M		 1269 for_each_slave(priv, cpsw_slave_open, priv);
1270
3b72c2fe 1271 /* Add default VLAN */
e6afea0b
M		 1272 if (!priv->data.dual_emac)
1273 cpsw_add_default_vlan(priv);
1274 else
1275 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1276 ALE_ALL_PORTS << priv->host_port,
1277 ALE_ALL_PORTS << priv->host_port, 0, 0);
3b72c2fe 1278
d9ba8f9e 1279 if (!cpsw_common_res_usage_state(priv)) {
d354eb85
M		 1280 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1281
d9ba8f9e
M		 1282 /* setup tx dma to fixed prio and zero offset */
1283 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1284 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1285
d9ba8f9e
M		 1286 /* disable priority elevation */
1287 __raw_writel(0, &priv->regs->ptype);
df828598 1288
d9ba8f9e
M		 1289 /* enable statistics collection only on all ports */
1290 __raw_writel(0x7, &priv->regs->stat_port_en);
df828598 1291
1923d6e4
M		 1292 /* Enable internal fifo flow control */
1293 writel(0x7, &priv->regs->flow_control);
1294
32a7432c
M		 1295 napi_enable(&priv_sl0->napi_rx);
1296 napi_enable(&priv_sl0->napi_tx);
d354eb85 1297
7da11600
M		 1298 if (priv_sl0->tx_irq_disabled) {
1299 priv_sl0->tx_irq_disabled = false;
1300 enable_irq(priv->irqs_table[1]);
1301 }
1302
1303 if (priv_sl0->rx_irq_disabled) {
1304 priv_sl0->rx_irq_disabled = false;
1305 enable_irq(priv->irqs_table[0]);
1306 }
1307
d9ba8f9e
M		 1308 if (WARN_ON(!priv->data.rx_descs))
1309 priv->data.rx_descs = 128;
df828598 1310
d9ba8f9e
M		 1311 for (i = 0; i < priv->data.rx_descs; i++) {
1312 struct sk_buff *skb;
df828598 1313
d9ba8f9e 1314 ret = -ENOMEM;
aacebbf8
SS		 1315 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1316 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1317 if (!skb)
aacebbf8 1318 goto err_cleanup;
d9ba8f9e 1319 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1320 skb_tailroom(skb), 0);
aacebbf8
SS		 1321 if (ret < 0) {
1322 kfree_skb(skb);
1323 goto err_cleanup;
1324 }
d9ba8f9e
M		 1325 }
1326 /* continue even if we didn't manage to submit all
1327 * receive descs
1328 */
1329 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
f280e89a
M		 1330
1331 if (cpts_register(&priv->pdev->dev, priv->cpts,
1332 priv->data.cpts_clock_mult,
1333 priv->data.cpts_clock_shift))
1334 dev_err(priv->dev, "error registering cpts device\n");
1335
df828598 1336 }
df828598 1337
ff5b8ef2
M		 1338 /* Enable Interrupt pacing if configured */
1339 if (priv->coal_intvl != 0) {
1340 struct ethtool_coalesce coal;
1341
1342 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1343 cpsw_set_coalesce(ndev, &coal);
1344 }
1345
f63a975e
M		 1346 cpdma_ctlr_start(priv->dma);
1347 cpsw_intr_enable(priv);
f63a975e 1348
d9ba8f9e
M		 1349 if (priv->data.dual_emac)
1350 priv->slaves[priv->emac_port].open_stat = true;
df828598 1351 return 0;
df828598 1352
aacebbf8
SS		 1353err_cleanup:
1354 cpdma_ctlr_stop(priv->dma);
1355 for_each_slave(priv, cpsw_slave_stop, priv);
1356 pm_runtime_put_sync(&priv->pdev->dev);
1357 netif_carrier_off(priv->ndev);
1358 return ret;
df828598
M		 1359}
1360
1361static int cpsw_ndo_stop(struct net_device *ndev)
1362{
1363 struct cpsw_priv *priv = netdev_priv(ndev);
1364
1365 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598 1366 netif_stop_queue(priv->ndev);
df828598 1367 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1368
1369 if (cpsw_common_res_usage_state(priv) <= 1) {
d354eb85
M		 1370 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1371
32a7432c
M		 1372 napi_disable(&priv_sl0->napi_rx);
1373 napi_disable(&priv_sl0->napi_tx);
f280e89a 1374 cpts_unregister(priv->cpts);
d9ba8f9e 1375 cpsw_intr_disable(priv);
d9ba8f9e
M		 1376 cpdma_ctlr_stop(priv->dma);
1377 cpsw_ale_stop(priv->ale);
1378 }
df828598 1379 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 1380 pm_runtime_put_sync(&priv->pdev->dev);
d9ba8f9e
M		 1381 if (priv->data.dual_emac)
1382 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1383 return 0;
1384}
1385
1386static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1387 struct net_device *ndev)
1388{
1389 struct cpsw_priv *priv = netdev_priv(ndev);
1390 int ret;
1391
1392 ndev->trans_start = jiffies;
1393
1394 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1395 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1396 ndev->stats.tx_dropped++;
df828598
M		 1397 return NETDEV_TX_OK;
1398 }
1399
9232b16d
M		 1400 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1401 priv->cpts->tx_enable)
2e5b38ab
RC		 1402 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1403
1404 skb_tx_timestamp(skb);
1405
d9ba8f9e 1406 ret = cpsw_tx_packet_submit(ndev, priv, skb);
df828598
M		 1407 if (unlikely(ret != 0)) {
1408 cpsw_err(priv, tx_err, "desc submit failed\n");
1409 goto fail;
1410 }
1411
fae50823
M		 1412 /* If there is no more tx desc left free then we need to
1413 * tell the kernel to stop sending us tx frames.
1414 */
d35162f8 1415 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1416 netif_stop_queue(ndev);
1417
df828598
M		 1418 return NETDEV_TX_OK;
1419fail:
8dc43ddc 1420 ndev->stats.tx_dropped++;
df828598
M		 1421 netif_stop_queue(ndev);
1422 return NETDEV_TX_BUSY;
1423}
1424
2e5b38ab
RC		 1425#ifdef CONFIG_TI_CPTS
1426
1427static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1428{
e86ac13b 1429 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1430 u32 ts_en, seq_id;
1431
9232b16d 1432 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1433 slave_write(slave, 0, CPSW1_TS_CTL);
1434 return;
1435 }
1436
1437 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1438 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1439
9232b16d 1440 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1441 ts_en |= CPSW_V1_TS_TX_EN;
1442
9232b16d 1443 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1444 ts_en |= CPSW_V1_TS_RX_EN;
1445
1446 slave_write(slave, ts_en, CPSW1_TS_CTL);
1447 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1448}
1449
1450static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1451{
d9ba8f9e 1452 struct cpsw_slave *slave;
2e5b38ab
RC		 1453 u32 ctrl, mtype;
1454
d9ba8f9e
M		 1455 if (priv->data.dual_emac)
1456 slave = &priv->slaves[priv->emac_port];
1457 else
e86ac13b 1458 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1459
2e5b38ab 1460 ctrl = slave_read(slave, CPSW2_CONTROL);
09c55372
GC		 1461 switch (priv->version) {
1462 case CPSW_VERSION_2:
1463 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1464
09c55372
GC		 1465 if (priv->cpts->tx_enable)
1466 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1467
09c55372
GC		 1468 if (priv->cpts->rx_enable)
1469 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1470 break;
09c55372
GC		 1471 case CPSW_VERSION_3:
1472 default:
1473 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1474
1475 if (priv->cpts->tx_enable)
1476 ctrl |= CTRL_V3_TX_TS_BITS;
1477
1478 if (priv->cpts->rx_enable)
1479 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1480 break;
09c55372 1481 }
2e5b38ab
RC		 1482
1483 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1484
1485 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1486 slave_write(slave, ctrl, CPSW2_CONTROL);
1487 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1488}
1489
a5b4145b 1490static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1491{
3177bf6f 1492 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1493 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1494 struct hwtstamp_config cfg;
1495
2ee91e54 1496 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1497 priv->version != CPSW_VERSION_2 &&
1498 priv->version != CPSW_VERSION_3)
2ee91e54
BH		 1499 return -EOPNOTSUPP;
1500
2e5b38ab
RC		 1501 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1502 return -EFAULT;
1503
1504 /* reserved for future extensions */
1505 if (cfg.flags)
1506 return -EINVAL;
1507
2ee91e54 1508 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1509 return -ERANGE;
2e5b38ab
RC		 1510
1511 switch (cfg.rx_filter) {
1512 case HWTSTAMP_FILTER_NONE:
1513 cpts->rx_enable = 0;
1514 break;
1515 case HWTSTAMP_FILTER_ALL:
1516 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1517 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1518 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1519 return -ERANGE;
1520 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1521 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1523 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1524 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1525 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1526 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1527 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1528 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1529 cpts->rx_enable = 1;
1530 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1531 break;
1532 default:
1533 return -ERANGE;
1534 }
1535
2ee91e54
BH		 1536 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1537
2e5b38ab
RC		 1538 switch (priv->version) {
1539 case CPSW_VERSION_1:
1540 cpsw_hwtstamp_v1(priv);
1541 break;
1542 case CPSW_VERSION_2:
f7d403cb 1543 case CPSW_VERSION_3:
2e5b38ab
RC		 1544 cpsw_hwtstamp_v2(priv);
1545 break;
1546 default:
2ee91e54 1547 WARN_ON(1);
2e5b38ab
RC		 1548 }
1549
1550 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1551}
1552
a5b4145b
BH		 1553static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1554{
1555 struct cpsw_priv *priv = netdev_priv(dev);
1556 struct cpts *cpts = priv->cpts;
1557 struct hwtstamp_config cfg;
1558
1559 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1560 priv->version != CPSW_VERSION_2 &&
1561 priv->version != CPSW_VERSION_3)
a5b4145b
BH		 1562 return -EOPNOTSUPP;
1563
1564 cfg.flags = 0;
1565 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1566 cfg.rx_filter = (cpts->rx_enable ?
1567 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1568
1569 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1570}
1571
2e5b38ab
RC		 1572#endif /*CONFIG_TI_CPTS*/
1573
1574static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1575{
11f2c988 1576 struct cpsw_priv *priv = netdev_priv(dev);
11f2c988
M		 1577 int slave_no = cpsw_slave_index(priv);
1578
2e5b38ab
RC		 1579 if (!netif_running(dev))
1580 return -EINVAL;
1581
11f2c988 1582 switch (cmd) {
2e5b38ab 1583#ifdef CONFIG_TI_CPTS
11f2c988 1584 case SIOCSHWTSTAMP:
a5b4145b
BH		 1585 return cpsw_hwtstamp_set(dev, req);
1586 case SIOCGHWTSTAMP:
1587 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1588#endif
11f2c988
M		 1589 }
1590
c1b59947
SS		 1591 if (!priv->slaves[slave_no].phy)
1592 return -EOPNOTSUPP;
1593 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1594}
1595
df828598
M		 1596static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1597{
1598 struct cpsw_priv *priv = netdev_priv(ndev);
1599
1600 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1601 ndev->stats.tx_errors++;
df828598 1602 cpsw_intr_disable(priv);
df828598
M		 1603 cpdma_chan_stop(priv->txch);
1604 cpdma_chan_start(priv->txch);
df828598 1605 cpsw_intr_enable(priv);
df828598
M		 1606}
1607
dcfd8d58
M		 1608static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1609{
1610 struct cpsw_priv *priv = netdev_priv(ndev);
1611 struct sockaddr *addr = (struct sockaddr *)p;
1612 int flags = 0;
1613 u16 vid = 0;
1614
1615 if (!is_valid_ether_addr(addr->sa_data))
1616 return -EADDRNOTAVAIL;
1617
1618 if (priv->data.dual_emac) {
1619 vid = priv->slaves[priv->emac_port].port_vlan;
1620 flags = ALE_VLAN;
1621 }
1622
1623 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1624 flags, vid);
1625 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1626 flags, vid);
1627
1628 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1629 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1630 for_each_slave(priv, cpsw_set_slave_mac, priv);
1631
1632 return 0;
1633}
1634
df828598
M		 1635#ifdef CONFIG_NET_POLL_CONTROLLER
1636static void cpsw_ndo_poll_controller(struct net_device *ndev)
1637{
1638 struct cpsw_priv *priv = netdev_priv(ndev);
1639
1640 cpsw_intr_disable(priv);
92cb13fb
FB		 1641 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1642 cpsw_tx_interrupt(priv->irqs_table[1], priv);
df828598 1643 cpsw_intr_enable(priv);
df828598
M		 1644}
1645#endif
1646
3b72c2fe
M		 1647static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1648 unsigned short vid)
1649{
1650 int ret;
9f6bd8fa
M		 1651 int unreg_mcast_mask = 0;
1652 u32 port_mask;
1e5c4bc4 1653
9f6bd8fa
M		 1654 if (priv->data.dual_emac) {
1655 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1656
9f6bd8fa
M		 1657 if (priv->ndev->flags & IFF_ALLMULTI)
1658 unreg_mcast_mask = port_mask;
1659 } else {
1660 port_mask = ALE_ALL_PORTS;
1661
1662 if (priv->ndev->flags & IFF_ALLMULTI)
1663 unreg_mcast_mask = ALE_ALL_PORTS;
1664 else
1665 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1666 }
3b72c2fe 1667
9f6bd8fa 1668 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1e5c4bc4 1669 unreg_mcast_mask << priv->host_port);
3b72c2fe
M		 1670 if (ret != 0)
1671 return ret;
1672
1673 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1674 priv->host_port, ALE_VLAN, vid);
1675 if (ret != 0)
1676 goto clean_vid;
1677
1678 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
9f6bd8fa 1679 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1680 if (ret != 0)
1681 goto clean_vlan_ucast;
1682 return 0;
1683
1684clean_vlan_ucast:
1685 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1686 priv->host_port, ALE_VLAN, vid);
1687clean_vid:
1688 cpsw_ale_del_vlan(priv->ale, vid, 0);
1689 return ret;
1690}
1691
1692static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1693 __be16 proto, u16 vid)
3b72c2fe
M		 1694{
1695 struct cpsw_priv *priv = netdev_priv(ndev);
1696
1697 if (vid == priv->data.default_vlan)
1698 return 0;
1699
02a54164
M		 1700 if (priv->data.dual_emac) {
1701 /* In dual EMAC, reserved VLAN id should not be used for
1702 * creating VLAN interfaces as this can break the dual
1703 * EMAC port separation
1704 */
1705 int i;
1706
1707 for (i = 0; i < priv->data.slaves; i++) {
1708 if (vid == priv->slaves[i].port_vlan)
1709 return -EINVAL;
1710 }
1711 }
1712
3b72c2fe
M		 1713 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1714 return cpsw_add_vlan_ale_entry(priv, vid);
1715}
1716
1717static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1718 __be16 proto, u16 vid)
3b72c2fe
M		 1719{
1720 struct cpsw_priv *priv = netdev_priv(ndev);
1721 int ret;
1722
1723 if (vid == priv->data.default_vlan)
1724 return 0;
1725
02a54164
M		 1726 if (priv->data.dual_emac) {
1727 int i;
1728
1729 for (i = 0; i < priv->data.slaves; i++) {
1730 if (vid == priv->slaves[i].port_vlan)
1731 return -EINVAL;
1732 }
1733 }
1734
3b72c2fe
M		 1735 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1736 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1737 if (ret != 0)
1738 return ret;
1739
1740 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1741 priv->host_port, ALE_VLAN, vid);
1742 if (ret != 0)
1743 return ret;
1744
1745 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1746 0, ALE_VLAN, vid);
1747}
1748
df828598
M		 1749static const struct net_device_ops cpsw_netdev_ops = {
1750 .ndo_open = cpsw_ndo_open,
1751 .ndo_stop = cpsw_ndo_stop,
1752 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1753 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1754 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1755 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1756 .ndo_change_mtu = eth_change_mtu,
df828598 1757 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1758 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1759#ifdef CONFIG_NET_POLL_CONTROLLER
1760 .ndo_poll_controller = cpsw_ndo_poll_controller,
1761#endif
3b72c2fe
M		 1762 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1763 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1764};
1765
52c4f0ec
M		 1766static int cpsw_get_regs_len(struct net_device *ndev)
1767{
1768 struct cpsw_priv *priv = netdev_priv(ndev);
1769
1770 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1771}
1772
1773static void cpsw_get_regs(struct net_device *ndev,
1774 struct ethtool_regs *regs, void *p)
1775{
1776 struct cpsw_priv *priv = netdev_priv(ndev);
1777 u32 *reg = p;
1778
1779 /* update CPSW IP version */
1780 regs->version = priv->version;
1781
1782 cpsw_ale_dump(priv->ale, reg);
1783}
1784
df828598
M		 1785static void cpsw_get_drvinfo(struct net_device *ndev,
1786 struct ethtool_drvinfo *info)
1787{
1788 struct cpsw_priv *priv = netdev_priv(ndev);
7826d43f 1789
52c4f0ec 1790 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f
JP		 1791 strlcpy(info->version, "1.0", sizeof(info->version));
1792 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
df828598
M		 1793}
1794
1795static u32 cpsw_get_msglevel(struct net_device *ndev)
1796{
1797 struct cpsw_priv *priv = netdev_priv(ndev);
1798 return priv->msg_enable;
1799}
1800
1801static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1802{
1803 struct cpsw_priv *priv = netdev_priv(ndev);
1804 priv->msg_enable = value;
1805}
1806
2e5b38ab
RC		 1807static int cpsw_get_ts_info(struct net_device *ndev,
1808 struct ethtool_ts_info *info)
1809{
1810#ifdef CONFIG_TI_CPTS
1811 struct cpsw_priv *priv = netdev_priv(ndev);
1812
1813 info->so_timestamping =
1814 SOF_TIMESTAMPING_TX_HARDWARE |
1815 SOF_TIMESTAMPING_TX_SOFTWARE |
1816 SOF_TIMESTAMPING_RX_HARDWARE |
1817 SOF_TIMESTAMPING_RX_SOFTWARE |
1818 SOF_TIMESTAMPING_SOFTWARE |
1819 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1820 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1821 info->tx_types =
1822 (1 << HWTSTAMP_TX_OFF) |
1823 (1 << HWTSTAMP_TX_ON);
1824 info->rx_filters =
1825 (1 << HWTSTAMP_FILTER_NONE) |
1826 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1827#else
1828 info->so_timestamping =
1829 SOF_TIMESTAMPING_TX_SOFTWARE |
1830 SOF_TIMESTAMPING_RX_SOFTWARE |
1831 SOF_TIMESTAMPING_SOFTWARE;
1832 info->phc_index = -1;
1833 info->tx_types = 0;
1834 info->rx_filters = 0;
1835#endif
1836 return 0;
1837}
1838
d3bb9c58
M		 1839static int cpsw_get_settings(struct net_device *ndev,
1840 struct ethtool_cmd *ecmd)
1841{
1842 struct cpsw_priv *priv = netdev_priv(ndev);
1843 int slave_no = cpsw_slave_index(priv);
1844
1845 if (priv->slaves[slave_no].phy)
1846 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1847 else
1848 return -EOPNOTSUPP;
1849}
1850
1851static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1852{
1853 struct cpsw_priv *priv = netdev_priv(ndev);
1854 int slave_no = cpsw_slave_index(priv);
1855
1856 if (priv->slaves[slave_no].phy)
1857 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1858 else
1859 return -EOPNOTSUPP;
1860}
1861
d8a64420
MU		 1862static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1863{
1864 struct cpsw_priv *priv = netdev_priv(ndev);
1865 int slave_no = cpsw_slave_index(priv);
1866
1867 wol->supported = 0;
1868 wol->wolopts = 0;
1869
1870 if (priv->slaves[slave_no].phy)
1871 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1872}
1873
1874static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1875{
1876 struct cpsw_priv *priv = netdev_priv(ndev);
1877 int slave_no = cpsw_slave_index(priv);
1878
1879 if (priv->slaves[slave_no].phy)
1880 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1881 else
1882 return -EOPNOTSUPP;
1883}
1884
1923d6e4
M		 1885static void cpsw_get_pauseparam(struct net_device *ndev,
1886 struct ethtool_pauseparam *pause)
1887{
1888 struct cpsw_priv *priv = netdev_priv(ndev);
1889
1890 pause->autoneg = AUTONEG_DISABLE;
1891 pause->rx_pause = priv->rx_pause ? true : false;
1892 pause->tx_pause = priv->tx_pause ? true : false;
1893}
1894
1895static int cpsw_set_pauseparam(struct net_device *ndev,
1896 struct ethtool_pauseparam *pause)
1897{
1898 struct cpsw_priv *priv = netdev_priv(ndev);
1899 bool link;
1900
1901 priv->rx_pause = pause->rx_pause ? true : false;
1902 priv->tx_pause = pause->tx_pause ? true : false;
1903
1904 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1905
1906 return 0;
1907}
1908
df828598
M		 1909static const struct ethtool_ops cpsw_ethtool_ops = {
1910 .get_drvinfo = cpsw_get_drvinfo,
1911 .get_msglevel = cpsw_get_msglevel,
1912 .set_msglevel = cpsw_set_msglevel,
1913 .get_link = ethtool_op_get_link,
2e5b38ab 1914 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1915 .get_settings = cpsw_get_settings,
1916 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1917 .get_coalesce = cpsw_get_coalesce,
1918 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1919 .get_sset_count = cpsw_get_sset_count,
1920 .get_strings = cpsw_get_strings,
1921 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 1922 .get_pauseparam = cpsw_get_pauseparam,
1923 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 1924 .get_wol = cpsw_get_wol,
1925 .set_wol = cpsw_set_wol,
52c4f0ec
M		 1926 .get_regs_len = cpsw_get_regs_len,
1927 .get_regs = cpsw_get_regs,
df828598
M		 1928};
1929
549985ee
RC		 1930static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1931 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1932{
1933 void __iomem *regs = priv->regs;
1934 int slave_num = slave->slave_num;
1935 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1936
1937 slave->data = data;
549985ee
RC		 1938 slave->regs = regs + slave_reg_ofs;
1939 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 1940 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 1941}
1942
9e42f715 1943static int cpsw_probe_dt(struct cpsw_priv *priv,
2eb32b0a
M		 1944 struct platform_device *pdev)
1945{
1946 struct device_node *node = pdev->dev.of_node;
1947 struct device_node *slave_node;
9e42f715 1948 struct cpsw_platform_data *data = &priv->data;
2eb32b0a
M		 1949 int i = 0, ret;
1950 u32 prop;
1951
1952 if (!node)
1953 return -EINVAL;
1954
1955 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 1956 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 1957 return -EINVAL;
1958 }
1959 data->slaves = prop;
1960
e86ac13b 1961 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 1962 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 1963 return -EINVAL;
78ca0b28 1964 }
e86ac13b 1965 data->active_slave = prop;
78ca0b28 1966
00ab94ee 1967 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 1968 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 1969 return -EINVAL;
00ab94ee
RC		 1970 }
1971 data->cpts_clock_mult = prop;
1972
1973 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 1974 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 1975 return -EINVAL;
00ab94ee
RC		 1976 }
1977 data->cpts_clock_shift = prop;
1978
aa1a15e2
DM		 1979 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1980 * sizeof(struct cpsw_slave_data),
1981 GFP_KERNEL);
b2adaca9 1982 if (!data->slave_data)
aa1a15e2 1983 return -ENOMEM;
2eb32b0a 1984
2eb32b0a 1985 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 1986 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 1987 return -EINVAL;
2eb32b0a
M		 1988 }
1989 data->channels = prop;
1990
2eb32b0a 1991 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 1992 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 1993 return -EINVAL;
2eb32b0a
M		 1994 }
1995 data->ale_entries = prop;
1996
2eb32b0a 1997 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 1998 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 1999 return -EINVAL;
2eb32b0a
M		 2000 }
2001 data->bd_ram_size = prop;
2002
2003 if (of_property_read_u32(node, "rx_descs", &prop)) {
88c99ff6 2004 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
aa1a15e2 2005 return -EINVAL;
2eb32b0a
M		 2006 }
2007 data->rx_descs = prop;
2008
2009 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2010 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2011 return -EINVAL;
2eb32b0a
M		 2012 }
2013 data->mac_control = prop;
2014
281abd96
MP		 2015 if (of_property_read_bool(node, "dual_emac"))
2016 data->dual_emac = 1;
d9ba8f9e 2017
549985ee
RC		 2018 /*
2019 * Populate all the child nodes here...
2020 */
2021 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2022 /* We do not want to force this, as in some cases may not have child */
2023 if (ret)
88c99ff6 2024 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2025
f468b10e 2026 for_each_child_of_node(node, slave_node) {
2eb32b0a 2027 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2028 const void *mac_addr = NULL;
549985ee
RC		 2029 int lenp;
2030 const __be32 *parp;
549985ee 2031
f468b10e
MP		 2032 /* This is no slave child node, continue */
2033 if (strcmp(slave_node->name, "slave"))
2034 continue;
2035
df637193 2036 priv->phy_node = of_parse_phandle(slave_node, "phy-handle", 0);
f1eea5c1 2037 parp = of_get_property(slave_node, "phy_id", &lenp);
1f71e8c9 2038 if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2039 struct device_node *phy_node;
2040 struct phy_device *phy_dev;
1f71e8c9 2041
dfc0a6d3
DR		 2042 /* In the case of a fixed PHY, the DT node associated
2043 * to the PHY is the Ethernet MAC DT node.
2044 */
1f71e8c9
MB		 2045 ret = of_phy_register_fixed_link(slave_node);
2046 if (ret)
2047 return ret;
dfc0a6d3
DR		 2048 phy_node = of_node_get(slave_node);
2049 phy_dev = of_phy_find_device(phy_node);
2050 if (!phy_dev)
1f71e8c9
MB		 2051 return -ENODEV;
2052 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
e5a03bfd
AL		 2053 PHY_ID_FMT, phy_dev->mdio.bus->id,
2054 phy_dev->mdio.addr);
f1eea5c1
DR		 2055 } else if (parp) {
2056 u32 phyid;
2057 struct device_node *mdio_node;
2058 struct platform_device *mdio;
2059
2060 if (lenp != (sizeof(__be32) * 2)) {
2061 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2062 goto no_phy_slave;
2063 }
2064 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2065 phyid = be32_to_cpup(parp+1);
2066 mdio = of_find_device_by_node(mdio_node);
2067 of_node_put(mdio_node);
2068 if (!mdio) {
2069 dev_err(&pdev->dev, "Missing mdio platform device\n");
2070 return -EINVAL;
2071 }
2072 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2073 PHY_ID_FMT, mdio->name, phyid);
2074 } else {
2075 dev_err(&pdev->dev, "No slave[%d] phy_id or fixed-link property\n", i);
47276fcc 2076 goto no_phy_slave;
2eb32b0a 2077 }
47276fcc
M		 2078 slave_data->phy_if = of_get_phy_mode(slave_node);
2079 if (slave_data->phy_if < 0) {
2080 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2081 i);
2082 return slave_data->phy_if;
2083 }
2084
2085no_phy_slave:
2eb32b0a 2086 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2087 if (mac_addr) {
2eb32b0a 2088 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2089 } else {
b6745f6e
M		 2090 ret = ti_cm_get_macid(&pdev->dev, i,
2091 slave_data->mac_addr);
2092 if (ret)
2093 return ret;
0ba517b1 2094 }
d9ba8f9e 2095 if (data->dual_emac) {
91c4166c 2096 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2097 &prop)) {
88c99ff6 2098 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2099 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2100 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2101 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2102 } else {
2103 slave_data->dual_emac_res_vlan = prop;
2104 }
2105 }
2106
2eb32b0a 2107 i++;
3a27bfac
M		 2108 if (i == data->slaves)
2109 break;
2eb32b0a
M		 2110 }
2111
2112 return 0;
2eb32b0a
M		 2113}
2114
d9ba8f9e
M		 2115static int cpsw_probe_dual_emac(struct platform_device *pdev,
2116 struct cpsw_priv *priv)
2117{
2118 struct cpsw_platform_data *data = &priv->data;
2119 struct net_device *ndev;
2120 struct cpsw_priv *priv_sl2;
2121 int ret = 0, i;
2122
2123 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2124 if (!ndev) {
88c99ff6 2125 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2126 return -ENOMEM;
2127 }
2128
2129 priv_sl2 = netdev_priv(ndev);
2130 spin_lock_init(&priv_sl2->lock);
2131 priv_sl2->data = *data;
2132 priv_sl2->pdev = pdev;
2133 priv_sl2->ndev = ndev;
2134 priv_sl2->dev = &ndev->dev;
2135 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2136 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2137
2138 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2139 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2140 ETH_ALEN);
88c99ff6 2141 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2142 } else {
2143 random_ether_addr(priv_sl2->mac_addr);
88c99ff6 2144 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2145 }
2146 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2147
2148 priv_sl2->slaves = priv->slaves;
2149 priv_sl2->clk = priv->clk;
2150
ff5b8ef2
M		 2151 priv_sl2->coal_intvl = 0;
2152 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2153
d9ba8f9e
M		 2154 priv_sl2->regs = priv->regs;
2155 priv_sl2->host_port = priv->host_port;
2156 priv_sl2->host_port_regs = priv->host_port_regs;
2157 priv_sl2->wr_regs = priv->wr_regs;
d9718546 2158 priv_sl2->hw_stats = priv->hw_stats;
d9ba8f9e
M		 2159 priv_sl2->dma = priv->dma;
2160 priv_sl2->txch = priv->txch;
2161 priv_sl2->rxch = priv->rxch;
2162 priv_sl2->ale = priv->ale;
2163 priv_sl2->emac_port = 1;
2164 priv->slaves[1].ndev = ndev;
2165 priv_sl2->cpts = priv->cpts;
2166 priv_sl2->version = priv->version;
2167
2168 for (i = 0; i < priv->num_irqs; i++) {
2169 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2170 priv_sl2->num_irqs = priv->num_irqs;
2171 }
f646968f 2172 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2173
2174 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2175 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2176
2177 /* register the network device */
2178 SET_NETDEV_DEV(ndev, &pdev->dev);
2179 ret = register_netdev(ndev);
2180 if (ret) {
88c99ff6 2181 dev_err(&pdev->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2182 free_netdev(ndev);
2183 ret = -ENODEV;
2184 }
2185
2186 return ret;
2187}
2188
7da11600
M		 2189#define CPSW_QUIRK_IRQ BIT(0)
2190
2191static struct platform_device_id cpsw_devtype[] = {
2192 {
2193 /* keep it for existing comaptibles */
2194 .name = "cpsw",
2195 .driver_data = CPSW_QUIRK_IRQ,
2196 }, {
2197 .name = "am335x-cpsw",
2198 .driver_data = CPSW_QUIRK_IRQ,
2199 }, {
2200 .name = "am4372-cpsw",
2201 .driver_data = 0,
2202 }, {
2203 .name = "dra7-cpsw",
2204 .driver_data = 0,
2205 }, {
2206 /* sentinel */
2207 }
2208};
2209MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2210
2211enum ti_cpsw_type {
2212 CPSW = 0,
2213 AM335X_CPSW,
2214 AM4372_CPSW,
2215 DRA7_CPSW,
2216};
2217
2218static const struct of_device_id cpsw_of_mtable[] = {
2219 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2220 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2221 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2222 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2223 { /* sentinel */ },
2224};
2225MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2226
663e12e6 2227static int cpsw_probe(struct platform_device *pdev)
df828598 2228{
d1bd9acf 2229 struct cpsw_platform_data *data;
df828598
M		 2230 struct net_device *ndev;
2231 struct cpsw_priv *priv;
2232 struct cpdma_params dma_params;
2233 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2234 void __iomem *ss_regs;
2235 struct resource *res, *ss_res;
7da11600 2236 const struct of_device_id *of_id;
1d147ccb 2237 struct gpio_descs *mode;
549985ee 2238 u32 slave_offset, sliver_offset, slave_size;
5087b915
FB		 2239 int ret = 0, i;
2240 int irq;
df828598 2241
df828598
M		 2242 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2243 if (!ndev) {
88c99ff6 2244 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2245 return -ENOMEM;
2246 }
2247
2248 platform_set_drvdata(pdev, ndev);
2249 priv = netdev_priv(ndev);
2250 spin_lock_init(&priv->lock);
df828598
M		 2251 priv->pdev = pdev;
2252 priv->ndev = ndev;
2253 priv->dev = &ndev->dev;
2254 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2255 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 2256 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
ab8e99d2 2257 if (!priv->cpts) {
88c99ff6 2258 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2259 ret = -ENOMEM;
9232b16d
M		 2260 goto clean_ndev_ret;
2261 }
df828598 2262
1d147ccb
M		 2263 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2264 if (IS_ERR(mode)) {
2265 ret = PTR_ERR(mode);
2266 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2267 goto clean_ndev_ret;
2268 }
2269
1fb19aa7
VH		 2270 /*
2271 * This may be required here for child devices.
2272 */
2273 pm_runtime_enable(&pdev->dev);
2274
739683b4
M		 2275 /* Select default pin state */
2276 pinctrl_pm_select_default_state(&pdev->dev);
2277
9e42f715 2278 if (cpsw_probe_dt(priv, pdev)) {
88c99ff6 2279 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2280 ret = -ENODEV;
aa1a15e2 2281 goto clean_runtime_disable_ret;
2eb32b0a 2282 }
df637193 2283 data = &priv->data;
2eb32b0a 2284
df828598
M		 2285 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2286 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2287 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2288 } else {
7efd26d0 2289 eth_random_addr(priv->mac_addr);
88c99ff6 2290 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2291 }
2292
2293 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2294
df637193
AG		 2295 priv->slaves = devm_kzalloc(&pdev->dev,
2296 sizeof(struct cpsw_slave) * data->slaves,
2297 GFP_KERNEL);
2298 if (!priv->slaves) {
2299 ret = -ENOMEM;
2300 goto clean_runtime_disable_ret;
2301 }
2302 for (i = 0; i < data->slaves; i++)
2303 priv->slaves[i].slave_num = i;
2304
d9ba8f9e
M		 2305 priv->slaves[0].ndev = ndev;
2306 priv->emac_port = 0;
2307
aa1a15e2 2308 priv->clk = devm_clk_get(&pdev->dev, "fck");
df828598 2309 if (IS_ERR(priv->clk)) {
aa1a15e2 2310 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2311 ret = -ENODEV;
aa1a15e2 2312 goto clean_runtime_disable_ret;
df828598 2313 }
ff5b8ef2
M		 2314 priv->coal_intvl = 0;
2315 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
df828598 2316
aa1a15e2
DM		 2317 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2318 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2319 if (IS_ERR(ss_regs)) {
2320 ret = PTR_ERR(ss_regs);
2321 goto clean_runtime_disable_ret;
df828598 2322 }
549985ee 2323 priv->regs = ss_regs;
549985ee 2324 priv->host_port = HOST_PORT_NUM;
df828598 2325
f280e89a
M		 2326 /* Need to enable clocks with runtime PM api to access module
2327 * registers
2328 */
2329 pm_runtime_get_sync(&pdev->dev);
2330 priv->version = readl(&priv->regs->id_ver);
2331 pm_runtime_put_sync(&pdev->dev);
2332
aa1a15e2
DM		 2333 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2334 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2335 if (IS_ERR(priv->wr_regs)) {
2336 ret = PTR_ERR(priv->wr_regs);
2337 goto clean_runtime_disable_ret;
df828598 2338 }
df828598
M		 2339
2340 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2341 memset(&ale_params, 0, sizeof(ale_params));
2342
2343 switch (priv->version) {
2344 case CPSW_VERSION_1:
2345 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546
M		 2346 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2347 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2348 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2349 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2350 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2351 slave_offset = CPSW1_SLAVE_OFFSET;
2352 slave_size = CPSW1_SLAVE_SIZE;
2353 sliver_offset = CPSW1_SLIVER_OFFSET;
2354 dma_params.desc_mem_phys = 0;
2355 break;
2356 case CPSW_VERSION_2:
c193f365 2357 case CPSW_VERSION_3:
926489be 2358 case CPSW_VERSION_4:
549985ee 2359 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546
M		 2360 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2361 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2362 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2363 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2364 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2365 slave_offset = CPSW2_SLAVE_OFFSET;
2366 slave_size = CPSW2_SLAVE_SIZE;
2367 sliver_offset = CPSW2_SLIVER_OFFSET;
2368 dma_params.desc_mem_phys =
aa1a15e2 2369 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2370 break;
2371 default:
2372 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2373 ret = -ENODEV;
aa1a15e2 2374 goto clean_runtime_disable_ret;
549985ee
RC		 2375 }
2376 for (i = 0; i < priv->data.slaves; i++) {
2377 struct cpsw_slave *slave = &priv->slaves[i];
2378 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2379 slave_offset += slave_size;
2380 sliver_offset += SLIVER_SIZE;
2381 }
2382
df828598 2383 dma_params.dev = &pdev->dev;
549985ee
RC		 2384 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2385 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2386 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2387 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2388 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2389
2390 dma_params.num_chan = data->channels;
2391 dma_params.has_soft_reset = true;
2392 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2393 dma_params.desc_mem_size = data->bd_ram_size;
2394 dma_params.desc_align = 16;
2395 dma_params.has_ext_regs = true;
549985ee 2396 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2397
2398 priv->dma = cpdma_ctlr_create(&dma_params);
2399 if (!priv->dma) {
2400 dev_err(priv->dev, "error initializing dma\n");
2401 ret = -ENOMEM;
aa1a15e2 2402 goto clean_runtime_disable_ret;
df828598
M		 2403 }
2404
2405 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2406 cpsw_tx_handler);
2407 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2408 cpsw_rx_handler);
2409
2410 if (WARN_ON(!priv->txch || !priv->rxch)) {
2411 dev_err(priv->dev, "error initializing dma channels\n");
2412 ret = -ENOMEM;
2413 goto clean_dma_ret;
2414 }
2415
df828598 2416 ale_params.dev = &ndev->dev;
df828598
M		 2417 ale_params.ale_ageout = ale_ageout;
2418 ale_params.ale_entries = data->ale_entries;
2419 ale_params.ale_ports = data->slaves;
2420
2421 priv->ale = cpsw_ale_create(&ale_params);
2422 if (!priv->ale) {
2423 dev_err(priv->dev, "error initializing ale engine\n");
2424 ret = -ENODEV;
2425 goto clean_dma_ret;
2426 }
2427
c03abd84 2428 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 2429 if (ndev->irq < 0) {
2430 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 2431 ret = ndev->irq;
df828598
M		 2432 goto clean_ale_ret;
2433 }
2434
7da11600
M		 2435 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2436 if (of_id) {
2437 pdev->id_entry = of_id->data;
2438 if (pdev->id_entry->driver_data)
2439 priv->quirk_irq = true;
2440 }
2441
c03abd84
FB		 2442 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2443 * MISC IRQs which are always kept disabled with this driver so
2444 * we will not request them.
2445 *
2446 * If anyone wants to implement support for those, make sure to
2447 * first request and append them to irqs_table array.
2448 */
c2b32e58 2449
c03abd84 2450 /* RX IRQ */
5087b915 2451 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 2452 if (irq < 0) {
2453 ret = irq;
5087b915 2454 goto clean_ale_ret;
c1e3334f 2455 }
5087b915 2456
c03abd84
FB		 2457 priv->irqs_table[0] = irq;
2458 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
5087b915
FB		 2459 0, dev_name(&pdev->dev), priv);
2460 if (ret < 0) {
2461 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2462 goto clean_ale_ret;
2463 }
2464
c03abd84 2465 /* TX IRQ */
5087b915 2466 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 2467 if (irq < 0) {
2468 ret = irq;
5087b915 2469 goto clean_ale_ret;
c1e3334f 2470 }
5087b915 2471
c03abd84
FB		 2472 priv->irqs_table[1] = irq;
2473 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
5087b915
FB		 2474 0, dev_name(&pdev->dev), priv);
2475 if (ret < 0) {
2476 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2477 goto clean_ale_ret;
df828598 2478 }
c03abd84 2479 priv->num_irqs = 2;
c2b32e58 2480
f646968f 2481 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2482
2483 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2484 ndev->ethtool_ops = &cpsw_ethtool_ops;
32a7432c 2485 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
d64b5e85 2486 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
df828598
M		 2487
2488 /* register the network device */
2489 SET_NETDEV_DEV(ndev, &pdev->dev);
2490 ret = register_netdev(ndev);
2491 if (ret) {
2492 dev_err(priv->dev, "error registering net device\n");
2493 ret = -ENODEV;
aa1a15e2 2494 goto clean_ale_ret;
df828598
M		 2495 }
2496
1a3b5056
OJ		 2497 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2498 &ss_res->start, ndev->irq);
df828598 2499
d9ba8f9e
M		 2500 if (priv->data.dual_emac) {
2501 ret = cpsw_probe_dual_emac(pdev, priv);
2502 if (ret) {
2503 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2504 goto clean_ale_ret;
d9ba8f9e
M		 2505 }
2506 }
2507
df828598
M		 2508 return 0;
2509
df828598
M		 2510clean_ale_ret:
2511 cpsw_ale_destroy(priv->ale);
2512clean_dma_ret:
2513 cpdma_chan_destroy(priv->txch);
2514 cpdma_chan_destroy(priv->rxch);
2515 cpdma_ctlr_destroy(priv->dma);
aa1a15e2 2516clean_runtime_disable_ret:
f150bd7f 2517 pm_runtime_disable(&pdev->dev);
df828598 2518clean_ndev_ret:
d1bd9acf 2519 free_netdev(priv->ndev);
df828598
M		 2520 return ret;
2521}
2522
030b16a0
M		 2523static int cpsw_remove_child_device(struct device *dev, void *c)
2524{
2525 struct platform_device *pdev = to_platform_device(dev);
2526
2527 of_device_unregister(pdev);
2528
2529 return 0;
2530}
2531
663e12e6 2532static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2533{
2534 struct net_device *ndev = platform_get_drvdata(pdev);
2535 struct cpsw_priv *priv = netdev_priv(ndev);
2536
d1bd9acf
SS		 2537 if (priv->data.dual_emac)
2538 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2539 unregister_netdev(ndev);
df828598 2540
df828598
M		 2541 cpsw_ale_destroy(priv->ale);
2542 cpdma_chan_destroy(priv->txch);
2543 cpdma_chan_destroy(priv->rxch);
2544 cpdma_ctlr_destroy(priv->dma);
f150bd7f 2545 pm_runtime_disable(&pdev->dev);
030b16a0 2546 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
d1bd9acf
SS		 2547 if (priv->data.dual_emac)
2548 free_netdev(cpsw_get_slave_ndev(priv, 1));
df828598 2549 free_netdev(ndev);
df828598
M		 2550 return 0;
2551}
2552
8963a504 2553#ifdef CONFIG_PM_SLEEP
df828598
M		 2554static int cpsw_suspend(struct device *dev)
2555{
2556 struct platform_device *pdev = to_platform_device(dev);
2557 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2558 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2559
618073e3
M		 2560 if (priv->data.dual_emac) {
2561 int i;
1e7a2e21 2562
618073e3
M		 2563 for (i = 0; i < priv->data.slaves; i++) {
2564 if (netif_running(priv->slaves[i].ndev))
2565 cpsw_ndo_stop(priv->slaves[i].ndev);
2566 soft_reset_slave(priv->slaves + i);
2567 }
2568 } else {
2569 if (netif_running(ndev))
2570 cpsw_ndo_stop(ndev);
2571 for_each_slave(priv, soft_reset_slave);
2572 }
1e7a2e21 2573
f150bd7f
M		 2574 pm_runtime_put_sync(&pdev->dev);
2575
739683b4
M		 2576 /* Select sleep pin state */
2577 pinctrl_pm_select_sleep_state(&pdev->dev);
2578
df828598
M		 2579 return 0;
2580}
2581
2582static int cpsw_resume(struct device *dev)
2583{
2584 struct platform_device *pdev = to_platform_device(dev);
2585 struct net_device *ndev = platform_get_drvdata(pdev);
618073e3 2586 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2587
f150bd7f 2588 pm_runtime_get_sync(&pdev->dev);
739683b4
M		 2589
2590 /* Select default pin state */
2591 pinctrl_pm_select_default_state(&pdev->dev);
2592
618073e3
M		 2593 if (priv->data.dual_emac) {
2594 int i;
2595
2596 for (i = 0; i < priv->data.slaves; i++) {
2597 if (netif_running(priv->slaves[i].ndev))
2598 cpsw_ndo_open(priv->slaves[i].ndev);
2599 }
2600 } else {
2601 if (netif_running(ndev))
2602 cpsw_ndo_open(ndev);
2603 }
df828598
M		 2604 return 0;
2605}
8963a504 2606#endif
df828598 2607
8963a504 2608static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 2609
2610static struct platform_driver cpsw_driver = {
2611 .driver = {
2612 .name = "cpsw",
df828598 2613 .pm = &cpsw_pm_ops,
1e5c76d4 2614 .of_match_table = cpsw_of_mtable,
df828598
M		 2615 },
2616 .probe = cpsw_probe,
663e12e6 2617 .remove = cpsw_remove,
df828598
M		 2618};
2619
6fb3b6b5 2620module_platform_driver(cpsw_driver);
df828598
M		 2621
2622MODULE_LICENSE("GPL");
2623MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2624MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2625MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
This page took 0.49006 seconds and 5 git commands to generate.