projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'regulator/for-next'
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
e05107e6 127#define CPDMA_TX_PRIORITY_MAP 0x01234567
df828598 128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
606f3993
IK		 143#define cpsw_slave_index(cpsw, priv) \
144 ((cpsw->data.dual_emac) ? priv->emac_port : \
145 cpsw->data.active_slave)
e38b5a3d 146#define IRQ_NUM 2
e05107e6 147#define CPSW_MAX_QUEUES 8
d3bb9c58 148
df828598
M		 149static int debug_level;
150module_param(debug_level, int, 0);
151MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
152
153static int ale_ageout = 10;
154module_param(ale_ageout, int, 0);
155MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
156
157static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
158module_param(rx_packet_max, int, 0);
159MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
160
996a5c27 161struct cpsw_wr_regs {
df828598
M		 162 u32 id_ver;
163 u32 soft_reset;
164 u32 control;
165 u32 int_control;
166 u32 rx_thresh_en;
167 u32 rx_en;
168 u32 tx_en;
169 u32 misc_en;
ff5b8ef2
M		 170 u32 mem_allign1[8];
171 u32 rx_thresh_stat;
172 u32 rx_stat;
173 u32 tx_stat;
174 u32 misc_stat;
175 u32 mem_allign2[8];
176 u32 rx_imax;
177 u32 tx_imax;
178
df828598
M		 179};
180
996a5c27 181struct cpsw_ss_regs {
df828598
M		 182 u32 id_ver;
183 u32 control;
184 u32 soft_reset;
185 u32 stat_port_en;
186 u32 ptype;
bd357af2
RC		 187 u32 soft_idle;
188 u32 thru_rate;
189 u32 gap_thresh;
190 u32 tx_start_wds;
191 u32 flow_control;
192 u32 vlan_ltype;
193 u32 ts_ltype;
194 u32 dlr_ltype;
df828598
M		 195};
196
9750a3ad
RC		 197/* CPSW_PORT_V1 */
198#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
199#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
200#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
201#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
202#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
203#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
204#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
205#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
206
207/* CPSW_PORT_V2 */
208#define CPSW2_CONTROL 0x00 /* Control Register */
209#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
210#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
211#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
212#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
213#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
214#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
215
216/* CPSW_PORT_V1 and V2 */
217#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
218#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
219#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
220
221/* CPSW_PORT_V2 only */
222#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
223#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
224#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
225#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
226#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
227#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
228#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
229#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
230
231/* Bit definitions for the CPSW2_CONTROL register */
232#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
233#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
234#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
235#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
236#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
237#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
238#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
239#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
240#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
241#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 242#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
243#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 244#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
245#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
246#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
247#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
248#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
249
09c55372
GC		 250#define CTRL_V2_TS_BITS \
251 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
252 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 253
09c55372
GC		 254#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
255#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
256#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
257
258
259#define CTRL_V3_TS_BITS \
260 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
261 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
262 TS_LTYPE1_EN)
263
264#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
265#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
266#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 267
268/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
269#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
270#define TS_SEQ_ID_OFFSET_MASK (0x3f)
271#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
272#define TS_MSG_TYPE_EN_MASK (0xffff)
273
274/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
275#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 276
2e5b38ab
RC		 277/* Bit definitions for the CPSW1_TS_CTL register */
278#define CPSW_V1_TS_RX_EN BIT(0)
279#define CPSW_V1_TS_TX_EN BIT(4)
280#define CPSW_V1_MSG_TYPE_OFS 16
281
282/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
283#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
284
df828598
M		 285struct cpsw_host_regs {
286 u32 max_blks;
287 u32 blk_cnt;
d9ba8f9e 288 u32 tx_in_ctl;
df828598
M		 289 u32 port_vlan;
290 u32 tx_pri_map;
291 u32 cpdma_tx_pri_map;
292 u32 cpdma_rx_chan_map;
293};
294
295struct cpsw_sliver_regs {
296 u32 id_ver;
297 u32 mac_control;
298 u32 mac_status;
299 u32 soft_reset;
300 u32 rx_maxlen;
301 u32 __reserved_0;
302 u32 rx_pause;
303 u32 tx_pause;
304 u32 __reserved_1;
305 u32 rx_pri_map;
306};
307
d9718546
M		 308struct cpsw_hw_stats {
309 u32 rxgoodframes;
310 u32 rxbroadcastframes;
311 u32 rxmulticastframes;
312 u32 rxpauseframes;
313 u32 rxcrcerrors;
314 u32 rxaligncodeerrors;
315 u32 rxoversizedframes;
316 u32 rxjabberframes;
317 u32 rxundersizedframes;
318 u32 rxfragments;
319 u32 __pad_0[2];
320 u32 rxoctets;
321 u32 txgoodframes;
322 u32 txbroadcastframes;
323 u32 txmulticastframes;
324 u32 txpauseframes;
325 u32 txdeferredframes;
326 u32 txcollisionframes;
327 u32 txsinglecollframes;
328 u32 txmultcollframes;
329 u32 txexcessivecollisions;
330 u32 txlatecollisions;
331 u32 txunderrun;
332 u32 txcarriersenseerrors;
333 u32 txoctets;
334 u32 octetframes64;
335 u32 octetframes65t127;
336 u32 octetframes128t255;
337 u32 octetframes256t511;
338 u32 octetframes512t1023;
339 u32 octetframes1024tup;
340 u32 netoctets;
341 u32 rxsofoverruns;
342 u32 rxmofoverruns;
343 u32 rxdmaoverruns;
344};
345
df828598 346struct cpsw_slave {
9750a3ad 347 void __iomem *regs;
df828598
M		 348 struct cpsw_sliver_regs __iomem *sliver;
349 int slave_num;
350 u32 mac_control;
351 struct cpsw_slave_data *data;
352 struct phy_device *phy;
d9ba8f9e
M		 353 struct net_device *ndev;
354 u32 port_vlan;
355 u32 open_stat;
df828598
M		 356};
357
9750a3ad
RC		 358static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
359{
360 return __raw_readl(slave->regs + offset);
361}
362
363static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
364{
365 __raw_writel(val, slave->regs + offset);
366}
367
649a1688 368struct cpsw_common {
56e31bd8 369 struct device *dev;
606f3993 370 struct cpsw_platform_data data;
dbc4ec52
IK		 371 struct napi_struct napi_rx;
372 struct napi_struct napi_tx;
5d8d0d4d
IK		 373 struct cpsw_ss_regs __iomem *regs;
374 struct cpsw_wr_regs __iomem *wr_regs;
375 u8 __iomem *hw_stats;
376 struct cpsw_host_regs __iomem *host_port_regs;
2a05a622
IK		 377 u32 version;
378 u32 coal_intvl;
379 u32 bus_freq_mhz;
380 int rx_packet_max;
606f3993 381 struct cpsw_slave *slaves;
2c836bd9 382 struct cpdma_ctlr *dma;
e05107e6
IK		 383 struct cpdma_chan *txch[CPSW_MAX_QUEUES];
384 struct cpdma_chan *rxch[CPSW_MAX_QUEUES];
2a05a622 385 struct cpsw_ale *ale;
e38b5a3d
IK		 386 bool quirk_irq;
387 bool rx_irq_disabled;
388 bool tx_irq_disabled;
389 u32 irqs_table[IRQ_NUM];
2a05a622 390 struct cpts *cpts;
e05107e6 391 int rx_ch_num, tx_ch_num;
649a1688
IK		 392};
393
394struct cpsw_priv {
df828598 395 struct net_device *ndev;
df828598 396 struct device *dev;
df828598 397 u32 msg_enable;
df828598 398 u8 mac_addr[ETH_ALEN];
1923d6e4
M		 399 bool rx_pause;
400 bool tx_pause;
d9ba8f9e 401 u32 emac_port;
649a1688 402 struct cpsw_common *cpsw;
df828598
M		 403};
404
d9718546
M		 405struct cpsw_stats {
406 char stat_string[ETH_GSTRING_LEN];
407 int type;
408 int sizeof_stat;
409 int stat_offset;
410};
411
412enum {
413 CPSW_STATS,
414 CPDMA_RX_STATS,
415 CPDMA_TX_STATS,
416};
417
418#define CPSW_STAT(m) CPSW_STATS, \
419 sizeof(((struct cpsw_hw_stats *)0)->m), \
420 offsetof(struct cpsw_hw_stats, m)
421#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
422 sizeof(((struct cpdma_chan_stats *)0)->m), \
423 offsetof(struct cpdma_chan_stats, m)
424#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
425 sizeof(((struct cpdma_chan_stats *)0)->m), \
426 offsetof(struct cpdma_chan_stats, m)
427
428static const struct cpsw_stats cpsw_gstrings_stats[] = {
429 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
430 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
431 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
432 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
433 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
434 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
435 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
436 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
437 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
438 { "Rx Fragments", CPSW_STAT(rxfragments) },
439 { "Rx Octets", CPSW_STAT(rxoctets) },
440 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
441 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
442 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
443 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
444 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
445 { "Collisions", CPSW_STAT(txcollisionframes) },
446 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
447 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
448 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
449 { "Late Collisions", CPSW_STAT(txlatecollisions) },
450 { "Tx Underrun", CPSW_STAT(txunderrun) },
451 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
452 { "Tx Octets", CPSW_STAT(txoctets) },
453 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
454 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
455 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
456 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
457 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
458 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
459 { "Net Octets", CPSW_STAT(netoctets) },
460 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
461 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
462 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
d9718546
M		 463};
464
e05107e6
IK		 465static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
466 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
467 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
468 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
469 { "misqueued", CPDMA_RX_STAT(misqueued) },
470 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
471 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
472 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
473 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
474 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
475 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
476 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
477 { "requeue", CPDMA_RX_STAT(requeue) },
478 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
479};
480
481#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
482#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
d9718546 483
649a1688 484#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
dbc4ec52 485#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
d9ba8f9e
M		 486#define for_each_slave(priv, func, arg...) \
487 do { \
6e6ceaed 488 struct cpsw_slave *slave; \
606f3993 489 struct cpsw_common *cpsw = (priv)->cpsw; \
6e6ceaed 490 int n; \
606f3993
IK		 491 if (cpsw->data.dual_emac) \
492 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
d9ba8f9e 493 else \
606f3993
IK		 494 for (n = cpsw->data.slaves, \
495 slave = cpsw->slaves; \
6e6ceaed
SS		 496 n; n--) \
497 (func)(slave++, ##arg); \
d9ba8f9e 498 } while (0)
d9ba8f9e 499
2a05a622 500#define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
d9ba8f9e 501 do { \
606f3993 502 if (!cpsw->data.dual_emac) \
d9ba8f9e
M		 503 break; \
504 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
606f3993 505 ndev = cpsw->slaves[0].ndev; \
d9ba8f9e
M		 506 skb->dev = ndev; \
507 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
606f3993 508 ndev = cpsw->slaves[1].ndev; \
d9ba8f9e
M		 509 skb->dev = ndev; \
510 } \
df828598 511 } while (0)
606f3993 512#define cpsw_add_mcast(cpsw, priv, addr) \
d9ba8f9e 513 do { \
606f3993
IK		 514 if (cpsw->data.dual_emac) { \
515 struct cpsw_slave *slave = cpsw->slaves + \
d9ba8f9e 516 priv->emac_port; \
6f1f5836 517 int slave_port = cpsw_get_slave_port( \
d9ba8f9e 518 slave->slave_num); \
2a05a622 519 cpsw_ale_add_mcast(cpsw->ale, addr, \
71a2cbb7 520 1 << slave_port | ALE_PORT_HOST, \
d9ba8f9e
M		 521 ALE_VLAN, slave->port_vlan, 0); \
522 } else { \
2a05a622 523 cpsw_ale_add_mcast(cpsw->ale, addr, \
61f1cef9 524 ALE_ALL_PORTS, \
d9ba8f9e
M		 525 0, 0, 0); \
526 } \
527 } while (0)
528
6f1f5836 529static inline int cpsw_get_slave_port(u32 slave_num)
d9ba8f9e 530{
71a2cbb7 531 return slave_num + 1;
d9ba8f9e 532}
df828598 533
0cd8f9cc
M		 534static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
535{
2a05a622
IK		 536 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
537 struct cpsw_ale *ale = cpsw->ale;
0cd8f9cc
M		 538 int i;
539
606f3993 540 if (cpsw->data.dual_emac) {
0cd8f9cc
M		 541 bool flag = false;
542
543 /* Enabling promiscuous mode for one interface will be
544 * common for both the interface as the interface shares
545 * the same hardware resource.
546 */
606f3993
IK		 547 for (i = 0; i < cpsw->data.slaves; i++)
548 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
0cd8f9cc
M		 549 flag = true;
550
551 if (!enable && flag) {
552 enable = true;
553 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
554 }
555
556 if (enable) {
557 /* Enable Bypass */
558 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
559
560 dev_dbg(&ndev->dev, "promiscuity enabled\n");
561 } else {
562 /* Disable Bypass */
563 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
564 dev_dbg(&ndev->dev, "promiscuity disabled\n");
565 }
566 } else {
567 if (enable) {
568 unsigned long timeout = jiffies + HZ;
569
6f979eb3 570 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
606f3993 571 for (i = 0; i <= cpsw->data.slaves; i++) {
0cd8f9cc
M		 572 cpsw_ale_control_set(ale, i,
573 ALE_PORT_NOLEARN, 1);
574 cpsw_ale_control_set(ale, i,
575 ALE_PORT_NO_SA_UPDATE, 1);
576 }
577
578 /* Clear All Untouched entries */
579 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
580 do {
581 cpu_relax();
582 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
583 break;
584 } while (time_after(timeout, jiffies));
585 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
586
587 /* Clear all mcast from ALE */
61f1cef9 588 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
0cd8f9cc
M		 589
590 /* Flood All Unicast Packets to Host port */
591 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
592 dev_dbg(&ndev->dev, "promiscuity enabled\n");
593 } else {
6f979eb3 594 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 595 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
596
6f979eb3 597 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
606f3993 598 for (i = 0; i <= cpsw->data.slaves; i++) {
0cd8f9cc
M		 599 cpsw_ale_control_set(ale, i,
600 ALE_PORT_NOLEARN, 0);
601 cpsw_ale_control_set(ale, i,
602 ALE_PORT_NO_SA_UPDATE, 0);
603 }
604 dev_dbg(&ndev->dev, "promiscuity disabled\n");
605 }
606 }
607}
608
5c50a856
M		 609static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
610{
611 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993 612 struct cpsw_common *cpsw = priv->cpsw;
25906052
M		 613 int vid;
614
606f3993
IK		 615 if (cpsw->data.dual_emac)
616 vid = cpsw->slaves[priv->emac_port].port_vlan;
25906052 617 else
606f3993 618 vid = cpsw->data.default_vlan;
5c50a856
M		 619
620 if (ndev->flags & IFF_PROMISC) {
621 /* Enable promiscuous mode */
0cd8f9cc 622 cpsw_set_promiscious(ndev, true);
2a05a622 623 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
5c50a856 624 return;
0cd8f9cc
M		 625 } else {
626 /* Disable promiscuous mode */
627 cpsw_set_promiscious(ndev, false);
5c50a856
M		 628 }
629
1e5c4bc4 630 /* Restore allmulti on vlans if necessary */
2a05a622 631 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
1e5c4bc4 632
5c50a856 633 /* Clear all mcast from ALE */
2a05a622 634 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
5c50a856
M		 635
636 if (!netdev_mc_empty(ndev)) {
637 struct netdev_hw_addr *ha;
638
639 /* program multicast address list into ALE register */
640 netdev_for_each_mc_addr(ha, ndev) {
606f3993 641 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
5c50a856
M		 642 }
643 }
644}
645
2c836bd9 646static void cpsw_intr_enable(struct cpsw_common *cpsw)
df828598 647{
5d8d0d4d
IK		 648 __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
649 __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
df828598 650
2c836bd9 651 cpdma_ctlr_int_ctrl(cpsw->dma, true);
df828598
M		 652 return;
653}
654
2c836bd9 655static void cpsw_intr_disable(struct cpsw_common *cpsw)
df828598 656{
5d8d0d4d
IK		 657 __raw_writel(0, &cpsw->wr_regs->tx_en);
658 __raw_writel(0, &cpsw->wr_regs->rx_en);
df828598 659
2c836bd9 660 cpdma_ctlr_int_ctrl(cpsw->dma, false);
df828598
M		 661 return;
662}
663
1a3b5056 664static void cpsw_tx_handler(void *token, int len, int status)
df828598 665{
e05107e6 666 struct netdev_queue *txq;
df828598
M		 667 struct sk_buff *skb = token;
668 struct net_device *ndev = skb->dev;
2a05a622 669 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 670
fae50823
M		 671 /* Check whether the queue is stopped due to stalled tx dma, if the
672 * queue is stopped then start the queue as we have free desc for tx
673 */
e05107e6
IK		 674 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
675 if (unlikely(netif_tx_queue_stopped(txq)))
676 netif_tx_wake_queue(txq);
677
2a05a622 678 cpts_tx_timestamp(cpsw->cpts, skb);
8dc43ddc
TK		 679 ndev->stats.tx_packets++;
680 ndev->stats.tx_bytes += len;
df828598
M		 681 dev_kfree_skb_any(skb);
682}
683
1a3b5056 684static void cpsw_rx_handler(void *token, int len, int status)
df828598 685{
e05107e6 686 struct cpdma_chan *ch;
df828598 687 struct sk_buff *skb = token;
b4727e69 688 struct sk_buff *new_skb;
df828598 689 struct net_device *ndev = skb->dev;
df828598 690 int ret = 0;
2a05a622 691 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 692
2a05a622 693 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
d9ba8f9e 694
16e5c57d 695 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822 696 bool ndev_status = false;
606f3993 697 struct cpsw_slave *slave = cpsw->slaves;
a0e2c822
M		 698 int n;
699
606f3993 700 if (cpsw->data.dual_emac) {
a0e2c822 701 /* In dual emac mode check for all interfaces */
606f3993 702 for (n = cpsw->data.slaves; n; n--, slave++)
a0e2c822
M		 703 if (netif_running(slave->ndev))
704 ndev_status = true;
705 }
706
707 if (ndev_status && (status >= 0)) {
708 /* The packet received is for the interface which
709 * is already down and the other interface is up
dbedd44e 710 * and running, instead of freeing which results
a0e2c822
M		 711 * in reducing of the number of rx descriptor in
712 * DMA engine, requeue skb back to cpdma.
713 */
714 new_skb = skb;
715 goto requeue;
716 }
717
b4727e69 718 /* the interface is going down, skbs are purged */
df828598
M		 719 dev_kfree_skb_any(skb);
720 return;
721 }
b4727e69 722
2a05a622 723 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
b4727e69 724 if (new_skb) {
e05107e6 725 skb_copy_queue_mapping(new_skb, skb);
df828598 726 skb_put(skb, len);
2a05a622 727 cpts_rx_timestamp(cpsw->cpts, skb);
df828598
M		 728 skb->protocol = eth_type_trans(skb, ndev);
729 netif_receive_skb(skb);
8dc43ddc
TK		 730 ndev->stats.rx_bytes += len;
731 ndev->stats.rx_packets++;
254a49d5 732 kmemleak_not_leak(new_skb);
b4727e69 733 } else {
8dc43ddc 734 ndev->stats.rx_dropped++;
b4727e69 735 new_skb = skb;
df828598
M		 736 }
737
a0e2c822 738requeue:
ce52c744
IK		 739 if (netif_dormant(ndev)) {
740 dev_kfree_skb_any(new_skb);
741 return;
742 }
743
e05107e6
IK		 744 ch = cpsw->rxch[skb_get_queue_mapping(new_skb)];
745 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
2c836bd9 746 skb_tailroom(new_skb), 0);
b4727e69
SS		 747 if (WARN_ON(ret < 0))
748 dev_kfree_skb_any(new_skb);
df828598
M		 749}
750
c03abd84 751static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598 752{
dbc4ec52 753 struct cpsw_common *cpsw = dev_id;
7ce67a38 754
5d8d0d4d 755 writel(0, &cpsw->wr_regs->tx_en);
2c836bd9 756 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
c03abd84 757
e38b5a3d
IK		 758 if (cpsw->quirk_irq) {
759 disable_irq_nosync(cpsw->irqs_table[1]);
760 cpsw->tx_irq_disabled = true;
7da11600
M		 761 }
762
dbc4ec52 763 napi_schedule(&cpsw->napi_tx);
c03abd84
FB		 764 return IRQ_HANDLED;
765}
766
767static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
768{
dbc4ec52 769 struct cpsw_common *cpsw = dev_id;
c03abd84 770
2c836bd9 771 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
5d8d0d4d 772 writel(0, &cpsw->wr_regs->rx_en);
fd51cf19 773
e38b5a3d
IK		 774 if (cpsw->quirk_irq) {
775 disable_irq_nosync(cpsw->irqs_table[0]);
776 cpsw->rx_irq_disabled = true;
7da11600
M		 777 }
778
dbc4ec52 779 napi_schedule(&cpsw->napi_rx);
d354eb85 780 return IRQ_HANDLED;
df828598
M		 781}
782
32a7432c
M		 783static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
784{
e05107e6
IK		 785 u32 ch_map;
786 int num_tx, ch;
dbc4ec52 787 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
32a7432c 788
e05107e6
IK		 789 /* process every unprocessed channel */
790 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
791 for (ch = 0, num_tx = 0; num_tx < budget; ch_map >>= 1, ch++) {
792 if (!ch_map) {
793 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
794 if (!ch_map)
795 break;
796
797 ch = 0;
798 }
799
800 if (!(ch_map & 0x01))
801 continue;
802
803 num_tx += cpdma_chan_process(cpsw->txch[ch], budget - num_tx);
804 }
805
32a7432c
M		 806 if (num_tx < budget) {
807 napi_complete(napi_tx);
5d8d0d4d 808 writel(0xff, &cpsw->wr_regs->tx_en);
e38b5a3d
IK		 809 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
810 cpsw->tx_irq_disabled = false;
811 enable_irq(cpsw->irqs_table[1]);
7da11600 812 }
32a7432c
M		 813 }
814
32a7432c
M		 815 return num_tx;
816}
817
818static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 819{
e05107e6
IK		 820 u32 ch_map;
821 int num_rx, ch;
dbc4ec52 822 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
df828598 823
e05107e6
IK		 824 /* process every unprocessed channel */
825 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
826 for (ch = 0, num_rx = 0; num_rx < budget; ch_map >>= 1, ch++) {
827 if (!ch_map) {
828 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
829 if (!ch_map)
830 break;
831
832 ch = 0;
833 }
834
835 if (!(ch_map & 0x01))
836 continue;
837
838 num_rx += cpdma_chan_process(cpsw->rxch[ch], budget - num_rx);
839 }
840
df828598 841 if (num_rx < budget) {
32a7432c 842 napi_complete(napi_rx);
5d8d0d4d 843 writel(0xff, &cpsw->wr_regs->rx_en);
e38b5a3d
IK		 844 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
845 cpsw->rx_irq_disabled = false;
846 enable_irq(cpsw->irqs_table[0]);
7da11600 847 }
df828598
M		 848 }
849
850 return num_rx;
851}
852
853static inline void soft_reset(const char *module, void __iomem *reg)
854{
855 unsigned long timeout = jiffies + HZ;
856
857 __raw_writel(1, reg);
858 do {
859 cpu_relax();
860 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
861
862 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
863}
864
865#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
866 ((mac)[2] << 16) | ((mac)[3] << 24))
867#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
868
869static void cpsw_set_slave_mac(struct cpsw_slave *slave,
870 struct cpsw_priv *priv)
871{
9750a3ad
RC		 872 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
873 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 874}
875
876static void _cpsw_adjust_link(struct cpsw_slave *slave,
877 struct cpsw_priv *priv, bool *link)
878{
879 struct phy_device *phy = slave->phy;
880 u32 mac_control = 0;
881 u32 slave_port;
606f3993 882 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 883
884 if (!phy)
885 return;
886
6f1f5836 887 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598
M		 888
889 if (phy->link) {
606f3993 890 mac_control = cpsw->data.mac_control;
df828598
M		 891
892 /* enable forwarding */
2a05a622 893 cpsw_ale_control_set(cpsw->ale, slave_port,
df828598
M		 894 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
895
896 if (phy->speed == 1000)
897 mac_control |= BIT(7); /* GIGABITEN */
898 if (phy->duplex)
899 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 900
901 /* set speed_in input in case RMII mode is used in 100Mbps */
902 if (phy->speed == 100)
903 mac_control |= BIT(15);
a81d8762
M		 904 else if (phy->speed == 10)
905 mac_control |= BIT(18); /* In Band mode */
342b7b74 906
1923d6e4
M		 907 if (priv->rx_pause)
908 mac_control |= BIT(3);
909
910 if (priv->tx_pause)
911 mac_control |= BIT(4);
912
df828598
M		 913 *link = true;
914 } else {
915 mac_control = 0;
916 /* disable forwarding */
2a05a622 917 cpsw_ale_control_set(cpsw->ale, slave_port,
df828598
M		 918 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
919 }
920
921 if (mac_control != slave->mac_control) {
922 phy_print_status(phy);
923 __raw_writel(mac_control, &slave->sliver->mac_control);
924 }
925
926 slave->mac_control = mac_control;
927}
928
929static void cpsw_adjust_link(struct net_device *ndev)
930{
931 struct cpsw_priv *priv = netdev_priv(ndev);
932 bool link = false;
933
934 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
935
936 if (link) {
937 netif_carrier_on(ndev);
938 if (netif_running(ndev))
e05107e6 939 netif_tx_wake_all_queues(ndev);
df828598
M		 940 } else {
941 netif_carrier_off(ndev);
e05107e6 942 netif_tx_stop_all_queues(ndev);
df828598
M		 943 }
944}
945
ff5b8ef2
M		 946static int cpsw_get_coalesce(struct net_device *ndev,
947 struct ethtool_coalesce *coal)
948{
2a05a622 949 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
ff5b8ef2 950
2a05a622 951 coal->rx_coalesce_usecs = cpsw->coal_intvl;
ff5b8ef2
M		 952 return 0;
953}
954
955static int cpsw_set_coalesce(struct net_device *ndev,
956 struct ethtool_coalesce *coal)
957{
958 struct cpsw_priv *priv = netdev_priv(ndev);
959 u32 int_ctrl;
960 u32 num_interrupts = 0;
961 u32 prescale = 0;
962 u32 addnl_dvdr = 1;
963 u32 coal_intvl = 0;
5d8d0d4d 964 struct cpsw_common *cpsw = priv->cpsw;
ff5b8ef2 965
ff5b8ef2
M		 966 coal_intvl = coal->rx_coalesce_usecs;
967
5d8d0d4d 968 int_ctrl = readl(&cpsw->wr_regs->int_control);
2a05a622 969 prescale = cpsw->bus_freq_mhz * 4;
ff5b8ef2 970
a84bc2a9
M		 971 if (!coal->rx_coalesce_usecs) {
972 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
973 goto update_return;
974 }
975
ff5b8ef2
M		 976 if (coal_intvl < CPSW_CMINTMIN_INTVL)
977 coal_intvl = CPSW_CMINTMIN_INTVL;
978
979 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
980 /* Interrupt pacer works with 4us Pulse, we can
981 * throttle further by dilating the 4us pulse.
982 */
983 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
984
985 if (addnl_dvdr > 1) {
986 prescale *= addnl_dvdr;
987 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
988 coal_intvl = (CPSW_CMINTMAX_INTVL
989 * addnl_dvdr);
990 } else {
991 addnl_dvdr = 1;
992 coal_intvl = CPSW_CMINTMAX_INTVL;
993 }
994 }
995
996 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
5d8d0d4d
IK		 997 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
998 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
ff5b8ef2
M		 999
1000 int_ctrl |= CPSW_INTPACEEN;
1001 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1002 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 1003
1004update_return:
5d8d0d4d 1005 writel(int_ctrl, &cpsw->wr_regs->int_control);
ff5b8ef2
M		 1006
1007 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
2a05a622 1008 cpsw->coal_intvl = coal_intvl;
ff5b8ef2
M		 1009
1010 return 0;
1011}
1012
d9718546
M		 1013static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1014{
e05107e6
IK		 1015 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1016
d9718546
M		 1017 switch (sset) {
1018 case ETH_SS_STATS:
e05107e6
IK		 1019 return (CPSW_STATS_COMMON_LEN +
1020 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1021 CPSW_STATS_CH_LEN);
d9718546
M		 1022 default:
1023 return -EOPNOTSUPP;
1024 }
1025}
1026
e05107e6
IK		 1027static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1028{
1029 int ch_stats_len;
1030 int line;
1031 int i;
1032
1033 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1034 for (i = 0; i < ch_stats_len; i++) {
1035 line = i % CPSW_STATS_CH_LEN;
1036 snprintf(*p, ETH_GSTRING_LEN,
1037 "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1038 i / CPSW_STATS_CH_LEN,
1039 cpsw_gstrings_ch_stats[line].stat_string);
1040 *p += ETH_GSTRING_LEN;
1041 }
1042}
1043
d9718546
M		 1044static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1045{
e05107e6 1046 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
d9718546
M		 1047 u8 *p = data;
1048 int i;
1049
1050 switch (stringset) {
1051 case ETH_SS_STATS:
e05107e6 1052 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
d9718546
M		 1053 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1054 ETH_GSTRING_LEN);
1055 p += ETH_GSTRING_LEN;
1056 }
e05107e6
IK		 1057
1058 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1059 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
d9718546
M		 1060 break;
1061 }
1062}
1063
1064static void cpsw_get_ethtool_stats(struct net_device *ndev,
1065 struct ethtool_stats *stats, u64 *data)
1066{
d9718546 1067 u8 *p;
2c836bd9 1068 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
e05107e6
IK		 1069 struct cpdma_chan_stats ch_stats;
1070 int i, l, ch;
d9718546
M		 1071
1072 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
e05107e6
IK		 1073 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1074 data[l] = readl(cpsw->hw_stats +
1075 cpsw_gstrings_stats[l].stat_offset);
1076
1077 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1078 cpdma_chan_get_stats(cpsw->rxch[ch], &ch_stats);
1079 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1080 p = (u8 *)&ch_stats +
1081 cpsw_gstrings_ch_stats[i].stat_offset;
1082 data[l] = *(u32 *)p;
1083 }
1084 }
d9718546 1085
e05107e6
IK		 1086 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1087 cpdma_chan_get_stats(cpsw->txch[ch], &ch_stats);
1088 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1089 p = (u8 *)&ch_stats +
1090 cpsw_gstrings_ch_stats[i].stat_offset;
1091 data[l] = *(u32 *)p;
d9718546
M		 1092 }
1093 }
1094}
1095
606f3993 1096static int cpsw_common_res_usage_state(struct cpsw_common *cpsw)
d9ba8f9e
M		 1097{
1098 u32 i;
1099 u32 usage_count = 0;
1100
606f3993 1101 if (!cpsw->data.dual_emac)
d9ba8f9e
M		 1102 return 0;
1103
606f3993
IK		 1104 for (i = 0; i < cpsw->data.slaves; i++)
1105 if (cpsw->slaves[i].open_stat)
d9ba8f9e
M		 1106 usage_count++;
1107
1108 return usage_count;
1109}
1110
27e9e103 1111static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
e05107e6
IK		 1112 struct sk_buff *skb,
1113 struct cpdma_chan *txch)
d9ba8f9e 1114{
2c836bd9
IK		 1115 struct cpsw_common *cpsw = priv->cpsw;
1116
e05107e6 1117 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
606f3993 1118 priv->emac_port + cpsw->data.dual_emac);
d9ba8f9e
M		 1119}
1120
1121static inline void cpsw_add_dual_emac_def_ale_entries(
1122 struct cpsw_priv *priv, struct cpsw_slave *slave,
1123 u32 slave_port)
1124{
2a05a622 1125 struct cpsw_common *cpsw = priv->cpsw;
71a2cbb7 1126 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
d9ba8f9e 1127
2a05a622 1128 if (cpsw->version == CPSW_VERSION_1)
d9ba8f9e
M		 1129 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1130 else
1131 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
2a05a622 1132 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
d9ba8f9e 1133 port_mask, port_mask, 0);
2a05a622 1134 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
d9ba8f9e 1135 port_mask, ALE_VLAN, slave->port_vlan, 0);
2a05a622
IK		 1136 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1137 HOST_PORT_NUM, ALE_VLAN |
1138 ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1139}
1140
1e7a2e21 1141static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1142{
1143 char name[32];
df828598 1144
1e7a2e21 1145 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1146 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1147}
1148
1149static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1150{
1151 u32 slave_port;
649a1688 1152 struct cpsw_common *cpsw = priv->cpsw;
1e7a2e21
DM		 1153
1154 soft_reset_slave(slave);
df828598
M		 1155
1156 /* setup priority mapping */
1157 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad 1158
2a05a622 1159 switch (cpsw->version) {
9750a3ad
RC		 1160 case CPSW_VERSION_1:
1161 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1162 break;
1163 case CPSW_VERSION_2:
c193f365 1164 case CPSW_VERSION_3:
926489be 1165 case CPSW_VERSION_4:
9750a3ad
RC		 1166 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1167 break;
1168 }
df828598
M		 1169
1170 /* setup max packet size, and mac address */
2a05a622 1171 __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
df828598
M		 1172 cpsw_set_slave_mac(slave, priv);
1173
1174 slave->mac_control = 0; /* no link yet */
1175
6f1f5836 1176 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598 1177
606f3993 1178 if (cpsw->data.dual_emac)
d9ba8f9e
M		 1179 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1180 else
2a05a622 1181 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
d9ba8f9e 1182 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1183
d733f754 1184 if (slave->data->phy_node) {
552165bc 1185 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
9e42f715 1186 &cpsw_adjust_link, 0, slave->data->phy_if);
d733f754
DR		 1187 if (!slave->phy) {
1188 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1189 slave->data->phy_node->full_name,
1190 slave->slave_num);
1191 return;
1192 }
1193 } else {
9e42f715 1194 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1195 &cpsw_adjust_link, slave->data->phy_if);
d733f754
DR		 1196 if (IS_ERR(slave->phy)) {
1197 dev_err(priv->dev,
1198 "phy \"%s\" not found on slave %d, err %ld\n",
1199 slave->data->phy_id, slave->slave_num,
1200 PTR_ERR(slave->phy));
1201 slave->phy = NULL;
1202 return;
1203 }
1204 }
2220943a 1205
d733f754 1206 phy_attached_info(slave->phy);
388367a5 1207
d733f754
DR		 1208 phy_start(slave->phy);
1209
1210 /* Configure GMII_SEL register */
56e31bd8 1211 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
df828598
M		 1212}
1213
3b72c2fe
M		 1214static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1215{
606f3993
IK		 1216 struct cpsw_common *cpsw = priv->cpsw;
1217 const int vlan = cpsw->data.default_vlan;
3b72c2fe
M		 1218 u32 reg;
1219 int i;
1e5c4bc4 1220 int unreg_mcast_mask;
3b72c2fe 1221
2a05a622 1222 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
3b72c2fe
M		 1223 CPSW2_PORT_VLAN;
1224
5d8d0d4d 1225 writel(vlan, &cpsw->host_port_regs->port_vlan);
3b72c2fe 1226
606f3993
IK		 1227 for (i = 0; i < cpsw->data.slaves; i++)
1228 slave_write(cpsw->slaves + i, vlan, reg);
3b72c2fe 1229
1e5c4bc4
LS		 1230 if (priv->ndev->flags & IFF_ALLMULTI)
1231 unreg_mcast_mask = ALE_ALL_PORTS;
1232 else
1233 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1234
2a05a622 1235 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
61f1cef9
GS		 1236 ALE_ALL_PORTS, ALE_ALL_PORTS,
1237 unreg_mcast_mask);
3b72c2fe
M		 1238}
1239
df828598
M		 1240static void cpsw_init_host_port(struct cpsw_priv *priv)
1241{
d9ba8f9e 1242 u32 fifo_mode;
5d8d0d4d
IK		 1243 u32 control_reg;
1244 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe 1245
df828598 1246 /* soft reset the controller and initialize ale */
5d8d0d4d 1247 soft_reset("cpsw", &cpsw->regs->soft_reset);
2a05a622 1248 cpsw_ale_start(cpsw->ale);
df828598
M		 1249
1250 /* switch to vlan unaware mode */
2a05a622 1251 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
3b72c2fe 1252 CPSW_ALE_VLAN_AWARE);
5d8d0d4d 1253 control_reg = readl(&cpsw->regs->control);
3b72c2fe 1254 control_reg |= CPSW_VLAN_AWARE;
5d8d0d4d 1255 writel(control_reg, &cpsw->regs->control);
606f3993 1256 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
d9ba8f9e 1257 CPSW_FIFO_NORMAL_MODE;
5d8d0d4d 1258 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
df828598
M		 1259
1260 /* setup host port priority mapping */
1261 __raw_writel(CPDMA_TX_PRIORITY_MAP,
5d8d0d4d
IK		 1262 &cpsw->host_port_regs->cpdma_tx_pri_map);
1263 __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
df828598 1264
2a05a622 1265 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
df828598
M		 1266 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1267
606f3993 1268 if (!cpsw->data.dual_emac) {
2a05a622 1269 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
d9ba8f9e 1270 0, 0);
2a05a622 1271 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
71a2cbb7 1272 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
d9ba8f9e 1273 }
df828598
M		 1274}
1275
3802dce1
IK		 1276static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1277{
1278 struct cpsw_common *cpsw = priv->cpsw;
1279 struct sk_buff *skb;
1280 int ch_buf_num;
e05107e6
IK		 1281 int ch, i, ret;
1282
1283 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1284 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxch[ch]);
1285 for (i = 0; i < ch_buf_num; i++) {
1286 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1287 cpsw->rx_packet_max,
1288 GFP_KERNEL);
1289 if (!skb) {
1290 cpsw_err(priv, ifup, "cannot allocate skb\n");
1291 return -ENOMEM;
1292 }
3802dce1 1293
e05107e6
IK		 1294 skb_set_queue_mapping(skb, ch);
1295 ret = cpdma_chan_submit(cpsw->rxch[ch], skb, skb->data,
1296 skb_tailroom(skb), 0);
1297 if (ret < 0) {
1298 cpsw_err(priv, ifup,
1299 "cannot submit skb to channel %d rx, error %d\n",
1300 ch, ret);
1301 kfree_skb(skb);
1302 return ret;
1303 }
1304 kmemleak_not_leak(skb);
3802dce1 1305 }
3802dce1 1306
e05107e6
IK		 1307 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1308 ch, ch_buf_num);
1309 }
3802dce1 1310
e05107e6 1311 return 0;
3802dce1
IK		 1312}
1313
2a05a622 1314static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
aacebbf8 1315{
3995d265
SP		 1316 u32 slave_port;
1317
6f1f5836 1318 slave_port = cpsw_get_slave_port(slave->slave_num);
3995d265 1319
aacebbf8
SS		 1320 if (!slave->phy)
1321 return;
1322 phy_stop(slave->phy);
1323 phy_disconnect(slave->phy);
1324 slave->phy = NULL;
2a05a622 1325 cpsw_ale_control_set(cpsw->ale, slave_port,
3995d265 1326 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1f95ba00 1327 soft_reset_slave(slave);
aacebbf8
SS		 1328}
1329
df828598
M		 1330static int cpsw_ndo_open(struct net_device *ndev)
1331{
1332 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1333 struct cpsw_common *cpsw = priv->cpsw;
3802dce1 1334 int ret;
df828598
M		 1335 u32 reg;
1336
56e31bd8 1337 ret = pm_runtime_get_sync(cpsw->dev);
108a6537 1338 if (ret < 0) {
56e31bd8 1339 pm_runtime_put_noidle(cpsw->dev);
108a6537
GS		 1340 return ret;
1341 }
3fa88c51 1342
606f3993 1343 if (!cpsw_common_res_usage_state(cpsw))
2c836bd9 1344 cpsw_intr_disable(cpsw);
df828598
M		 1345 netif_carrier_off(ndev);
1346
e05107e6
IK		 1347 /* Notify the stack of the actual queue counts. */
1348 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1349 if (ret) {
1350 dev_err(priv->dev, "cannot set real number of tx queues\n");
1351 goto err_cleanup;
1352 }
1353
1354 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1355 if (ret) {
1356 dev_err(priv->dev, "cannot set real number of rx queues\n");
1357 goto err_cleanup;
1358 }
1359
2a05a622 1360 reg = cpsw->version;
df828598
M		 1361
1362 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1363 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1364 CPSW_RTL_VERSION(reg));
1365
1366 /* initialize host and slave ports */
606f3993 1367 if (!cpsw_common_res_usage_state(cpsw))
d9ba8f9e 1368 cpsw_init_host_port(priv);
df828598
M		 1369 for_each_slave(priv, cpsw_slave_open, priv);
1370
3b72c2fe 1371 /* Add default VLAN */
606f3993 1372 if (!cpsw->data.dual_emac)
e6afea0b
M		 1373 cpsw_add_default_vlan(priv);
1374 else
2a05a622 1375 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
61f1cef9 1376 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
3b72c2fe 1377
606f3993 1378 if (!cpsw_common_res_usage_state(cpsw)) {
d9ba8f9e 1379 /* setup tx dma to fixed prio and zero offset */
2c836bd9
IK		 1380 cpdma_control_set(cpsw->dma, CPDMA_TX_PRIO_FIXED, 1);
1381 cpdma_control_set(cpsw->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1382
d9ba8f9e 1383 /* disable priority elevation */
5d8d0d4d 1384 __raw_writel(0, &cpsw->regs->ptype);
df828598 1385
d9ba8f9e 1386 /* enable statistics collection only on all ports */
5d8d0d4d 1387 __raw_writel(0x7, &cpsw->regs->stat_port_en);
df828598 1388
1923d6e4 1389 /* Enable internal fifo flow control */
5d8d0d4d 1390 writel(0x7, &cpsw->regs->flow_control);
1923d6e4 1391
dbc4ec52
IK		 1392 napi_enable(&cpsw->napi_rx);
1393 napi_enable(&cpsw->napi_tx);
d354eb85 1394
e38b5a3d
IK		 1395 if (cpsw->tx_irq_disabled) {
1396 cpsw->tx_irq_disabled = false;
1397 enable_irq(cpsw->irqs_table[1]);
7da11600
M		 1398 }
1399
e38b5a3d
IK		 1400 if (cpsw->rx_irq_disabled) {
1401 cpsw->rx_irq_disabled = false;
1402 enable_irq(cpsw->irqs_table[0]);
7da11600
M		 1403 }
1404
3802dce1
IK		 1405 ret = cpsw_fill_rx_channels(priv);
1406 if (ret < 0)
1407 goto err_cleanup;
f280e89a 1408
2a05a622 1409 if (cpts_register(cpsw->dev, cpsw->cpts,
606f3993
IK		 1410 cpsw->data.cpts_clock_mult,
1411 cpsw->data.cpts_clock_shift))
f280e89a
M		 1412 dev_err(priv->dev, "error registering cpts device\n");
1413
df828598 1414 }
df828598 1415
ff5b8ef2 1416 /* Enable Interrupt pacing if configured */
2a05a622 1417 if (cpsw->coal_intvl != 0) {
ff5b8ef2
M		 1418 struct ethtool_coalesce coal;
1419
2a05a622 1420 coal.rx_coalesce_usecs = cpsw->coal_intvl;
ff5b8ef2
M		 1421 cpsw_set_coalesce(ndev, &coal);
1422 }
1423
2c836bd9
IK		 1424 cpdma_ctlr_start(cpsw->dma);
1425 cpsw_intr_enable(cpsw);
f63a975e 1426
606f3993
IK		 1427 if (cpsw->data.dual_emac)
1428 cpsw->slaves[priv->emac_port].open_stat = true;
e05107e6
IK		 1429
1430 netif_tx_start_all_queues(ndev);
1431
df828598 1432 return 0;
df828598 1433
aacebbf8 1434err_cleanup:
2c836bd9 1435 cpdma_ctlr_stop(cpsw->dma);
2a05a622 1436 for_each_slave(priv, cpsw_slave_stop, cpsw);
56e31bd8 1437 pm_runtime_put_sync(cpsw->dev);
aacebbf8
SS		 1438 netif_carrier_off(priv->ndev);
1439 return ret;
df828598
M		 1440}
1441
1442static int cpsw_ndo_stop(struct net_device *ndev)
1443{
1444 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1445 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1446
1447 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
e05107e6 1448 netif_tx_stop_all_queues(priv->ndev);
df828598 1449 netif_carrier_off(priv->ndev);
d9ba8f9e 1450
606f3993 1451 if (cpsw_common_res_usage_state(cpsw) <= 1) {
dbc4ec52
IK		 1452 napi_disable(&cpsw->napi_rx);
1453 napi_disable(&cpsw->napi_tx);
2a05a622 1454 cpts_unregister(cpsw->cpts);
2c836bd9
IK		 1455 cpsw_intr_disable(cpsw);
1456 cpdma_ctlr_stop(cpsw->dma);
2a05a622 1457 cpsw_ale_stop(cpsw->ale);
d9ba8f9e 1458 }
2a05a622 1459 for_each_slave(priv, cpsw_slave_stop, cpsw);
56e31bd8 1460 pm_runtime_put_sync(cpsw->dev);
606f3993
IK		 1461 if (cpsw->data.dual_emac)
1462 cpsw->slaves[priv->emac_port].open_stat = false;
df828598
M		 1463 return 0;
1464}
1465
1466static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1467 struct net_device *ndev)
1468{
1469 struct cpsw_priv *priv = netdev_priv(ndev);
2c836bd9 1470 struct cpsw_common *cpsw = priv->cpsw;
e05107e6
IK		 1471 struct netdev_queue *txq;
1472 struct cpdma_chan *txch;
1473 int ret, q_idx;
df828598 1474
860e9538 1475 netif_trans_update(ndev);
df828598
M		 1476
1477 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1478 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1479 ndev->stats.tx_dropped++;
df828598
M		 1480 return NETDEV_TX_OK;
1481 }
1482
9232b16d 1483 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2a05a622 1484 cpsw->cpts->tx_enable)
2e5b38ab
RC		 1485 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1486
1487 skb_tx_timestamp(skb);
1488
e05107e6
IK		 1489 q_idx = skb_get_queue_mapping(skb);
1490 if (q_idx >= cpsw->tx_ch_num)
1491 q_idx = q_idx % cpsw->tx_ch_num;
1492
1493 txch = cpsw->txch[q_idx];
1494 ret = cpsw_tx_packet_submit(priv, skb, txch);
df828598
M		 1495 if (unlikely(ret != 0)) {
1496 cpsw_err(priv, tx_err, "desc submit failed\n");
1497 goto fail;
1498 }
1499
fae50823
M		 1500 /* If there is no more tx desc left free then we need to
1501 * tell the kernel to stop sending us tx frames.
1502 */
e05107e6
IK		 1503 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1504 txq = netdev_get_tx_queue(ndev, q_idx);
1505 netif_tx_stop_queue(txq);
1506 }
fae50823 1507
df828598
M		 1508 return NETDEV_TX_OK;
1509fail:
8dc43ddc 1510 ndev->stats.tx_dropped++;
e05107e6
IK		 1511 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1512 netif_tx_stop_queue(txq);
df828598
M		 1513 return NETDEV_TX_BUSY;
1514}
1515
2e5b38ab
RC		 1516#ifdef CONFIG_TI_CPTS
1517
2a05a622 1518static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
2e5b38ab 1519{
606f3993 1520 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2e5b38ab
RC		 1521 u32 ts_en, seq_id;
1522
2a05a622 1523 if (!cpsw->cpts->tx_enable && !cpsw->cpts->rx_enable) {
2e5b38ab
RC		 1524 slave_write(slave, 0, CPSW1_TS_CTL);
1525 return;
1526 }
1527
1528 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1529 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1530
2a05a622 1531 if (cpsw->cpts->tx_enable)
2e5b38ab
RC		 1532 ts_en |= CPSW_V1_TS_TX_EN;
1533
2a05a622 1534 if (cpsw->cpts->rx_enable)
2e5b38ab
RC		 1535 ts_en |= CPSW_V1_TS_RX_EN;
1536
1537 slave_write(slave, ts_en, CPSW1_TS_CTL);
1538 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1539}
1540
1541static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1542{
d9ba8f9e 1543 struct cpsw_slave *slave;
5d8d0d4d 1544 struct cpsw_common *cpsw = priv->cpsw;
2e5b38ab
RC		 1545 u32 ctrl, mtype;
1546
606f3993
IK		 1547 if (cpsw->data.dual_emac)
1548 slave = &cpsw->slaves[priv->emac_port];
d9ba8f9e 1549 else
606f3993 1550 slave = &cpsw->slaves[cpsw->data.active_slave];
d9ba8f9e 1551
2e5b38ab 1552 ctrl = slave_read(slave, CPSW2_CONTROL);
2a05a622 1553 switch (cpsw->version) {
09c55372
GC		 1554 case CPSW_VERSION_2:
1555 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1556
2a05a622 1557 if (cpsw->cpts->tx_enable)
09c55372 1558 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1559
2a05a622 1560 if (cpsw->cpts->rx_enable)
09c55372 1561 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1562 break;
09c55372
GC		 1563 case CPSW_VERSION_3:
1564 default:
1565 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1566
2a05a622 1567 if (cpsw->cpts->tx_enable)
09c55372
GC		 1568 ctrl |= CTRL_V3_TX_TS_BITS;
1569
2a05a622 1570 if (cpsw->cpts->rx_enable)
09c55372 1571 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1572 break;
09c55372 1573 }
2e5b38ab
RC		 1574
1575 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1576
1577 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1578 slave_write(slave, ctrl, CPSW2_CONTROL);
5d8d0d4d 1579 __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
2e5b38ab
RC		 1580}
1581
a5b4145b 1582static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1583{
3177bf6f 1584 struct cpsw_priv *priv = netdev_priv(dev);
2e5b38ab 1585 struct hwtstamp_config cfg;
2a05a622
IK		 1586 struct cpsw_common *cpsw = priv->cpsw;
1587 struct cpts *cpts = cpsw->cpts;
2e5b38ab 1588
2a05a622
IK		 1589 if (cpsw->version != CPSW_VERSION_1 &&
1590 cpsw->version != CPSW_VERSION_2 &&
1591 cpsw->version != CPSW_VERSION_3)
2ee91e54
BH		 1592 return -EOPNOTSUPP;
1593
2e5b38ab
RC		 1594 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1595 return -EFAULT;
1596
1597 /* reserved for future extensions */
1598 if (cfg.flags)
1599 return -EINVAL;
1600
2ee91e54 1601 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1602 return -ERANGE;
2e5b38ab
RC		 1603
1604 switch (cfg.rx_filter) {
1605 case HWTSTAMP_FILTER_NONE:
1606 cpts->rx_enable = 0;
1607 break;
1608 case HWTSTAMP_FILTER_ALL:
1609 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1610 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1611 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1612 return -ERANGE;
1613 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1614 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1616 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1617 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1618 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1619 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1620 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1621 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1622 cpts->rx_enable = 1;
1623 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1624 break;
1625 default:
1626 return -ERANGE;
1627 }
1628
2ee91e54
BH		 1629 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1630
2a05a622 1631 switch (cpsw->version) {
2e5b38ab 1632 case CPSW_VERSION_1:
2a05a622 1633 cpsw_hwtstamp_v1(cpsw);
2e5b38ab
RC		 1634 break;
1635 case CPSW_VERSION_2:
f7d403cb 1636 case CPSW_VERSION_3:
2e5b38ab
RC		 1637 cpsw_hwtstamp_v2(priv);
1638 break;
1639 default:
2ee91e54 1640 WARN_ON(1);
2e5b38ab
RC		 1641 }
1642
1643 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1644}
1645
a5b4145b
BH		 1646static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1647{
2a05a622
IK		 1648 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1649 struct cpts *cpts = cpsw->cpts;
a5b4145b
BH		 1650 struct hwtstamp_config cfg;
1651
2a05a622
IK		 1652 if (cpsw->version != CPSW_VERSION_1 &&
1653 cpsw->version != CPSW_VERSION_2 &&
1654 cpsw->version != CPSW_VERSION_3)
a5b4145b
BH		 1655 return -EOPNOTSUPP;
1656
1657 cfg.flags = 0;
1658 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1659 cfg.rx_filter = (cpts->rx_enable ?
1660 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1661
1662 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1663}
1664
2e5b38ab
RC		 1665#endif /*CONFIG_TI_CPTS*/
1666
1667static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1668{
11f2c988 1669 struct cpsw_priv *priv = netdev_priv(dev);
606f3993
IK		 1670 struct cpsw_common *cpsw = priv->cpsw;
1671 int slave_no = cpsw_slave_index(cpsw, priv);
11f2c988 1672
2e5b38ab
RC		 1673 if (!netif_running(dev))
1674 return -EINVAL;
1675
11f2c988 1676 switch (cmd) {
2e5b38ab 1677#ifdef CONFIG_TI_CPTS
11f2c988 1678 case SIOCSHWTSTAMP:
a5b4145b
BH		 1679 return cpsw_hwtstamp_set(dev, req);
1680 case SIOCGHWTSTAMP:
1681 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1682#endif
11f2c988
M		 1683 }
1684
606f3993 1685 if (!cpsw->slaves[slave_no].phy)
c1b59947 1686 return -EOPNOTSUPP;
606f3993 1687 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1688}
1689
df828598
M		 1690static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1691{
1692 struct cpsw_priv *priv = netdev_priv(ndev);
2c836bd9 1693 struct cpsw_common *cpsw = priv->cpsw;
e05107e6 1694 int ch;
df828598
M		 1695
1696 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1697 ndev->stats.tx_errors++;
2c836bd9 1698 cpsw_intr_disable(cpsw);
e05107e6
IK		 1699 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1700 cpdma_chan_stop(cpsw->txch[ch]);
1701 cpdma_chan_start(cpsw->txch[ch]);
1702 }
1703
2c836bd9 1704 cpsw_intr_enable(cpsw);
df828598
M		 1705}
1706
dcfd8d58
M		 1707static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1708{
1709 struct cpsw_priv *priv = netdev_priv(ndev);
1710 struct sockaddr *addr = (struct sockaddr *)p;
649a1688 1711 struct cpsw_common *cpsw = priv->cpsw;
dcfd8d58
M		 1712 int flags = 0;
1713 u16 vid = 0;
a6c5d14f 1714 int ret;
dcfd8d58
M		 1715
1716 if (!is_valid_ether_addr(addr->sa_data))
1717 return -EADDRNOTAVAIL;
1718
56e31bd8 1719 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1720 if (ret < 0) {
56e31bd8 1721 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1722 return ret;
1723 }
1724
606f3993
IK		 1725 if (cpsw->data.dual_emac) {
1726 vid = cpsw->slaves[priv->emac_port].port_vlan;
dcfd8d58
M		 1727 flags = ALE_VLAN;
1728 }
1729
2a05a622 1730 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
dcfd8d58 1731 flags, vid);
2a05a622 1732 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
dcfd8d58
M		 1733 flags, vid);
1734
1735 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1736 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1737 for_each_slave(priv, cpsw_set_slave_mac, priv);
1738
56e31bd8 1739 pm_runtime_put(cpsw->dev);
a6c5d14f 1740
dcfd8d58
M		 1741 return 0;
1742}
1743
df828598
M		 1744#ifdef CONFIG_NET_POLL_CONTROLLER
1745static void cpsw_ndo_poll_controller(struct net_device *ndev)
1746{
dbc4ec52 1747 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 1748
dbc4ec52
IK		 1749 cpsw_intr_disable(cpsw);
1750 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1751 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1752 cpsw_intr_enable(cpsw);
df828598
M		 1753}
1754#endif
1755
3b72c2fe
M		 1756static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1757 unsigned short vid)
1758{
1759 int ret;
9f6bd8fa
M		 1760 int unreg_mcast_mask = 0;
1761 u32 port_mask;
606f3993 1762 struct cpsw_common *cpsw = priv->cpsw;
1e5c4bc4 1763
606f3993 1764 if (cpsw->data.dual_emac) {
9f6bd8fa 1765 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1766
9f6bd8fa
M		 1767 if (priv->ndev->flags & IFF_ALLMULTI)
1768 unreg_mcast_mask = port_mask;
1769 } else {
1770 port_mask = ALE_ALL_PORTS;
1771
1772 if (priv->ndev->flags & IFF_ALLMULTI)
1773 unreg_mcast_mask = ALE_ALL_PORTS;
1774 else
1775 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1776 }
3b72c2fe 1777
2a05a622 1778 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
61f1cef9 1779 unreg_mcast_mask);
3b72c2fe
M		 1780 if (ret != 0)
1781 return ret;
1782
2a05a622 1783 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
71a2cbb7 1784 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1785 if (ret != 0)
1786 goto clean_vid;
1787
2a05a622 1788 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
9f6bd8fa 1789 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1790 if (ret != 0)
1791 goto clean_vlan_ucast;
1792 return 0;
1793
1794clean_vlan_ucast:
2a05a622 1795 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
71a2cbb7 1796 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe 1797clean_vid:
2a05a622 1798 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
3b72c2fe
M		 1799 return ret;
1800}
1801
1802static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1803 __be16 proto, u16 vid)
3b72c2fe
M		 1804{
1805 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1806 struct cpsw_common *cpsw = priv->cpsw;
a6c5d14f 1807 int ret;
3b72c2fe 1808
606f3993 1809 if (vid == cpsw->data.default_vlan)
3b72c2fe
M		 1810 return 0;
1811
56e31bd8 1812 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1813 if (ret < 0) {
56e31bd8 1814 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1815 return ret;
1816 }
1817
606f3993 1818 if (cpsw->data.dual_emac) {
02a54164
M		 1819 /* In dual EMAC, reserved VLAN id should not be used for
1820 * creating VLAN interfaces as this can break the dual
1821 * EMAC port separation
1822 */
1823 int i;
1824
606f3993
IK		 1825 for (i = 0; i < cpsw->data.slaves; i++) {
1826 if (vid == cpsw->slaves[i].port_vlan)
02a54164
M		 1827 return -EINVAL;
1828 }
1829 }
1830
3b72c2fe 1831 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
a6c5d14f
GS		 1832 ret = cpsw_add_vlan_ale_entry(priv, vid);
1833
56e31bd8 1834 pm_runtime_put(cpsw->dev);
a6c5d14f 1835 return ret;
3b72c2fe
M		 1836}
1837
1838static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1839 __be16 proto, u16 vid)
3b72c2fe
M		 1840{
1841 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1842 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe
M		 1843 int ret;
1844
606f3993 1845 if (vid == cpsw->data.default_vlan)
3b72c2fe
M		 1846 return 0;
1847
56e31bd8 1848 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1849 if (ret < 0) {
56e31bd8 1850 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1851 return ret;
1852 }
1853
606f3993 1854 if (cpsw->data.dual_emac) {
02a54164
M		 1855 int i;
1856
606f3993
IK		 1857 for (i = 0; i < cpsw->data.slaves; i++) {
1858 if (vid == cpsw->slaves[i].port_vlan)
02a54164
M		 1859 return -EINVAL;
1860 }
1861 }
1862
3b72c2fe 1863 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2a05a622 1864 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
3b72c2fe
M		 1865 if (ret != 0)
1866 return ret;
1867
2a05a622 1868 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
61f1cef9 1869 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1870 if (ret != 0)
1871 return ret;
1872
2a05a622 1873 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
a6c5d14f 1874 0, ALE_VLAN, vid);
56e31bd8 1875 pm_runtime_put(cpsw->dev);
a6c5d14f 1876 return ret;
3b72c2fe
M		 1877}
1878
df828598
M		 1879static const struct net_device_ops cpsw_netdev_ops = {
1880 .ndo_open = cpsw_ndo_open,
1881 .ndo_stop = cpsw_ndo_stop,
1882 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1883 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1884 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1885 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1886 .ndo_change_mtu = eth_change_mtu,
df828598 1887 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1888 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1889#ifdef CONFIG_NET_POLL_CONTROLLER
1890 .ndo_poll_controller = cpsw_ndo_poll_controller,
1891#endif
3b72c2fe
M		 1892 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1893 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1894};
1895
52c4f0ec
M		 1896static int cpsw_get_regs_len(struct net_device *ndev)
1897{
606f3993 1898 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
52c4f0ec 1899
606f3993 1900 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
52c4f0ec
M		 1901}
1902
1903static void cpsw_get_regs(struct net_device *ndev,
1904 struct ethtool_regs *regs, void *p)
1905{
52c4f0ec 1906 u32 *reg = p;
2a05a622 1907 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
52c4f0ec
M		 1908
1909 /* update CPSW IP version */
2a05a622 1910 regs->version = cpsw->version;
52c4f0ec 1911
2a05a622 1912 cpsw_ale_dump(cpsw->ale, reg);
52c4f0ec
M		 1913}
1914
df828598
M		 1915static void cpsw_get_drvinfo(struct net_device *ndev,
1916 struct ethtool_drvinfo *info)
1917{
649a1688 1918 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
56e31bd8 1919 struct platform_device *pdev = to_platform_device(cpsw->dev);
7826d43f 1920
52c4f0ec 1921 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f 1922 strlcpy(info->version, "1.0", sizeof(info->version));
56e31bd8 1923 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
df828598
M		 1924}
1925
1926static u32 cpsw_get_msglevel(struct net_device *ndev)
1927{
1928 struct cpsw_priv *priv = netdev_priv(ndev);
1929 return priv->msg_enable;
1930}
1931
1932static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1933{
1934 struct cpsw_priv *priv = netdev_priv(ndev);
1935 priv->msg_enable = value;
1936}
1937
2e5b38ab
RC		 1938static int cpsw_get_ts_info(struct net_device *ndev,
1939 struct ethtool_ts_info *info)
1940{
1941#ifdef CONFIG_TI_CPTS
2a05a622 1942 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2e5b38ab
RC		 1943
1944 info->so_timestamping =
1945 SOF_TIMESTAMPING_TX_HARDWARE |
1946 SOF_TIMESTAMPING_TX_SOFTWARE |
1947 SOF_TIMESTAMPING_RX_HARDWARE |
1948 SOF_TIMESTAMPING_RX_SOFTWARE |
1949 SOF_TIMESTAMPING_SOFTWARE |
1950 SOF_TIMESTAMPING_RAW_HARDWARE;
2a05a622 1951 info->phc_index = cpsw->cpts->phc_index;
2e5b38ab
RC		 1952 info->tx_types =
1953 (1 << HWTSTAMP_TX_OFF) |
1954 (1 << HWTSTAMP_TX_ON);
1955 info->rx_filters =
1956 (1 << HWTSTAMP_FILTER_NONE) |
1957 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1958#else
1959 info->so_timestamping =
1960 SOF_TIMESTAMPING_TX_SOFTWARE |
1961 SOF_TIMESTAMPING_RX_SOFTWARE |
1962 SOF_TIMESTAMPING_SOFTWARE;
1963 info->phc_index = -1;
1964 info->tx_types = 0;
1965 info->rx_filters = 0;
1966#endif
1967 return 0;
1968}
1969
d3bb9c58
M		 1970static int cpsw_get_settings(struct net_device *ndev,
1971 struct ethtool_cmd *ecmd)
1972{
1973 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 1974 struct cpsw_common *cpsw = priv->cpsw;
1975 int slave_no = cpsw_slave_index(cpsw, priv);
d3bb9c58 1976
606f3993
IK		 1977 if (cpsw->slaves[slave_no].phy)
1978 return phy_ethtool_gset(cpsw->slaves[slave_no].phy, ecmd);
d3bb9c58
M		 1979 else
1980 return -EOPNOTSUPP;
1981}
1982
1983static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1984{
1985 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 1986 struct cpsw_common *cpsw = priv->cpsw;
1987 int slave_no = cpsw_slave_index(cpsw, priv);
d3bb9c58 1988
606f3993
IK		 1989 if (cpsw->slaves[slave_no].phy)
1990 return phy_ethtool_sset(cpsw->slaves[slave_no].phy, ecmd);
d3bb9c58
M		 1991 else
1992 return -EOPNOTSUPP;
1993}
1994
d8a64420
MU		 1995static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1996{
1997 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 1998 struct cpsw_common *cpsw = priv->cpsw;
1999 int slave_no = cpsw_slave_index(cpsw, priv);
d8a64420
MU		 2000
2001 wol->supported = 0;
2002 wol->wolopts = 0;
2003
606f3993
IK		 2004 if (cpsw->slaves[slave_no].phy)
2005 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
d8a64420
MU		 2006}
2007
2008static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2009{
2010 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2011 struct cpsw_common *cpsw = priv->cpsw;
2012 int slave_no = cpsw_slave_index(cpsw, priv);
d8a64420 2013
606f3993
IK		 2014 if (cpsw->slaves[slave_no].phy)
2015 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
d8a64420
MU		 2016 else
2017 return -EOPNOTSUPP;
2018}
2019
1923d6e4
M		 2020static void cpsw_get_pauseparam(struct net_device *ndev,
2021 struct ethtool_pauseparam *pause)
2022{
2023 struct cpsw_priv *priv = netdev_priv(ndev);
2024
2025 pause->autoneg = AUTONEG_DISABLE;
2026 pause->rx_pause = priv->rx_pause ? true : false;
2027 pause->tx_pause = priv->tx_pause ? true : false;
2028}
2029
2030static int cpsw_set_pauseparam(struct net_device *ndev,
2031 struct ethtool_pauseparam *pause)
2032{
2033 struct cpsw_priv *priv = netdev_priv(ndev);
2034 bool link;
2035
2036 priv->rx_pause = pause->rx_pause ? true : false;
2037 priv->tx_pause = pause->tx_pause ? true : false;
2038
2039 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1923d6e4
M		 2040 return 0;
2041}
2042
7898b1da
GS		 2043static int cpsw_ethtool_op_begin(struct net_device *ndev)
2044{
2045 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 2046 struct cpsw_common *cpsw = priv->cpsw;
7898b1da
GS		 2047 int ret;
2048
56e31bd8 2049 ret = pm_runtime_get_sync(cpsw->dev);
7898b1da
GS		 2050 if (ret < 0) {
2051 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
56e31bd8 2052 pm_runtime_put_noidle(cpsw->dev);
7898b1da
GS		 2053 }
2054
2055 return ret;
2056}
2057
2058static void cpsw_ethtool_op_complete(struct net_device *ndev)
2059{
2060 struct cpsw_priv *priv = netdev_priv(ndev);
2061 int ret;
2062
56e31bd8 2063 ret = pm_runtime_put(priv->cpsw->dev);
7898b1da
GS		 2064 if (ret < 0)
2065 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2066}
2067
ce52c744
IK		 2068static void cpsw_get_channels(struct net_device *ndev,
2069 struct ethtool_channels *ch)
2070{
2071 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2072
2073 ch->max_combined = 0;
2074 ch->max_rx = CPSW_MAX_QUEUES;
2075 ch->max_tx = CPSW_MAX_QUEUES;
2076 ch->max_other = 0;
2077 ch->other_count = 0;
2078 ch->rx_count = cpsw->rx_ch_num;
2079 ch->tx_count = cpsw->tx_ch_num;
2080 ch->combined_count = 0;
2081}
2082
2083static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2084 struct ethtool_channels *ch)
2085{
2086 if (ch->combined_count)
2087 return -EINVAL;
2088
2089 /* verify we have at least one channel in each direction */
2090 if (!ch->rx_count || !ch->tx_count)
2091 return -EINVAL;
2092
2093 if (ch->rx_count > cpsw->data.channels ||
2094 ch->tx_count > cpsw->data.channels)
2095 return -EINVAL;
2096
2097 return 0;
2098}
2099
2100static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2101{
2102 int (*poll)(struct napi_struct *, int);
2103 struct cpsw_common *cpsw = priv->cpsw;
2104 void (*handler)(void *, int, int);
2105 struct cpdma_chan **chan;
2106 int ret, *ch;
2107
2108 if (rx) {
2109 ch = &cpsw->rx_ch_num;
2110 chan = cpsw->rxch;
2111 handler = cpsw_rx_handler;
2112 poll = cpsw_rx_poll;
2113 } else {
2114 ch = &cpsw->tx_ch_num;
2115 chan = cpsw->txch;
2116 handler = cpsw_tx_handler;
2117 poll = cpsw_tx_poll;
2118 }
2119
2120 while (*ch < ch_num) {
2121 chan[*ch] = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2122
2123 if (IS_ERR(chan[*ch]))
2124 return PTR_ERR(chan[*ch]);
2125
2126 if (!chan[*ch])
2127 return -EINVAL;
2128
2129 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2130 (rx ? "rx" : "tx"));
2131 (*ch)++;
2132 }
2133
2134 while (*ch > ch_num) {
2135 (*ch)--;
2136
2137 ret = cpdma_chan_destroy(chan[*ch]);
2138 if (ret)
2139 return ret;
2140
2141 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2142 (rx ? "rx" : "tx"));
2143 }
2144
2145 return 0;
2146}
2147
2148static int cpsw_update_channels(struct cpsw_priv *priv,
2149 struct ethtool_channels *ch)
2150{
2151 int ret;
2152
2153 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2154 if (ret)
2155 return ret;
2156
2157 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2158 if (ret)
2159 return ret;
2160
2161 return 0;
2162}
2163
2164static int cpsw_set_channels(struct net_device *ndev,
2165 struct ethtool_channels *chs)
2166{
2167 struct cpsw_priv *priv = netdev_priv(ndev);
2168 struct cpsw_common *cpsw = priv->cpsw;
2169 struct cpsw_slave *slave;
2170 int i, ret;
2171
2172 ret = cpsw_check_ch_settings(cpsw, chs);
2173 if (ret < 0)
2174 return ret;
2175
2176 /* Disable NAPI scheduling */
2177 cpsw_intr_disable(cpsw);
2178
2179 /* Stop all transmit queues for every network device.
2180 * Disable re-using rx descriptors with dormant_on.
2181 */
2182 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2183 if (!(slave->ndev && netif_running(slave->ndev)))
2184 continue;
2185
2186 netif_tx_stop_all_queues(slave->ndev);
2187 netif_dormant_on(slave->ndev);
2188 }
2189
2190 /* Handle rest of tx packets and stop cpdma channels */
2191 cpdma_ctlr_stop(cpsw->dma);
2192 ret = cpsw_update_channels(priv, chs);
2193 if (ret)
2194 goto err;
2195
2196 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2197 if (!(slave->ndev && netif_running(slave->ndev)))
2198 continue;
2199
2200 /* Inform stack about new count of queues */
2201 ret = netif_set_real_num_tx_queues(slave->ndev,
2202 cpsw->tx_ch_num);
2203 if (ret) {
2204 dev_err(priv->dev, "cannot set real number of tx queues\n");
2205 goto err;
2206 }
2207
2208 ret = netif_set_real_num_rx_queues(slave->ndev,
2209 cpsw->rx_ch_num);
2210 if (ret) {
2211 dev_err(priv->dev, "cannot set real number of rx queues\n");
2212 goto err;
2213 }
2214
2215 /* Enable rx packets handling */
2216 netif_dormant_off(slave->ndev);
2217 }
2218
2219 if (cpsw_common_res_usage_state(cpsw)) {
e19ac157
WY		 2220 ret = cpsw_fill_rx_channels(priv);
2221 if (ret)
ce52c744
IK		 2222 goto err;
2223
2224 /* After this receive is started */
2225 cpdma_ctlr_start(cpsw->dma);
2226 cpsw_intr_enable(cpsw);
2227 }
2228
2229 /* Resume transmit for every affected interface */
2230 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2231 if (!(slave->ndev && netif_running(slave->ndev)))
2232 continue;
2233 netif_tx_start_all_queues(slave->ndev);
2234 }
2235 return 0;
2236err:
2237 dev_err(priv->dev, "cannot update channels number, closing device\n");
2238 dev_close(ndev);
2239 return ret;
2240}
2241
df828598
M		 2242static const struct ethtool_ops cpsw_ethtool_ops = {
2243 .get_drvinfo = cpsw_get_drvinfo,
2244 .get_msglevel = cpsw_get_msglevel,
2245 .set_msglevel = cpsw_set_msglevel,
2246 .get_link = ethtool_op_get_link,
2e5b38ab 2247 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 2248 .get_settings = cpsw_get_settings,
2249 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 2250 .get_coalesce = cpsw_get_coalesce,
2251 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 2252 .get_sset_count = cpsw_get_sset_count,
2253 .get_strings = cpsw_get_strings,
2254 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 2255 .get_pauseparam = cpsw_get_pauseparam,
2256 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 2257 .get_wol = cpsw_get_wol,
2258 .set_wol = cpsw_set_wol,
52c4f0ec
M		 2259 .get_regs_len = cpsw_get_regs_len,
2260 .get_regs = cpsw_get_regs,
7898b1da
GS		 2261 .begin = cpsw_ethtool_op_begin,
2262 .complete = cpsw_ethtool_op_complete,
ce52c744
IK		 2263 .get_channels = cpsw_get_channels,
2264 .set_channels = cpsw_set_channels,
df828598
M		 2265};
2266
606f3993 2267static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
549985ee 2268 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598 2269{
5d8d0d4d 2270 void __iomem *regs = cpsw->regs;
df828598 2271 int slave_num = slave->slave_num;
606f3993 2272 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
df828598
M		 2273
2274 slave->data = data;
549985ee
RC		 2275 slave->regs = regs + slave_reg_ofs;
2276 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 2277 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 2278}
2279
552165bc 2280static int cpsw_probe_dt(struct cpsw_platform_data *data,
2eb32b0a
M		 2281 struct platform_device *pdev)
2282{
2283 struct device_node *node = pdev->dev.of_node;
2284 struct device_node *slave_node;
2285 int i = 0, ret;
2286 u32 prop;
2287
2288 if (!node)
2289 return -EINVAL;
2290
2291 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 2292 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 2293 return -EINVAL;
2294 }
2295 data->slaves = prop;
2296
e86ac13b 2297 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 2298 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 2299 return -EINVAL;
78ca0b28 2300 }
e86ac13b 2301 data->active_slave = prop;
78ca0b28 2302
00ab94ee 2303 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 2304 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 2305 return -EINVAL;
00ab94ee
RC		 2306 }
2307 data->cpts_clock_mult = prop;
2308
2309 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 2310 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 2311 return -EINVAL;
00ab94ee
RC		 2312 }
2313 data->cpts_clock_shift = prop;
2314
aa1a15e2
DM		 2315 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2316 * sizeof(struct cpsw_slave_data),
2317 GFP_KERNEL);
b2adaca9 2318 if (!data->slave_data)
aa1a15e2 2319 return -ENOMEM;
2eb32b0a 2320
2eb32b0a 2321 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 2322 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 2323 return -EINVAL;
2eb32b0a
M		 2324 }
2325 data->channels = prop;
2326
2eb32b0a 2327 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 2328 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 2329 return -EINVAL;
2eb32b0a
M		 2330 }
2331 data->ale_entries = prop;
2332
2eb32b0a 2333 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 2334 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 2335 return -EINVAL;
2eb32b0a
M		 2336 }
2337 data->bd_ram_size = prop;
2338
2eb32b0a 2339 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2340 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2341 return -EINVAL;
2eb32b0a
M		 2342 }
2343 data->mac_control = prop;
2344
281abd96
MP		 2345 if (of_property_read_bool(node, "dual_emac"))
2346 data->dual_emac = 1;
d9ba8f9e 2347
549985ee
RC		 2348 /*
2349 * Populate all the child nodes here...
2350 */
2351 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2352 /* We do not want to force this, as in some cases may not have child */
2353 if (ret)
88c99ff6 2354 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2355
8658aaf2 2356 for_each_available_child_of_node(node, slave_node) {
2eb32b0a 2357 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2358 const void *mac_addr = NULL;
549985ee
RC		 2359 int lenp;
2360 const __be32 *parp;
549985ee 2361
f468b10e
MP		 2362 /* This is no slave child node, continue */
2363 if (strcmp(slave_node->name, "slave"))
2364 continue;
2365
552165bc
DR		 2366 slave_data->phy_node = of_parse_phandle(slave_node,
2367 "phy-handle", 0);
f1eea5c1 2368 parp = of_get_property(slave_node, "phy_id", &lenp);
ae092b5b
DR		 2369 if (slave_data->phy_node) {
2370 dev_dbg(&pdev->dev,
2371 "slave[%d] using phy-handle=\"%s\"\n",
2372 i, slave_data->phy_node->full_name);
2373 } else if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2374 /* In the case of a fixed PHY, the DT node associated
2375 * to the PHY is the Ethernet MAC DT node.
2376 */
1f71e8c9
MB		 2377 ret = of_phy_register_fixed_link(slave_node);
2378 if (ret)
2379 return ret;
06cd6d6e 2380 slave_data->phy_node = of_node_get(slave_node);
f1eea5c1
DR		 2381 } else if (parp) {
2382 u32 phyid;
2383 struct device_node *mdio_node;
2384 struct platform_device *mdio;
2385
2386 if (lenp != (sizeof(__be32) * 2)) {
2387 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2388 goto no_phy_slave;
2389 }
2390 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2391 phyid = be32_to_cpup(parp+1);
2392 mdio = of_find_device_by_node(mdio_node);
2393 of_node_put(mdio_node);
2394 if (!mdio) {
2395 dev_err(&pdev->dev, "Missing mdio platform device\n");
2396 return -EINVAL;
2397 }
2398 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2399 PHY_ID_FMT, mdio->name, phyid);
2400 } else {
ae092b5b
DR		 2401 dev_err(&pdev->dev,
2402 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2403 i);
47276fcc 2404 goto no_phy_slave;
2eb32b0a 2405 }
47276fcc
M		 2406 slave_data->phy_if = of_get_phy_mode(slave_node);
2407 if (slave_data->phy_if < 0) {
2408 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2409 i);
2410 return slave_data->phy_if;
2411 }
2412
2413no_phy_slave:
2eb32b0a 2414 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2415 if (mac_addr) {
2eb32b0a 2416 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2417 } else {
b6745f6e
M		 2418 ret = ti_cm_get_macid(&pdev->dev, i,
2419 slave_data->mac_addr);
2420 if (ret)
2421 return ret;
0ba517b1 2422 }
d9ba8f9e 2423 if (data->dual_emac) {
91c4166c 2424 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2425 &prop)) {
88c99ff6 2426 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2427 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2428 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2429 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2430 } else {
2431 slave_data->dual_emac_res_vlan = prop;
2432 }
2433 }
2434
2eb32b0a 2435 i++;
3a27bfac
M		 2436 if (i == data->slaves)
2437 break;
2eb32b0a
M		 2438 }
2439
2440 return 0;
2eb32b0a
M		 2441}
2442
56e31bd8 2443static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
d9ba8f9e 2444{
606f3993
IK		 2445 struct cpsw_common *cpsw = priv->cpsw;
2446 struct cpsw_platform_data *data = &cpsw->data;
d9ba8f9e
M		 2447 struct net_device *ndev;
2448 struct cpsw_priv *priv_sl2;
e38b5a3d 2449 int ret = 0;
d9ba8f9e 2450
e05107e6 2451 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
d9ba8f9e 2452 if (!ndev) {
56e31bd8 2453 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2454 return -ENOMEM;
2455 }
2456
2457 priv_sl2 = netdev_priv(ndev);
606f3993 2458 priv_sl2->cpsw = cpsw;
d9ba8f9e
M		 2459 priv_sl2->ndev = ndev;
2460 priv_sl2->dev = &ndev->dev;
2461 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
d9ba8f9e
M		 2462
2463 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2464 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2465 ETH_ALEN);
56e31bd8
IK		 2466 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2467 priv_sl2->mac_addr);
d9ba8f9e
M		 2468 } else {
2469 random_ether_addr(priv_sl2->mac_addr);
56e31bd8
IK		 2470 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2471 priv_sl2->mac_addr);
d9ba8f9e
M		 2472 }
2473 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2474
d9ba8f9e 2475 priv_sl2->emac_port = 1;
606f3993 2476 cpsw->slaves[1].ndev = ndev;
f646968f 2477 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2478
2479 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2480 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2481
2482 /* register the network device */
56e31bd8 2483 SET_NETDEV_DEV(ndev, cpsw->dev);
d9ba8f9e
M		 2484 ret = register_netdev(ndev);
2485 if (ret) {
56e31bd8 2486 dev_err(cpsw->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2487 free_netdev(ndev);
2488 ret = -ENODEV;
2489 }
2490
2491 return ret;
2492}
2493
7da11600
M		 2494#define CPSW_QUIRK_IRQ BIT(0)
2495
2496static struct platform_device_id cpsw_devtype[] = {
2497 {
2498 /* keep it for existing comaptibles */
2499 .name = "cpsw",
2500 .driver_data = CPSW_QUIRK_IRQ,
2501 }, {
2502 .name = "am335x-cpsw",
2503 .driver_data = CPSW_QUIRK_IRQ,
2504 }, {
2505 .name = "am4372-cpsw",
2506 .driver_data = 0,
2507 }, {
2508 .name = "dra7-cpsw",
2509 .driver_data = 0,
2510 }, {
2511 /* sentinel */
2512 }
2513};
2514MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2515
2516enum ti_cpsw_type {
2517 CPSW = 0,
2518 AM335X_CPSW,
2519 AM4372_CPSW,
2520 DRA7_CPSW,
2521};
2522
2523static const struct of_device_id cpsw_of_mtable[] = {
2524 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2525 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2526 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2527 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2528 { /* sentinel */ },
2529};
2530MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2531
663e12e6 2532static int cpsw_probe(struct platform_device *pdev)
df828598 2533{
ef4183a1 2534 struct clk *clk;
d1bd9acf 2535 struct cpsw_platform_data *data;
df828598
M		 2536 struct net_device *ndev;
2537 struct cpsw_priv *priv;
2538 struct cpdma_params dma_params;
2539 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2540 void __iomem *ss_regs;
2541 struct resource *res, *ss_res;
7da11600 2542 const struct of_device_id *of_id;
1d147ccb 2543 struct gpio_descs *mode;
549985ee 2544 u32 slave_offset, sliver_offset, slave_size;
649a1688 2545 struct cpsw_common *cpsw;
5087b915
FB		 2546 int ret = 0, i;
2547 int irq;
df828598 2548
649a1688 2549 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
56e31bd8 2550 cpsw->dev = &pdev->dev;
649a1688 2551
e05107e6 2552 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
df828598 2553 if (!ndev) {
88c99ff6 2554 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2555 return -ENOMEM;
2556 }
2557
2558 platform_set_drvdata(pdev, ndev);
2559 priv = netdev_priv(ndev);
649a1688 2560 priv->cpsw = cpsw;
df828598
M		 2561 priv->ndev = ndev;
2562 priv->dev = &ndev->dev;
2563 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2a05a622
IK		 2564 cpsw->rx_packet_max = max(rx_packet_max, 128);
2565 cpsw->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2566 if (!cpsw->cpts) {
88c99ff6 2567 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2568 ret = -ENOMEM;
9232b16d
M		 2569 goto clean_ndev_ret;
2570 }
df828598 2571
1d147ccb
M		 2572 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2573 if (IS_ERR(mode)) {
2574 ret = PTR_ERR(mode);
2575 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2576 goto clean_ndev_ret;
2577 }
2578
1fb19aa7
VH		 2579 /*
2580 * This may be required here for child devices.
2581 */
2582 pm_runtime_enable(&pdev->dev);
2583
739683b4
M		 2584 /* Select default pin state */
2585 pinctrl_pm_select_default_state(&pdev->dev);
2586
606f3993 2587 if (cpsw_probe_dt(&cpsw->data, pdev)) {
88c99ff6 2588 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2589 ret = -ENODEV;
aa1a15e2 2590 goto clean_runtime_disable_ret;
2eb32b0a 2591 }
606f3993 2592 data = &cpsw->data;
e05107e6
IK		 2593 cpsw->rx_ch_num = 1;
2594 cpsw->tx_ch_num = 1;
2eb32b0a 2595
df828598
M		 2596 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2597 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2598 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2599 } else {
7efd26d0 2600 eth_random_addr(priv->mac_addr);
88c99ff6 2601 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2602 }
2603
2604 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2605
606f3993 2606 cpsw->slaves = devm_kzalloc(&pdev->dev,
aa1a15e2
DM		 2607 sizeof(struct cpsw_slave) * data->slaves,
2608 GFP_KERNEL);
606f3993 2609 if (!cpsw->slaves) {
aa1a15e2
DM		 2610 ret = -ENOMEM;
2611 goto clean_runtime_disable_ret;
df828598
M		 2612 }
2613 for (i = 0; i < data->slaves; i++)
606f3993 2614 cpsw->slaves[i].slave_num = i;
df828598 2615
606f3993 2616 cpsw->slaves[0].ndev = ndev;
d9ba8f9e
M		 2617 priv->emac_port = 0;
2618
ef4183a1
IK		 2619 clk = devm_clk_get(&pdev->dev, "fck");
2620 if (IS_ERR(clk)) {
aa1a15e2 2621 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2622 ret = -ENODEV;
aa1a15e2 2623 goto clean_runtime_disable_ret;
df828598 2624 }
2a05a622 2625 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
df828598 2626
aa1a15e2
DM		 2627 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2628 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2629 if (IS_ERR(ss_regs)) {
2630 ret = PTR_ERR(ss_regs);
2631 goto clean_runtime_disable_ret;
df828598 2632 }
5d8d0d4d 2633 cpsw->regs = ss_regs;
df828598 2634
f280e89a
M		 2635 /* Need to enable clocks with runtime PM api to access module
2636 * registers
2637 */
108a6537
GS		 2638 ret = pm_runtime_get_sync(&pdev->dev);
2639 if (ret < 0) {
2640 pm_runtime_put_noidle(&pdev->dev);
2641 goto clean_runtime_disable_ret;
2642 }
2a05a622 2643 cpsw->version = readl(&cpsw->regs->id_ver);
f280e89a
M		 2644 pm_runtime_put_sync(&pdev->dev);
2645
aa1a15e2 2646 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5d8d0d4d
IK		 2647 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2648 if (IS_ERR(cpsw->wr_regs)) {
2649 ret = PTR_ERR(cpsw->wr_regs);
aa1a15e2 2650 goto clean_runtime_disable_ret;
df828598 2651 }
df828598
M		 2652
2653 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2654 memset(&ale_params, 0, sizeof(ale_params));
2655
2a05a622 2656 switch (cpsw->version) {
549985ee 2657 case CPSW_VERSION_1:
5d8d0d4d 2658 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2a05a622 2659 cpsw->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
5d8d0d4d 2660 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2661 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2662 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2663 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2664 slave_offset = CPSW1_SLAVE_OFFSET;
2665 slave_size = CPSW1_SLAVE_SIZE;
2666 sliver_offset = CPSW1_SLIVER_OFFSET;
2667 dma_params.desc_mem_phys = 0;
2668 break;
2669 case CPSW_VERSION_2:
c193f365 2670 case CPSW_VERSION_3:
926489be 2671 case CPSW_VERSION_4:
5d8d0d4d 2672 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2a05a622 2673 cpsw->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
5d8d0d4d 2674 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2675 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2676 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2677 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2678 slave_offset = CPSW2_SLAVE_OFFSET;
2679 slave_size = CPSW2_SLAVE_SIZE;
2680 sliver_offset = CPSW2_SLIVER_OFFSET;
2681 dma_params.desc_mem_phys =
aa1a15e2 2682 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2683 break;
2684 default:
2a05a622 2685 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
549985ee 2686 ret = -ENODEV;
aa1a15e2 2687 goto clean_runtime_disable_ret;
549985ee 2688 }
606f3993
IK		 2689 for (i = 0; i < cpsw->data.slaves; i++) {
2690 struct cpsw_slave *slave = &cpsw->slaves[i];
2691
2692 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
549985ee
RC		 2693 slave_offset += slave_size;
2694 sliver_offset += SLIVER_SIZE;
2695 }
2696
df828598 2697 dma_params.dev = &pdev->dev;
549985ee
RC		 2698 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2699 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2700 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2701 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2702 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2703
2704 dma_params.num_chan = data->channels;
2705 dma_params.has_soft_reset = true;
2706 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2707 dma_params.desc_mem_size = data->bd_ram_size;
2708 dma_params.desc_align = 16;
2709 dma_params.has_ext_regs = true;
549985ee 2710 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598 2711
2c836bd9
IK		 2712 cpsw->dma = cpdma_ctlr_create(&dma_params);
2713 if (!cpsw->dma) {
df828598
M		 2714 dev_err(priv->dev, "error initializing dma\n");
2715 ret = -ENOMEM;
aa1a15e2 2716 goto clean_runtime_disable_ret;
df828598
M		 2717 }
2718
925d65e6
IK		 2719 cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
2720 cpsw->rxch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
e05107e6 2721 if (WARN_ON(!cpsw->rxch[0] || !cpsw->txch[0])) {
df828598
M		 2722 dev_err(priv->dev, "error initializing dma channels\n");
2723 ret = -ENOMEM;
2724 goto clean_dma_ret;
2725 }
2726
df828598 2727 ale_params.dev = &ndev->dev;
df828598
M		 2728 ale_params.ale_ageout = ale_ageout;
2729 ale_params.ale_entries = data->ale_entries;
2730 ale_params.ale_ports = data->slaves;
2731
2a05a622
IK		 2732 cpsw->ale = cpsw_ale_create(&ale_params);
2733 if (!cpsw->ale) {
df828598
M		 2734 dev_err(priv->dev, "error initializing ale engine\n");
2735 ret = -ENODEV;
2736 goto clean_dma_ret;
2737 }
2738
c03abd84 2739 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 2740 if (ndev->irq < 0) {
2741 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 2742 ret = ndev->irq;
df828598
M		 2743 goto clean_ale_ret;
2744 }
2745
7da11600
M		 2746 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2747 if (of_id) {
2748 pdev->id_entry = of_id->data;
2749 if (pdev->id_entry->driver_data)
e38b5a3d 2750 cpsw->quirk_irq = true;
7da11600
M		 2751 }
2752
c03abd84
FB		 2753 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2754 * MISC IRQs which are always kept disabled with this driver so
2755 * we will not request them.
2756 *
2757 * If anyone wants to implement support for those, make sure to
2758 * first request and append them to irqs_table array.
2759 */
c2b32e58 2760
c03abd84 2761 /* RX IRQ */
5087b915 2762 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 2763 if (irq < 0) {
2764 ret = irq;
5087b915 2765 goto clean_ale_ret;
c1e3334f 2766 }
5087b915 2767
e38b5a3d 2768 cpsw->irqs_table[0] = irq;
c03abd84 2769 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
dbc4ec52 2770 0, dev_name(&pdev->dev), cpsw);
5087b915
FB		 2771 if (ret < 0) {
2772 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2773 goto clean_ale_ret;
2774 }
2775
c03abd84 2776 /* TX IRQ */
5087b915 2777 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 2778 if (irq < 0) {
2779 ret = irq;
5087b915 2780 goto clean_ale_ret;
c1e3334f 2781 }
5087b915 2782
e38b5a3d 2783 cpsw->irqs_table[1] = irq;
c03abd84 2784 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
dbc4ec52 2785 0, dev_name(&pdev->dev), cpsw);
5087b915
FB		 2786 if (ret < 0) {
2787 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2788 goto clean_ale_ret;
df828598 2789 }
c2b32e58 2790
f646968f 2791 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2792
2793 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2794 ndev->ethtool_ops = &cpsw_ethtool_ops;
dbc4ec52
IK		 2795 netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2796 netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
df828598
M		 2797
2798 /* register the network device */
2799 SET_NETDEV_DEV(ndev, &pdev->dev);
2800 ret = register_netdev(ndev);
2801 if (ret) {
2802 dev_err(priv->dev, "error registering net device\n");
2803 ret = -ENODEV;
aa1a15e2 2804 goto clean_ale_ret;
df828598
M		 2805 }
2806
1a3b5056
OJ		 2807 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2808 &ss_res->start, ndev->irq);
df828598 2809
606f3993 2810 if (cpsw->data.dual_emac) {
56e31bd8 2811 ret = cpsw_probe_dual_emac(priv);
d9ba8f9e
M		 2812 if (ret) {
2813 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2814 goto clean_ale_ret;
d9ba8f9e
M		 2815 }
2816 }
2817
df828598
M		 2818 return 0;
2819
df828598 2820clean_ale_ret:
2a05a622 2821 cpsw_ale_destroy(cpsw->ale);
df828598 2822clean_dma_ret:
2c836bd9 2823 cpdma_ctlr_destroy(cpsw->dma);
aa1a15e2 2824clean_runtime_disable_ret:
f150bd7f 2825 pm_runtime_disable(&pdev->dev);
df828598 2826clean_ndev_ret:
d1bd9acf 2827 free_netdev(priv->ndev);
df828598
M		 2828 return ret;
2829}
2830
663e12e6 2831static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2832{
2833 struct net_device *ndev = platform_get_drvdata(pdev);
2a05a622 2834 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
8a0b6dc9
GS		 2835 int ret;
2836
2837 ret = pm_runtime_get_sync(&pdev->dev);
2838 if (ret < 0) {
2839 pm_runtime_put_noidle(&pdev->dev);
2840 return ret;
2841 }
df828598 2842
606f3993
IK		 2843 if (cpsw->data.dual_emac)
2844 unregister_netdev(cpsw->slaves[1].ndev);
d1bd9acf 2845 unregister_netdev(ndev);
df828598 2846
2a05a622 2847 cpsw_ale_destroy(cpsw->ale);
2c836bd9 2848 cpdma_ctlr_destroy(cpsw->dma);
3bf2cb3a 2849 of_platform_depopulate(&pdev->dev);
8a0b6dc9
GS		 2850 pm_runtime_put_sync(&pdev->dev);
2851 pm_runtime_disable(&pdev->dev);
606f3993
IK		 2852 if (cpsw->data.dual_emac)
2853 free_netdev(cpsw->slaves[1].ndev);
df828598 2854 free_netdev(ndev);
df828598
M		 2855 return 0;
2856}
2857
8963a504 2858#ifdef CONFIG_PM_SLEEP
df828598
M		 2859static int cpsw_suspend(struct device *dev)
2860{
2861 struct platform_device *pdev = to_platform_device(dev);
2862 struct net_device *ndev = platform_get_drvdata(pdev);
606f3993 2863 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 2864
606f3993 2865 if (cpsw->data.dual_emac) {
618073e3 2866 int i;
1e7a2e21 2867
606f3993
IK		 2868 for (i = 0; i < cpsw->data.slaves; i++) {
2869 if (netif_running(cpsw->slaves[i].ndev))
2870 cpsw_ndo_stop(cpsw->slaves[i].ndev);
618073e3
M		 2871 }
2872 } else {
2873 if (netif_running(ndev))
2874 cpsw_ndo_stop(ndev);
618073e3 2875 }
1e7a2e21 2876
739683b4 2877 /* Select sleep pin state */
56e31bd8 2878 pinctrl_pm_select_sleep_state(dev);
739683b4 2879
df828598
M		 2880 return 0;
2881}
2882
2883static int cpsw_resume(struct device *dev)
2884{
2885 struct platform_device *pdev = to_platform_device(dev);
2886 struct net_device *ndev = platform_get_drvdata(pdev);
606f3993 2887 struct cpsw_common *cpsw = netdev_priv(ndev);
df828598 2888
739683b4 2889 /* Select default pin state */
56e31bd8 2890 pinctrl_pm_select_default_state(dev);
739683b4 2891
606f3993 2892 if (cpsw->data.dual_emac) {
618073e3
M		 2893 int i;
2894
606f3993
IK		 2895 for (i = 0; i < cpsw->data.slaves; i++) {
2896 if (netif_running(cpsw->slaves[i].ndev))
2897 cpsw_ndo_open(cpsw->slaves[i].ndev);
618073e3
M		 2898 }
2899 } else {
2900 if (netif_running(ndev))
2901 cpsw_ndo_open(ndev);
2902 }
df828598
M		 2903 return 0;
2904}
8963a504 2905#endif
df828598 2906
8963a504 2907static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 2908
2909static struct platform_driver cpsw_driver = {
2910 .driver = {
2911 .name = "cpsw",
df828598 2912 .pm = &cpsw_pm_ops,
1e5c76d4 2913 .of_match_table = cpsw_of_mtable,
df828598
M		 2914 },
2915 .probe = cpsw_probe,
663e12e6 2916 .remove = cpsw_remove,
df828598
M		 2917};
2918
6fb3b6b5 2919module_platform_driver(cpsw_driver);
df828598
M		 2920
2921MODULE_LICENSE("GPL");
2922MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2923MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2924MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
This page took 0.60753 seconds and 5 git commands to generate.