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drivers: net: cpsw: don't ignore phy-mode if phy-handle is used
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
127#define CPDMA_TX_PRIORITY_MAP 0x76543210
128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
d3bb9c58
M		 143#define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
df828598
M		 147static int debug_level;
148module_param(debug_level, int, 0);
149MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151static int ale_ageout = 10;
152module_param(ale_ageout, int, 0);
153MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156module_param(rx_packet_max, int, 0);
157MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
996a5c27 159struct cpsw_wr_regs {
df828598
M		 160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
ff5b8ef2
M		 168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
df828598
M		 177};
178
996a5c27 179struct cpsw_ss_regs {
df828598
M		 180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
bd357af2
RC		 185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
df828598
M		 193};
194
9750a3ad
RC		 195/* CPSW_PORT_V1 */
196#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205/* CPSW_PORT_V2 */
206#define CPSW2_CONTROL 0x00 /* Control Register */
207#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214/* CPSW_PORT_V1 and V2 */
215#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219/* CPSW_PORT_V2 only */
220#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229/* Bit definitions for the CPSW2_CONTROL register */
230#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 240#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 242#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
09c55372
GC		 248#define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 251
09c55372
GC		 252#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257#define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 265
266/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268#define TS_SEQ_ID_OFFSET_MASK (0x3f)
269#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270#define TS_MSG_TYPE_EN_MASK (0xffff)
271
272/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 274
2e5b38ab
RC		 275/* Bit definitions for the CPSW1_TS_CTL register */
276#define CPSW_V1_TS_RX_EN BIT(0)
277#define CPSW_V1_TS_TX_EN BIT(4)
278#define CPSW_V1_MSG_TYPE_OFS 16
279
280/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
df828598
M		 283struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
d9ba8f9e 286 u32 tx_in_ctl;
df828598
M		 287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291};
292
293struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304};
305
d9718546
M		 306struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342};
343
df828598 344struct cpsw_slave {
9750a3ad 345 void __iomem *regs;
df828598
M		 346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
d9ba8f9e
M		 351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
df828598
M		 354};
355
9750a3ad
RC		 356static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357{
358 return __raw_readl(slave->regs + offset);
359}
360
361static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362{
363 __raw_writel(val, slave->regs + offset);
364}
365
df828598
M		 366struct cpsw_priv {
367 spinlock_t lock;
368 struct platform_device *pdev;
369 struct net_device *ndev;
32a7432c
M		 370 struct napi_struct napi_rx;
371 struct napi_struct napi_tx;
df828598
M		 372 struct device *dev;
373 struct cpsw_platform_data data;
996a5c27
RC		 374 struct cpsw_ss_regs __iomem *regs;
375 struct cpsw_wr_regs __iomem *wr_regs;
d9718546 376 u8 __iomem *hw_stats;
df828598
M		 377 struct cpsw_host_regs __iomem *host_port_regs;
378 u32 msg_enable;
e90cfac6 379 u32 version;
ff5b8ef2
M		 380 u32 coal_intvl;
381 u32 bus_freq_mhz;
df828598
M		 382 int rx_packet_max;
383 int host_port;
384 struct clk *clk;
385 u8 mac_addr[ETH_ALEN];
386 struct cpsw_slave *slaves;
387 struct cpdma_ctlr *dma;
388 struct cpdma_chan *txch, *rxch;
389 struct cpsw_ale *ale;
1923d6e4
M		 390 bool rx_pause;
391 bool tx_pause;
7da11600
M		 392 bool quirk_irq;
393 bool rx_irq_disabled;
394 bool tx_irq_disabled;
df828598
M		 395 /* snapshot of IRQ numbers */
396 u32 irqs_table[4];
397 u32 num_irqs;
9232b16d 398 struct cpts *cpts;
d9ba8f9e 399 u32 emac_port;
df828598
M		 400};
401
d9718546
M		 402struct cpsw_stats {
403 char stat_string[ETH_GSTRING_LEN];
404 int type;
405 int sizeof_stat;
406 int stat_offset;
407};
408
409enum {
410 CPSW_STATS,
411 CPDMA_RX_STATS,
412 CPDMA_TX_STATS,
413};
414
415#define CPSW_STAT(m) CPSW_STATS, \
416 sizeof(((struct cpsw_hw_stats *)0)->m), \
417 offsetof(struct cpsw_hw_stats, m)
418#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
419 sizeof(((struct cpdma_chan_stats *)0)->m), \
420 offsetof(struct cpdma_chan_stats, m)
421#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
422 sizeof(((struct cpdma_chan_stats *)0)->m), \
423 offsetof(struct cpdma_chan_stats, m)
424
425static const struct cpsw_stats cpsw_gstrings_stats[] = {
426 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
427 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
428 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
429 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
430 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
431 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
432 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
433 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
434 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
435 { "Rx Fragments", CPSW_STAT(rxfragments) },
436 { "Rx Octets", CPSW_STAT(rxoctets) },
437 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
438 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
439 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
440 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
441 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
442 { "Collisions", CPSW_STAT(txcollisionframes) },
443 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
444 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
445 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
446 { "Late Collisions", CPSW_STAT(txlatecollisions) },
447 { "Tx Underrun", CPSW_STAT(txunderrun) },
448 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
449 { "Tx Octets", CPSW_STAT(txoctets) },
450 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
451 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
452 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
453 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
454 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
455 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
456 { "Net Octets", CPSW_STAT(netoctets) },
457 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
458 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
459 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
460 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
461 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
462 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
463 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
464 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
465 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
466 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
467 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
468 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
469 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
470 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
471 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
472 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
473 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
474 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
475 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
476 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
477 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
478 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
479 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
480 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
481 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
482 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
483 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
484 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
485 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
486};
487
488#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
489
df828598 490#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 491#define for_each_slave(priv, func, arg...) \
492 do { \
6e6ceaed
SS		 493 struct cpsw_slave *slave; \
494 int n; \
d9ba8f9e
M		 495 if (priv->data.dual_emac) \
496 (func)((priv)->slaves + priv->emac_port, ##arg);\
497 else \
6e6ceaed
SS		 498 for (n = (priv)->data.slaves, \
499 slave = (priv)->slaves; \
500 n; n--) \
501 (func)(slave++, ##arg); \
d9ba8f9e
M		 502 } while (0)
503#define cpsw_get_slave_ndev(priv, __slave_no__) \
1973db0d
M		 504 ((__slave_no__ < priv->data.slaves) ? \
505 priv->slaves[__slave_no__].ndev : NULL)
d9ba8f9e 506#define cpsw_get_slave_priv(priv, __slave_no__) \
1973db0d
M		 507 (((__slave_no__ < priv->data.slaves) && \
508 (priv->slaves[__slave_no__].ndev)) ? \
d9ba8f9e
M		 509 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
510
511#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
512 do { \
513 if (!priv->data.dual_emac) \
514 break; \
515 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
516 ndev = cpsw_get_slave_ndev(priv, 0); \
517 priv = netdev_priv(ndev); \
518 skb->dev = ndev; \
519 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
520 ndev = cpsw_get_slave_ndev(priv, 1); \
521 priv = netdev_priv(ndev); \
522 skb->dev = ndev; \
523 } \
df828598 524 } while (0)
d9ba8f9e
M		 525#define cpsw_add_mcast(priv, addr) \
526 do { \
527 if (priv->data.dual_emac) { \
528 struct cpsw_slave *slave = priv->slaves + \
529 priv->emac_port; \
530 int slave_port = cpsw_get_slave_port(priv, \
531 slave->slave_num); \
532 cpsw_ale_add_mcast(priv->ale, addr, \
533 1 << slave_port | 1 << priv->host_port, \
534 ALE_VLAN, slave->port_vlan, 0); \
535 } else { \
536 cpsw_ale_add_mcast(priv->ale, addr, \
537 ALE_ALL_PORTS << priv->host_port, \
538 0, 0, 0); \
539 } \
540 } while (0)
541
542static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
543{
544 if (priv->host_port == 0)
545 return slave_num + 1;
546 else
547 return slave_num;
548}
df828598 549
0cd8f9cc
M		 550static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
551{
552 struct cpsw_priv *priv = netdev_priv(ndev);
553 struct cpsw_ale *ale = priv->ale;
554 int i;
555
556 if (priv->data.dual_emac) {
557 bool flag = false;
558
559 /* Enabling promiscuous mode for one interface will be
560 * common for both the interface as the interface shares
561 * the same hardware resource.
562 */
0d961b3b 563 for (i = 0; i < priv->data.slaves; i++)
0cd8f9cc
M		 564 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
565 flag = true;
566
567 if (!enable && flag) {
568 enable = true;
569 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
570 }
571
572 if (enable) {
573 /* Enable Bypass */
574 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
575
576 dev_dbg(&ndev->dev, "promiscuity enabled\n");
577 } else {
578 /* Disable Bypass */
579 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
580 dev_dbg(&ndev->dev, "promiscuity disabled\n");
581 }
582 } else {
583 if (enable) {
584 unsigned long timeout = jiffies + HZ;
585
6f979eb3
LS		 586 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
587 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 588 cpsw_ale_control_set(ale, i,
589 ALE_PORT_NOLEARN, 1);
590 cpsw_ale_control_set(ale, i,
591 ALE_PORT_NO_SA_UPDATE, 1);
592 }
593
594 /* Clear All Untouched entries */
595 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
596 do {
597 cpu_relax();
598 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
599 break;
600 } while (time_after(timeout, jiffies));
601 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
602
603 /* Clear all mcast from ALE */
604 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
25906052 605 priv->host_port, -1);
0cd8f9cc
M		 606
607 /* Flood All Unicast Packets to Host port */
608 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
609 dev_dbg(&ndev->dev, "promiscuity enabled\n");
610 } else {
6f979eb3 611 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 612 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
613
6f979eb3
LS		 614 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
615 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 616 cpsw_ale_control_set(ale, i,
617 ALE_PORT_NOLEARN, 0);
618 cpsw_ale_control_set(ale, i,
619 ALE_PORT_NO_SA_UPDATE, 0);
620 }
621 dev_dbg(&ndev->dev, "promiscuity disabled\n");
622 }
623 }
624}
625
5c50a856
M		 626static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
627{
628 struct cpsw_priv *priv = netdev_priv(ndev);
25906052
M		 629 int vid;
630
631 if (priv->data.dual_emac)
632 vid = priv->slaves[priv->emac_port].port_vlan;
633 else
634 vid = priv->data.default_vlan;
5c50a856
M		 635
636 if (ndev->flags & IFF_PROMISC) {
637 /* Enable promiscuous mode */
0cd8f9cc 638 cpsw_set_promiscious(ndev, true);
1e5c4bc4 639 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
5c50a856 640 return;
0cd8f9cc
M		 641 } else {
642 /* Disable promiscuous mode */
643 cpsw_set_promiscious(ndev, false);
5c50a856
M		 644 }
645
1e5c4bc4
LS		 646 /* Restore allmulti on vlans if necessary */
647 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
648
5c50a856 649 /* Clear all mcast from ALE */
25906052
M		 650 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
651 vid);
5c50a856
M		 652
653 if (!netdev_mc_empty(ndev)) {
654 struct netdev_hw_addr *ha;
655
656 /* program multicast address list into ALE register */
657 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 658 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 659 }
660 }
661}
662
df828598
M		 663static void cpsw_intr_enable(struct cpsw_priv *priv)
664{
996a5c27
RC		 665 __raw_writel(0xFF, &priv->wr_regs->tx_en);
666 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 667
668 cpdma_ctlr_int_ctrl(priv->dma, true);
669 return;
670}
671
672static void cpsw_intr_disable(struct cpsw_priv *priv)
673{
996a5c27
RC		 674 __raw_writel(0, &priv->wr_regs->tx_en);
675 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 676
677 cpdma_ctlr_int_ctrl(priv->dma, false);
678 return;
679}
680
1a3b5056 681static void cpsw_tx_handler(void *token, int len, int status)
df828598
M		 682{
683 struct sk_buff *skb = token;
684 struct net_device *ndev = skb->dev;
685 struct cpsw_priv *priv = netdev_priv(ndev);
686
fae50823
M		 687 /* Check whether the queue is stopped due to stalled tx dma, if the
688 * queue is stopped then start the queue as we have free desc for tx
689 */
df828598 690 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 691 netif_wake_queue(ndev);
9232b16d 692 cpts_tx_timestamp(priv->cpts, skb);
8dc43ddc
TK		 693 ndev->stats.tx_packets++;
694 ndev->stats.tx_bytes += len;
df828598
M		 695 dev_kfree_skb_any(skb);
696}
697
1a3b5056 698static void cpsw_rx_handler(void *token, int len, int status)
df828598
M		 699{
700 struct sk_buff *skb = token;
b4727e69 701 struct sk_buff *new_skb;
df828598
M		 702 struct net_device *ndev = skb->dev;
703 struct cpsw_priv *priv = netdev_priv(ndev);
704 int ret = 0;
705
d9ba8f9e
M		 706 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
707
16e5c57d 708 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822
M		 709 bool ndev_status = false;
710 struct cpsw_slave *slave = priv->slaves;
711 int n;
712
713 if (priv->data.dual_emac) {
714 /* In dual emac mode check for all interfaces */
715 for (n = priv->data.slaves; n; n--, slave++)
716 if (netif_running(slave->ndev))
717 ndev_status = true;
718 }
719
720 if (ndev_status && (status >= 0)) {
721 /* The packet received is for the interface which
722 * is already down and the other interface is up
dbedd44e 723 * and running, instead of freeing which results
a0e2c822
M		 724 * in reducing of the number of rx descriptor in
725 * DMA engine, requeue skb back to cpdma.
726 */
727 new_skb = skb;
728 goto requeue;
729 }
730
b4727e69 731 /* the interface is going down, skbs are purged */
df828598
M		 732 dev_kfree_skb_any(skb);
733 return;
734 }
b4727e69
SS		 735
736 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
737 if (new_skb) {
df828598 738 skb_put(skb, len);
9232b16d 739 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 740 skb->protocol = eth_type_trans(skb, ndev);
741 netif_receive_skb(skb);
8dc43ddc
TK		 742 ndev->stats.rx_bytes += len;
743 ndev->stats.rx_packets++;
b4727e69 744 } else {
8dc43ddc 745 ndev->stats.rx_dropped++;
b4727e69 746 new_skb = skb;
df828598
M		 747 }
748
a0e2c822 749requeue:
b4727e69
SS		 750 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
751 skb_tailroom(new_skb), 0);
752 if (WARN_ON(ret < 0))
753 dev_kfree_skb_any(new_skb);
df828598
M		 754}
755
c03abd84 756static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598
M		 757{
758 struct cpsw_priv *priv = dev_id;
7ce67a38 759
32a7432c 760 writel(0, &priv->wr_regs->tx_en);
c03abd84 761 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
c03abd84 762
7da11600
M		 763 if (priv->quirk_irq) {
764 disable_irq_nosync(priv->irqs_table[1]);
765 priv->tx_irq_disabled = true;
766 }
767
32a7432c 768 napi_schedule(&priv->napi_tx);
c03abd84
FB		 769 return IRQ_HANDLED;
770}
771
772static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
773{
774 struct cpsw_priv *priv = dev_id;
775
776 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
870915fe 777 writel(0, &priv->wr_regs->rx_en);
fd51cf19 778
7da11600
M		 779 if (priv->quirk_irq) {
780 disable_irq_nosync(priv->irqs_table[0]);
781 priv->rx_irq_disabled = true;
782 }
783
32a7432c 784 napi_schedule(&priv->napi_rx);
d354eb85 785 return IRQ_HANDLED;
df828598
M		 786}
787
32a7432c
M		 788static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
789{
790 struct cpsw_priv *priv = napi_to_priv(napi_tx);
791 int num_tx;
792
793 num_tx = cpdma_chan_process(priv->txch, budget);
794 if (num_tx < budget) {
795 napi_complete(napi_tx);
796 writel(0xff, &priv->wr_regs->tx_en);
7da11600
M		 797 if (priv->quirk_irq && priv->tx_irq_disabled) {
798 priv->tx_irq_disabled = false;
799 enable_irq(priv->irqs_table[1]);
800 }
32a7432c
M		 801 }
802
803 if (num_tx)
804 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
805
806 return num_tx;
807}
808
809static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 810{
32a7432c 811 struct cpsw_priv *priv = napi_to_priv(napi_rx);
1e353cdd 812 int num_rx;
df828598 813
510a1e72 814 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 815 if (num_rx < budget) {
32a7432c 816 napi_complete(napi_rx);
870915fe 817 writel(0xff, &priv->wr_regs->rx_en);
7da11600
M		 818 if (priv->quirk_irq && priv->rx_irq_disabled) {
819 priv->rx_irq_disabled = false;
820 enable_irq(priv->irqs_table[0]);
821 }
df828598
M		 822 }
823
1e353cdd
M		 824 if (num_rx)
825 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
510a1e72 826
df828598
M		 827 return num_rx;
828}
829
830static inline void soft_reset(const char *module, void __iomem *reg)
831{
832 unsigned long timeout = jiffies + HZ;
833
834 __raw_writel(1, reg);
835 do {
836 cpu_relax();
837 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
838
839 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
840}
841
842#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
843 ((mac)[2] << 16) | ((mac)[3] << 24))
844#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
845
846static void cpsw_set_slave_mac(struct cpsw_slave *slave,
847 struct cpsw_priv *priv)
848{
9750a3ad
RC		 849 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
850 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 851}
852
853static void _cpsw_adjust_link(struct cpsw_slave *slave,
854 struct cpsw_priv *priv, bool *link)
855{
856 struct phy_device *phy = slave->phy;
857 u32 mac_control = 0;
858 u32 slave_port;
859
860 if (!phy)
861 return;
862
863 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
864
865 if (phy->link) {
866 mac_control = priv->data.mac_control;
867
868 /* enable forwarding */
869 cpsw_ale_control_set(priv->ale, slave_port,
870 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
871
872 if (phy->speed == 1000)
873 mac_control |= BIT(7); /* GIGABITEN */
874 if (phy->duplex)
875 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 876
877 /* set speed_in input in case RMII mode is used in 100Mbps */
878 if (phy->speed == 100)
879 mac_control |= BIT(15);
a81d8762
M		 880 else if (phy->speed == 10)
881 mac_control |= BIT(18); /* In Band mode */
342b7b74 882
1923d6e4
M		 883 if (priv->rx_pause)
884 mac_control |= BIT(3);
885
886 if (priv->tx_pause)
887 mac_control |= BIT(4);
888
df828598
M		 889 *link = true;
890 } else {
891 mac_control = 0;
892 /* disable forwarding */
893 cpsw_ale_control_set(priv->ale, slave_port,
894 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
895 }
896
897 if (mac_control != slave->mac_control) {
898 phy_print_status(phy);
899 __raw_writel(mac_control, &slave->sliver->mac_control);
900 }
901
902 slave->mac_control = mac_control;
903}
904
905static void cpsw_adjust_link(struct net_device *ndev)
906{
907 struct cpsw_priv *priv = netdev_priv(ndev);
908 bool link = false;
909
910 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
911
912 if (link) {
913 netif_carrier_on(ndev);
914 if (netif_running(ndev))
915 netif_wake_queue(ndev);
916 } else {
917 netif_carrier_off(ndev);
918 netif_stop_queue(ndev);
919 }
920}
921
ff5b8ef2
M		 922static int cpsw_get_coalesce(struct net_device *ndev,
923 struct ethtool_coalesce *coal)
924{
925 struct cpsw_priv *priv = netdev_priv(ndev);
926
927 coal->rx_coalesce_usecs = priv->coal_intvl;
928 return 0;
929}
930
931static int cpsw_set_coalesce(struct net_device *ndev,
932 struct ethtool_coalesce *coal)
933{
934 struct cpsw_priv *priv = netdev_priv(ndev);
935 u32 int_ctrl;
936 u32 num_interrupts = 0;
937 u32 prescale = 0;
938 u32 addnl_dvdr = 1;
939 u32 coal_intvl = 0;
940
ff5b8ef2
M		 941 coal_intvl = coal->rx_coalesce_usecs;
942
943 int_ctrl = readl(&priv->wr_regs->int_control);
944 prescale = priv->bus_freq_mhz * 4;
945
a84bc2a9
M		 946 if (!coal->rx_coalesce_usecs) {
947 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
948 goto update_return;
949 }
950
ff5b8ef2
M		 951 if (coal_intvl < CPSW_CMINTMIN_INTVL)
952 coal_intvl = CPSW_CMINTMIN_INTVL;
953
954 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
955 /* Interrupt pacer works with 4us Pulse, we can
956 * throttle further by dilating the 4us pulse.
957 */
958 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
959
960 if (addnl_dvdr > 1) {
961 prescale *= addnl_dvdr;
962 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
963 coal_intvl = (CPSW_CMINTMAX_INTVL
964 * addnl_dvdr);
965 } else {
966 addnl_dvdr = 1;
967 coal_intvl = CPSW_CMINTMAX_INTVL;
968 }
969 }
970
971 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
972 writel(num_interrupts, &priv->wr_regs->rx_imax);
973 writel(num_interrupts, &priv->wr_regs->tx_imax);
974
975 int_ctrl |= CPSW_INTPACEEN;
976 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
977 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 978
979update_return:
ff5b8ef2
M		 980 writel(int_ctrl, &priv->wr_regs->int_control);
981
982 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
983 if (priv->data.dual_emac) {
984 int i;
985
986 for (i = 0; i < priv->data.slaves; i++) {
987 priv = netdev_priv(priv->slaves[i].ndev);
988 priv->coal_intvl = coal_intvl;
989 }
990 } else {
991 priv->coal_intvl = coal_intvl;
992 }
993
994 return 0;
995}
996
d9718546
M		 997static int cpsw_get_sset_count(struct net_device *ndev, int sset)
998{
999 switch (sset) {
1000 case ETH_SS_STATS:
1001 return CPSW_STATS_LEN;
1002 default:
1003 return -EOPNOTSUPP;
1004 }
1005}
1006
1007static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1008{
1009 u8 *p = data;
1010 int i;
1011
1012 switch (stringset) {
1013 case ETH_SS_STATS:
1014 for (i = 0; i < CPSW_STATS_LEN; i++) {
1015 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1016 ETH_GSTRING_LEN);
1017 p += ETH_GSTRING_LEN;
1018 }
1019 break;
1020 }
1021}
1022
1023static void cpsw_get_ethtool_stats(struct net_device *ndev,
1024 struct ethtool_stats *stats, u64 *data)
1025{
1026 struct cpsw_priv *priv = netdev_priv(ndev);
1027 struct cpdma_chan_stats rx_stats;
1028 struct cpdma_chan_stats tx_stats;
1029 u32 val;
1030 u8 *p;
1031 int i;
1032
1033 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1034 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1035 cpdma_chan_get_stats(priv->txch, &tx_stats);
1036
1037 for (i = 0; i < CPSW_STATS_LEN; i++) {
1038 switch (cpsw_gstrings_stats[i].type) {
1039 case CPSW_STATS:
1040 val = readl(priv->hw_stats +
1041 cpsw_gstrings_stats[i].stat_offset);
1042 data[i] = val;
1043 break;
1044
1045 case CPDMA_RX_STATS:
1046 p = (u8 *)&rx_stats +
1047 cpsw_gstrings_stats[i].stat_offset;
1048 data[i] = *(u32 *)p;
1049 break;
1050
1051 case CPDMA_TX_STATS:
1052 p = (u8 *)&tx_stats +
1053 cpsw_gstrings_stats[i].stat_offset;
1054 data[i] = *(u32 *)p;
1055 break;
1056 }
1057 }
1058}
1059
d9ba8f9e
M		 1060static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1061{
1062 u32 i;
1063 u32 usage_count = 0;
1064
1065 if (!priv->data.dual_emac)
1066 return 0;
1067
1068 for (i = 0; i < priv->data.slaves; i++)
1069 if (priv->slaves[i].open_stat)
1070 usage_count++;
1071
1072 return usage_count;
1073}
1074
1075static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1076 struct cpsw_priv *priv, struct sk_buff *skb)
1077{
1078 if (!priv->data.dual_emac)
1079 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1080 skb->len, 0);
d9ba8f9e
M		 1081
1082 if (ndev == cpsw_get_slave_ndev(priv, 0))
1083 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1084 skb->len, 1);
d9ba8f9e
M		 1085 else
1086 return cpdma_chan_submit(priv->txch, skb, skb->data,
aef614e1 1087 skb->len, 2);
d9ba8f9e
M		 1088}
1089
1090static inline void cpsw_add_dual_emac_def_ale_entries(
1091 struct cpsw_priv *priv, struct cpsw_slave *slave,
1092 u32 slave_port)
1093{
1094 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1095
1096 if (priv->version == CPSW_VERSION_1)
1097 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1098 else
1099 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1100 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1101 port_mask, port_mask, 0);
1102 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1103 port_mask, ALE_VLAN, slave->port_vlan, 0);
1104 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
56887149 1105 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1106}
1107
1e7a2e21 1108static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1109{
1110 char name[32];
df828598 1111
1e7a2e21 1112 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1113 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1114}
1115
1116static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1117{
1118 u32 slave_port;
1119
1120 soft_reset_slave(slave);
df828598
M		 1121
1122 /* setup priority mapping */
1123 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 1124
1125 switch (priv->version) {
1126 case CPSW_VERSION_1:
1127 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1128 break;
1129 case CPSW_VERSION_2:
c193f365 1130 case CPSW_VERSION_3:
926489be 1131 case CPSW_VERSION_4:
9750a3ad
RC		 1132 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1133 break;
1134 }
df828598
M		 1135
1136 /* setup max packet size, and mac address */
1137 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1138 cpsw_set_slave_mac(slave, priv);
1139
1140 slave->mac_control = 0; /* no link yet */
1141
1142 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1143
d9ba8f9e
M		 1144 if (priv->data.dual_emac)
1145 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1146 else
1147 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1148 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1149
d733f754 1150 if (slave->data->phy_node) {
552165bc 1151 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
9e42f715 1152 &cpsw_adjust_link, 0, slave->data->phy_if);
d733f754
DR		 1153 if (!slave->phy) {
1154 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1155 slave->data->phy_node->full_name,
1156 slave->slave_num);
1157 return;
1158 }
1159 } else {
9e42f715 1160 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1161 &cpsw_adjust_link, slave->data->phy_if);
d733f754
DR		 1162 if (IS_ERR(slave->phy)) {
1163 dev_err(priv->dev,
1164 "phy \"%s\" not found on slave %d, err %ld\n",
1165 slave->data->phy_id, slave->slave_num,
1166 PTR_ERR(slave->phy));
1167 slave->phy = NULL;
1168 return;
1169 }
1170 }
2220943a 1171
d733f754 1172 phy_attached_info(slave->phy);
388367a5 1173
d733f754
DR		 1174 phy_start(slave->phy);
1175
1176 /* Configure GMII_SEL register */
1177 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
df828598
M		 1178}
1179
3b72c2fe
M		 1180static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1181{
1182 const int vlan = priv->data.default_vlan;
1183 const int port = priv->host_port;
1184 u32 reg;
1185 int i;
1e5c4bc4 1186 int unreg_mcast_mask;
3b72c2fe
M		 1187
1188 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1189 CPSW2_PORT_VLAN;
1190
1191 writel(vlan, &priv->host_port_regs->port_vlan);
1192
0237c110 1193 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1194 slave_write(priv->slaves + i, vlan, reg);
1195
1e5c4bc4
LS		 1196 if (priv->ndev->flags & IFF_ALLMULTI)
1197 unreg_mcast_mask = ALE_ALL_PORTS;
1198 else
1199 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1200
3b72c2fe
M		 1201 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1202 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1e5c4bc4 1203 unreg_mcast_mask << port);
3b72c2fe
M		 1204}
1205
df828598
M		 1206static void cpsw_init_host_port(struct cpsw_priv *priv)
1207{
3b72c2fe 1208 u32 control_reg;
d9ba8f9e 1209 u32 fifo_mode;
3b72c2fe 1210
df828598
M		 1211 /* soft reset the controller and initialize ale */
1212 soft_reset("cpsw", &priv->regs->soft_reset);
1213 cpsw_ale_start(priv->ale);
1214
1215 /* switch to vlan unaware mode */
3b72c2fe
M		 1216 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1217 CPSW_ALE_VLAN_AWARE);
1218 control_reg = readl(&priv->regs->control);
1219 control_reg |= CPSW_VLAN_AWARE;
1220 writel(control_reg, &priv->regs->control);
d9ba8f9e
M		 1221 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1222 CPSW_FIFO_NORMAL_MODE;
1223 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
df828598
M		 1224
1225 /* setup host port priority mapping */
1226 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1227 &priv->host_port_regs->cpdma_tx_pri_map);
1228 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1229
1230 cpsw_ale_control_set(priv->ale, priv->host_port,
1231 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1232
d9ba8f9e
M		 1233 if (!priv->data.dual_emac) {
1234 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1235 0, 0);
1236 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1237 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1238 }
df828598
M		 1239}
1240
aacebbf8
SS		 1241static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1242{
3995d265
SP		 1243 u32 slave_port;
1244
1245 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1246
aacebbf8
SS		 1247 if (!slave->phy)
1248 return;
1249 phy_stop(slave->phy);
1250 phy_disconnect(slave->phy);
1251 slave->phy = NULL;
3995d265
SP		 1252 cpsw_ale_control_set(priv->ale, slave_port,
1253 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
aacebbf8
SS		 1254}
1255
df828598
M		 1256static int cpsw_ndo_open(struct net_device *ndev)
1257{
1258 struct cpsw_priv *priv = netdev_priv(ndev);
1259 int i, ret;
1260 u32 reg;
1261
3fa88c51
GS		 1262 pm_runtime_get_sync(&priv->pdev->dev);
1263
d9ba8f9e
M		 1264 if (!cpsw_common_res_usage_state(priv))
1265 cpsw_intr_disable(priv);
df828598
M		 1266 netif_carrier_off(ndev);
1267
549985ee 1268 reg = priv->version;
df828598
M		 1269
1270 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1271 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1272 CPSW_RTL_VERSION(reg));
1273
1274 /* initialize host and slave ports */
d9ba8f9e
M		 1275 if (!cpsw_common_res_usage_state(priv))
1276 cpsw_init_host_port(priv);
df828598
M		 1277 for_each_slave(priv, cpsw_slave_open, priv);
1278
3b72c2fe 1279 /* Add default VLAN */
e6afea0b
M		 1280 if (!priv->data.dual_emac)
1281 cpsw_add_default_vlan(priv);
1282 else
1283 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1284 ALE_ALL_PORTS << priv->host_port,
1285 ALE_ALL_PORTS << priv->host_port, 0, 0);
3b72c2fe 1286
d9ba8f9e 1287 if (!cpsw_common_res_usage_state(priv)) {
d354eb85
M		 1288 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1289
d9ba8f9e
M		 1290 /* setup tx dma to fixed prio and zero offset */
1291 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1292 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1293
d9ba8f9e
M		 1294 /* disable priority elevation */
1295 __raw_writel(0, &priv->regs->ptype);
df828598 1296
d9ba8f9e
M		 1297 /* enable statistics collection only on all ports */
1298 __raw_writel(0x7, &priv->regs->stat_port_en);
df828598 1299
1923d6e4
M		 1300 /* Enable internal fifo flow control */
1301 writel(0x7, &priv->regs->flow_control);
1302
32a7432c
M		 1303 napi_enable(&priv_sl0->napi_rx);
1304 napi_enable(&priv_sl0->napi_tx);
d354eb85 1305
7da11600
M		 1306 if (priv_sl0->tx_irq_disabled) {
1307 priv_sl0->tx_irq_disabled = false;
1308 enable_irq(priv->irqs_table[1]);
1309 }
1310
1311 if (priv_sl0->rx_irq_disabled) {
1312 priv_sl0->rx_irq_disabled = false;
1313 enable_irq(priv->irqs_table[0]);
1314 }
1315
d9ba8f9e
M		 1316 if (WARN_ON(!priv->data.rx_descs))
1317 priv->data.rx_descs = 128;
df828598 1318
d9ba8f9e
M		 1319 for (i = 0; i < priv->data.rx_descs; i++) {
1320 struct sk_buff *skb;
df828598 1321
d9ba8f9e 1322 ret = -ENOMEM;
aacebbf8
SS		 1323 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1324 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1325 if (!skb)
aacebbf8 1326 goto err_cleanup;
d9ba8f9e 1327 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1328 skb_tailroom(skb), 0);
aacebbf8
SS		 1329 if (ret < 0) {
1330 kfree_skb(skb);
1331 goto err_cleanup;
1332 }
d9ba8f9e
M		 1333 }
1334 /* continue even if we didn't manage to submit all
1335 * receive descs
1336 */
1337 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
f280e89a
M		 1338
1339 if (cpts_register(&priv->pdev->dev, priv->cpts,
1340 priv->data.cpts_clock_mult,
1341 priv->data.cpts_clock_shift))
1342 dev_err(priv->dev, "error registering cpts device\n");
1343
df828598 1344 }
df828598 1345
ff5b8ef2
M		 1346 /* Enable Interrupt pacing if configured */
1347 if (priv->coal_intvl != 0) {
1348 struct ethtool_coalesce coal;
1349
1350 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1351 cpsw_set_coalesce(ndev, &coal);
1352 }
1353
f63a975e
M		 1354 cpdma_ctlr_start(priv->dma);
1355 cpsw_intr_enable(priv);
f63a975e 1356
d9ba8f9e
M		 1357 if (priv->data.dual_emac)
1358 priv->slaves[priv->emac_port].open_stat = true;
df828598 1359 return 0;
df828598 1360
aacebbf8
SS		 1361err_cleanup:
1362 cpdma_ctlr_stop(priv->dma);
1363 for_each_slave(priv, cpsw_slave_stop, priv);
1364 pm_runtime_put_sync(&priv->pdev->dev);
1365 netif_carrier_off(priv->ndev);
1366 return ret;
df828598
M		 1367}
1368
1369static int cpsw_ndo_stop(struct net_device *ndev)
1370{
1371 struct cpsw_priv *priv = netdev_priv(ndev);
1372
1373 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598 1374 netif_stop_queue(priv->ndev);
df828598 1375 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1376
1377 if (cpsw_common_res_usage_state(priv) <= 1) {
d354eb85
M		 1378 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1379
32a7432c
M		 1380 napi_disable(&priv_sl0->napi_rx);
1381 napi_disable(&priv_sl0->napi_tx);
f280e89a 1382 cpts_unregister(priv->cpts);
d9ba8f9e 1383 cpsw_intr_disable(priv);
d9ba8f9e
M		 1384 cpdma_ctlr_stop(priv->dma);
1385 cpsw_ale_stop(priv->ale);
1386 }
df828598 1387 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 1388 pm_runtime_put_sync(&priv->pdev->dev);
d9ba8f9e
M		 1389 if (priv->data.dual_emac)
1390 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1391 return 0;
1392}
1393
1394static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1395 struct net_device *ndev)
1396{
1397 struct cpsw_priv *priv = netdev_priv(ndev);
1398 int ret;
1399
1400 ndev->trans_start = jiffies;
1401
1402 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1403 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1404 ndev->stats.tx_dropped++;
df828598
M		 1405 return NETDEV_TX_OK;
1406 }
1407
9232b16d
M		 1408 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1409 priv->cpts->tx_enable)
2e5b38ab
RC		 1410 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1411
1412 skb_tx_timestamp(skb);
1413
d9ba8f9e 1414 ret = cpsw_tx_packet_submit(ndev, priv, skb);
df828598
M		 1415 if (unlikely(ret != 0)) {
1416 cpsw_err(priv, tx_err, "desc submit failed\n");
1417 goto fail;
1418 }
1419
fae50823
M		 1420 /* If there is no more tx desc left free then we need to
1421 * tell the kernel to stop sending us tx frames.
1422 */
d35162f8 1423 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1424 netif_stop_queue(ndev);
1425
df828598
M		 1426 return NETDEV_TX_OK;
1427fail:
8dc43ddc 1428 ndev->stats.tx_dropped++;
df828598
M		 1429 netif_stop_queue(ndev);
1430 return NETDEV_TX_BUSY;
1431}
1432
2e5b38ab
RC		 1433#ifdef CONFIG_TI_CPTS
1434
1435static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1436{
e86ac13b 1437 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1438 u32 ts_en, seq_id;
1439
9232b16d 1440 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1441 slave_write(slave, 0, CPSW1_TS_CTL);
1442 return;
1443 }
1444
1445 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1446 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1447
9232b16d 1448 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1449 ts_en |= CPSW_V1_TS_TX_EN;
1450
9232b16d 1451 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1452 ts_en |= CPSW_V1_TS_RX_EN;
1453
1454 slave_write(slave, ts_en, CPSW1_TS_CTL);
1455 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1456}
1457
1458static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1459{
d9ba8f9e 1460 struct cpsw_slave *slave;
2e5b38ab
RC		 1461 u32 ctrl, mtype;
1462
d9ba8f9e
M		 1463 if (priv->data.dual_emac)
1464 slave = &priv->slaves[priv->emac_port];
1465 else
e86ac13b 1466 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1467
2e5b38ab 1468 ctrl = slave_read(slave, CPSW2_CONTROL);
09c55372
GC		 1469 switch (priv->version) {
1470 case CPSW_VERSION_2:
1471 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1472
09c55372
GC		 1473 if (priv->cpts->tx_enable)
1474 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1475
09c55372
GC		 1476 if (priv->cpts->rx_enable)
1477 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1478 break;
09c55372
GC		 1479 case CPSW_VERSION_3:
1480 default:
1481 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1482
1483 if (priv->cpts->tx_enable)
1484 ctrl |= CTRL_V3_TX_TS_BITS;
1485
1486 if (priv->cpts->rx_enable)
1487 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1488 break;
09c55372 1489 }
2e5b38ab
RC		 1490
1491 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1492
1493 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1494 slave_write(slave, ctrl, CPSW2_CONTROL);
1495 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1496}
1497
a5b4145b 1498static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1499{
3177bf6f 1500 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1501 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1502 struct hwtstamp_config cfg;
1503
2ee91e54 1504 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1505 priv->version != CPSW_VERSION_2 &&
1506 priv->version != CPSW_VERSION_3)
2ee91e54
BH		 1507 return -EOPNOTSUPP;
1508
2e5b38ab
RC		 1509 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1510 return -EFAULT;
1511
1512 /* reserved for future extensions */
1513 if (cfg.flags)
1514 return -EINVAL;
1515
2ee91e54 1516 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1517 return -ERANGE;
2e5b38ab
RC		 1518
1519 switch (cfg.rx_filter) {
1520 case HWTSTAMP_FILTER_NONE:
1521 cpts->rx_enable = 0;
1522 break;
1523 case HWTSTAMP_FILTER_ALL:
1524 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1525 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1526 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1527 return -ERANGE;
1528 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1529 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1530 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1531 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1532 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1533 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1534 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1535 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1536 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1537 cpts->rx_enable = 1;
1538 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1539 break;
1540 default:
1541 return -ERANGE;
1542 }
1543
2ee91e54
BH		 1544 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1545
2e5b38ab
RC		 1546 switch (priv->version) {
1547 case CPSW_VERSION_1:
1548 cpsw_hwtstamp_v1(priv);
1549 break;
1550 case CPSW_VERSION_2:
f7d403cb 1551 case CPSW_VERSION_3:
2e5b38ab
RC		 1552 cpsw_hwtstamp_v2(priv);
1553 break;
1554 default:
2ee91e54 1555 WARN_ON(1);
2e5b38ab
RC		 1556 }
1557
1558 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1559}
1560
a5b4145b
BH		 1561static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1562{
1563 struct cpsw_priv *priv = netdev_priv(dev);
1564 struct cpts *cpts = priv->cpts;
1565 struct hwtstamp_config cfg;
1566
1567 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1568 priv->version != CPSW_VERSION_2 &&
1569 priv->version != CPSW_VERSION_3)
a5b4145b
BH		 1570 return -EOPNOTSUPP;
1571
1572 cfg.flags = 0;
1573 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1574 cfg.rx_filter = (cpts->rx_enable ?
1575 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1576
1577 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1578}
1579
2e5b38ab
RC		 1580#endif /*CONFIG_TI_CPTS*/
1581
1582static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1583{
11f2c988 1584 struct cpsw_priv *priv = netdev_priv(dev);
11f2c988
M		 1585 int slave_no = cpsw_slave_index(priv);
1586
2e5b38ab
RC		 1587 if (!netif_running(dev))
1588 return -EINVAL;
1589
11f2c988 1590 switch (cmd) {
2e5b38ab 1591#ifdef CONFIG_TI_CPTS
11f2c988 1592 case SIOCSHWTSTAMP:
a5b4145b
BH		 1593 return cpsw_hwtstamp_set(dev, req);
1594 case SIOCGHWTSTAMP:
1595 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1596#endif
11f2c988
M		 1597 }
1598
c1b59947
SS		 1599 if (!priv->slaves[slave_no].phy)
1600 return -EOPNOTSUPP;
1601 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1602}
1603
df828598
M		 1604static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1605{
1606 struct cpsw_priv *priv = netdev_priv(ndev);
1607
1608 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1609 ndev->stats.tx_errors++;
df828598 1610 cpsw_intr_disable(priv);
df828598
M		 1611 cpdma_chan_stop(priv->txch);
1612 cpdma_chan_start(priv->txch);
df828598 1613 cpsw_intr_enable(priv);
df828598
M		 1614}
1615
dcfd8d58
M		 1616static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1617{
1618 struct cpsw_priv *priv = netdev_priv(ndev);
1619 struct sockaddr *addr = (struct sockaddr *)p;
1620 int flags = 0;
1621 u16 vid = 0;
1622
1623 if (!is_valid_ether_addr(addr->sa_data))
1624 return -EADDRNOTAVAIL;
1625
1626 if (priv->data.dual_emac) {
1627 vid = priv->slaves[priv->emac_port].port_vlan;
1628 flags = ALE_VLAN;
1629 }
1630
1631 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1632 flags, vid);
1633 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1634 flags, vid);
1635
1636 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1637 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1638 for_each_slave(priv, cpsw_set_slave_mac, priv);
1639
1640 return 0;
1641}
1642
df828598
M		 1643#ifdef CONFIG_NET_POLL_CONTROLLER
1644static void cpsw_ndo_poll_controller(struct net_device *ndev)
1645{
1646 struct cpsw_priv *priv = netdev_priv(ndev);
1647
1648 cpsw_intr_disable(priv);
92cb13fb
FB		 1649 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1650 cpsw_tx_interrupt(priv->irqs_table[1], priv);
df828598 1651 cpsw_intr_enable(priv);
df828598
M		 1652}
1653#endif
1654
3b72c2fe
M		 1655static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1656 unsigned short vid)
1657{
1658 int ret;
9f6bd8fa
M		 1659 int unreg_mcast_mask = 0;
1660 u32 port_mask;
1e5c4bc4 1661
9f6bd8fa
M		 1662 if (priv->data.dual_emac) {
1663 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1664
9f6bd8fa
M		 1665 if (priv->ndev->flags & IFF_ALLMULTI)
1666 unreg_mcast_mask = port_mask;
1667 } else {
1668 port_mask = ALE_ALL_PORTS;
1669
1670 if (priv->ndev->flags & IFF_ALLMULTI)
1671 unreg_mcast_mask = ALE_ALL_PORTS;
1672 else
1673 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1674 }
3b72c2fe 1675
9f6bd8fa 1676 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1e5c4bc4 1677 unreg_mcast_mask << priv->host_port);
3b72c2fe
M		 1678 if (ret != 0)
1679 return ret;
1680
1681 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1682 priv->host_port, ALE_VLAN, vid);
1683 if (ret != 0)
1684 goto clean_vid;
1685
1686 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
9f6bd8fa 1687 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1688 if (ret != 0)
1689 goto clean_vlan_ucast;
1690 return 0;
1691
1692clean_vlan_ucast:
1693 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1694 priv->host_port, ALE_VLAN, vid);
1695clean_vid:
1696 cpsw_ale_del_vlan(priv->ale, vid, 0);
1697 return ret;
1698}
1699
1700static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1701 __be16 proto, u16 vid)
3b72c2fe
M		 1702{
1703 struct cpsw_priv *priv = netdev_priv(ndev);
1704
1705 if (vid == priv->data.default_vlan)
1706 return 0;
1707
02a54164
M		 1708 if (priv->data.dual_emac) {
1709 /* In dual EMAC, reserved VLAN id should not be used for
1710 * creating VLAN interfaces as this can break the dual
1711 * EMAC port separation
1712 */
1713 int i;
1714
1715 for (i = 0; i < priv->data.slaves; i++) {
1716 if (vid == priv->slaves[i].port_vlan)
1717 return -EINVAL;
1718 }
1719 }
1720
3b72c2fe
M		 1721 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1722 return cpsw_add_vlan_ale_entry(priv, vid);
1723}
1724
1725static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1726 __be16 proto, u16 vid)
3b72c2fe
M		 1727{
1728 struct cpsw_priv *priv = netdev_priv(ndev);
1729 int ret;
1730
1731 if (vid == priv->data.default_vlan)
1732 return 0;
1733
02a54164
M		 1734 if (priv->data.dual_emac) {
1735 int i;
1736
1737 for (i = 0; i < priv->data.slaves; i++) {
1738 if (vid == priv->slaves[i].port_vlan)
1739 return -EINVAL;
1740 }
1741 }
1742
3b72c2fe
M		 1743 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1744 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1745 if (ret != 0)
1746 return ret;
1747
1748 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1749 priv->host_port, ALE_VLAN, vid);
1750 if (ret != 0)
1751 return ret;
1752
1753 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1754 0, ALE_VLAN, vid);
1755}
1756
df828598
M		 1757static const struct net_device_ops cpsw_netdev_ops = {
1758 .ndo_open = cpsw_ndo_open,
1759 .ndo_stop = cpsw_ndo_stop,
1760 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1761 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1762 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1763 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1764 .ndo_change_mtu = eth_change_mtu,
df828598 1765 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1766 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1767#ifdef CONFIG_NET_POLL_CONTROLLER
1768 .ndo_poll_controller = cpsw_ndo_poll_controller,
1769#endif
3b72c2fe
M		 1770 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1771 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1772};
1773
52c4f0ec
M		 1774static int cpsw_get_regs_len(struct net_device *ndev)
1775{
1776 struct cpsw_priv *priv = netdev_priv(ndev);
1777
1778 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1779}
1780
1781static void cpsw_get_regs(struct net_device *ndev,
1782 struct ethtool_regs *regs, void *p)
1783{
1784 struct cpsw_priv *priv = netdev_priv(ndev);
1785 u32 *reg = p;
1786
1787 /* update CPSW IP version */
1788 regs->version = priv->version;
1789
1790 cpsw_ale_dump(priv->ale, reg);
1791}
1792
df828598
M		 1793static void cpsw_get_drvinfo(struct net_device *ndev,
1794 struct ethtool_drvinfo *info)
1795{
1796 struct cpsw_priv *priv = netdev_priv(ndev);
7826d43f 1797
52c4f0ec 1798 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f
JP		 1799 strlcpy(info->version, "1.0", sizeof(info->version));
1800 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
df828598
M		 1801}
1802
1803static u32 cpsw_get_msglevel(struct net_device *ndev)
1804{
1805 struct cpsw_priv *priv = netdev_priv(ndev);
1806 return priv->msg_enable;
1807}
1808
1809static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1810{
1811 struct cpsw_priv *priv = netdev_priv(ndev);
1812 priv->msg_enable = value;
1813}
1814
2e5b38ab
RC		 1815static int cpsw_get_ts_info(struct net_device *ndev,
1816 struct ethtool_ts_info *info)
1817{
1818#ifdef CONFIG_TI_CPTS
1819 struct cpsw_priv *priv = netdev_priv(ndev);
1820
1821 info->so_timestamping =
1822 SOF_TIMESTAMPING_TX_HARDWARE |
1823 SOF_TIMESTAMPING_TX_SOFTWARE |
1824 SOF_TIMESTAMPING_RX_HARDWARE |
1825 SOF_TIMESTAMPING_RX_SOFTWARE |
1826 SOF_TIMESTAMPING_SOFTWARE |
1827 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1828 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1829 info->tx_types =
1830 (1 << HWTSTAMP_TX_OFF) |
1831 (1 << HWTSTAMP_TX_ON);
1832 info->rx_filters =
1833 (1 << HWTSTAMP_FILTER_NONE) |
1834 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1835#else
1836 info->so_timestamping =
1837 SOF_TIMESTAMPING_TX_SOFTWARE |
1838 SOF_TIMESTAMPING_RX_SOFTWARE |
1839 SOF_TIMESTAMPING_SOFTWARE;
1840 info->phc_index = -1;
1841 info->tx_types = 0;
1842 info->rx_filters = 0;
1843#endif
1844 return 0;
1845}
1846
d3bb9c58
M		 1847static int cpsw_get_settings(struct net_device *ndev,
1848 struct ethtool_cmd *ecmd)
1849{
1850 struct cpsw_priv *priv = netdev_priv(ndev);
1851 int slave_no = cpsw_slave_index(priv);
1852
1853 if (priv->slaves[slave_no].phy)
1854 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1855 else
1856 return -EOPNOTSUPP;
1857}
1858
1859static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1860{
1861 struct cpsw_priv *priv = netdev_priv(ndev);
1862 int slave_no = cpsw_slave_index(priv);
1863
1864 if (priv->slaves[slave_no].phy)
1865 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1866 else
1867 return -EOPNOTSUPP;
1868}
1869
d8a64420
MU		 1870static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1871{
1872 struct cpsw_priv *priv = netdev_priv(ndev);
1873 int slave_no = cpsw_slave_index(priv);
1874
1875 wol->supported = 0;
1876 wol->wolopts = 0;
1877
1878 if (priv->slaves[slave_no].phy)
1879 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1880}
1881
1882static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1883{
1884 struct cpsw_priv *priv = netdev_priv(ndev);
1885 int slave_no = cpsw_slave_index(priv);
1886
1887 if (priv->slaves[slave_no].phy)
1888 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1889 else
1890 return -EOPNOTSUPP;
1891}
1892
1923d6e4
M		 1893static void cpsw_get_pauseparam(struct net_device *ndev,
1894 struct ethtool_pauseparam *pause)
1895{
1896 struct cpsw_priv *priv = netdev_priv(ndev);
1897
1898 pause->autoneg = AUTONEG_DISABLE;
1899 pause->rx_pause = priv->rx_pause ? true : false;
1900 pause->tx_pause = priv->tx_pause ? true : false;
1901}
1902
1903static int cpsw_set_pauseparam(struct net_device *ndev,
1904 struct ethtool_pauseparam *pause)
1905{
1906 struct cpsw_priv *priv = netdev_priv(ndev);
1907 bool link;
1908
1909 priv->rx_pause = pause->rx_pause ? true : false;
1910 priv->tx_pause = pause->tx_pause ? true : false;
1911
1912 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1913
1914 return 0;
1915}
1916
df828598
M		 1917static const struct ethtool_ops cpsw_ethtool_ops = {
1918 .get_drvinfo = cpsw_get_drvinfo,
1919 .get_msglevel = cpsw_get_msglevel,
1920 .set_msglevel = cpsw_set_msglevel,
1921 .get_link = ethtool_op_get_link,
2e5b38ab 1922 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1923 .get_settings = cpsw_get_settings,
1924 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1925 .get_coalesce = cpsw_get_coalesce,
1926 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1927 .get_sset_count = cpsw_get_sset_count,
1928 .get_strings = cpsw_get_strings,
1929 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 1930 .get_pauseparam = cpsw_get_pauseparam,
1931 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 1932 .get_wol = cpsw_get_wol,
1933 .set_wol = cpsw_set_wol,
52c4f0ec
M		 1934 .get_regs_len = cpsw_get_regs_len,
1935 .get_regs = cpsw_get_regs,
df828598
M		 1936};
1937
549985ee
RC		 1938static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1939 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1940{
1941 void __iomem *regs = priv->regs;
1942 int slave_num = slave->slave_num;
1943 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1944
1945 slave->data = data;
549985ee
RC		 1946 slave->regs = regs + slave_reg_ofs;
1947 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 1948 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 1949}
1950
552165bc 1951static int cpsw_probe_dt(struct cpsw_platform_data *data,
2eb32b0a
M		 1952 struct platform_device *pdev)
1953{
1954 struct device_node *node = pdev->dev.of_node;
1955 struct device_node *slave_node;
1956 int i = 0, ret;
1957 u32 prop;
1958
1959 if (!node)
1960 return -EINVAL;
1961
1962 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 1963 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 1964 return -EINVAL;
1965 }
1966 data->slaves = prop;
1967
e86ac13b 1968 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 1969 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 1970 return -EINVAL;
78ca0b28 1971 }
e86ac13b 1972 data->active_slave = prop;
78ca0b28 1973
00ab94ee 1974 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 1975 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 1976 return -EINVAL;
00ab94ee
RC		 1977 }
1978 data->cpts_clock_mult = prop;
1979
1980 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 1981 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 1982 return -EINVAL;
00ab94ee
RC		 1983 }
1984 data->cpts_clock_shift = prop;
1985
aa1a15e2
DM		 1986 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1987 * sizeof(struct cpsw_slave_data),
1988 GFP_KERNEL);
b2adaca9 1989 if (!data->slave_data)
aa1a15e2 1990 return -ENOMEM;
2eb32b0a 1991
2eb32b0a 1992 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 1993 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 1994 return -EINVAL;
2eb32b0a
M		 1995 }
1996 data->channels = prop;
1997
2eb32b0a 1998 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 1999 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 2000 return -EINVAL;
2eb32b0a
M		 2001 }
2002 data->ale_entries = prop;
2003
2eb32b0a 2004 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 2005 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 2006 return -EINVAL;
2eb32b0a
M		 2007 }
2008 data->bd_ram_size = prop;
2009
2010 if (of_property_read_u32(node, "rx_descs", &prop)) {
88c99ff6 2011 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
aa1a15e2 2012 return -EINVAL;
2eb32b0a
M		 2013 }
2014 data->rx_descs = prop;
2015
2016 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2017 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2018 return -EINVAL;
2eb32b0a
M		 2019 }
2020 data->mac_control = prop;
2021
281abd96
MP		 2022 if (of_property_read_bool(node, "dual_emac"))
2023 data->dual_emac = 1;
d9ba8f9e 2024
549985ee
RC		 2025 /*
2026 * Populate all the child nodes here...
2027 */
2028 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2029 /* We do not want to force this, as in some cases may not have child */
2030 if (ret)
88c99ff6 2031 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2032
f468b10e 2033 for_each_child_of_node(node, slave_node) {
2eb32b0a 2034 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2035 const void *mac_addr = NULL;
549985ee
RC		 2036 int lenp;
2037 const __be32 *parp;
549985ee 2038
f468b10e
MP		 2039 /* This is no slave child node, continue */
2040 if (strcmp(slave_node->name, "slave"))
2041 continue;
2042
552165bc
DR		 2043 slave_data->phy_node = of_parse_phandle(slave_node,
2044 "phy-handle", 0);
f1eea5c1 2045 parp = of_get_property(slave_node, "phy_id", &lenp);
ae092b5b
DR		 2046 if (slave_data->phy_node) {
2047 dev_dbg(&pdev->dev,
2048 "slave[%d] using phy-handle=\"%s\"\n",
2049 i, slave_data->phy_node->full_name);
2050 } else if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2051 struct device_node *phy_node;
2052 struct phy_device *phy_dev;
1f71e8c9 2053
dfc0a6d3
DR		 2054 /* In the case of a fixed PHY, the DT node associated
2055 * to the PHY is the Ethernet MAC DT node.
2056 */
1f71e8c9
MB		 2057 ret = of_phy_register_fixed_link(slave_node);
2058 if (ret)
2059 return ret;
dfc0a6d3
DR		 2060 phy_node = of_node_get(slave_node);
2061 phy_dev = of_phy_find_device(phy_node);
2062 if (!phy_dev)
1f71e8c9
MB		 2063 return -ENODEV;
2064 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
e5a03bfd
AL		 2065 PHY_ID_FMT, phy_dev->mdio.bus->id,
2066 phy_dev->mdio.addr);
f1eea5c1
DR		 2067 } else if (parp) {
2068 u32 phyid;
2069 struct device_node *mdio_node;
2070 struct platform_device *mdio;
2071
2072 if (lenp != (sizeof(__be32) * 2)) {
2073 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2074 goto no_phy_slave;
2075 }
2076 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2077 phyid = be32_to_cpup(parp+1);
2078 mdio = of_find_device_by_node(mdio_node);
2079 of_node_put(mdio_node);
2080 if (!mdio) {
2081 dev_err(&pdev->dev, "Missing mdio platform device\n");
2082 return -EINVAL;
2083 }
2084 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2085 PHY_ID_FMT, mdio->name, phyid);
2086 } else {
ae092b5b
DR		 2087 dev_err(&pdev->dev,
2088 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2089 i);
47276fcc 2090 goto no_phy_slave;
2eb32b0a 2091 }
47276fcc
M		 2092 slave_data->phy_if = of_get_phy_mode(slave_node);
2093 if (slave_data->phy_if < 0) {
2094 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2095 i);
2096 return slave_data->phy_if;
2097 }
2098
2099no_phy_slave:
2eb32b0a 2100 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2101 if (mac_addr) {
2eb32b0a 2102 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2103 } else {
b6745f6e
M		 2104 ret = ti_cm_get_macid(&pdev->dev, i,
2105 slave_data->mac_addr);
2106 if (ret)
2107 return ret;
0ba517b1 2108 }
d9ba8f9e 2109 if (data->dual_emac) {
91c4166c 2110 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2111 &prop)) {
88c99ff6 2112 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2113 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2114 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2115 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2116 } else {
2117 slave_data->dual_emac_res_vlan = prop;
2118 }
2119 }
2120
2eb32b0a 2121 i++;
3a27bfac
M		 2122 if (i == data->slaves)
2123 break;
2eb32b0a
M		 2124 }
2125
2126 return 0;
2eb32b0a
M		 2127}
2128
d9ba8f9e
M		 2129static int cpsw_probe_dual_emac(struct platform_device *pdev,
2130 struct cpsw_priv *priv)
2131{
2132 struct cpsw_platform_data *data = &priv->data;
2133 struct net_device *ndev;
2134 struct cpsw_priv *priv_sl2;
2135 int ret = 0, i;
2136
2137 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2138 if (!ndev) {
88c99ff6 2139 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2140 return -ENOMEM;
2141 }
2142
2143 priv_sl2 = netdev_priv(ndev);
2144 spin_lock_init(&priv_sl2->lock);
2145 priv_sl2->data = *data;
2146 priv_sl2->pdev = pdev;
2147 priv_sl2->ndev = ndev;
2148 priv_sl2->dev = &ndev->dev;
2149 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2150 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2151
2152 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2153 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2154 ETH_ALEN);
88c99ff6 2155 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2156 } else {
2157 random_ether_addr(priv_sl2->mac_addr);
88c99ff6 2158 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2159 }
2160 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2161
2162 priv_sl2->slaves = priv->slaves;
2163 priv_sl2->clk = priv->clk;
2164
ff5b8ef2
M		 2165 priv_sl2->coal_intvl = 0;
2166 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2167
d9ba8f9e
M		 2168 priv_sl2->regs = priv->regs;
2169 priv_sl2->host_port = priv->host_port;
2170 priv_sl2->host_port_regs = priv->host_port_regs;
2171 priv_sl2->wr_regs = priv->wr_regs;
d9718546 2172 priv_sl2->hw_stats = priv->hw_stats;
d9ba8f9e
M		 2173 priv_sl2->dma = priv->dma;
2174 priv_sl2->txch = priv->txch;
2175 priv_sl2->rxch = priv->rxch;
2176 priv_sl2->ale = priv->ale;
2177 priv_sl2->emac_port = 1;
2178 priv->slaves[1].ndev = ndev;
2179 priv_sl2->cpts = priv->cpts;
2180 priv_sl2->version = priv->version;
2181
2182 for (i = 0; i < priv->num_irqs; i++) {
2183 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2184 priv_sl2->num_irqs = priv->num_irqs;
2185 }
f646968f 2186 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2187
2188 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2189 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2190
2191 /* register the network device */
2192 SET_NETDEV_DEV(ndev, &pdev->dev);
2193 ret = register_netdev(ndev);
2194 if (ret) {
88c99ff6 2195 dev_err(&pdev->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2196 free_netdev(ndev);
2197 ret = -ENODEV;
2198 }
2199
2200 return ret;
2201}
2202
7da11600
M		 2203#define CPSW_QUIRK_IRQ BIT(0)
2204
2205static struct platform_device_id cpsw_devtype[] = {
2206 {
2207 /* keep it for existing comaptibles */
2208 .name = "cpsw",
2209 .driver_data = CPSW_QUIRK_IRQ,
2210 }, {
2211 .name = "am335x-cpsw",
2212 .driver_data = CPSW_QUIRK_IRQ,
2213 }, {
2214 .name = "am4372-cpsw",
2215 .driver_data = 0,
2216 }, {
2217 .name = "dra7-cpsw",
2218 .driver_data = 0,
2219 }, {
2220 /* sentinel */
2221 }
2222};
2223MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2224
2225enum ti_cpsw_type {
2226 CPSW = 0,
2227 AM335X_CPSW,
2228 AM4372_CPSW,
2229 DRA7_CPSW,
2230};
2231
2232static const struct of_device_id cpsw_of_mtable[] = {
2233 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2234 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2235 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2236 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2237 { /* sentinel */ },
2238};
2239MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2240
663e12e6 2241static int cpsw_probe(struct platform_device *pdev)
df828598 2242{
d1bd9acf 2243 struct cpsw_platform_data *data;
df828598
M		 2244 struct net_device *ndev;
2245 struct cpsw_priv *priv;
2246 struct cpdma_params dma_params;
2247 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2248 void __iomem *ss_regs;
2249 struct resource *res, *ss_res;
7da11600 2250 const struct of_device_id *of_id;
1d147ccb 2251 struct gpio_descs *mode;
549985ee 2252 u32 slave_offset, sliver_offset, slave_size;
5087b915
FB		 2253 int ret = 0, i;
2254 int irq;
df828598 2255
df828598
M		 2256 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2257 if (!ndev) {
88c99ff6 2258 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2259 return -ENOMEM;
2260 }
2261
2262 platform_set_drvdata(pdev, ndev);
2263 priv = netdev_priv(ndev);
2264 spin_lock_init(&priv->lock);
df828598
M		 2265 priv->pdev = pdev;
2266 priv->ndev = ndev;
2267 priv->dev = &ndev->dev;
2268 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2269 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 2270 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
ab8e99d2 2271 if (!priv->cpts) {
88c99ff6 2272 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2273 ret = -ENOMEM;
9232b16d
M		 2274 goto clean_ndev_ret;
2275 }
df828598 2276
1d147ccb
M		 2277 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2278 if (IS_ERR(mode)) {
2279 ret = PTR_ERR(mode);
2280 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2281 goto clean_ndev_ret;
2282 }
2283
1fb19aa7
VH		 2284 /*
2285 * This may be required here for child devices.
2286 */
2287 pm_runtime_enable(&pdev->dev);
2288
739683b4
M		 2289 /* Select default pin state */
2290 pinctrl_pm_select_default_state(&pdev->dev);
2291
552165bc 2292 if (cpsw_probe_dt(&priv->data, pdev)) {
88c99ff6 2293 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2294 ret = -ENODEV;
aa1a15e2 2295 goto clean_runtime_disable_ret;
2eb32b0a 2296 }
df637193 2297 data = &priv->data;
2eb32b0a 2298
df828598
M		 2299 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2300 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2301 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2302 } else {
7efd26d0 2303 eth_random_addr(priv->mac_addr);
88c99ff6 2304 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2305 }
2306
2307 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2308
df637193
AG		 2309 priv->slaves = devm_kzalloc(&pdev->dev,
2310 sizeof(struct cpsw_slave) * data->slaves,
2311 GFP_KERNEL);
2312 if (!priv->slaves) {
2313 ret = -ENOMEM;
2314 goto clean_runtime_disable_ret;
2315 }
2316 for (i = 0; i < data->slaves; i++)
2317 priv->slaves[i].slave_num = i;
2318
d9ba8f9e
M		 2319 priv->slaves[0].ndev = ndev;
2320 priv->emac_port = 0;
2321
aa1a15e2 2322 priv->clk = devm_clk_get(&pdev->dev, "fck");
df828598 2323 if (IS_ERR(priv->clk)) {
aa1a15e2 2324 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2325 ret = -ENODEV;
aa1a15e2 2326 goto clean_runtime_disable_ret;
df828598 2327 }
ff5b8ef2
M		 2328 priv->coal_intvl = 0;
2329 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
df828598 2330
aa1a15e2
DM		 2331 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2332 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2333 if (IS_ERR(ss_regs)) {
2334 ret = PTR_ERR(ss_regs);
2335 goto clean_runtime_disable_ret;
df828598 2336 }
549985ee 2337 priv->regs = ss_regs;
549985ee 2338 priv->host_port = HOST_PORT_NUM;
df828598 2339
f280e89a
M		 2340 /* Need to enable clocks with runtime PM api to access module
2341 * registers
2342 */
2343 pm_runtime_get_sync(&pdev->dev);
2344 priv->version = readl(&priv->regs->id_ver);
2345 pm_runtime_put_sync(&pdev->dev);
2346
aa1a15e2
DM		 2347 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2348 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2349 if (IS_ERR(priv->wr_regs)) {
2350 ret = PTR_ERR(priv->wr_regs);
2351 goto clean_runtime_disable_ret;
df828598 2352 }
df828598
M		 2353
2354 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2355 memset(&ale_params, 0, sizeof(ale_params));
2356
2357 switch (priv->version) {
2358 case CPSW_VERSION_1:
2359 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546
M		 2360 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2361 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2362 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2363 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2364 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2365 slave_offset = CPSW1_SLAVE_OFFSET;
2366 slave_size = CPSW1_SLAVE_SIZE;
2367 sliver_offset = CPSW1_SLIVER_OFFSET;
2368 dma_params.desc_mem_phys = 0;
2369 break;
2370 case CPSW_VERSION_2:
c193f365 2371 case CPSW_VERSION_3:
926489be 2372 case CPSW_VERSION_4:
549985ee 2373 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546
M		 2374 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2375 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2376 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2377 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2378 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2379 slave_offset = CPSW2_SLAVE_OFFSET;
2380 slave_size = CPSW2_SLAVE_SIZE;
2381 sliver_offset = CPSW2_SLIVER_OFFSET;
2382 dma_params.desc_mem_phys =
aa1a15e2 2383 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2384 break;
2385 default:
2386 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2387 ret = -ENODEV;
aa1a15e2 2388 goto clean_runtime_disable_ret;
549985ee
RC		 2389 }
2390 for (i = 0; i < priv->data.slaves; i++) {
2391 struct cpsw_slave *slave = &priv->slaves[i];
2392 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2393 slave_offset += slave_size;
2394 sliver_offset += SLIVER_SIZE;
2395 }
2396
df828598 2397 dma_params.dev = &pdev->dev;
549985ee
RC		 2398 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2399 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2400 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2401 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2402 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2403
2404 dma_params.num_chan = data->channels;
2405 dma_params.has_soft_reset = true;
2406 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2407 dma_params.desc_mem_size = data->bd_ram_size;
2408 dma_params.desc_align = 16;
2409 dma_params.has_ext_regs = true;
549985ee 2410 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2411
2412 priv->dma = cpdma_ctlr_create(&dma_params);
2413 if (!priv->dma) {
2414 dev_err(priv->dev, "error initializing dma\n");
2415 ret = -ENOMEM;
aa1a15e2 2416 goto clean_runtime_disable_ret;
df828598
M		 2417 }
2418
2419 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2420 cpsw_tx_handler);
2421 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2422 cpsw_rx_handler);
2423
2424 if (WARN_ON(!priv->txch || !priv->rxch)) {
2425 dev_err(priv->dev, "error initializing dma channels\n");
2426 ret = -ENOMEM;
2427 goto clean_dma_ret;
2428 }
2429
df828598 2430 ale_params.dev = &ndev->dev;
df828598
M		 2431 ale_params.ale_ageout = ale_ageout;
2432 ale_params.ale_entries = data->ale_entries;
2433 ale_params.ale_ports = data->slaves;
2434
2435 priv->ale = cpsw_ale_create(&ale_params);
2436 if (!priv->ale) {
2437 dev_err(priv->dev, "error initializing ale engine\n");
2438 ret = -ENODEV;
2439 goto clean_dma_ret;
2440 }
2441
c03abd84 2442 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 2443 if (ndev->irq < 0) {
2444 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 2445 ret = ndev->irq;
df828598
M		 2446 goto clean_ale_ret;
2447 }
2448
7da11600
M		 2449 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2450 if (of_id) {
2451 pdev->id_entry = of_id->data;
2452 if (pdev->id_entry->driver_data)
2453 priv->quirk_irq = true;
2454 }
2455
c03abd84
FB		 2456 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2457 * MISC IRQs which are always kept disabled with this driver so
2458 * we will not request them.
2459 *
2460 * If anyone wants to implement support for those, make sure to
2461 * first request and append them to irqs_table array.
2462 */
c2b32e58 2463
c03abd84 2464 /* RX IRQ */
5087b915 2465 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 2466 if (irq < 0) {
2467 ret = irq;
5087b915 2468 goto clean_ale_ret;
c1e3334f 2469 }
5087b915 2470
c03abd84
FB		 2471 priv->irqs_table[0] = irq;
2472 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
5087b915
FB		 2473 0, dev_name(&pdev->dev), priv);
2474 if (ret < 0) {
2475 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2476 goto clean_ale_ret;
2477 }
2478
c03abd84 2479 /* TX IRQ */
5087b915 2480 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 2481 if (irq < 0) {
2482 ret = irq;
5087b915 2483 goto clean_ale_ret;
c1e3334f 2484 }
5087b915 2485
c03abd84
FB		 2486 priv->irqs_table[1] = irq;
2487 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
5087b915
FB		 2488 0, dev_name(&pdev->dev), priv);
2489 if (ret < 0) {
2490 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2491 goto clean_ale_ret;
df828598 2492 }
c03abd84 2493 priv->num_irqs = 2;
c2b32e58 2494
f646968f 2495 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2496
2497 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2498 ndev->ethtool_ops = &cpsw_ethtool_ops;
32a7432c 2499 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
d64b5e85 2500 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
df828598
M		 2501
2502 /* register the network device */
2503 SET_NETDEV_DEV(ndev, &pdev->dev);
2504 ret = register_netdev(ndev);
2505 if (ret) {
2506 dev_err(priv->dev, "error registering net device\n");
2507 ret = -ENODEV;
aa1a15e2 2508 goto clean_ale_ret;
df828598
M		 2509 }
2510
1a3b5056
OJ		 2511 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2512 &ss_res->start, ndev->irq);
df828598 2513
d9ba8f9e
M		 2514 if (priv->data.dual_emac) {
2515 ret = cpsw_probe_dual_emac(pdev, priv);
2516 if (ret) {
2517 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2518 goto clean_ale_ret;
d9ba8f9e
M		 2519 }
2520 }
2521
df828598
M		 2522 return 0;
2523
df828598
M		 2524clean_ale_ret:
2525 cpsw_ale_destroy(priv->ale);
2526clean_dma_ret:
2527 cpdma_chan_destroy(priv->txch);
2528 cpdma_chan_destroy(priv->rxch);
2529 cpdma_ctlr_destroy(priv->dma);
aa1a15e2 2530clean_runtime_disable_ret:
f150bd7f 2531 pm_runtime_disable(&pdev->dev);
df828598 2532clean_ndev_ret:
d1bd9acf 2533 free_netdev(priv->ndev);
df828598
M		 2534 return ret;
2535}
2536
030b16a0
M		 2537static int cpsw_remove_child_device(struct device *dev, void *c)
2538{
2539 struct platform_device *pdev = to_platform_device(dev);
2540
2541 of_device_unregister(pdev);
2542
2543 return 0;
2544}
2545
663e12e6 2546static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2547{
2548 struct net_device *ndev = platform_get_drvdata(pdev);
2549 struct cpsw_priv *priv = netdev_priv(ndev);
2550
d1bd9acf
SS		 2551 if (priv->data.dual_emac)
2552 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2553 unregister_netdev(ndev);
df828598 2554
df828598
M		 2555 cpsw_ale_destroy(priv->ale);
2556 cpdma_chan_destroy(priv->txch);
2557 cpdma_chan_destroy(priv->rxch);
2558 cpdma_ctlr_destroy(priv->dma);
f150bd7f 2559 pm_runtime_disable(&pdev->dev);
030b16a0 2560 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
d1bd9acf
SS		 2561 if (priv->data.dual_emac)
2562 free_netdev(cpsw_get_slave_ndev(priv, 1));
df828598 2563 free_netdev(ndev);
df828598
M		 2564 return 0;
2565}
2566
8963a504 2567#ifdef CONFIG_PM_SLEEP
df828598
M		 2568static int cpsw_suspend(struct device *dev)
2569{
2570 struct platform_device *pdev = to_platform_device(dev);
2571 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2572 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2573
618073e3
M		 2574 if (priv->data.dual_emac) {
2575 int i;
1e7a2e21 2576
618073e3
M		 2577 for (i = 0; i < priv->data.slaves; i++) {
2578 if (netif_running(priv->slaves[i].ndev))
2579 cpsw_ndo_stop(priv->slaves[i].ndev);
2580 soft_reset_slave(priv->slaves + i);
2581 }
2582 } else {
2583 if (netif_running(ndev))
2584 cpsw_ndo_stop(ndev);
2585 for_each_slave(priv, soft_reset_slave);
2586 }
1e7a2e21 2587
f150bd7f
M		 2588 pm_runtime_put_sync(&pdev->dev);
2589
739683b4
M		 2590 /* Select sleep pin state */
2591 pinctrl_pm_select_sleep_state(&pdev->dev);
2592
df828598
M		 2593 return 0;
2594}
2595
2596static int cpsw_resume(struct device *dev)
2597{
2598 struct platform_device *pdev = to_platform_device(dev);
2599 struct net_device *ndev = platform_get_drvdata(pdev);
618073e3 2600 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2601
f150bd7f 2602 pm_runtime_get_sync(&pdev->dev);
739683b4
M		 2603
2604 /* Select default pin state */
2605 pinctrl_pm_select_default_state(&pdev->dev);
2606
618073e3
M		 2607 if (priv->data.dual_emac) {
2608 int i;
2609
2610 for (i = 0; i < priv->data.slaves; i++) {
2611 if (netif_running(priv->slaves[i].ndev))
2612 cpsw_ndo_open(priv->slaves[i].ndev);
2613 }
2614 } else {
2615 if (netif_running(ndev))
2616 cpsw_ndo_open(ndev);
2617 }
df828598
M		 2618 return 0;
2619}
8963a504 2620#endif
df828598 2621
8963a504 2622static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 2623
2624static struct platform_driver cpsw_driver = {
2625 .driver = {
2626 .name = "cpsw",
df828598 2627 .pm = &cpsw_pm_ops,
1e5c76d4 2628 .of_match_table = cpsw_of_mtable,
df828598
M		 2629 },
2630 .probe = cpsw_probe,
663e12e6 2631 .remove = cpsw_remove,
df828598
M		 2632};
2633
6fb3b6b5 2634module_platform_driver(cpsw_driver);
df828598
M		 2635
2636MODULE_LICENSE("GPL");
2637MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2638MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2639MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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