[deliverable/linux.git] / drivers / net / fec.h

/****************************************************************************/

/*
 *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
 *		   processors.
 *
 *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
 *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
 */

/****************************************************************************/
#ifndef FEC_H
#define	FEC_H
/****************************************************************************/

#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
    defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
/*
 *	Just figures, Motorola would have to change the offsets for
 *	registers in the same peripheral device on different models
 *	of the ColdFire!
 */
#define FEC_IEVENT		0x004 /* Interrupt event reg */
#define FEC_IMASK		0x008 /* Interrupt mask reg */
#define FEC_R_DES_ACTIVE	0x010 /* Receive descriptor reg */
#define FEC_X_DES_ACTIVE	0x014 /* Transmit descriptor reg */
#define FEC_ECNTRL		0x024 /* Ethernet control reg */
#define FEC_MII_DATA		0x040 /* MII manage frame reg */
#define FEC_MII_SPEED		0x044 /* MII speed control reg */
#define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
#define FEC_R_CNTRL		0x084 /* Receive control reg */
#define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
#define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
#define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
#define FEC_OPD			0x0ec /* Opcode + Pause duration */
#define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
#define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
#define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
#define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
#define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
#define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
#define FEC_R_FSTART		0x150 /* FIFO receive start reg */
#define FEC_R_DES_START		0x180 /* Receive descriptor ring */
#define FEC_X_DES_START		0x184 /* Transmit descriptor ring */
#define FEC_R_BUFF_SIZE		0x188 /* Maximum receive buff size */
#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
#define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */

#else

#define FEC_ECNTRL		0x000 /* Ethernet control reg */
#define FEC_IEVENT		0x004 /* Interrupt even reg */
#define FEC_IMASK		0x008 /* Interrupt mask reg */
#define FEC_IVEC		0x00c /* Interrupt vec status reg */
#define FEC_R_DES_ACTIVE	0x010 /* Receive descriptor reg */
#define FEC_X_DES_ACTIVE	0x014 /* Transmit descriptor reg */
#define FEC_MII_DATA		0x040 /* MII manage frame reg */
#define FEC_MII_SPEED		0x044 /* MII speed control reg */
#define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
#define FEC_R_FSTART		0x090 /* FIFO receive start reg */
#define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
#define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
#define FEC_R_CNTRL		0x104 /* Receive control reg */
#define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
#define FEC_X_CNTRL		0x144 /* Transmit Control reg */
#define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
#define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
#define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
#define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
#define FEC_R_DES_START		0x3d0 /* Receive descriptor ring */
#define FEC_X_DES_START		0x3d4 /* Transmit descriptor ring */
#define FEC_R_BUFF_SIZE		0x3d8 /* Maximum receive buff size */
#define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */

#endif /* CONFIG_M5272 */


/*
 *	Define the buffer descriptor structure.
 */
#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
struct bufdesc {
	unsigned short cbd_datlen;	/* Data length */
	unsigned short cbd_sc;	/* Control and status info */
	unsigned long cbd_bufaddr;	/* Buffer address */
};
#else
struct bufdesc {
	unsigned short	cbd_sc;			/* Control and status info */
	unsigned short	cbd_datlen;		/* Data length */
	unsigned long	cbd_bufaddr;		/* Buffer address */
};
#endif

/*
 *	The following definitions courtesy of commproc.h, which where
 *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
 */
#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
#define BD_SC_CM        ((ushort)0x0200)        /* Continuous mode */
#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
#define BD_SC_CD        ((ushort)0x0001)        /* ?? */

/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
#define BD_ENET_RX_WRAP         ((ushort)0x2000)
#define BD_ENET_RX_INTR         ((ushort)0x1000)
#define BD_ENET_RX_LAST         ((ushort)0x0800)
#define BD_ENET_RX_FIRST        ((ushort)0x0400)
#define BD_ENET_RX_MISS         ((ushort)0x0100)
#define BD_ENET_RX_LG           ((ushort)0x0020)
#define BD_ENET_RX_NO           ((ushort)0x0010)
#define BD_ENET_RX_SH           ((ushort)0x0008)
#define BD_ENET_RX_CR           ((ushort)0x0004)
#define BD_ENET_RX_OV           ((ushort)0x0002)
#define BD_ENET_RX_CL           ((ushort)0x0001)
#define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */

/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY        ((ushort)0x8000)
#define BD_ENET_TX_PAD          ((ushort)0x4000)
#define BD_ENET_TX_WRAP         ((ushort)0x2000)
#define BD_ENET_TX_INTR         ((ushort)0x1000)
#define BD_ENET_TX_LAST         ((ushort)0x0800)
#define BD_ENET_TX_TC           ((ushort)0x0400)
#define BD_ENET_TX_DEF          ((ushort)0x0200)
#define BD_ENET_TX_HB           ((ushort)0x0100)
#define BD_ENET_TX_LC           ((ushort)0x0080)
#define BD_ENET_TX_RL           ((ushort)0x0040)
#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
#define BD_ENET_TX_UN           ((ushort)0x0002)
#define BD_ENET_TX_CSL          ((ushort)0x0001)
#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */


/****************************************************************************/
#endif /* FEC_H */
Commit	Line	Data
1da177e4 LT	1	/****************************************************************************/
	2
	3	/*
7a77d918 GU	4	* fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
7a77d918 GU	5	* processors.
1da177e4	6	*
7a77d918	7	* (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
1da177e4 LT	8	* (C) Copyright 2000-2001, Lineo (www.lineo.com)
	9	*/
	10
	11	/****************************************************************************/
	12	#ifndef FEC_H
	13	#define FEC_H
	14	/****************************************************************************/
	15
7a77d918	16	#if defined(CONFIG_M523x) \|\| defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
b5680e0b SG	17	defined(CONFIG_M520x) \|\| defined(CONFIG_M532x) \|\| \
b5680e0b SG	18	defined(CONFIG_ARCH_MXC) \|\| defined(CONFIG_SOC_IMX28)
1da177e4 LT	19	/*
	20	* Just figures, Motorola would have to change the offsets for
	21	* registers in the same peripheral device on different models
	22	* of the ColdFire!
	23	*/
f44d6305 SH	24	#define FEC_IEVENT 0x004 /* Interrupt event reg */
	25	#define FEC_IMASK 0x008 /* Interrupt mask reg */
	26	#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
	27	#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
	28	#define FEC_ECNTRL 0x024 /* Ethernet control reg */
	29	#define FEC_MII_DATA 0x040 /* MII manage frame reg */
	30	#define FEC_MII_SPEED 0x044 /* MII speed control reg */
	31	#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
	32	#define FEC_R_CNTRL 0x084 /* Receive control reg */
	33	#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
	34	#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
	35	#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
	36	#define FEC_OPD 0x0ec /* Opcode + Pause duration */
	37	#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
	38	#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
	39	#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
	40	#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
	41	#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
	42	#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
	43	#define FEC_R_FSTART 0x150 /* FIFO receive start reg */
	44	#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
	45	#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
	46	#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
5eb32bd0 BS	47	#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
5eb32bd0 BS	48	#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
1da177e4 LT	49
	50	#else
	51
9ff1a91c GU	52	#define FEC_ECNTRL 0x000 /* Ethernet control reg */
	53	#define FEC_IEVENT 0x004 /* Interrupt even reg */
	54	#define FEC_IMASK 0x008 /* Interrupt mask reg */
	55	#define FEC_IVEC 0x00c /* Interrupt vec status reg */
	56	#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
5ca1ea23	57	#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
f44d6305 SH	58	#define FEC_MII_DATA 0x040 /* MII manage frame reg */
	59	#define FEC_MII_SPEED 0x044 /* MII speed control reg */
	60	#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
	61	#define FEC_R_FSTART 0x090 /* FIFO receive start reg */
	62	#define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
	63	#define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
	64	#define FEC_R_CNTRL 0x104 /* Receive control reg */
	65	#define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
	66	#define FEC_X_CNTRL 0x144 /* Transmit Control reg */
	67	#define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
	68	#define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
	69	#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
	70	#define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
	71	#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */
	72	#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */
	73	#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */
	74	#define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
1da177e4 LT	75
	76	#endif /* CONFIG_M5272 */
	77
	78
	79	/*
	80	* Define the buffer descriptor structure.
	81	*/
b5680e0b	82	#if defined(CONFIG_ARCH_MXC) \|\| defined(CONFIG_SOC_IMX28)
2e28532f	83	struct bufdesc {
196719ec SH	84	unsigned short cbd_datlen; /* Data length */
	85	unsigned short cbd_sc; /* Control and status info */
	86	unsigned long cbd_bufaddr; /* Buffer address */
2e28532f	87	};
196719ec	88	#else
2e28532f	89	struct bufdesc {
1da177e4 LT	90	unsigned short cbd_sc; /* Control and status info */
	91	unsigned short cbd_datlen; /* Data length */
	92	unsigned long cbd_bufaddr; /* Buffer address */
2e28532f	93	};
196719ec	94	#endif
1da177e4 LT	95
	96	/*
	97	* The following definitions courtesy of commproc.h, which where
	98	* Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
	99	*/
25985edc	100	#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
1da177e4 LT	101	#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
	102	#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
	103	#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
25985edc	104	#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
1da177e4 LT	105	#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
	106	#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
	107	#define BD_SC_BR ((ushort)0x0020) /* Break received */
	108	#define BD_SC_FR ((ushort)0x0010) /* Framing error */
	109	#define BD_SC_PR ((ushort)0x0008) /* Parity error */
	110	#define BD_SC_OV ((ushort)0x0002) /* Overrun */
	111	#define BD_SC_CD ((ushort)0x0001) /* ?? */
	112
	113	/* Buffer descriptor control/status used by Ethernet receive.
	114	*/
	115	#define BD_ENET_RX_EMPTY ((ushort)0x8000)
	116	#define BD_ENET_RX_WRAP ((ushort)0x2000)
	117	#define BD_ENET_RX_INTR ((ushort)0x1000)
	118	#define BD_ENET_RX_LAST ((ushort)0x0800)
	119	#define BD_ENET_RX_FIRST ((ushort)0x0400)
	120	#define BD_ENET_RX_MISS ((ushort)0x0100)
	121	#define BD_ENET_RX_LG ((ushort)0x0020)
	122	#define BD_ENET_RX_NO ((ushort)0x0010)
	123	#define BD_ENET_RX_SH ((ushort)0x0008)
	124	#define BD_ENET_RX_CR ((ushort)0x0004)
	125	#define BD_ENET_RX_OV ((ushort)0x0002)
	126	#define BD_ENET_RX_CL ((ushort)0x0001)
	127	#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
	128
	129	/* Buffer descriptor control/status used by Ethernet transmit.
	130	*/
	131	#define BD_ENET_TX_READY ((ushort)0x8000)
	132	#define BD_ENET_TX_PAD ((ushort)0x4000)
	133	#define BD_ENET_TX_WRAP ((ushort)0x2000)
	134	#define BD_ENET_TX_INTR ((ushort)0x1000)
	135	#define BD_ENET_TX_LAST ((ushort)0x0800)
	136	#define BD_ENET_TX_TC ((ushort)0x0400)
	137	#define BD_ENET_TX_DEF ((ushort)0x0200)
	138	#define BD_ENET_TX_HB ((ushort)0x0100)
	139	#define BD_ENET_TX_LC ((ushort)0x0080)
	140	#define BD_ENET_TX_RL ((ushort)0x0040)
	141	#define BD_ENET_TX_RCMASK ((ushort)0x003c)
	142	#define BD_ENET_TX_UN ((ushort)0x0002)
	143	#define BD_ENET_TX_CSL ((ushort)0x0001)
	144	#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
	145
	146
	147	/****************************************************************************/
	148	#endif /* FEC_H */