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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* e1000_82575 | |
29 | * e1000_82576 | |
30 | */ | |
31 | ||
32 | #include <linux/types.h> | |
33 | #include <linux/slab.h> | |
2d064c06 | 34 | #include <linux/if_ether.h> |
9d5c8243 AK |
35 | |
36 | #include "e1000_mac.h" | |
37 | #include "e1000_82575.h" | |
38 | ||
39 | static s32 igb_get_invariants_82575(struct e1000_hw *); | |
40 | static s32 igb_acquire_phy_82575(struct e1000_hw *); | |
41 | static void igb_release_phy_82575(struct e1000_hw *); | |
42 | static s32 igb_acquire_nvm_82575(struct e1000_hw *); | |
43 | static void igb_release_nvm_82575(struct e1000_hw *); | |
44 | static s32 igb_check_for_link_82575(struct e1000_hw *); | |
45 | static s32 igb_get_cfg_done_82575(struct e1000_hw *); | |
46 | static s32 igb_init_hw_82575(struct e1000_hw *); | |
47 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); | |
48 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); | |
9d5c8243 AK |
49 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
50 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); | |
51 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); | |
52 | static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *); | |
53 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); | |
54 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); | |
55 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); | |
f3e7841c | 56 | static void igb_configure_pcs_link_82575(struct e1000_hw *); |
9d5c8243 AK |
57 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
58 | u16 *); | |
59 | static s32 igb_get_phy_id_82575(struct e1000_hw *); | |
60 | static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); | |
61 | static bool igb_sgmii_active_82575(struct e1000_hw *); | |
62 | static s32 igb_reset_init_script_82575(struct e1000_hw *); | |
63 | static s32 igb_read_mac_addr_82575(struct e1000_hw *); | |
009bc06e | 64 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); |
9d5c8243 | 65 | |
9d5c8243 AK |
66 | static s32 igb_get_invariants_82575(struct e1000_hw *hw) |
67 | { | |
68 | struct e1000_phy_info *phy = &hw->phy; | |
69 | struct e1000_nvm_info *nvm = &hw->nvm; | |
70 | struct e1000_mac_info *mac = &hw->mac; | |
c1889bfe | 71 | struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; |
9d5c8243 AK |
72 | u32 eecd; |
73 | s32 ret_val; | |
74 | u16 size; | |
75 | u32 ctrl_ext = 0; | |
76 | ||
77 | switch (hw->device_id) { | |
78 | case E1000_DEV_ID_82575EB_COPPER: | |
79 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
80 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
81 | mac->type = e1000_82575; | |
82 | break; | |
2d064c06 | 83 | case E1000_DEV_ID_82576: |
9eb2341d | 84 | case E1000_DEV_ID_82576_NS: |
2d064c06 AD |
85 | case E1000_DEV_ID_82576_FIBER: |
86 | case E1000_DEV_ID_82576_SERDES: | |
c8ea5ea9 | 87 | case E1000_DEV_ID_82576_QUAD_COPPER: |
4703bf73 | 88 | case E1000_DEV_ID_82576_SERDES_QUAD: |
2d064c06 AD |
89 | mac->type = e1000_82576; |
90 | break; | |
9d5c8243 AK |
91 | default: |
92 | return -E1000_ERR_MAC_INIT; | |
93 | break; | |
94 | } | |
95 | ||
9d5c8243 AK |
96 | /* Set media type */ |
97 | /* | |
98 | * The 82575 uses bits 22:23 for link mode. The mode can be changed | |
99 | * based on the EEPROM. We cannot rely upon device ID. There | |
100 | * is no distinguishable difference between fiber and internal | |
101 | * SerDes mode on the 82575. There can be an external PHY attached | |
102 | * on the SGMII interface. For this, we'll set sgmii_active to true. | |
103 | */ | |
104 | phy->media_type = e1000_media_type_copper; | |
105 | dev_spec->sgmii_active = false; | |
106 | ||
107 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
108 | if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == | |
109 | E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { | |
110 | hw->phy.media_type = e1000_media_type_internal_serdes; | |
111 | ctrl_ext |= E1000_CTRL_I2C_ENA; | |
112 | } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { | |
113 | dev_spec->sgmii_active = true; | |
114 | ctrl_ext |= E1000_CTRL_I2C_ENA; | |
115 | } else { | |
116 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; | |
117 | } | |
118 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
119 | ||
120 | /* Set mta register count */ | |
121 | mac->mta_reg_count = 128; | |
122 | /* Set rar entry count */ | |
123 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; | |
2d064c06 AD |
124 | if (mac->type == e1000_82576) |
125 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; | |
9d5c8243 AK |
126 | /* Set if part includes ASF firmware */ |
127 | mac->asf_firmware_present = true; | |
128 | /* Set if manageability features are enabled. */ | |
129 | mac->arc_subsystem_valid = | |
130 | (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) | |
131 | ? true : false; | |
132 | ||
133 | /* physical interface link setup */ | |
134 | mac->ops.setup_physical_interface = | |
135 | (hw->phy.media_type == e1000_media_type_copper) | |
136 | ? igb_setup_copper_link_82575 | |
137 | : igb_setup_fiber_serdes_link_82575; | |
138 | ||
139 | /* NVM initialization */ | |
140 | eecd = rd32(E1000_EECD); | |
141 | ||
142 | nvm->opcode_bits = 8; | |
143 | nvm->delay_usec = 1; | |
144 | switch (nvm->override) { | |
145 | case e1000_nvm_override_spi_large: | |
146 | nvm->page_size = 32; | |
147 | nvm->address_bits = 16; | |
148 | break; | |
149 | case e1000_nvm_override_spi_small: | |
150 | nvm->page_size = 8; | |
151 | nvm->address_bits = 8; | |
152 | break; | |
153 | default: | |
154 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
155 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
156 | break; | |
157 | } | |
158 | ||
159 | nvm->type = e1000_nvm_eeprom_spi; | |
160 | ||
161 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
162 | E1000_EECD_SIZE_EX_SHIFT); | |
163 | ||
164 | /* | |
165 | * Added to a constant, "size" becomes the left-shift value | |
166 | * for setting word_size. | |
167 | */ | |
168 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
5c3cad75 JK |
169 | |
170 | /* EEPROM access above 16k is unsupported */ | |
171 | if (size > 14) | |
172 | size = 14; | |
9d5c8243 AK |
173 | nvm->word_size = 1 << size; |
174 | ||
175 | /* setup PHY parameters */ | |
176 | if (phy->media_type != e1000_media_type_copper) { | |
177 | phy->type = e1000_phy_none; | |
178 | return 0; | |
179 | } | |
180 | ||
181 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
182 | phy->reset_delay_us = 100; | |
183 | ||
184 | /* PHY function pointers */ | |
185 | if (igb_sgmii_active_82575(hw)) { | |
a8d2a0c2 AD |
186 | phy->ops.reset = igb_phy_hw_reset_sgmii_82575; |
187 | phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; | |
188 | phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; | |
9d5c8243 | 189 | } else { |
a8d2a0c2 AD |
190 | phy->ops.reset = igb_phy_hw_reset; |
191 | phy->ops.read_reg = igb_read_phy_reg_igp; | |
192 | phy->ops.write_reg = igb_write_phy_reg_igp; | |
9d5c8243 AK |
193 | } |
194 | ||
19e588e7 AD |
195 | /* set lan id */ |
196 | hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> | |
197 | E1000_STATUS_FUNC_SHIFT; | |
198 | ||
9d5c8243 AK |
199 | /* Set phy->phy_addr and phy->id. */ |
200 | ret_val = igb_get_phy_id_82575(hw); | |
201 | if (ret_val) | |
202 | return ret_val; | |
203 | ||
204 | /* Verify phy id and set remaining function pointers */ | |
205 | switch (phy->id) { | |
206 | case M88E1111_I_PHY_ID: | |
207 | phy->type = e1000_phy_m88; | |
208 | phy->ops.get_phy_info = igb_get_phy_info_m88; | |
209 | phy->ops.get_cable_length = igb_get_cable_length_m88; | |
210 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; | |
211 | break; | |
212 | case IGP03E1000_E_PHY_ID: | |
213 | phy->type = e1000_phy_igp_3; | |
214 | phy->ops.get_phy_info = igb_get_phy_info_igp; | |
215 | phy->ops.get_cable_length = igb_get_cable_length_igp_2; | |
216 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; | |
217 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; | |
218 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; | |
219 | break; | |
220 | default: | |
221 | return -E1000_ERR_PHY; | |
222 | } | |
223 | ||
4ae196df AD |
224 | /* if 82576 then initialize mailbox parameters */ |
225 | if (mac->type == e1000_82576) | |
226 | igb_init_mbx_params_pf(hw); | |
227 | ||
9d5c8243 AK |
228 | return 0; |
229 | } | |
230 | ||
231 | /** | |
733596be | 232 | * igb_acquire_phy_82575 - Acquire rights to access PHY |
9d5c8243 AK |
233 | * @hw: pointer to the HW structure |
234 | * | |
235 | * Acquire access rights to the correct PHY. This is a | |
236 | * function pointer entry point called by the api module. | |
237 | **/ | |
238 | static s32 igb_acquire_phy_82575(struct e1000_hw *hw) | |
239 | { | |
240 | u16 mask; | |
241 | ||
242 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
243 | ||
244 | return igb_acquire_swfw_sync_82575(hw, mask); | |
245 | } | |
246 | ||
247 | /** | |
733596be | 248 | * igb_release_phy_82575 - Release rights to access PHY |
9d5c8243 AK |
249 | * @hw: pointer to the HW structure |
250 | * | |
251 | * A wrapper to release access rights to the correct PHY. This is a | |
252 | * function pointer entry point called by the api module. | |
253 | **/ | |
254 | static void igb_release_phy_82575(struct e1000_hw *hw) | |
255 | { | |
256 | u16 mask; | |
257 | ||
258 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
259 | igb_release_swfw_sync_82575(hw, mask); | |
260 | } | |
261 | ||
262 | /** | |
733596be | 263 | * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii |
9d5c8243 AK |
264 | * @hw: pointer to the HW structure |
265 | * @offset: register offset to be read | |
266 | * @data: pointer to the read data | |
267 | * | |
268 | * Reads the PHY register at offset using the serial gigabit media independent | |
269 | * interface and stores the retrieved information in data. | |
270 | **/ | |
271 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
272 | u16 *data) | |
273 | { | |
274 | struct e1000_phy_info *phy = &hw->phy; | |
275 | u32 i, i2ccmd = 0; | |
276 | ||
277 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 278 | hw_dbg("PHY Address %u is out of range\n", offset); |
9d5c8243 AK |
279 | return -E1000_ERR_PARAM; |
280 | } | |
281 | ||
282 | /* | |
283 | * Set up Op-code, Phy Address, and register address in the I2CCMD | |
284 | * register. The MAC will take care of interfacing with the | |
285 | * PHY to retrieve the desired data. | |
286 | */ | |
287 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
288 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | | |
289 | (E1000_I2CCMD_OPCODE_READ)); | |
290 | ||
291 | wr32(E1000_I2CCMD, i2ccmd); | |
292 | ||
293 | /* Poll the ready bit to see if the I2C read completed */ | |
294 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
295 | udelay(50); | |
296 | i2ccmd = rd32(E1000_I2CCMD); | |
297 | if (i2ccmd & E1000_I2CCMD_READY) | |
298 | break; | |
299 | } | |
300 | if (!(i2ccmd & E1000_I2CCMD_READY)) { | |
652fff32 | 301 | hw_dbg("I2CCMD Read did not complete\n"); |
9d5c8243 AK |
302 | return -E1000_ERR_PHY; |
303 | } | |
304 | if (i2ccmd & E1000_I2CCMD_ERROR) { | |
652fff32 | 305 | hw_dbg("I2CCMD Error bit set\n"); |
9d5c8243 AK |
306 | return -E1000_ERR_PHY; |
307 | } | |
308 | ||
309 | /* Need to byte-swap the 16-bit value. */ | |
310 | *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | /** | |
733596be | 316 | * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii |
9d5c8243 AK |
317 | * @hw: pointer to the HW structure |
318 | * @offset: register offset to write to | |
319 | * @data: data to write at register offset | |
320 | * | |
321 | * Writes the data to PHY register at the offset using the serial gigabit | |
322 | * media independent interface. | |
323 | **/ | |
324 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
325 | u16 data) | |
326 | { | |
327 | struct e1000_phy_info *phy = &hw->phy; | |
328 | u32 i, i2ccmd = 0; | |
329 | u16 phy_data_swapped; | |
330 | ||
331 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 332 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
333 | return -E1000_ERR_PARAM; |
334 | } | |
335 | ||
336 | /* Swap the data bytes for the I2C interface */ | |
337 | phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); | |
338 | ||
339 | /* | |
340 | * Set up Op-code, Phy Address, and register address in the I2CCMD | |
341 | * register. The MAC will take care of interfacing with the | |
342 | * PHY to retrieve the desired data. | |
343 | */ | |
344 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
345 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | | |
346 | E1000_I2CCMD_OPCODE_WRITE | | |
347 | phy_data_swapped); | |
348 | ||
349 | wr32(E1000_I2CCMD, i2ccmd); | |
350 | ||
351 | /* Poll the ready bit to see if the I2C read completed */ | |
352 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
353 | udelay(50); | |
354 | i2ccmd = rd32(E1000_I2CCMD); | |
355 | if (i2ccmd & E1000_I2CCMD_READY) | |
356 | break; | |
357 | } | |
358 | if (!(i2ccmd & E1000_I2CCMD_READY)) { | |
652fff32 | 359 | hw_dbg("I2CCMD Write did not complete\n"); |
9d5c8243 AK |
360 | return -E1000_ERR_PHY; |
361 | } | |
362 | if (i2ccmd & E1000_I2CCMD_ERROR) { | |
652fff32 | 363 | hw_dbg("I2CCMD Error bit set\n"); |
9d5c8243 AK |
364 | return -E1000_ERR_PHY; |
365 | } | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | /** | |
733596be | 371 | * igb_get_phy_id_82575 - Retrieve PHY addr and id |
9d5c8243 AK |
372 | * @hw: pointer to the HW structure |
373 | * | |
652fff32 | 374 | * Retrieves the PHY address and ID for both PHY's which do and do not use |
9d5c8243 AK |
375 | * sgmi interface. |
376 | **/ | |
377 | static s32 igb_get_phy_id_82575(struct e1000_hw *hw) | |
378 | { | |
379 | struct e1000_phy_info *phy = &hw->phy; | |
380 | s32 ret_val = 0; | |
381 | u16 phy_id; | |
382 | ||
383 | /* | |
384 | * For SGMII PHYs, we try the list of possible addresses until | |
385 | * we find one that works. For non-SGMII PHYs | |
386 | * (e.g. integrated copper PHYs), an address of 1 should | |
387 | * work. The result of this function should mean phy->phy_addr | |
388 | * and phy->id are set correctly. | |
389 | */ | |
390 | if (!(igb_sgmii_active_82575(hw))) { | |
391 | phy->addr = 1; | |
392 | ret_val = igb_get_phy_id(hw); | |
393 | goto out; | |
394 | } | |
395 | ||
396 | /* | |
397 | * The address field in the I2CCMD register is 3 bits and 0 is invalid. | |
398 | * Therefore, we need to test 1-7 | |
399 | */ | |
400 | for (phy->addr = 1; phy->addr < 8; phy->addr++) { | |
401 | ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); | |
402 | if (ret_val == 0) { | |
652fff32 AK |
403 | hw_dbg("Vendor ID 0x%08X read at address %u\n", |
404 | phy_id, phy->addr); | |
9d5c8243 AK |
405 | /* |
406 | * At the time of this writing, The M88 part is | |
407 | * the only supported SGMII PHY product. | |
408 | */ | |
409 | if (phy_id == M88_VENDOR) | |
410 | break; | |
411 | } else { | |
652fff32 | 412 | hw_dbg("PHY address %u was unreadable\n", phy->addr); |
9d5c8243 AK |
413 | } |
414 | } | |
415 | ||
416 | /* A valid PHY type couldn't be found. */ | |
417 | if (phy->addr == 8) { | |
418 | phy->addr = 0; | |
419 | ret_val = -E1000_ERR_PHY; | |
420 | goto out; | |
421 | } | |
422 | ||
423 | ret_val = igb_get_phy_id(hw); | |
424 | ||
425 | out: | |
426 | return ret_val; | |
427 | } | |
428 | ||
429 | /** | |
733596be | 430 | * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset |
9d5c8243 AK |
431 | * @hw: pointer to the HW structure |
432 | * | |
433 | * Resets the PHY using the serial gigabit media independent interface. | |
434 | **/ | |
435 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) | |
436 | { | |
437 | s32 ret_val; | |
438 | ||
439 | /* | |
440 | * This isn't a true "hard" reset, but is the only reset | |
441 | * available to us at this time. | |
442 | */ | |
443 | ||
652fff32 | 444 | hw_dbg("Soft resetting SGMII attached PHY...\n"); |
9d5c8243 AK |
445 | |
446 | /* | |
447 | * SFP documentation requires the following to configure the SPF module | |
448 | * to work on SGMII. No further documentation is given. | |
449 | */ | |
a8d2a0c2 | 450 | ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); |
9d5c8243 AK |
451 | if (ret_val) |
452 | goto out; | |
453 | ||
454 | ret_val = igb_phy_sw_reset(hw); | |
455 | ||
456 | out: | |
457 | return ret_val; | |
458 | } | |
459 | ||
460 | /** | |
733596be | 461 | * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state |
9d5c8243 AK |
462 | * @hw: pointer to the HW structure |
463 | * @active: true to enable LPLU, false to disable | |
464 | * | |
465 | * Sets the LPLU D0 state according to the active flag. When | |
466 | * activating LPLU this function also disables smart speed | |
467 | * and vice versa. LPLU will not be activated unless the | |
468 | * device autonegotiation advertisement meets standards of | |
469 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
470 | * This is a function pointer entry point only called by | |
471 | * PHY setup routines. | |
472 | **/ | |
473 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) | |
474 | { | |
475 | struct e1000_phy_info *phy = &hw->phy; | |
476 | s32 ret_val; | |
477 | u16 data; | |
478 | ||
a8d2a0c2 | 479 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
480 | if (ret_val) |
481 | goto out; | |
482 | ||
483 | if (active) { | |
484 | data |= IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 485 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 486 | data); |
9d5c8243 AK |
487 | if (ret_val) |
488 | goto out; | |
489 | ||
490 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 491 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 492 | &data); |
9d5c8243 | 493 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
a8d2a0c2 | 494 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 495 | data); |
9d5c8243 AK |
496 | if (ret_val) |
497 | goto out; | |
498 | } else { | |
499 | data &= ~IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 500 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 501 | data); |
9d5c8243 AK |
502 | /* |
503 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
504 | * during Dx states where the power conservation is most | |
505 | * important. During driver activity we should enable | |
506 | * SmartSpeed, so performance is maintained. | |
507 | */ | |
508 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 509 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 510 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
511 | if (ret_val) |
512 | goto out; | |
513 | ||
514 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 515 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 516 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
517 | if (ret_val) |
518 | goto out; | |
519 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 520 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 521 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
522 | if (ret_val) |
523 | goto out; | |
524 | ||
525 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 526 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 527 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
528 | if (ret_val) |
529 | goto out; | |
530 | } | |
531 | } | |
532 | ||
533 | out: | |
534 | return ret_val; | |
535 | } | |
536 | ||
537 | /** | |
733596be | 538 | * igb_acquire_nvm_82575 - Request for access to EEPROM |
9d5c8243 AK |
539 | * @hw: pointer to the HW structure |
540 | * | |
652fff32 | 541 | * Acquire the necessary semaphores for exclusive access to the EEPROM. |
9d5c8243 AK |
542 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
543 | * Return successful if access grant bit set, else clear the request for | |
544 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
545 | **/ | |
546 | static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) | |
547 | { | |
548 | s32 ret_val; | |
549 | ||
550 | ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
551 | if (ret_val) | |
552 | goto out; | |
553 | ||
554 | ret_val = igb_acquire_nvm(hw); | |
555 | ||
556 | if (ret_val) | |
557 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
558 | ||
559 | out: | |
560 | return ret_val; | |
561 | } | |
562 | ||
563 | /** | |
733596be | 564 | * igb_release_nvm_82575 - Release exclusive access to EEPROM |
9d5c8243 AK |
565 | * @hw: pointer to the HW structure |
566 | * | |
567 | * Stop any current commands to the EEPROM and clear the EEPROM request bit, | |
568 | * then release the semaphores acquired. | |
569 | **/ | |
570 | static void igb_release_nvm_82575(struct e1000_hw *hw) | |
571 | { | |
572 | igb_release_nvm(hw); | |
573 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
574 | } | |
575 | ||
576 | /** | |
733596be | 577 | * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore |
9d5c8243 AK |
578 | * @hw: pointer to the HW structure |
579 | * @mask: specifies which semaphore to acquire | |
580 | * | |
581 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
582 | * will also specify which port we're acquiring the lock for. | |
583 | **/ | |
584 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
585 | { | |
586 | u32 swfw_sync; | |
587 | u32 swmask = mask; | |
588 | u32 fwmask = mask << 16; | |
589 | s32 ret_val = 0; | |
590 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ | |
591 | ||
592 | while (i < timeout) { | |
593 | if (igb_get_hw_semaphore(hw)) { | |
594 | ret_val = -E1000_ERR_SWFW_SYNC; | |
595 | goto out; | |
596 | } | |
597 | ||
598 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
599 | if (!(swfw_sync & (fwmask | swmask))) | |
600 | break; | |
601 | ||
602 | /* | |
603 | * Firmware currently using resource (fwmask) | |
604 | * or other software thread using resource (swmask) | |
605 | */ | |
606 | igb_put_hw_semaphore(hw); | |
607 | mdelay(5); | |
608 | i++; | |
609 | } | |
610 | ||
611 | if (i == timeout) { | |
652fff32 | 612 | hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
9d5c8243 AK |
613 | ret_val = -E1000_ERR_SWFW_SYNC; |
614 | goto out; | |
615 | } | |
616 | ||
617 | swfw_sync |= swmask; | |
618 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
619 | ||
620 | igb_put_hw_semaphore(hw); | |
621 | ||
622 | out: | |
623 | return ret_val; | |
624 | } | |
625 | ||
626 | /** | |
733596be | 627 | * igb_release_swfw_sync_82575 - Release SW/FW semaphore |
9d5c8243 AK |
628 | * @hw: pointer to the HW structure |
629 | * @mask: specifies which semaphore to acquire | |
630 | * | |
631 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
632 | * will also specify which port we're releasing the lock for. | |
633 | **/ | |
634 | static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
635 | { | |
636 | u32 swfw_sync; | |
637 | ||
638 | while (igb_get_hw_semaphore(hw) != 0); | |
639 | /* Empty */ | |
640 | ||
641 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
642 | swfw_sync &= ~mask; | |
643 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
644 | ||
645 | igb_put_hw_semaphore(hw); | |
646 | } | |
647 | ||
648 | /** | |
733596be | 649 | * igb_get_cfg_done_82575 - Read config done bit |
9d5c8243 AK |
650 | * @hw: pointer to the HW structure |
651 | * | |
652 | * Read the management control register for the config done bit for | |
653 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | |
654 | * to read the config done bit, so an error is *ONLY* logged and returns | |
655 | * 0. If we were to return with error, EEPROM-less silicon | |
656 | * would not be able to be reset or change link. | |
657 | **/ | |
658 | static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) | |
659 | { | |
660 | s32 timeout = PHY_CFG_TIMEOUT; | |
661 | s32 ret_val = 0; | |
662 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
663 | ||
664 | if (hw->bus.func == 1) | |
665 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
666 | ||
667 | while (timeout) { | |
668 | if (rd32(E1000_EEMNGCTL) & mask) | |
669 | break; | |
670 | msleep(1); | |
671 | timeout--; | |
672 | } | |
673 | if (!timeout) | |
652fff32 | 674 | hw_dbg("MNG configuration cycle has not completed.\n"); |
9d5c8243 AK |
675 | |
676 | /* If EEPROM is not marked present, init the PHY manually */ | |
677 | if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && | |
678 | (hw->phy.type == e1000_phy_igp_3)) | |
679 | igb_phy_init_script_igp3(hw); | |
680 | ||
681 | return ret_val; | |
682 | } | |
683 | ||
684 | /** | |
733596be | 685 | * igb_check_for_link_82575 - Check for link |
9d5c8243 AK |
686 | * @hw: pointer to the HW structure |
687 | * | |
688 | * If sgmii is enabled, then use the pcs register to determine link, otherwise | |
689 | * use the generic interface for determining link. | |
690 | **/ | |
691 | static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |
692 | { | |
693 | s32 ret_val; | |
694 | u16 speed, duplex; | |
695 | ||
696 | /* SGMII link check is done through the PCS register. */ | |
697 | if ((hw->phy.media_type != e1000_media_type_copper) || | |
5d0932a5 | 698 | (igb_sgmii_active_82575(hw))) { |
9d5c8243 | 699 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
2d064c06 | 700 | &duplex); |
5d0932a5 AD |
701 | /* |
702 | * Use this flag to determine if link needs to be checked or | |
703 | * not. If we have link clear the flag so that we do not | |
704 | * continue to check for link. | |
705 | */ | |
706 | hw->mac.get_link_status = !hw->mac.serdes_has_link; | |
707 | } else { | |
9d5c8243 | 708 | ret_val = igb_check_for_copper_link(hw); |
5d0932a5 | 709 | } |
9d5c8243 AK |
710 | |
711 | return ret_val; | |
712 | } | |
9d5c8243 | 713 | /** |
733596be | 714 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
9d5c8243 AK |
715 | * @hw: pointer to the HW structure |
716 | * @speed: stores the current speed | |
717 | * @duplex: stores the current duplex | |
718 | * | |
652fff32 | 719 | * Using the physical coding sub-layer (PCS), retrieve the current speed and |
9d5c8243 AK |
720 | * duplex, then store the values in the pointers provided. |
721 | **/ | |
722 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, | |
723 | u16 *duplex) | |
724 | { | |
725 | struct e1000_mac_info *mac = &hw->mac; | |
726 | u32 pcs; | |
727 | ||
728 | /* Set up defaults for the return values of this function */ | |
729 | mac->serdes_has_link = false; | |
730 | *speed = 0; | |
731 | *duplex = 0; | |
732 | ||
733 | /* | |
734 | * Read the PCS Status register for link state. For non-copper mode, | |
735 | * the status register is not accurate. The PCS status register is | |
736 | * used instead. | |
737 | */ | |
738 | pcs = rd32(E1000_PCS_LSTAT); | |
739 | ||
740 | /* | |
741 | * The link up bit determines when link is up on autoneg. The sync ok | |
742 | * gets set once both sides sync up and agree upon link. Stable link | |
743 | * can be determined by checking for both link up and link sync ok | |
744 | */ | |
745 | if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { | |
746 | mac->serdes_has_link = true; | |
747 | ||
748 | /* Detect and store PCS speed */ | |
749 | if (pcs & E1000_PCS_LSTS_SPEED_1000) { | |
750 | *speed = SPEED_1000; | |
751 | } else if (pcs & E1000_PCS_LSTS_SPEED_100) { | |
752 | *speed = SPEED_100; | |
753 | } else { | |
754 | *speed = SPEED_10; | |
755 | } | |
756 | ||
757 | /* Detect and store PCS duplex */ | |
758 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { | |
759 | *duplex = FULL_DUPLEX; | |
760 | } else { | |
761 | *duplex = HALF_DUPLEX; | |
762 | } | |
763 | } | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
2d064c06 AD |
768 | /** |
769 | * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down | |
9d5c8243 | 770 | * @hw: pointer to the HW structure |
9d5c8243 | 771 | * |
2d064c06 AD |
772 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
773 | * when management pass thru is not enabled. | |
9d5c8243 | 774 | **/ |
2d064c06 | 775 | void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 776 | { |
2d064c06 AD |
777 | u32 reg; |
778 | ||
099e1cb7 | 779 | if (hw->phy.media_type != e1000_media_type_internal_serdes) |
2d064c06 AD |
780 | return; |
781 | ||
782 | /* if the management interface is not enabled, then power down */ | |
783 | if (!igb_enable_mng_pass_thru(hw)) { | |
784 | /* Disable PCS to turn off link */ | |
785 | reg = rd32(E1000_PCS_CFG0); | |
786 | reg &= ~E1000_PCS_CFG_PCS_EN; | |
787 | wr32(E1000_PCS_CFG0, reg); | |
788 | ||
789 | /* shutdown the laser */ | |
790 | reg = rd32(E1000_CTRL_EXT); | |
791 | reg |= E1000_CTRL_EXT_SDP7_DATA; | |
792 | wr32(E1000_CTRL_EXT, reg); | |
793 | ||
794 | /* flush the write to verify completion */ | |
795 | wrfl(); | |
796 | msleep(1); | |
797 | } | |
9d5c8243 AK |
798 | |
799 | return; | |
800 | } | |
801 | ||
802 | /** | |
733596be | 803 | * igb_reset_hw_82575 - Reset hardware |
9d5c8243 AK |
804 | * @hw: pointer to the HW structure |
805 | * | |
806 | * This resets the hardware into a known state. This is a | |
807 | * function pointer entry point called by the api module. | |
808 | **/ | |
809 | static s32 igb_reset_hw_82575(struct e1000_hw *hw) | |
810 | { | |
811 | u32 ctrl, icr; | |
812 | s32 ret_val; | |
813 | ||
814 | /* | |
815 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
816 | * on the last TLP read/write transaction when MAC is reset. | |
817 | */ | |
818 | ret_val = igb_disable_pcie_master(hw); | |
819 | if (ret_val) | |
652fff32 | 820 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
9d5c8243 | 821 | |
009bc06e AD |
822 | /* set the completion timeout for interface */ |
823 | ret_val = igb_set_pcie_completion_timeout(hw); | |
824 | if (ret_val) { | |
825 | hw_dbg("PCI-E Set completion timeout has failed.\n"); | |
826 | } | |
827 | ||
652fff32 | 828 | hw_dbg("Masking off all interrupts\n"); |
9d5c8243 AK |
829 | wr32(E1000_IMC, 0xffffffff); |
830 | ||
831 | wr32(E1000_RCTL, 0); | |
832 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
833 | wrfl(); | |
834 | ||
835 | msleep(10); | |
836 | ||
837 | ctrl = rd32(E1000_CTRL); | |
838 | ||
652fff32 | 839 | hw_dbg("Issuing a global reset to MAC\n"); |
9d5c8243 AK |
840 | wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); |
841 | ||
842 | ret_val = igb_get_auto_rd_done(hw); | |
843 | if (ret_val) { | |
844 | /* | |
845 | * When auto config read does not complete, do not | |
846 | * return with an error. This can happen in situations | |
847 | * where there is no eeprom and prevents getting link. | |
848 | */ | |
652fff32 | 849 | hw_dbg("Auto Read Done did not complete\n"); |
9d5c8243 AK |
850 | } |
851 | ||
852 | /* If EEPROM is not present, run manual init scripts */ | |
853 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
854 | igb_reset_init_script_82575(hw); | |
855 | ||
856 | /* Clear any pending interrupt events. */ | |
857 | wr32(E1000_IMC, 0xffffffff); | |
858 | icr = rd32(E1000_ICR); | |
859 | ||
5ac16659 AD |
860 | /* Install any alternate MAC address into RAR0 */ |
861 | ret_val = igb_check_alt_mac_addr(hw); | |
9d5c8243 AK |
862 | |
863 | return ret_val; | |
864 | } | |
865 | ||
866 | /** | |
733596be | 867 | * igb_init_hw_82575 - Initialize hardware |
9d5c8243 AK |
868 | * @hw: pointer to the HW structure |
869 | * | |
870 | * This inits the hardware readying it for operation. | |
871 | **/ | |
872 | static s32 igb_init_hw_82575(struct e1000_hw *hw) | |
873 | { | |
874 | struct e1000_mac_info *mac = &hw->mac; | |
875 | s32 ret_val; | |
876 | u16 i, rar_count = mac->rar_entry_count; | |
877 | ||
878 | /* Initialize identification LED */ | |
879 | ret_val = igb_id_led_init(hw); | |
880 | if (ret_val) { | |
652fff32 | 881 | hw_dbg("Error initializing identification LED\n"); |
9d5c8243 AK |
882 | /* This is not fatal and we should not stop init due to this */ |
883 | } | |
884 | ||
885 | /* Disabling VLAN filtering */ | |
652fff32 | 886 | hw_dbg("Initializing the IEEE VLAN\n"); |
9d5c8243 AK |
887 | igb_clear_vfta(hw); |
888 | ||
889 | /* Setup the receive address */ | |
5ac16659 AD |
890 | igb_init_rx_addrs(hw, rar_count); |
891 | ||
9d5c8243 | 892 | /* Zero out the Multicast HASH table */ |
652fff32 | 893 | hw_dbg("Zeroing the MTA\n"); |
9d5c8243 AK |
894 | for (i = 0; i < mac->mta_reg_count; i++) |
895 | array_wr32(E1000_MTA, i, 0); | |
896 | ||
897 | /* Setup link and flow control */ | |
898 | ret_val = igb_setup_link(hw); | |
899 | ||
900 | /* | |
901 | * Clear all of the statistics registers (clear on read). It is | |
902 | * important that we do this after we have tried to establish link | |
903 | * because the symbol error count will increment wildly if there | |
904 | * is no link. | |
905 | */ | |
906 | igb_clear_hw_cntrs_82575(hw); | |
907 | ||
908 | return ret_val; | |
909 | } | |
910 | ||
911 | /** | |
733596be | 912 | * igb_setup_copper_link_82575 - Configure copper link settings |
9d5c8243 AK |
913 | * @hw: pointer to the HW structure |
914 | * | |
915 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
916 | * for link, once link is established calls to configure collision distance | |
917 | * and flow control are called. | |
918 | **/ | |
919 | static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) | |
920 | { | |
12645a19 | 921 | u32 ctrl; |
9d5c8243 AK |
922 | s32 ret_val; |
923 | bool link; | |
924 | ||
925 | ctrl = rd32(E1000_CTRL); | |
926 | ctrl |= E1000_CTRL_SLU; | |
927 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
928 | wr32(E1000_CTRL, ctrl); | |
929 | ||
930 | switch (hw->phy.type) { | |
931 | case e1000_phy_m88: | |
932 | ret_val = igb_copper_link_setup_m88(hw); | |
933 | break; | |
934 | case e1000_phy_igp_3: | |
935 | ret_val = igb_copper_link_setup_igp(hw); | |
9d5c8243 AK |
936 | break; |
937 | default: | |
938 | ret_val = -E1000_ERR_PHY; | |
939 | break; | |
940 | } | |
941 | ||
942 | if (ret_val) | |
943 | goto out; | |
944 | ||
945 | if (hw->mac.autoneg) { | |
946 | /* | |
947 | * Setup autoneg and flow control advertisement | |
948 | * and perform autonegotiation. | |
949 | */ | |
950 | ret_val = igb_copper_link_autoneg(hw); | |
951 | if (ret_val) | |
952 | goto out; | |
953 | } else { | |
954 | /* | |
955 | * PHY will be set to 10H, 10F, 100H or 100F | |
956 | * depending on user settings. | |
957 | */ | |
652fff32 | 958 | hw_dbg("Forcing Speed and Duplex\n"); |
a8d2a0c2 | 959 | ret_val = hw->phy.ops.force_speed_duplex(hw); |
9d5c8243 | 960 | if (ret_val) { |
652fff32 | 961 | hw_dbg("Error Forcing Speed and Duplex\n"); |
9d5c8243 AK |
962 | goto out; |
963 | } | |
964 | } | |
965 | ||
f3e7841c | 966 | igb_configure_pcs_link_82575(hw); |
9d5c8243 AK |
967 | |
968 | /* | |
969 | * Check link status. Wait up to 100 microseconds for link to become | |
970 | * valid. | |
971 | */ | |
652fff32 | 972 | ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); |
9d5c8243 AK |
973 | if (ret_val) |
974 | goto out; | |
975 | ||
976 | if (link) { | |
652fff32 | 977 | hw_dbg("Valid link established!!!\n"); |
9d5c8243 AK |
978 | /* Config the MAC and PHY after link is up */ |
979 | igb_config_collision_dist(hw); | |
980 | ret_val = igb_config_fc_after_link_up(hw); | |
981 | } else { | |
652fff32 | 982 | hw_dbg("Unable to establish link!!!\n"); |
9d5c8243 AK |
983 | } |
984 | ||
985 | out: | |
986 | return ret_val; | |
987 | } | |
988 | ||
989 | /** | |
733596be | 990 | * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes |
9d5c8243 AK |
991 | * @hw: pointer to the HW structure |
992 | * | |
993 | * Configures speed and duplex for fiber and serdes links. | |
994 | **/ | |
995 | static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw) | |
996 | { | |
997 | u32 reg; | |
998 | ||
999 | /* | |
1000 | * On the 82575, SerDes loopback mode persists until it is | |
1001 | * explicitly turned off or a power cycle is performed. A read to | |
1002 | * the register does not indicate its status. Therefore, we ensure | |
1003 | * loopback mode is disabled during initialization. | |
1004 | */ | |
1005 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); | |
1006 | ||
1007 | /* Force link up, set 1gb, set both sw defined pins */ | |
1008 | reg = rd32(E1000_CTRL); | |
1009 | reg |= E1000_CTRL_SLU | | |
1010 | E1000_CTRL_SPD_1000 | | |
1011 | E1000_CTRL_FRCSPD | | |
1012 | E1000_CTRL_SWDPIN0 | | |
1013 | E1000_CTRL_SWDPIN1; | |
1014 | wr32(E1000_CTRL, reg); | |
1015 | ||
921aa749 AD |
1016 | /* Power on phy for 82576 fiber adapters */ |
1017 | if (hw->mac.type == e1000_82576) { | |
1018 | reg = rd32(E1000_CTRL_EXT); | |
1019 | reg &= ~E1000_CTRL_EXT_SDP7_DATA; | |
1020 | wr32(E1000_CTRL_EXT, reg); | |
1021 | } | |
1022 | ||
9d5c8243 AK |
1023 | /* Set switch control to serdes energy detect */ |
1024 | reg = rd32(E1000_CONNSW); | |
1025 | reg |= E1000_CONNSW_ENRGSRC; | |
1026 | wr32(E1000_CONNSW, reg); | |
1027 | ||
1028 | /* | |
1029 | * New SerDes mode allows for forcing speed or autonegotiating speed | |
1030 | * at 1gb. Autoneg should be default set by most drivers. This is the | |
1031 | * mode that will be compatible with older link partners and switches. | |
1032 | * However, both are supported by the hardware and some drivers/tools. | |
1033 | */ | |
1034 | reg = rd32(E1000_PCS_LCTL); | |
1035 | ||
1036 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | | |
1037 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | |
1038 | ||
1039 | if (hw->mac.autoneg) { | |
1040 | /* Set PCS register for autoneg */ | |
1041 | reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ | |
1042 | E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ | |
1043 | E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ | |
1044 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ | |
652fff32 | 1045 | hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); |
9d5c8243 AK |
1046 | } else { |
1047 | /* Set PCS register for forced speed */ | |
1048 | reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ | |
1049 | E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ | |
1050 | E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ | |
1051 | E1000_PCS_LCTL_FSD | /* Force Speed */ | |
1052 | E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ | |
652fff32 | 1053 | hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); |
9d5c8243 | 1054 | } |
726c09e7 AD |
1055 | |
1056 | if (hw->mac.type == e1000_82576) { | |
1057 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1058 | igb_force_mac_fc(hw); | |
1059 | } | |
1060 | ||
9d5c8243 AK |
1061 | wr32(E1000_PCS_LCTL, reg); |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | /** | |
733596be | 1067 | * igb_configure_pcs_link_82575 - Configure PCS link |
9d5c8243 AK |
1068 | * @hw: pointer to the HW structure |
1069 | * | |
1070 | * Configure the physical coding sub-layer (PCS) link. The PCS link is | |
1071 | * only used on copper connections where the serialized gigabit media | |
1072 | * independent interface (sgmii) is being used. Configures the link | |
1073 | * for auto-negotiation or forces speed/duplex. | |
1074 | **/ | |
f3e7841c | 1075 | static void igb_configure_pcs_link_82575(struct e1000_hw *hw) |
9d5c8243 AK |
1076 | { |
1077 | struct e1000_mac_info *mac = &hw->mac; | |
1078 | u32 reg = 0; | |
1079 | ||
1080 | if (hw->phy.media_type != e1000_media_type_copper || | |
1081 | !(igb_sgmii_active_82575(hw))) | |
f3e7841c | 1082 | return; |
9d5c8243 AK |
1083 | |
1084 | /* For SGMII, we need to issue a PCS autoneg restart */ | |
1085 | reg = rd32(E1000_PCS_LCTL); | |
1086 | ||
1087 | /* AN time out should be disabled for SGMII mode */ | |
1088 | reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); | |
1089 | ||
1090 | if (mac->autoneg) { | |
1091 | /* Make sure forced speed and force link are not set */ | |
1092 | reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | |
1093 | ||
1094 | /* | |
1095 | * The PHY should be setup prior to calling this function. | |
1096 | * All we need to do is restart autoneg and enable autoneg. | |
1097 | */ | |
1098 | reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; | |
1099 | } else { | |
652fff32 | 1100 | /* Set PCS register for forced speed */ |
9d5c8243 AK |
1101 | |
1102 | /* Turn off bits for full duplex, speed, and autoneg */ | |
1103 | reg &= ~(E1000_PCS_LCTL_FSV_1000 | | |
1104 | E1000_PCS_LCTL_FSV_100 | | |
1105 | E1000_PCS_LCTL_FDV_FULL | | |
1106 | E1000_PCS_LCTL_AN_ENABLE); | |
1107 | ||
1108 | /* Check for duplex first */ | |
1109 | if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) | |
1110 | reg |= E1000_PCS_LCTL_FDV_FULL; | |
1111 | ||
1112 | /* Now set speed */ | |
1113 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) | |
1114 | reg |= E1000_PCS_LCTL_FSV_100; | |
1115 | ||
1116 | /* Force speed and force link */ | |
1117 | reg |= E1000_PCS_LCTL_FSD | | |
1118 | E1000_PCS_LCTL_FORCE_LINK | | |
1119 | E1000_PCS_LCTL_FLV_LINK_UP; | |
1120 | ||
652fff32 | 1121 | hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n", |
9d5c8243 AK |
1122 | reg); |
1123 | } | |
1124 | wr32(E1000_PCS_LCTL, reg); | |
9d5c8243 AK |
1125 | } |
1126 | ||
1127 | /** | |
733596be | 1128 | * igb_sgmii_active_82575 - Return sgmii state |
9d5c8243 AK |
1129 | * @hw: pointer to the HW structure |
1130 | * | |
1131 | * 82575 silicon has a serialized gigabit media independent interface (sgmii) | |
1132 | * which can be enabled for use in the embedded applications. Simply | |
1133 | * return the current state of the sgmii interface. | |
1134 | **/ | |
1135 | static bool igb_sgmii_active_82575(struct e1000_hw *hw) | |
1136 | { | |
c1889bfe | 1137 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
c1889bfe | 1138 | return dev_spec->sgmii_active; |
9d5c8243 AK |
1139 | } |
1140 | ||
1141 | /** | |
733596be | 1142 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
9d5c8243 AK |
1143 | * @hw: pointer to the HW structure |
1144 | * | |
1145 | * Inits recommended HW defaults after a reset when there is no EEPROM | |
1146 | * detected. This is only for the 82575. | |
1147 | **/ | |
1148 | static s32 igb_reset_init_script_82575(struct e1000_hw *hw) | |
1149 | { | |
1150 | if (hw->mac.type == e1000_82575) { | |
652fff32 | 1151 | hw_dbg("Running reset init script for 82575\n"); |
9d5c8243 AK |
1152 | /* SerDes configuration via SERDESCTRL */ |
1153 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); | |
1154 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); | |
1155 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); | |
1156 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); | |
1157 | ||
1158 | /* CCM configuration via CCMCTL register */ | |
1159 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); | |
1160 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); | |
1161 | ||
1162 | /* PCIe lanes configuration */ | |
1163 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); | |
1164 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); | |
1165 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); | |
1166 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); | |
1167 | ||
1168 | /* PCIe PLL Configuration */ | |
1169 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); | |
1170 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); | |
1171 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); | |
1172 | } | |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
1177 | /** | |
733596be | 1178 | * igb_read_mac_addr_82575 - Read device MAC address |
9d5c8243 AK |
1179 | * @hw: pointer to the HW structure |
1180 | **/ | |
1181 | static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) | |
1182 | { | |
1183 | s32 ret_val = 0; | |
1184 | ||
1185 | if (igb_check_alt_mac_addr(hw)) | |
1186 | ret_val = igb_read_mac_addr(hw); | |
1187 | ||
1188 | return ret_val; | |
1189 | } | |
1190 | ||
1191 | /** | |
733596be | 1192 | * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters |
9d5c8243 AK |
1193 | * @hw: pointer to the HW structure |
1194 | * | |
1195 | * Clears the hardware counters by reading the counter registers. | |
1196 | **/ | |
1197 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) | |
1198 | { | |
1199 | u32 temp; | |
1200 | ||
1201 | igb_clear_hw_cntrs_base(hw); | |
1202 | ||
1203 | temp = rd32(E1000_PRC64); | |
1204 | temp = rd32(E1000_PRC127); | |
1205 | temp = rd32(E1000_PRC255); | |
1206 | temp = rd32(E1000_PRC511); | |
1207 | temp = rd32(E1000_PRC1023); | |
1208 | temp = rd32(E1000_PRC1522); | |
1209 | temp = rd32(E1000_PTC64); | |
1210 | temp = rd32(E1000_PTC127); | |
1211 | temp = rd32(E1000_PTC255); | |
1212 | temp = rd32(E1000_PTC511); | |
1213 | temp = rd32(E1000_PTC1023); | |
1214 | temp = rd32(E1000_PTC1522); | |
1215 | ||
1216 | temp = rd32(E1000_ALGNERRC); | |
1217 | temp = rd32(E1000_RXERRC); | |
1218 | temp = rd32(E1000_TNCRS); | |
1219 | temp = rd32(E1000_CEXTERR); | |
1220 | temp = rd32(E1000_TSCTC); | |
1221 | temp = rd32(E1000_TSCTFC); | |
1222 | ||
1223 | temp = rd32(E1000_MGTPRC); | |
1224 | temp = rd32(E1000_MGTPDC); | |
1225 | temp = rd32(E1000_MGTPTC); | |
1226 | ||
1227 | temp = rd32(E1000_IAC); | |
1228 | temp = rd32(E1000_ICRXOC); | |
1229 | ||
1230 | temp = rd32(E1000_ICRXPTC); | |
1231 | temp = rd32(E1000_ICRXATC); | |
1232 | temp = rd32(E1000_ICTXPTC); | |
1233 | temp = rd32(E1000_ICTXATC); | |
1234 | temp = rd32(E1000_ICTXQEC); | |
1235 | temp = rd32(E1000_ICTXQMTC); | |
1236 | temp = rd32(E1000_ICRXDMTC); | |
1237 | ||
1238 | temp = rd32(E1000_CBTMPC); | |
1239 | temp = rd32(E1000_HTDPMC); | |
1240 | temp = rd32(E1000_CBRMPC); | |
1241 | temp = rd32(E1000_RPTHC); | |
1242 | temp = rd32(E1000_HGPTC); | |
1243 | temp = rd32(E1000_HTCBDPC); | |
1244 | temp = rd32(E1000_HGORCL); | |
1245 | temp = rd32(E1000_HGORCH); | |
1246 | temp = rd32(E1000_HGOTCL); | |
1247 | temp = rd32(E1000_HGOTCH); | |
1248 | temp = rd32(E1000_LENERRS); | |
1249 | ||
1250 | /* This register should not be read in copper configurations */ | |
1251 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
1252 | temp = rd32(E1000_SCVPC); | |
1253 | } | |
1254 | ||
662d7205 AD |
1255 | /** |
1256 | * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable | |
1257 | * @hw: pointer to the HW structure | |
1258 | * | |
1259 | * After rx enable if managability is enabled then there is likely some | |
1260 | * bad data at the start of the fifo and possibly in the DMA fifo. This | |
1261 | * function clears the fifos and flushes any packets that came in as rx was | |
1262 | * being enabled. | |
1263 | **/ | |
1264 | void igb_rx_fifo_flush_82575(struct e1000_hw *hw) | |
1265 | { | |
1266 | u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; | |
1267 | int i, ms_wait; | |
1268 | ||
1269 | if (hw->mac.type != e1000_82575 || | |
1270 | !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) | |
1271 | return; | |
1272 | ||
1273 | /* Disable all RX queues */ | |
1274 | for (i = 0; i < 4; i++) { | |
1275 | rxdctl[i] = rd32(E1000_RXDCTL(i)); | |
1276 | wr32(E1000_RXDCTL(i), | |
1277 | rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); | |
1278 | } | |
1279 | /* Poll all queues to verify they have shut down */ | |
1280 | for (ms_wait = 0; ms_wait < 10; ms_wait++) { | |
1281 | msleep(1); | |
1282 | rx_enabled = 0; | |
1283 | for (i = 0; i < 4; i++) | |
1284 | rx_enabled |= rd32(E1000_RXDCTL(i)); | |
1285 | if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) | |
1286 | break; | |
1287 | } | |
1288 | ||
1289 | if (ms_wait == 10) | |
1290 | hw_dbg("Queue disable timed out after 10ms\n"); | |
1291 | ||
1292 | /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all | |
1293 | * incoming packets are rejected. Set enable and wait 2ms so that | |
1294 | * any packet that was coming in as RCTL.EN was set is flushed | |
1295 | */ | |
1296 | rfctl = rd32(E1000_RFCTL); | |
1297 | wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); | |
1298 | ||
1299 | rlpml = rd32(E1000_RLPML); | |
1300 | wr32(E1000_RLPML, 0); | |
1301 | ||
1302 | rctl = rd32(E1000_RCTL); | |
1303 | temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); | |
1304 | temp_rctl |= E1000_RCTL_LPE; | |
1305 | ||
1306 | wr32(E1000_RCTL, temp_rctl); | |
1307 | wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); | |
1308 | wrfl(); | |
1309 | msleep(2); | |
1310 | ||
1311 | /* Enable RX queues that were previously enabled and restore our | |
1312 | * previous state | |
1313 | */ | |
1314 | for (i = 0; i < 4; i++) | |
1315 | wr32(E1000_RXDCTL(i), rxdctl[i]); | |
1316 | wr32(E1000_RCTL, rctl); | |
1317 | wrfl(); | |
1318 | ||
1319 | wr32(E1000_RLPML, rlpml); | |
1320 | wr32(E1000_RFCTL, rfctl); | |
1321 | ||
1322 | /* Flush receive errors generated by workaround */ | |
1323 | rd32(E1000_ROC); | |
1324 | rd32(E1000_RNBC); | |
1325 | rd32(E1000_MPC); | |
1326 | } | |
1327 | ||
009bc06e AD |
1328 | /** |
1329 | * igb_set_pcie_completion_timeout - set pci-e completion timeout | |
1330 | * @hw: pointer to the HW structure | |
1331 | * | |
1332 | * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, | |
1333 | * however the hardware default for these parts is 500us to 1ms which is less | |
1334 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
1335 | * increase the value to either 10ms to 200ms for capability version 1 config, | |
1336 | * or 16ms to 55ms for version 2. | |
1337 | **/ | |
1338 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) | |
1339 | { | |
1340 | u32 gcr = rd32(E1000_GCR); | |
1341 | s32 ret_val = 0; | |
1342 | u16 pcie_devctl2; | |
1343 | ||
1344 | /* only take action if timeout value is defaulted to 0 */ | |
1345 | if (gcr & E1000_GCR_CMPL_TMOUT_MASK) | |
1346 | goto out; | |
1347 | ||
1348 | /* | |
1349 | * if capababilities version is type 1 we can write the | |
1350 | * timeout of 10ms to 200ms through the GCR register | |
1351 | */ | |
1352 | if (!(gcr & E1000_GCR_CAP_VER2)) { | |
1353 | gcr |= E1000_GCR_CMPL_TMOUT_10ms; | |
1354 | goto out; | |
1355 | } | |
1356 | ||
1357 | /* | |
1358 | * for version 2 capabilities we need to write the config space | |
1359 | * directly in order to set the completion timeout value for | |
1360 | * 16ms to 55ms | |
1361 | */ | |
1362 | ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1363 | &pcie_devctl2); | |
1364 | if (ret_val) | |
1365 | goto out; | |
1366 | ||
1367 | pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; | |
1368 | ||
1369 | ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1370 | &pcie_devctl2); | |
1371 | out: | |
1372 | /* disable completion timeout resend */ | |
1373 | gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; | |
1374 | ||
1375 | wr32(E1000_GCR, gcr); | |
1376 | return ret_val; | |
1377 | } | |
1378 | ||
4ae196df AD |
1379 | /** |
1380 | * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback | |
1381 | * @hw: pointer to the hardware struct | |
1382 | * @enable: state to enter, either enabled or disabled | |
1383 | * | |
1384 | * enables/disables L2 switch loopback functionality. | |
1385 | **/ | |
1386 | void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) | |
1387 | { | |
1388 | u32 dtxswc = rd32(E1000_DTXSWC); | |
1389 | ||
1390 | if (enable) | |
1391 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1392 | else | |
1393 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1394 | ||
1395 | wr32(E1000_DTXSWC, dtxswc); | |
1396 | } | |
1397 | ||
1398 | /** | |
1399 | * igb_vmdq_set_replication_pf - enable or disable vmdq replication | |
1400 | * @hw: pointer to the hardware struct | |
1401 | * @enable: state to enter, either enabled or disabled | |
1402 | * | |
1403 | * enables/disables replication of packets across multiple pools. | |
1404 | **/ | |
1405 | void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) | |
1406 | { | |
1407 | u32 vt_ctl = rd32(E1000_VT_CTL); | |
1408 | ||
1409 | if (enable) | |
1410 | vt_ctl |= E1000_VT_CTL_VM_REPL_EN; | |
1411 | else | |
1412 | vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; | |
1413 | ||
1414 | wr32(E1000_VT_CTL, vt_ctl); | |
1415 | } | |
1416 | ||
9d5c8243 AK |
1417 | static struct e1000_mac_operations e1000_mac_ops_82575 = { |
1418 | .reset_hw = igb_reset_hw_82575, | |
1419 | .init_hw = igb_init_hw_82575, | |
1420 | .check_for_link = igb_check_for_link_82575, | |
2d064c06 | 1421 | .rar_set = igb_rar_set, |
9d5c8243 AK |
1422 | .read_mac_addr = igb_read_mac_addr_82575, |
1423 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, | |
1424 | }; | |
1425 | ||
1426 | static struct e1000_phy_operations e1000_phy_ops_82575 = { | |
a8d2a0c2 | 1427 | .acquire = igb_acquire_phy_82575, |
9d5c8243 | 1428 | .get_cfg_done = igb_get_cfg_done_82575, |
a8d2a0c2 | 1429 | .release = igb_release_phy_82575, |
9d5c8243 AK |
1430 | }; |
1431 | ||
1432 | static struct e1000_nvm_operations e1000_nvm_ops_82575 = { | |
312c75ae AD |
1433 | .acquire = igb_acquire_nvm_82575, |
1434 | .read = igb_read_nvm_eerd, | |
1435 | .release = igb_release_nvm_82575, | |
1436 | .write = igb_write_nvm_spi, | |
9d5c8243 AK |
1437 | }; |
1438 | ||
1439 | const struct e1000_info e1000_82575_info = { | |
1440 | .get_invariants = igb_get_invariants_82575, | |
1441 | .mac_ops = &e1000_mac_ops_82575, | |
1442 | .phy_ops = &e1000_phy_ops_82575, | |
1443 | .nvm_ops = &e1000_nvm_ops_82575, | |
1444 | }; | |
1445 |