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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* e1000_82575 | |
29 | * e1000_82576 | |
30 | */ | |
31 | ||
32 | #include <linux/types.h> | |
2d064c06 | 33 | #include <linux/if_ether.h> |
9d5c8243 AK |
34 | |
35 | #include "e1000_mac.h" | |
36 | #include "e1000_82575.h" | |
37 | ||
38 | static s32 igb_get_invariants_82575(struct e1000_hw *); | |
39 | static s32 igb_acquire_phy_82575(struct e1000_hw *); | |
40 | static void igb_release_phy_82575(struct e1000_hw *); | |
41 | static s32 igb_acquire_nvm_82575(struct e1000_hw *); | |
42 | static void igb_release_nvm_82575(struct e1000_hw *); | |
43 | static s32 igb_check_for_link_82575(struct e1000_hw *); | |
44 | static s32 igb_get_cfg_done_82575(struct e1000_hw *); | |
45 | static s32 igb_init_hw_82575(struct e1000_hw *); | |
46 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); | |
47 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); | |
bb2ac47b AD |
48 | static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); |
49 | static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); | |
9d5c8243 | 50 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
bb2ac47b | 51 | static s32 igb_reset_hw_82580(struct e1000_hw *); |
9d5c8243 AK |
52 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
53 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); | |
2fb02a26 | 54 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *); |
9d5c8243 AK |
55 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); |
56 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); | |
57 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); | |
9d5c8243 AK |
58 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
59 | u16 *); | |
60 | static s32 igb_get_phy_id_82575(struct e1000_hw *); | |
61 | static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); | |
62 | static bool igb_sgmii_active_82575(struct e1000_hw *); | |
63 | static s32 igb_reset_init_script_82575(struct e1000_hw *); | |
64 | static s32 igb_read_mac_addr_82575(struct e1000_hw *); | |
009bc06e | 65 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); |
99870a73 | 66 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); |
9d5c8243 | 67 | |
bb2ac47b AD |
68 | static const u16 e1000_82580_rxpbs_table[] = |
69 | { 36, 72, 144, 1, 2, 4, 8, 16, | |
70 | 35, 70, 140 }; | |
71 | #define E1000_82580_RXPBS_TABLE_SIZE \ | |
72 | (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) | |
73 | ||
4085f746 NN |
74 | /** |
75 | * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO | |
76 | * @hw: pointer to the HW structure | |
77 | * | |
78 | * Called to determine if the I2C pins are being used for I2C or as an | |
79 | * external MDIO interface since the two options are mutually exclusive. | |
80 | **/ | |
81 | static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) | |
82 | { | |
83 | u32 reg = 0; | |
84 | bool ext_mdio = false; | |
85 | ||
86 | switch (hw->mac.type) { | |
87 | case e1000_82575: | |
88 | case e1000_82576: | |
89 | reg = rd32(E1000_MDIC); | |
90 | ext_mdio = !!(reg & E1000_MDIC_DEST); | |
91 | break; | |
92 | case e1000_82580: | |
93 | case e1000_i350: | |
94 | reg = rd32(E1000_MDICNFG); | |
95 | ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); | |
96 | break; | |
97 | default: | |
98 | break; | |
99 | } | |
100 | return ext_mdio; | |
101 | } | |
102 | ||
9d5c8243 AK |
103 | static s32 igb_get_invariants_82575(struct e1000_hw *hw) |
104 | { | |
105 | struct e1000_phy_info *phy = &hw->phy; | |
106 | struct e1000_nvm_info *nvm = &hw->nvm; | |
107 | struct e1000_mac_info *mac = &hw->mac; | |
c1889bfe | 108 | struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; |
9d5c8243 AK |
109 | u32 eecd; |
110 | s32 ret_val; | |
111 | u16 size; | |
112 | u32 ctrl_ext = 0; | |
113 | ||
114 | switch (hw->device_id) { | |
115 | case E1000_DEV_ID_82575EB_COPPER: | |
116 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
117 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
118 | mac->type = e1000_82575; | |
119 | break; | |
2d064c06 | 120 | case E1000_DEV_ID_82576: |
9eb2341d | 121 | case E1000_DEV_ID_82576_NS: |
747d49ba | 122 | case E1000_DEV_ID_82576_NS_SERDES: |
2d064c06 AD |
123 | case E1000_DEV_ID_82576_FIBER: |
124 | case E1000_DEV_ID_82576_SERDES: | |
c8ea5ea9 | 125 | case E1000_DEV_ID_82576_QUAD_COPPER: |
b894fa26 | 126 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
4703bf73 | 127 | case E1000_DEV_ID_82576_SERDES_QUAD: |
2d064c06 AD |
128 | mac->type = e1000_82576; |
129 | break; | |
bb2ac47b AD |
130 | case E1000_DEV_ID_82580_COPPER: |
131 | case E1000_DEV_ID_82580_FIBER: | |
6493d24f | 132 | case E1000_DEV_ID_82580_QUAD_FIBER: |
bb2ac47b AD |
133 | case E1000_DEV_ID_82580_SERDES: |
134 | case E1000_DEV_ID_82580_SGMII: | |
135 | case E1000_DEV_ID_82580_COPPER_DUAL: | |
308fb39a JG |
136 | case E1000_DEV_ID_DH89XXCC_SGMII: |
137 | case E1000_DEV_ID_DH89XXCC_SERDES: | |
1b5dda33 GJ |
138 | case E1000_DEV_ID_DH89XXCC_BACKPLANE: |
139 | case E1000_DEV_ID_DH89XXCC_SFP: | |
bb2ac47b AD |
140 | mac->type = e1000_82580; |
141 | break; | |
d2ba2ed8 AD |
142 | case E1000_DEV_ID_I350_COPPER: |
143 | case E1000_DEV_ID_I350_FIBER: | |
144 | case E1000_DEV_ID_I350_SERDES: | |
145 | case E1000_DEV_ID_I350_SGMII: | |
146 | mac->type = e1000_i350; | |
147 | break; | |
9d5c8243 AK |
148 | default: |
149 | return -E1000_ERR_MAC_INIT; | |
150 | break; | |
151 | } | |
152 | ||
9d5c8243 AK |
153 | /* Set media type */ |
154 | /* | |
155 | * The 82575 uses bits 22:23 for link mode. The mode can be changed | |
156 | * based on the EEPROM. We cannot rely upon device ID. There | |
157 | * is no distinguishable difference between fiber and internal | |
158 | * SerDes mode on the 82575. There can be an external PHY attached | |
159 | * on the SGMII interface. For this, we'll set sgmii_active to true. | |
160 | */ | |
161 | phy->media_type = e1000_media_type_copper; | |
162 | dev_spec->sgmii_active = false; | |
163 | ||
164 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
2fb02a26 AD |
165 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
166 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
9d5c8243 | 167 | dev_spec->sgmii_active = true; |
2fb02a26 | 168 | break; |
bb2ac47b | 169 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: |
2fb02a26 AD |
170 | case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: |
171 | hw->phy.media_type = e1000_media_type_internal_serdes; | |
2fb02a26 AD |
172 | break; |
173 | default: | |
2fb02a26 | 174 | break; |
9d5c8243 | 175 | } |
2fb02a26 | 176 | |
9d5c8243 AK |
177 | /* Set mta register count */ |
178 | mac->mta_reg_count = 128; | |
179 | /* Set rar entry count */ | |
180 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; | |
2d064c06 AD |
181 | if (mac->type == e1000_82576) |
182 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; | |
bb2ac47b AD |
183 | if (mac->type == e1000_82580) |
184 | mac->rar_entry_count = E1000_RAR_ENTRIES_82580; | |
d2ba2ed8 AD |
185 | if (mac->type == e1000_i350) |
186 | mac->rar_entry_count = E1000_RAR_ENTRIES_I350; | |
bb2ac47b | 187 | /* reset */ |
d2ba2ed8 | 188 | if (mac->type >= e1000_82580) |
bb2ac47b AD |
189 | mac->ops.reset_hw = igb_reset_hw_82580; |
190 | else | |
191 | mac->ops.reset_hw = igb_reset_hw_82575; | |
9d5c8243 AK |
192 | /* Set if part includes ASF firmware */ |
193 | mac->asf_firmware_present = true; | |
194 | /* Set if manageability features are enabled. */ | |
195 | mac->arc_subsystem_valid = | |
196 | (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) | |
197 | ? true : false; | |
198 | ||
199 | /* physical interface link setup */ | |
200 | mac->ops.setup_physical_interface = | |
201 | (hw->phy.media_type == e1000_media_type_copper) | |
202 | ? igb_setup_copper_link_82575 | |
2fb02a26 | 203 | : igb_setup_serdes_link_82575; |
9d5c8243 AK |
204 | |
205 | /* NVM initialization */ | |
206 | eecd = rd32(E1000_EECD); | |
207 | ||
208 | nvm->opcode_bits = 8; | |
209 | nvm->delay_usec = 1; | |
210 | switch (nvm->override) { | |
211 | case e1000_nvm_override_spi_large: | |
212 | nvm->page_size = 32; | |
213 | nvm->address_bits = 16; | |
214 | break; | |
215 | case e1000_nvm_override_spi_small: | |
216 | nvm->page_size = 8; | |
217 | nvm->address_bits = 8; | |
218 | break; | |
219 | default: | |
220 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
221 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
222 | break; | |
223 | } | |
224 | ||
225 | nvm->type = e1000_nvm_eeprom_spi; | |
226 | ||
227 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
228 | E1000_EECD_SIZE_EX_SHIFT); | |
229 | ||
230 | /* | |
231 | * Added to a constant, "size" becomes the left-shift value | |
232 | * for setting word_size. | |
233 | */ | |
234 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
5c3cad75 JK |
235 | |
236 | /* EEPROM access above 16k is unsupported */ | |
237 | if (size > 14) | |
238 | size = 14; | |
9d5c8243 AK |
239 | nvm->word_size = 1 << size; |
240 | ||
a0c98605 AD |
241 | /* if 82576 then initialize mailbox parameters */ |
242 | if (mac->type == e1000_82576) | |
243 | igb_init_mbx_params_pf(hw); | |
244 | ||
9d5c8243 AK |
245 | /* setup PHY parameters */ |
246 | if (phy->media_type != e1000_media_type_copper) { | |
247 | phy->type = e1000_phy_none; | |
248 | return 0; | |
249 | } | |
250 | ||
251 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
252 | phy->reset_delay_us = 100; | |
253 | ||
99870a73 AD |
254 | ctrl_ext = rd32(E1000_CTRL_EXT); |
255 | ||
9d5c8243 | 256 | /* PHY function pointers */ |
99870a73 | 257 | if (igb_sgmii_active_82575(hw)) { |
4085f746 | 258 | phy->ops.reset = igb_phy_hw_reset_sgmii_82575; |
99870a73 AD |
259 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
260 | } else { | |
4085f746 | 261 | phy->ops.reset = igb_phy_hw_reset; |
99870a73 AD |
262 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; |
263 | } | |
264 | ||
265 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
266 | igb_reset_mdicnfg_82580(hw); | |
4085f746 NN |
267 | |
268 | if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { | |
269 | phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; | |
270 | phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; | |
d2ba2ed8 | 271 | } else if (hw->mac.type >= e1000_82580) { |
4085f746 NN |
272 | phy->ops.read_reg = igb_read_phy_reg_82580; |
273 | phy->ops.write_reg = igb_write_phy_reg_82580; | |
9d5c8243 | 274 | } else { |
4085f746 NN |
275 | phy->ops.read_reg = igb_read_phy_reg_igp; |
276 | phy->ops.write_reg = igb_write_phy_reg_igp; | |
9d5c8243 AK |
277 | } |
278 | ||
19e588e7 AD |
279 | /* set lan id */ |
280 | hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> | |
281 | E1000_STATUS_FUNC_SHIFT; | |
282 | ||
9d5c8243 AK |
283 | /* Set phy->phy_addr and phy->id. */ |
284 | ret_val = igb_get_phy_id_82575(hw); | |
285 | if (ret_val) | |
286 | return ret_val; | |
287 | ||
288 | /* Verify phy id and set remaining function pointers */ | |
289 | switch (phy->id) { | |
308fb39a JG |
290 | case I347AT4_E_PHY_ID: |
291 | case M88E1112_E_PHY_ID: | |
9d5c8243 AK |
292 | case M88E1111_I_PHY_ID: |
293 | phy->type = e1000_phy_m88; | |
294 | phy->ops.get_phy_info = igb_get_phy_info_m88; | |
308fb39a JG |
295 | |
296 | if (phy->id == I347AT4_E_PHY_ID || | |
297 | phy->id == M88E1112_E_PHY_ID) | |
298 | phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; | |
299 | else | |
300 | phy->ops.get_cable_length = igb_get_cable_length_m88; | |
301 | ||
9d5c8243 AK |
302 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; |
303 | break; | |
304 | case IGP03E1000_E_PHY_ID: | |
305 | phy->type = e1000_phy_igp_3; | |
306 | phy->ops.get_phy_info = igb_get_phy_info_igp; | |
307 | phy->ops.get_cable_length = igb_get_cable_length_igp_2; | |
308 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; | |
309 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; | |
310 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; | |
311 | break; | |
bb2ac47b | 312 | case I82580_I_PHY_ID: |
d2ba2ed8 | 313 | case I350_I_PHY_ID: |
bb2ac47b AD |
314 | phy->type = e1000_phy_82580; |
315 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580; | |
316 | phy->ops.get_cable_length = igb_get_cable_length_82580; | |
317 | phy->ops.get_phy_info = igb_get_phy_info_82580; | |
318 | break; | |
9d5c8243 AK |
319 | default: |
320 | return -E1000_ERR_PHY; | |
321 | } | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | /** | |
733596be | 327 | * igb_acquire_phy_82575 - Acquire rights to access PHY |
9d5c8243 AK |
328 | * @hw: pointer to the HW structure |
329 | * | |
330 | * Acquire access rights to the correct PHY. This is a | |
331 | * function pointer entry point called by the api module. | |
332 | **/ | |
333 | static s32 igb_acquire_phy_82575(struct e1000_hw *hw) | |
334 | { | |
008c3422 | 335 | u16 mask = E1000_SWFW_PHY0_SM; |
9d5c8243 | 336 | |
008c3422 AD |
337 | if (hw->bus.func == E1000_FUNC_1) |
338 | mask = E1000_SWFW_PHY1_SM; | |
ede3ef0d NN |
339 | else if (hw->bus.func == E1000_FUNC_2) |
340 | mask = E1000_SWFW_PHY2_SM; | |
341 | else if (hw->bus.func == E1000_FUNC_3) | |
342 | mask = E1000_SWFW_PHY3_SM; | |
9d5c8243 AK |
343 | |
344 | return igb_acquire_swfw_sync_82575(hw, mask); | |
345 | } | |
346 | ||
347 | /** | |
733596be | 348 | * igb_release_phy_82575 - Release rights to access PHY |
9d5c8243 AK |
349 | * @hw: pointer to the HW structure |
350 | * | |
351 | * A wrapper to release access rights to the correct PHY. This is a | |
352 | * function pointer entry point called by the api module. | |
353 | **/ | |
354 | static void igb_release_phy_82575(struct e1000_hw *hw) | |
355 | { | |
008c3422 AD |
356 | u16 mask = E1000_SWFW_PHY0_SM; |
357 | ||
358 | if (hw->bus.func == E1000_FUNC_1) | |
359 | mask = E1000_SWFW_PHY1_SM; | |
ede3ef0d NN |
360 | else if (hw->bus.func == E1000_FUNC_2) |
361 | mask = E1000_SWFW_PHY2_SM; | |
362 | else if (hw->bus.func == E1000_FUNC_3) | |
363 | mask = E1000_SWFW_PHY3_SM; | |
9d5c8243 | 364 | |
9d5c8243 AK |
365 | igb_release_swfw_sync_82575(hw, mask); |
366 | } | |
367 | ||
368 | /** | |
733596be | 369 | * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii |
9d5c8243 AK |
370 | * @hw: pointer to the HW structure |
371 | * @offset: register offset to be read | |
372 | * @data: pointer to the read data | |
373 | * | |
374 | * Reads the PHY register at offset using the serial gigabit media independent | |
375 | * interface and stores the retrieved information in data. | |
376 | **/ | |
377 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
378 | u16 *data) | |
379 | { | |
bf6f7a92 | 380 | s32 ret_val = -E1000_ERR_PARAM; |
9d5c8243 AK |
381 | |
382 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 383 | hw_dbg("PHY Address %u is out of range\n", offset); |
bf6f7a92 | 384 | goto out; |
9d5c8243 AK |
385 | } |
386 | ||
bf6f7a92 AD |
387 | ret_val = hw->phy.ops.acquire(hw); |
388 | if (ret_val) | |
389 | goto out; | |
9d5c8243 | 390 | |
bf6f7a92 | 391 | ret_val = igb_read_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 392 | |
bf6f7a92 AD |
393 | hw->phy.ops.release(hw); |
394 | ||
395 | out: | |
396 | return ret_val; | |
9d5c8243 AK |
397 | } |
398 | ||
399 | /** | |
733596be | 400 | * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii |
9d5c8243 AK |
401 | * @hw: pointer to the HW structure |
402 | * @offset: register offset to write to | |
403 | * @data: data to write at register offset | |
404 | * | |
405 | * Writes the data to PHY register at the offset using the serial gigabit | |
406 | * media independent interface. | |
407 | **/ | |
408 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
409 | u16 data) | |
410 | { | |
bf6f7a92 AD |
411 | s32 ret_val = -E1000_ERR_PARAM; |
412 | ||
9d5c8243 AK |
413 | |
414 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 415 | hw_dbg("PHY Address %d is out of range\n", offset); |
bf6f7a92 | 416 | goto out; |
9d5c8243 AK |
417 | } |
418 | ||
bf6f7a92 AD |
419 | ret_val = hw->phy.ops.acquire(hw); |
420 | if (ret_val) | |
421 | goto out; | |
9d5c8243 | 422 | |
bf6f7a92 | 423 | ret_val = igb_write_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 424 | |
bf6f7a92 AD |
425 | hw->phy.ops.release(hw); |
426 | ||
427 | out: | |
428 | return ret_val; | |
9d5c8243 AK |
429 | } |
430 | ||
431 | /** | |
733596be | 432 | * igb_get_phy_id_82575 - Retrieve PHY addr and id |
9d5c8243 AK |
433 | * @hw: pointer to the HW structure |
434 | * | |
652fff32 | 435 | * Retrieves the PHY address and ID for both PHY's which do and do not use |
9d5c8243 AK |
436 | * sgmi interface. |
437 | **/ | |
438 | static s32 igb_get_phy_id_82575(struct e1000_hw *hw) | |
439 | { | |
440 | struct e1000_phy_info *phy = &hw->phy; | |
441 | s32 ret_val = 0; | |
442 | u16 phy_id; | |
2fb02a26 | 443 | u32 ctrl_ext; |
4085f746 | 444 | u32 mdic; |
9d5c8243 AK |
445 | |
446 | /* | |
447 | * For SGMII PHYs, we try the list of possible addresses until | |
448 | * we find one that works. For non-SGMII PHYs | |
449 | * (e.g. integrated copper PHYs), an address of 1 should | |
450 | * work. The result of this function should mean phy->phy_addr | |
451 | * and phy->id are set correctly. | |
452 | */ | |
453 | if (!(igb_sgmii_active_82575(hw))) { | |
454 | phy->addr = 1; | |
455 | ret_val = igb_get_phy_id(hw); | |
456 | goto out; | |
457 | } | |
458 | ||
4085f746 NN |
459 | if (igb_sgmii_uses_mdio_82575(hw)) { |
460 | switch (hw->mac.type) { | |
461 | case e1000_82575: | |
462 | case e1000_82576: | |
463 | mdic = rd32(E1000_MDIC); | |
464 | mdic &= E1000_MDIC_PHY_MASK; | |
465 | phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; | |
466 | break; | |
467 | case e1000_82580: | |
468 | case e1000_i350: | |
469 | mdic = rd32(E1000_MDICNFG); | |
470 | mdic &= E1000_MDICNFG_PHY_MASK; | |
471 | phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; | |
472 | break; | |
473 | default: | |
474 | ret_val = -E1000_ERR_PHY; | |
475 | goto out; | |
476 | break; | |
477 | } | |
478 | ret_val = igb_get_phy_id(hw); | |
479 | goto out; | |
480 | } | |
481 | ||
2fb02a26 AD |
482 | /* Power on sgmii phy if it is disabled */ |
483 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
484 | wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); | |
485 | wrfl(); | |
486 | msleep(300); | |
487 | ||
9d5c8243 AK |
488 | /* |
489 | * The address field in the I2CCMD register is 3 bits and 0 is invalid. | |
490 | * Therefore, we need to test 1-7 | |
491 | */ | |
492 | for (phy->addr = 1; phy->addr < 8; phy->addr++) { | |
493 | ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); | |
494 | if (ret_val == 0) { | |
652fff32 AK |
495 | hw_dbg("Vendor ID 0x%08X read at address %u\n", |
496 | phy_id, phy->addr); | |
9d5c8243 AK |
497 | /* |
498 | * At the time of this writing, The M88 part is | |
499 | * the only supported SGMII PHY product. | |
500 | */ | |
501 | if (phy_id == M88_VENDOR) | |
502 | break; | |
503 | } else { | |
652fff32 | 504 | hw_dbg("PHY address %u was unreadable\n", phy->addr); |
9d5c8243 AK |
505 | } |
506 | } | |
507 | ||
508 | /* A valid PHY type couldn't be found. */ | |
509 | if (phy->addr == 8) { | |
510 | phy->addr = 0; | |
511 | ret_val = -E1000_ERR_PHY; | |
512 | goto out; | |
2fb02a26 AD |
513 | } else { |
514 | ret_val = igb_get_phy_id(hw); | |
9d5c8243 AK |
515 | } |
516 | ||
2fb02a26 AD |
517 | /* restore previous sfp cage power state */ |
518 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
9d5c8243 AK |
519 | |
520 | out: | |
521 | return ret_val; | |
522 | } | |
523 | ||
524 | /** | |
733596be | 525 | * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset |
9d5c8243 AK |
526 | * @hw: pointer to the HW structure |
527 | * | |
528 | * Resets the PHY using the serial gigabit media independent interface. | |
529 | **/ | |
530 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) | |
531 | { | |
532 | s32 ret_val; | |
533 | ||
534 | /* | |
535 | * This isn't a true "hard" reset, but is the only reset | |
536 | * available to us at this time. | |
537 | */ | |
538 | ||
652fff32 | 539 | hw_dbg("Soft resetting SGMII attached PHY...\n"); |
9d5c8243 AK |
540 | |
541 | /* | |
542 | * SFP documentation requires the following to configure the SPF module | |
543 | * to work on SGMII. No further documentation is given. | |
544 | */ | |
a8d2a0c2 | 545 | ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); |
9d5c8243 AK |
546 | if (ret_val) |
547 | goto out; | |
548 | ||
549 | ret_val = igb_phy_sw_reset(hw); | |
550 | ||
551 | out: | |
552 | return ret_val; | |
553 | } | |
554 | ||
555 | /** | |
733596be | 556 | * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state |
9d5c8243 AK |
557 | * @hw: pointer to the HW structure |
558 | * @active: true to enable LPLU, false to disable | |
559 | * | |
560 | * Sets the LPLU D0 state according to the active flag. When | |
561 | * activating LPLU this function also disables smart speed | |
562 | * and vice versa. LPLU will not be activated unless the | |
563 | * device autonegotiation advertisement meets standards of | |
564 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
565 | * This is a function pointer entry point only called by | |
566 | * PHY setup routines. | |
567 | **/ | |
568 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) | |
569 | { | |
570 | struct e1000_phy_info *phy = &hw->phy; | |
571 | s32 ret_val; | |
572 | u16 data; | |
573 | ||
a8d2a0c2 | 574 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
575 | if (ret_val) |
576 | goto out; | |
577 | ||
578 | if (active) { | |
579 | data |= IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 580 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 581 | data); |
9d5c8243 AK |
582 | if (ret_val) |
583 | goto out; | |
584 | ||
585 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 586 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 587 | &data); |
9d5c8243 | 588 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
a8d2a0c2 | 589 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 590 | data); |
9d5c8243 AK |
591 | if (ret_val) |
592 | goto out; | |
593 | } else { | |
594 | data &= ~IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 595 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 596 | data); |
9d5c8243 AK |
597 | /* |
598 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
599 | * during Dx states where the power conservation is most | |
600 | * important. During driver activity we should enable | |
601 | * SmartSpeed, so performance is maintained. | |
602 | */ | |
603 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 604 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 605 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
606 | if (ret_val) |
607 | goto out; | |
608 | ||
609 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 610 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 611 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
612 | if (ret_val) |
613 | goto out; | |
614 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 615 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 616 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
617 | if (ret_val) |
618 | goto out; | |
619 | ||
620 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 621 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 622 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
623 | if (ret_val) |
624 | goto out; | |
625 | } | |
626 | } | |
627 | ||
628 | out: | |
629 | return ret_val; | |
630 | } | |
631 | ||
632 | /** | |
733596be | 633 | * igb_acquire_nvm_82575 - Request for access to EEPROM |
9d5c8243 AK |
634 | * @hw: pointer to the HW structure |
635 | * | |
652fff32 | 636 | * Acquire the necessary semaphores for exclusive access to the EEPROM. |
9d5c8243 AK |
637 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
638 | * Return successful if access grant bit set, else clear the request for | |
639 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
640 | **/ | |
641 | static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) | |
642 | { | |
643 | s32 ret_val; | |
644 | ||
645 | ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
646 | if (ret_val) | |
647 | goto out; | |
648 | ||
649 | ret_val = igb_acquire_nvm(hw); | |
650 | ||
651 | if (ret_val) | |
652 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
653 | ||
654 | out: | |
655 | return ret_val; | |
656 | } | |
657 | ||
658 | /** | |
733596be | 659 | * igb_release_nvm_82575 - Release exclusive access to EEPROM |
9d5c8243 AK |
660 | * @hw: pointer to the HW structure |
661 | * | |
662 | * Stop any current commands to the EEPROM and clear the EEPROM request bit, | |
663 | * then release the semaphores acquired. | |
664 | **/ | |
665 | static void igb_release_nvm_82575(struct e1000_hw *hw) | |
666 | { | |
667 | igb_release_nvm(hw); | |
668 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
669 | } | |
670 | ||
671 | /** | |
733596be | 672 | * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore |
9d5c8243 AK |
673 | * @hw: pointer to the HW structure |
674 | * @mask: specifies which semaphore to acquire | |
675 | * | |
676 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
677 | * will also specify which port we're acquiring the lock for. | |
678 | **/ | |
679 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
680 | { | |
681 | u32 swfw_sync; | |
682 | u32 swmask = mask; | |
683 | u32 fwmask = mask << 16; | |
684 | s32 ret_val = 0; | |
685 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ | |
686 | ||
687 | while (i < timeout) { | |
688 | if (igb_get_hw_semaphore(hw)) { | |
689 | ret_val = -E1000_ERR_SWFW_SYNC; | |
690 | goto out; | |
691 | } | |
692 | ||
693 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
694 | if (!(swfw_sync & (fwmask | swmask))) | |
695 | break; | |
696 | ||
697 | /* | |
698 | * Firmware currently using resource (fwmask) | |
699 | * or other software thread using resource (swmask) | |
700 | */ | |
701 | igb_put_hw_semaphore(hw); | |
702 | mdelay(5); | |
703 | i++; | |
704 | } | |
705 | ||
706 | if (i == timeout) { | |
652fff32 | 707 | hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
9d5c8243 AK |
708 | ret_val = -E1000_ERR_SWFW_SYNC; |
709 | goto out; | |
710 | } | |
711 | ||
712 | swfw_sync |= swmask; | |
713 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
714 | ||
715 | igb_put_hw_semaphore(hw); | |
716 | ||
717 | out: | |
718 | return ret_val; | |
719 | } | |
720 | ||
721 | /** | |
733596be | 722 | * igb_release_swfw_sync_82575 - Release SW/FW semaphore |
9d5c8243 AK |
723 | * @hw: pointer to the HW structure |
724 | * @mask: specifies which semaphore to acquire | |
725 | * | |
726 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
727 | * will also specify which port we're releasing the lock for. | |
728 | **/ | |
729 | static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
730 | { | |
731 | u32 swfw_sync; | |
732 | ||
733 | while (igb_get_hw_semaphore(hw) != 0); | |
734 | /* Empty */ | |
735 | ||
736 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
737 | swfw_sync &= ~mask; | |
738 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
739 | ||
740 | igb_put_hw_semaphore(hw); | |
741 | } | |
742 | ||
743 | /** | |
733596be | 744 | * igb_get_cfg_done_82575 - Read config done bit |
9d5c8243 AK |
745 | * @hw: pointer to the HW structure |
746 | * | |
747 | * Read the management control register for the config done bit for | |
748 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | |
749 | * to read the config done bit, so an error is *ONLY* logged and returns | |
750 | * 0. If we were to return with error, EEPROM-less silicon | |
751 | * would not be able to be reset or change link. | |
752 | **/ | |
753 | static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) | |
754 | { | |
755 | s32 timeout = PHY_CFG_TIMEOUT; | |
756 | s32 ret_val = 0; | |
757 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
758 | ||
759 | if (hw->bus.func == 1) | |
760 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
bb2ac47b AD |
761 | else if (hw->bus.func == E1000_FUNC_2) |
762 | mask = E1000_NVM_CFG_DONE_PORT_2; | |
763 | else if (hw->bus.func == E1000_FUNC_3) | |
764 | mask = E1000_NVM_CFG_DONE_PORT_3; | |
9d5c8243 AK |
765 | |
766 | while (timeout) { | |
767 | if (rd32(E1000_EEMNGCTL) & mask) | |
768 | break; | |
769 | msleep(1); | |
770 | timeout--; | |
771 | } | |
772 | if (!timeout) | |
652fff32 | 773 | hw_dbg("MNG configuration cycle has not completed.\n"); |
9d5c8243 AK |
774 | |
775 | /* If EEPROM is not marked present, init the PHY manually */ | |
776 | if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && | |
777 | (hw->phy.type == e1000_phy_igp_3)) | |
778 | igb_phy_init_script_igp3(hw); | |
779 | ||
780 | return ret_val; | |
781 | } | |
782 | ||
783 | /** | |
733596be | 784 | * igb_check_for_link_82575 - Check for link |
9d5c8243 AK |
785 | * @hw: pointer to the HW structure |
786 | * | |
787 | * If sgmii is enabled, then use the pcs register to determine link, otherwise | |
788 | * use the generic interface for determining link. | |
789 | **/ | |
790 | static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |
791 | { | |
792 | s32 ret_val; | |
793 | u16 speed, duplex; | |
794 | ||
70d92f86 | 795 | if (hw->phy.media_type != e1000_media_type_copper) { |
9d5c8243 | 796 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
2d064c06 | 797 | &duplex); |
5d0932a5 AD |
798 | /* |
799 | * Use this flag to determine if link needs to be checked or | |
800 | * not. If we have link clear the flag so that we do not | |
801 | * continue to check for link. | |
802 | */ | |
803 | hw->mac.get_link_status = !hw->mac.serdes_has_link; | |
804 | } else { | |
9d5c8243 | 805 | ret_val = igb_check_for_copper_link(hw); |
5d0932a5 | 806 | } |
9d5c8243 AK |
807 | |
808 | return ret_val; | |
809 | } | |
70d92f86 | 810 | |
88a268c1 NN |
811 | /** |
812 | * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown | |
813 | * @hw: pointer to the HW structure | |
814 | **/ | |
815 | void igb_power_up_serdes_link_82575(struct e1000_hw *hw) | |
816 | { | |
817 | u32 reg; | |
818 | ||
819 | ||
820 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
821 | !igb_sgmii_active_82575(hw)) | |
822 | return; | |
823 | ||
824 | /* Enable PCS to turn on link */ | |
825 | reg = rd32(E1000_PCS_CFG0); | |
826 | reg |= E1000_PCS_CFG_PCS_EN; | |
827 | wr32(E1000_PCS_CFG0, reg); | |
828 | ||
829 | /* Power up the laser */ | |
830 | reg = rd32(E1000_CTRL_EXT); | |
831 | reg &= ~E1000_CTRL_EXT_SDP3_DATA; | |
832 | wr32(E1000_CTRL_EXT, reg); | |
833 | ||
834 | /* flush the write to verify completion */ | |
835 | wrfl(); | |
836 | msleep(1); | |
837 | } | |
838 | ||
9d5c8243 | 839 | /** |
733596be | 840 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
9d5c8243 AK |
841 | * @hw: pointer to the HW structure |
842 | * @speed: stores the current speed | |
843 | * @duplex: stores the current duplex | |
844 | * | |
652fff32 | 845 | * Using the physical coding sub-layer (PCS), retrieve the current speed and |
9d5c8243 AK |
846 | * duplex, then store the values in the pointers provided. |
847 | **/ | |
848 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, | |
849 | u16 *duplex) | |
850 | { | |
851 | struct e1000_mac_info *mac = &hw->mac; | |
852 | u32 pcs; | |
853 | ||
854 | /* Set up defaults for the return values of this function */ | |
855 | mac->serdes_has_link = false; | |
856 | *speed = 0; | |
857 | *duplex = 0; | |
858 | ||
859 | /* | |
860 | * Read the PCS Status register for link state. For non-copper mode, | |
861 | * the status register is not accurate. The PCS status register is | |
862 | * used instead. | |
863 | */ | |
864 | pcs = rd32(E1000_PCS_LSTAT); | |
865 | ||
866 | /* | |
867 | * The link up bit determines when link is up on autoneg. The sync ok | |
868 | * gets set once both sides sync up and agree upon link. Stable link | |
869 | * can be determined by checking for both link up and link sync ok | |
870 | */ | |
871 | if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { | |
872 | mac->serdes_has_link = true; | |
873 | ||
874 | /* Detect and store PCS speed */ | |
875 | if (pcs & E1000_PCS_LSTS_SPEED_1000) { | |
876 | *speed = SPEED_1000; | |
877 | } else if (pcs & E1000_PCS_LSTS_SPEED_100) { | |
878 | *speed = SPEED_100; | |
879 | } else { | |
880 | *speed = SPEED_10; | |
881 | } | |
882 | ||
883 | /* Detect and store PCS duplex */ | |
884 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { | |
885 | *duplex = FULL_DUPLEX; | |
886 | } else { | |
887 | *duplex = HALF_DUPLEX; | |
888 | } | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
2d064c06 | 894 | /** |
2fb02a26 | 895 | * igb_shutdown_serdes_link_82575 - Remove link during power down |
9d5c8243 | 896 | * @hw: pointer to the HW structure |
9d5c8243 | 897 | * |
2d064c06 AD |
898 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
899 | * when management pass thru is not enabled. | |
9d5c8243 | 900 | **/ |
2fb02a26 | 901 | void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 902 | { |
2d064c06 AD |
903 | u32 reg; |
904 | ||
53c992fa | 905 | if (hw->phy.media_type != e1000_media_type_internal_serdes && |
2fb02a26 | 906 | igb_sgmii_active_82575(hw)) |
2d064c06 AD |
907 | return; |
908 | ||
53c992fa | 909 | if (!igb_enable_mng_pass_thru(hw)) { |
2d064c06 AD |
910 | /* Disable PCS to turn off link */ |
911 | reg = rd32(E1000_PCS_CFG0); | |
912 | reg &= ~E1000_PCS_CFG_PCS_EN; | |
913 | wr32(E1000_PCS_CFG0, reg); | |
914 | ||
915 | /* shutdown the laser */ | |
916 | reg = rd32(E1000_CTRL_EXT); | |
2fb02a26 | 917 | reg |= E1000_CTRL_EXT_SDP3_DATA; |
2d064c06 AD |
918 | wr32(E1000_CTRL_EXT, reg); |
919 | ||
920 | /* flush the write to verify completion */ | |
921 | wrfl(); | |
922 | msleep(1); | |
923 | } | |
9d5c8243 AK |
924 | } |
925 | ||
926 | /** | |
733596be | 927 | * igb_reset_hw_82575 - Reset hardware |
9d5c8243 AK |
928 | * @hw: pointer to the HW structure |
929 | * | |
930 | * This resets the hardware into a known state. This is a | |
931 | * function pointer entry point called by the api module. | |
932 | **/ | |
933 | static s32 igb_reset_hw_82575(struct e1000_hw *hw) | |
934 | { | |
935 | u32 ctrl, icr; | |
936 | s32 ret_val; | |
937 | ||
938 | /* | |
939 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
940 | * on the last TLP read/write transaction when MAC is reset. | |
941 | */ | |
942 | ret_val = igb_disable_pcie_master(hw); | |
943 | if (ret_val) | |
652fff32 | 944 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
9d5c8243 | 945 | |
009bc06e AD |
946 | /* set the completion timeout for interface */ |
947 | ret_val = igb_set_pcie_completion_timeout(hw); | |
948 | if (ret_val) { | |
949 | hw_dbg("PCI-E Set completion timeout has failed.\n"); | |
950 | } | |
951 | ||
652fff32 | 952 | hw_dbg("Masking off all interrupts\n"); |
9d5c8243 AK |
953 | wr32(E1000_IMC, 0xffffffff); |
954 | ||
955 | wr32(E1000_RCTL, 0); | |
956 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
957 | wrfl(); | |
958 | ||
959 | msleep(10); | |
960 | ||
961 | ctrl = rd32(E1000_CTRL); | |
962 | ||
652fff32 | 963 | hw_dbg("Issuing a global reset to MAC\n"); |
9d5c8243 AK |
964 | wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); |
965 | ||
966 | ret_val = igb_get_auto_rd_done(hw); | |
967 | if (ret_val) { | |
968 | /* | |
969 | * When auto config read does not complete, do not | |
970 | * return with an error. This can happen in situations | |
971 | * where there is no eeprom and prevents getting link. | |
972 | */ | |
652fff32 | 973 | hw_dbg("Auto Read Done did not complete\n"); |
9d5c8243 AK |
974 | } |
975 | ||
976 | /* If EEPROM is not present, run manual init scripts */ | |
977 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
978 | igb_reset_init_script_82575(hw); | |
979 | ||
980 | /* Clear any pending interrupt events. */ | |
981 | wr32(E1000_IMC, 0xffffffff); | |
982 | icr = rd32(E1000_ICR); | |
983 | ||
5ac16659 AD |
984 | /* Install any alternate MAC address into RAR0 */ |
985 | ret_val = igb_check_alt_mac_addr(hw); | |
9d5c8243 AK |
986 | |
987 | return ret_val; | |
988 | } | |
989 | ||
990 | /** | |
733596be | 991 | * igb_init_hw_82575 - Initialize hardware |
9d5c8243 AK |
992 | * @hw: pointer to the HW structure |
993 | * | |
994 | * This inits the hardware readying it for operation. | |
995 | **/ | |
996 | static s32 igb_init_hw_82575(struct e1000_hw *hw) | |
997 | { | |
998 | struct e1000_mac_info *mac = &hw->mac; | |
999 | s32 ret_val; | |
1000 | u16 i, rar_count = mac->rar_entry_count; | |
1001 | ||
1002 | /* Initialize identification LED */ | |
1003 | ret_val = igb_id_led_init(hw); | |
1004 | if (ret_val) { | |
652fff32 | 1005 | hw_dbg("Error initializing identification LED\n"); |
9d5c8243 AK |
1006 | /* This is not fatal and we should not stop init due to this */ |
1007 | } | |
1008 | ||
1009 | /* Disabling VLAN filtering */ | |
652fff32 | 1010 | hw_dbg("Initializing the IEEE VLAN\n"); |
9d5c8243 AK |
1011 | igb_clear_vfta(hw); |
1012 | ||
1013 | /* Setup the receive address */ | |
5ac16659 AD |
1014 | igb_init_rx_addrs(hw, rar_count); |
1015 | ||
9d5c8243 | 1016 | /* Zero out the Multicast HASH table */ |
652fff32 | 1017 | hw_dbg("Zeroing the MTA\n"); |
9d5c8243 AK |
1018 | for (i = 0; i < mac->mta_reg_count; i++) |
1019 | array_wr32(E1000_MTA, i, 0); | |
1020 | ||
68d480c4 AD |
1021 | /* Zero out the Unicast HASH table */ |
1022 | hw_dbg("Zeroing the UTA\n"); | |
1023 | for (i = 0; i < mac->uta_reg_count; i++) | |
1024 | array_wr32(E1000_UTA, i, 0); | |
1025 | ||
9d5c8243 AK |
1026 | /* Setup link and flow control */ |
1027 | ret_val = igb_setup_link(hw); | |
1028 | ||
1029 | /* | |
1030 | * Clear all of the statistics registers (clear on read). It is | |
1031 | * important that we do this after we have tried to establish link | |
1032 | * because the symbol error count will increment wildly if there | |
1033 | * is no link. | |
1034 | */ | |
1035 | igb_clear_hw_cntrs_82575(hw); | |
1036 | ||
1037 | return ret_val; | |
1038 | } | |
1039 | ||
1040 | /** | |
733596be | 1041 | * igb_setup_copper_link_82575 - Configure copper link settings |
9d5c8243 AK |
1042 | * @hw: pointer to the HW structure |
1043 | * | |
1044 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1045 | * for link, once link is established calls to configure collision distance | |
1046 | * and flow control are called. | |
1047 | **/ | |
1048 | static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) | |
1049 | { | |
12645a19 | 1050 | u32 ctrl; |
9d5c8243 | 1051 | s32 ret_val; |
9d5c8243 AK |
1052 | |
1053 | ctrl = rd32(E1000_CTRL); | |
1054 | ctrl |= E1000_CTRL_SLU; | |
1055 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1056 | wr32(E1000_CTRL, ctrl); | |
1057 | ||
2fb02a26 AD |
1058 | ret_val = igb_setup_serdes_link_82575(hw); |
1059 | if (ret_val) | |
1060 | goto out; | |
1061 | ||
1062 | if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { | |
bb2ac47b AD |
1063 | /* allow time for SFP cage time to power up phy */ |
1064 | msleep(300); | |
1065 | ||
2fb02a26 AD |
1066 | ret_val = hw->phy.ops.reset(hw); |
1067 | if (ret_val) { | |
1068 | hw_dbg("Error resetting the PHY.\n"); | |
1069 | goto out; | |
1070 | } | |
1071 | } | |
9d5c8243 AK |
1072 | switch (hw->phy.type) { |
1073 | case e1000_phy_m88: | |
308fb39a JG |
1074 | if (hw->phy.id == I347AT4_E_PHY_ID || |
1075 | hw->phy.id == M88E1112_E_PHY_ID) | |
1076 | ret_val = igb_copper_link_setup_m88_gen2(hw); | |
1077 | else | |
1078 | ret_val = igb_copper_link_setup_m88(hw); | |
9d5c8243 AK |
1079 | break; |
1080 | case e1000_phy_igp_3: | |
1081 | ret_val = igb_copper_link_setup_igp(hw); | |
9d5c8243 | 1082 | break; |
bb2ac47b AD |
1083 | case e1000_phy_82580: |
1084 | ret_val = igb_copper_link_setup_82580(hw); | |
1085 | break; | |
9d5c8243 AK |
1086 | default: |
1087 | ret_val = -E1000_ERR_PHY; | |
1088 | break; | |
1089 | } | |
1090 | ||
1091 | if (ret_val) | |
1092 | goto out; | |
1093 | ||
81fadd81 | 1094 | ret_val = igb_setup_copper_link(hw); |
9d5c8243 AK |
1095 | out: |
1096 | return ret_val; | |
1097 | } | |
1098 | ||
1099 | /** | |
70d92f86 | 1100 | * igb_setup_serdes_link_82575 - Setup link for serdes |
9d5c8243 AK |
1101 | * @hw: pointer to the HW structure |
1102 | * | |
70d92f86 AD |
1103 | * Configure the physical coding sub-layer (PCS) link. The PCS link is |
1104 | * used on copper connections where the serialized gigabit media independent | |
1105 | * interface (sgmii), or serdes fiber is being used. Configures the link | |
1106 | * for auto-negotiation or forces speed/duplex. | |
9d5c8243 | 1107 | **/ |
2fb02a26 | 1108 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 1109 | { |
bb2ac47b AD |
1110 | u32 ctrl_ext, ctrl_reg, reg; |
1111 | bool pcs_autoneg; | |
2fb02a26 AD |
1112 | |
1113 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
1114 | !igb_sgmii_active_82575(hw)) | |
1115 | return 0; | |
9d5c8243 AK |
1116 | |
1117 | /* | |
1118 | * On the 82575, SerDes loopback mode persists until it is | |
1119 | * explicitly turned off or a power cycle is performed. A read to | |
1120 | * the register does not indicate its status. Therefore, we ensure | |
1121 | * loopback mode is disabled during initialization. | |
1122 | */ | |
1123 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); | |
1124 | ||
2fb02a26 | 1125 | /* power on the sfp cage if present */ |
bb2ac47b AD |
1126 | ctrl_ext = rd32(E1000_CTRL_EXT); |
1127 | ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; | |
1128 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
2fb02a26 AD |
1129 | |
1130 | ctrl_reg = rd32(E1000_CTRL); | |
1131 | ctrl_reg |= E1000_CTRL_SLU; | |
1132 | ||
1133 | if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { | |
1134 | /* set both sw defined pins */ | |
1135 | ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; | |
1136 | ||
1137 | /* Set switch control to serdes energy detect */ | |
1138 | reg = rd32(E1000_CONNSW); | |
1139 | reg |= E1000_CONNSW_ENRGSRC; | |
1140 | wr32(E1000_CONNSW, reg); | |
1141 | } | |
1142 | ||
1143 | reg = rd32(E1000_PCS_LCTL); | |
1144 | ||
bb2ac47b AD |
1145 | /* default pcs_autoneg to the same setting as mac autoneg */ |
1146 | pcs_autoneg = hw->mac.autoneg; | |
2fb02a26 | 1147 | |
bb2ac47b AD |
1148 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
1149 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
1150 | /* sgmii mode lets the phy handle forcing speed/duplex */ | |
1151 | pcs_autoneg = true; | |
1152 | /* autoneg time out should be disabled for SGMII mode */ | |
2fb02a26 | 1153 | reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); |
bb2ac47b AD |
1154 | break; |
1155 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: | |
1156 | /* disable PCS autoneg and support parallel detect only */ | |
1157 | pcs_autoneg = false; | |
1158 | default: | |
1159 | /* | |
1160 | * non-SGMII modes only supports a speed of 1000/Full for the | |
1161 | * link so it is best to just force the MAC and let the pcs | |
1162 | * link either autoneg or be forced to 1000/Full | |
1163 | */ | |
2fb02a26 AD |
1164 | ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | |
1165 | E1000_CTRL_FD | E1000_CTRL_FRCDPX; | |
bb2ac47b AD |
1166 | |
1167 | /* set speed of 1000/Full if speed/duplex is forced */ | |
1168 | reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; | |
1169 | break; | |
921aa749 AD |
1170 | } |
1171 | ||
2fb02a26 | 1172 | wr32(E1000_CTRL, ctrl_reg); |
9d5c8243 AK |
1173 | |
1174 | /* | |
1175 | * New SerDes mode allows for forcing speed or autonegotiating speed | |
1176 | * at 1gb. Autoneg should be default set by most drivers. This is the | |
1177 | * mode that will be compatible with older link partners and switches. | |
1178 | * However, both are supported by the hardware and some drivers/tools. | |
1179 | */ | |
9d5c8243 AK |
1180 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
1181 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | |
1182 | ||
2fb02a26 AD |
1183 | /* |
1184 | * We force flow control to prevent the CTRL register values from being | |
1185 | * overwritten by the autonegotiated flow control values | |
1186 | */ | |
1187 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1188 | ||
bb2ac47b | 1189 | if (pcs_autoneg) { |
9d5c8243 | 1190 | /* Set PCS register for autoneg */ |
bb2ac47b | 1191 | reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ |
70d92f86 | 1192 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ |
bb2ac47b | 1193 | hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); |
9d5c8243 | 1194 | } else { |
bb2ac47b | 1195 | /* Set PCS register for forced link */ |
d68caec6 | 1196 | reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ |
bb2ac47b AD |
1197 | |
1198 | hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); | |
9d5c8243 | 1199 | } |
726c09e7 | 1200 | |
9d5c8243 AK |
1201 | wr32(E1000_PCS_LCTL, reg); |
1202 | ||
2fb02a26 AD |
1203 | if (!igb_sgmii_active_82575(hw)) |
1204 | igb_force_mac_fc(hw); | |
9d5c8243 | 1205 | |
2fb02a26 | 1206 | return 0; |
9d5c8243 AK |
1207 | } |
1208 | ||
1209 | /** | |
733596be | 1210 | * igb_sgmii_active_82575 - Return sgmii state |
9d5c8243 AK |
1211 | * @hw: pointer to the HW structure |
1212 | * | |
1213 | * 82575 silicon has a serialized gigabit media independent interface (sgmii) | |
1214 | * which can be enabled for use in the embedded applications. Simply | |
1215 | * return the current state of the sgmii interface. | |
1216 | **/ | |
1217 | static bool igb_sgmii_active_82575(struct e1000_hw *hw) | |
1218 | { | |
c1889bfe | 1219 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
c1889bfe | 1220 | return dev_spec->sgmii_active; |
9d5c8243 AK |
1221 | } |
1222 | ||
1223 | /** | |
733596be | 1224 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
9d5c8243 AK |
1225 | * @hw: pointer to the HW structure |
1226 | * | |
1227 | * Inits recommended HW defaults after a reset when there is no EEPROM | |
1228 | * detected. This is only for the 82575. | |
1229 | **/ | |
1230 | static s32 igb_reset_init_script_82575(struct e1000_hw *hw) | |
1231 | { | |
1232 | if (hw->mac.type == e1000_82575) { | |
652fff32 | 1233 | hw_dbg("Running reset init script for 82575\n"); |
9d5c8243 AK |
1234 | /* SerDes configuration via SERDESCTRL */ |
1235 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); | |
1236 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); | |
1237 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); | |
1238 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); | |
1239 | ||
1240 | /* CCM configuration via CCMCTL register */ | |
1241 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); | |
1242 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); | |
1243 | ||
1244 | /* PCIe lanes configuration */ | |
1245 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); | |
1246 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); | |
1247 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); | |
1248 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); | |
1249 | ||
1250 | /* PCIe PLL Configuration */ | |
1251 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); | |
1252 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); | |
1253 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); | |
1254 | } | |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | /** | |
733596be | 1260 | * igb_read_mac_addr_82575 - Read device MAC address |
9d5c8243 AK |
1261 | * @hw: pointer to the HW structure |
1262 | **/ | |
1263 | static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) | |
1264 | { | |
1265 | s32 ret_val = 0; | |
1266 | ||
22896639 AD |
1267 | /* |
1268 | * If there's an alternate MAC address place it in RAR0 | |
1269 | * so that it will override the Si installed default perm | |
1270 | * address. | |
1271 | */ | |
1272 | ret_val = igb_check_alt_mac_addr(hw); | |
1273 | if (ret_val) | |
1274 | goto out; | |
1275 | ||
1276 | ret_val = igb_read_mac_addr(hw); | |
9d5c8243 | 1277 | |
22896639 | 1278 | out: |
9d5c8243 AK |
1279 | return ret_val; |
1280 | } | |
1281 | ||
88a268c1 NN |
1282 | /** |
1283 | * igb_power_down_phy_copper_82575 - Remove link during PHY power down | |
1284 | * @hw: pointer to the HW structure | |
1285 | * | |
1286 | * In the case of a PHY power down to save power, or to turn off link during a | |
1287 | * driver unload, or wake on lan is not enabled, remove the link. | |
1288 | **/ | |
1289 | void igb_power_down_phy_copper_82575(struct e1000_hw *hw) | |
1290 | { | |
1291 | /* If the management interface is not enabled, then power down */ | |
1292 | if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) | |
1293 | igb_power_down_phy_copper(hw); | |
88a268c1 NN |
1294 | } |
1295 | ||
9d5c8243 | 1296 | /** |
733596be | 1297 | * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters |
9d5c8243 AK |
1298 | * @hw: pointer to the HW structure |
1299 | * | |
1300 | * Clears the hardware counters by reading the counter registers. | |
1301 | **/ | |
1302 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) | |
1303 | { | |
9d5c8243 AK |
1304 | igb_clear_hw_cntrs_base(hw); |
1305 | ||
cc9073bb AD |
1306 | rd32(E1000_PRC64); |
1307 | rd32(E1000_PRC127); | |
1308 | rd32(E1000_PRC255); | |
1309 | rd32(E1000_PRC511); | |
1310 | rd32(E1000_PRC1023); | |
1311 | rd32(E1000_PRC1522); | |
1312 | rd32(E1000_PTC64); | |
1313 | rd32(E1000_PTC127); | |
1314 | rd32(E1000_PTC255); | |
1315 | rd32(E1000_PTC511); | |
1316 | rd32(E1000_PTC1023); | |
1317 | rd32(E1000_PTC1522); | |
1318 | ||
1319 | rd32(E1000_ALGNERRC); | |
1320 | rd32(E1000_RXERRC); | |
1321 | rd32(E1000_TNCRS); | |
1322 | rd32(E1000_CEXTERR); | |
1323 | rd32(E1000_TSCTC); | |
1324 | rd32(E1000_TSCTFC); | |
1325 | ||
1326 | rd32(E1000_MGTPRC); | |
1327 | rd32(E1000_MGTPDC); | |
1328 | rd32(E1000_MGTPTC); | |
1329 | ||
1330 | rd32(E1000_IAC); | |
1331 | rd32(E1000_ICRXOC); | |
1332 | ||
1333 | rd32(E1000_ICRXPTC); | |
1334 | rd32(E1000_ICRXATC); | |
1335 | rd32(E1000_ICTXPTC); | |
1336 | rd32(E1000_ICTXATC); | |
1337 | rd32(E1000_ICTXQEC); | |
1338 | rd32(E1000_ICTXQMTC); | |
1339 | rd32(E1000_ICRXDMTC); | |
1340 | ||
1341 | rd32(E1000_CBTMPC); | |
1342 | rd32(E1000_HTDPMC); | |
1343 | rd32(E1000_CBRMPC); | |
1344 | rd32(E1000_RPTHC); | |
1345 | rd32(E1000_HGPTC); | |
1346 | rd32(E1000_HTCBDPC); | |
1347 | rd32(E1000_HGORCL); | |
1348 | rd32(E1000_HGORCH); | |
1349 | rd32(E1000_HGOTCL); | |
1350 | rd32(E1000_HGOTCH); | |
1351 | rd32(E1000_LENERRS); | |
9d5c8243 AK |
1352 | |
1353 | /* This register should not be read in copper configurations */ | |
2fb02a26 AD |
1354 | if (hw->phy.media_type == e1000_media_type_internal_serdes || |
1355 | igb_sgmii_active_82575(hw)) | |
cc9073bb | 1356 | rd32(E1000_SCVPC); |
9d5c8243 AK |
1357 | } |
1358 | ||
662d7205 AD |
1359 | /** |
1360 | * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable | |
1361 | * @hw: pointer to the HW structure | |
1362 | * | |
1363 | * After rx enable if managability is enabled then there is likely some | |
1364 | * bad data at the start of the fifo and possibly in the DMA fifo. This | |
1365 | * function clears the fifos and flushes any packets that came in as rx was | |
1366 | * being enabled. | |
1367 | **/ | |
1368 | void igb_rx_fifo_flush_82575(struct e1000_hw *hw) | |
1369 | { | |
1370 | u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; | |
1371 | int i, ms_wait; | |
1372 | ||
1373 | if (hw->mac.type != e1000_82575 || | |
1374 | !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) | |
1375 | return; | |
1376 | ||
1377 | /* Disable all RX queues */ | |
1378 | for (i = 0; i < 4; i++) { | |
1379 | rxdctl[i] = rd32(E1000_RXDCTL(i)); | |
1380 | wr32(E1000_RXDCTL(i), | |
1381 | rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); | |
1382 | } | |
1383 | /* Poll all queues to verify they have shut down */ | |
1384 | for (ms_wait = 0; ms_wait < 10; ms_wait++) { | |
1385 | msleep(1); | |
1386 | rx_enabled = 0; | |
1387 | for (i = 0; i < 4; i++) | |
1388 | rx_enabled |= rd32(E1000_RXDCTL(i)); | |
1389 | if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) | |
1390 | break; | |
1391 | } | |
1392 | ||
1393 | if (ms_wait == 10) | |
1394 | hw_dbg("Queue disable timed out after 10ms\n"); | |
1395 | ||
1396 | /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all | |
1397 | * incoming packets are rejected. Set enable and wait 2ms so that | |
1398 | * any packet that was coming in as RCTL.EN was set is flushed | |
1399 | */ | |
1400 | rfctl = rd32(E1000_RFCTL); | |
1401 | wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); | |
1402 | ||
1403 | rlpml = rd32(E1000_RLPML); | |
1404 | wr32(E1000_RLPML, 0); | |
1405 | ||
1406 | rctl = rd32(E1000_RCTL); | |
1407 | temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); | |
1408 | temp_rctl |= E1000_RCTL_LPE; | |
1409 | ||
1410 | wr32(E1000_RCTL, temp_rctl); | |
1411 | wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); | |
1412 | wrfl(); | |
1413 | msleep(2); | |
1414 | ||
1415 | /* Enable RX queues that were previously enabled and restore our | |
1416 | * previous state | |
1417 | */ | |
1418 | for (i = 0; i < 4; i++) | |
1419 | wr32(E1000_RXDCTL(i), rxdctl[i]); | |
1420 | wr32(E1000_RCTL, rctl); | |
1421 | wrfl(); | |
1422 | ||
1423 | wr32(E1000_RLPML, rlpml); | |
1424 | wr32(E1000_RFCTL, rfctl); | |
1425 | ||
1426 | /* Flush receive errors generated by workaround */ | |
1427 | rd32(E1000_ROC); | |
1428 | rd32(E1000_RNBC); | |
1429 | rd32(E1000_MPC); | |
1430 | } | |
1431 | ||
009bc06e AD |
1432 | /** |
1433 | * igb_set_pcie_completion_timeout - set pci-e completion timeout | |
1434 | * @hw: pointer to the HW structure | |
1435 | * | |
1436 | * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, | |
1437 | * however the hardware default for these parts is 500us to 1ms which is less | |
1438 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
1439 | * increase the value to either 10ms to 200ms for capability version 1 config, | |
1440 | * or 16ms to 55ms for version 2. | |
1441 | **/ | |
1442 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) | |
1443 | { | |
1444 | u32 gcr = rd32(E1000_GCR); | |
1445 | s32 ret_val = 0; | |
1446 | u16 pcie_devctl2; | |
1447 | ||
1448 | /* only take action if timeout value is defaulted to 0 */ | |
1449 | if (gcr & E1000_GCR_CMPL_TMOUT_MASK) | |
1450 | goto out; | |
1451 | ||
1452 | /* | |
1453 | * if capababilities version is type 1 we can write the | |
1454 | * timeout of 10ms to 200ms through the GCR register | |
1455 | */ | |
1456 | if (!(gcr & E1000_GCR_CAP_VER2)) { | |
1457 | gcr |= E1000_GCR_CMPL_TMOUT_10ms; | |
1458 | goto out; | |
1459 | } | |
1460 | ||
1461 | /* | |
1462 | * for version 2 capabilities we need to write the config space | |
1463 | * directly in order to set the completion timeout value for | |
1464 | * 16ms to 55ms | |
1465 | */ | |
1466 | ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1467 | &pcie_devctl2); | |
1468 | if (ret_val) | |
1469 | goto out; | |
1470 | ||
1471 | pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; | |
1472 | ||
1473 | ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1474 | &pcie_devctl2); | |
1475 | out: | |
1476 | /* disable completion timeout resend */ | |
1477 | gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; | |
1478 | ||
1479 | wr32(E1000_GCR, gcr); | |
1480 | return ret_val; | |
1481 | } | |
1482 | ||
13800469 GR |
1483 | /** |
1484 | * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing | |
1485 | * @hw: pointer to the hardware struct | |
1486 | * @enable: state to enter, either enabled or disabled | |
1487 | * @pf: Physical Function pool - do not set anti-spoofing for the PF | |
1488 | * | |
1489 | * enables/disables L2 switch anti-spoofing functionality. | |
1490 | **/ | |
1491 | void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) | |
1492 | { | |
1493 | u32 dtxswc; | |
1494 | ||
1495 | switch (hw->mac.type) { | |
1496 | case e1000_82576: | |
1497 | case e1000_i350: | |
1498 | dtxswc = rd32(E1000_DTXSWC); | |
1499 | if (enable) { | |
1500 | dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | | |
1501 | E1000_DTXSWC_VLAN_SPOOF_MASK); | |
1502 | /* The PF can spoof - it has to in order to | |
1503 | * support emulation mode NICs */ | |
1504 | dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); | |
1505 | } else { | |
1506 | dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | | |
1507 | E1000_DTXSWC_VLAN_SPOOF_MASK); | |
1508 | } | |
1509 | wr32(E1000_DTXSWC, dtxswc); | |
1510 | break; | |
1511 | default: | |
1512 | break; | |
1513 | } | |
1514 | } | |
1515 | ||
4ae196df AD |
1516 | /** |
1517 | * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback | |
1518 | * @hw: pointer to the hardware struct | |
1519 | * @enable: state to enter, either enabled or disabled | |
1520 | * | |
1521 | * enables/disables L2 switch loopback functionality. | |
1522 | **/ | |
1523 | void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) | |
1524 | { | |
1525 | u32 dtxswc = rd32(E1000_DTXSWC); | |
1526 | ||
1527 | if (enable) | |
1528 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1529 | else | |
1530 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1531 | ||
1532 | wr32(E1000_DTXSWC, dtxswc); | |
1533 | } | |
1534 | ||
1535 | /** | |
1536 | * igb_vmdq_set_replication_pf - enable or disable vmdq replication | |
1537 | * @hw: pointer to the hardware struct | |
1538 | * @enable: state to enter, either enabled or disabled | |
1539 | * | |
1540 | * enables/disables replication of packets across multiple pools. | |
1541 | **/ | |
1542 | void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) | |
1543 | { | |
1544 | u32 vt_ctl = rd32(E1000_VT_CTL); | |
1545 | ||
1546 | if (enable) | |
1547 | vt_ctl |= E1000_VT_CTL_VM_REPL_EN; | |
1548 | else | |
1549 | vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; | |
1550 | ||
1551 | wr32(E1000_VT_CTL, vt_ctl); | |
1552 | } | |
1553 | ||
bb2ac47b AD |
1554 | /** |
1555 | * igb_read_phy_reg_82580 - Read 82580 MDI control register | |
1556 | * @hw: pointer to the HW structure | |
1557 | * @offset: register offset to be read | |
1558 | * @data: pointer to the read data | |
1559 | * | |
1560 | * Reads the MDI control register in the PHY at offset and stores the | |
1561 | * information read to data. | |
1562 | **/ | |
1563 | static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) | |
1564 | { | |
bb2ac47b AD |
1565 | s32 ret_val; |
1566 | ||
1567 | ||
1568 | ret_val = hw->phy.ops.acquire(hw); | |
1569 | if (ret_val) | |
1570 | goto out; | |
1571 | ||
bb2ac47b AD |
1572 | ret_val = igb_read_phy_reg_mdic(hw, offset, data); |
1573 | ||
1574 | hw->phy.ops.release(hw); | |
1575 | ||
1576 | out: | |
1577 | return ret_val; | |
1578 | } | |
1579 | ||
1580 | /** | |
1581 | * igb_write_phy_reg_82580 - Write 82580 MDI control register | |
1582 | * @hw: pointer to the HW structure | |
1583 | * @offset: register offset to write to | |
1584 | * @data: data to write to register at offset | |
1585 | * | |
1586 | * Writes data to MDI control register in the PHY at offset. | |
1587 | **/ | |
1588 | static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) | |
1589 | { | |
bb2ac47b AD |
1590 | s32 ret_val; |
1591 | ||
1592 | ||
1593 | ret_val = hw->phy.ops.acquire(hw); | |
1594 | if (ret_val) | |
1595 | goto out; | |
1596 | ||
bb2ac47b AD |
1597 | ret_val = igb_write_phy_reg_mdic(hw, offset, data); |
1598 | ||
1599 | hw->phy.ops.release(hw); | |
1600 | ||
1601 | out: | |
1602 | return ret_val; | |
1603 | } | |
1604 | ||
08451e25 NN |
1605 | /** |
1606 | * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits | |
1607 | * @hw: pointer to the HW structure | |
1608 | * | |
1609 | * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on | |
1610 | * the values found in the EEPROM. This addresses an issue in which these | |
1611 | * bits are not restored from EEPROM after reset. | |
1612 | **/ | |
1613 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) | |
1614 | { | |
1615 | s32 ret_val = 0; | |
1616 | u32 mdicnfg; | |
1b5dda33 | 1617 | u16 nvm_data = 0; |
08451e25 NN |
1618 | |
1619 | if (hw->mac.type != e1000_82580) | |
1620 | goto out; | |
1621 | if (!igb_sgmii_active_82575(hw)) | |
1622 | goto out; | |
1623 | ||
1624 | ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + | |
1625 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
1626 | &nvm_data); | |
1627 | if (ret_val) { | |
1628 | hw_dbg("NVM Read Error\n"); | |
1629 | goto out; | |
1630 | } | |
1631 | ||
1632 | mdicnfg = rd32(E1000_MDICNFG); | |
1633 | if (nvm_data & NVM_WORD24_EXT_MDIO) | |
1634 | mdicnfg |= E1000_MDICNFG_EXT_MDIO; | |
1635 | if (nvm_data & NVM_WORD24_COM_MDIO) | |
1636 | mdicnfg |= E1000_MDICNFG_COM_MDIO; | |
1637 | wr32(E1000_MDICNFG, mdicnfg); | |
1638 | out: | |
1639 | return ret_val; | |
1640 | } | |
1641 | ||
bb2ac47b AD |
1642 | /** |
1643 | * igb_reset_hw_82580 - Reset hardware | |
1644 | * @hw: pointer to the HW structure | |
1645 | * | |
1646 | * This resets function or entire device (all ports, etc.) | |
1647 | * to a known state. | |
1648 | **/ | |
1649 | static s32 igb_reset_hw_82580(struct e1000_hw *hw) | |
1650 | { | |
1651 | s32 ret_val = 0; | |
1652 | /* BH SW mailbox bit in SW_FW_SYNC */ | |
1653 | u16 swmbsw_mask = E1000_SW_SYNCH_MB; | |
1654 | u32 ctrl, icr; | |
1655 | bool global_device_reset = hw->dev_spec._82575.global_device_reset; | |
1656 | ||
1657 | ||
1658 | hw->dev_spec._82575.global_device_reset = false; | |
1659 | ||
1660 | /* Get current control state. */ | |
1661 | ctrl = rd32(E1000_CTRL); | |
1662 | ||
1663 | /* | |
1664 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
1665 | * on the last TLP read/write transaction when MAC is reset. | |
1666 | */ | |
1667 | ret_val = igb_disable_pcie_master(hw); | |
1668 | if (ret_val) | |
1669 | hw_dbg("PCI-E Master disable polling has failed.\n"); | |
1670 | ||
1671 | hw_dbg("Masking off all interrupts\n"); | |
1672 | wr32(E1000_IMC, 0xffffffff); | |
1673 | wr32(E1000_RCTL, 0); | |
1674 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
1675 | wrfl(); | |
1676 | ||
1677 | msleep(10); | |
1678 | ||
1679 | /* Determine whether or not a global dev reset is requested */ | |
1680 | if (global_device_reset && | |
1681 | igb_acquire_swfw_sync_82575(hw, swmbsw_mask)) | |
1682 | global_device_reset = false; | |
1683 | ||
1684 | if (global_device_reset && | |
1685 | !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) | |
1686 | ctrl |= E1000_CTRL_DEV_RST; | |
1687 | else | |
1688 | ctrl |= E1000_CTRL_RST; | |
1689 | ||
1690 | wr32(E1000_CTRL, ctrl); | |
1691 | ||
1692 | /* Add delay to insure DEV_RST has time to complete */ | |
1693 | if (global_device_reset) | |
1694 | msleep(5); | |
1695 | ||
1696 | ret_val = igb_get_auto_rd_done(hw); | |
1697 | if (ret_val) { | |
1698 | /* | |
1699 | * When auto config read does not complete, do not | |
1700 | * return with an error. This can happen in situations | |
1701 | * where there is no eeprom and prevents getting link. | |
1702 | */ | |
1703 | hw_dbg("Auto Read Done did not complete\n"); | |
1704 | } | |
1705 | ||
1706 | /* If EEPROM is not present, run manual init scripts */ | |
1707 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
1708 | igb_reset_init_script_82575(hw); | |
1709 | ||
1710 | /* clear global device reset status bit */ | |
1711 | wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); | |
1712 | ||
1713 | /* Clear any pending interrupt events. */ | |
1714 | wr32(E1000_IMC, 0xffffffff); | |
1715 | icr = rd32(E1000_ICR); | |
1716 | ||
08451e25 NN |
1717 | ret_val = igb_reset_mdicnfg_82580(hw); |
1718 | if (ret_val) | |
1719 | hw_dbg("Could not reset MDICNFG based on EEPROM\n"); | |
1720 | ||
bb2ac47b AD |
1721 | /* Install any alternate MAC address into RAR0 */ |
1722 | ret_val = igb_check_alt_mac_addr(hw); | |
1723 | ||
1724 | /* Release semaphore */ | |
1725 | if (global_device_reset) | |
1726 | igb_release_swfw_sync_82575(hw, swmbsw_mask); | |
1727 | ||
1728 | return ret_val; | |
1729 | } | |
1730 | ||
1731 | /** | |
1732 | * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size | |
1733 | * @data: data received by reading RXPBS register | |
1734 | * | |
1735 | * The 82580 uses a table based approach for packet buffer allocation sizes. | |
1736 | * This function converts the retrieved value into the correct table value | |
1737 | * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 | |
1738 | * 0x0 36 72 144 1 2 4 8 16 | |
1739 | * 0x8 35 70 140 rsv rsv rsv rsv rsv | |
1740 | */ | |
1741 | u16 igb_rxpbs_adjust_82580(u32 data) | |
1742 | { | |
1743 | u16 ret_val = 0; | |
1744 | ||
1745 | if (data < E1000_82580_RXPBS_TABLE_SIZE) | |
1746 | ret_val = e1000_82580_rxpbs_table[data]; | |
1747 | ||
1748 | return ret_val; | |
1749 | } | |
1750 | ||
9d5c8243 | 1751 | static struct e1000_mac_operations e1000_mac_ops_82575 = { |
9d5c8243 AK |
1752 | .init_hw = igb_init_hw_82575, |
1753 | .check_for_link = igb_check_for_link_82575, | |
2d064c06 | 1754 | .rar_set = igb_rar_set, |
9d5c8243 AK |
1755 | .read_mac_addr = igb_read_mac_addr_82575, |
1756 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, | |
1757 | }; | |
1758 | ||
1759 | static struct e1000_phy_operations e1000_phy_ops_82575 = { | |
a8d2a0c2 | 1760 | .acquire = igb_acquire_phy_82575, |
9d5c8243 | 1761 | .get_cfg_done = igb_get_cfg_done_82575, |
a8d2a0c2 | 1762 | .release = igb_release_phy_82575, |
9d5c8243 AK |
1763 | }; |
1764 | ||
1765 | static struct e1000_nvm_operations e1000_nvm_ops_82575 = { | |
312c75ae AD |
1766 | .acquire = igb_acquire_nvm_82575, |
1767 | .read = igb_read_nvm_eerd, | |
1768 | .release = igb_release_nvm_82575, | |
1769 | .write = igb_write_nvm_spi, | |
9d5c8243 AK |
1770 | }; |
1771 | ||
1772 | const struct e1000_info e1000_82575_info = { | |
1773 | .get_invariants = igb_get_invariants_82575, | |
1774 | .mac_ops = &e1000_mac_ops_82575, | |
1775 | .phy_ops = &e1000_phy_ops_82575, | |
1776 | .nvm_ops = &e1000_nvm_ops_82575, | |
1777 | }; | |
1778 |