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igb: Add anti-spoofing feature documentation
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
32#include <linux/types.h>
2d064c06 33#include <linux/if_ether.h>
9d5c8243
AK		 34
35#include "e1000_mac.h"
36#include "e1000_82575.h"
37
38static s32 igb_get_invariants_82575(struct e1000_hw *);
39static s32 igb_acquire_phy_82575(struct e1000_hw *);
40static void igb_release_phy_82575(struct e1000_hw *);
41static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42static void igb_release_nvm_82575(struct e1000_hw *);
43static s32 igb_check_for_link_82575(struct e1000_hw *);
44static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45static s32 igb_init_hw_82575(struct e1000_hw *);
46static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 48static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 50static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 51static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243
AK		 52static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 54static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 55static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
56static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
57static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 58static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
59 u16 *);
60static s32 igb_get_phy_id_82575(struct e1000_hw *);
61static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
62static bool igb_sgmii_active_82575(struct e1000_hw *);
63static s32 igb_reset_init_script_82575(struct e1000_hw *);
64static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 65static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
99870a73 66static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
4322e561
CW		 67static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
68static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
69static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw,
70 u16 offset);
71static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
72 u16 offset);
73static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
74static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
bb2ac47b
AD		 75static const u16 e1000_82580_rxpbs_table[] =
76 { 36, 72, 144, 1, 2, 4, 8, 16,
77 35, 70, 140 };
78#define E1000_82580_RXPBS_TABLE_SIZE \
79 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
80
4085f746
NN		 81/**
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
83 * @hw: pointer to the HW structure
84 *
85 * Called to determine if the I2C pins are being used for I2C or as an
86 * external MDIO interface since the two options are mutually exclusive.
87 **/
88static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
89{
90 u32 reg = 0;
91 bool ext_mdio = false;
92
93 switch (hw->mac.type) {
94 case e1000_82575:
95 case e1000_82576:
96 reg = rd32(E1000_MDIC);
97 ext_mdio = !!(reg & E1000_MDIC_DEST);
98 break;
99 case e1000_82580:
100 case e1000_i350:
101 reg = rd32(E1000_MDICNFG);
102 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
103 break;
104 default:
105 break;
106 }
107 return ext_mdio;
108}
109
9d5c8243
AK		 110static s32 igb_get_invariants_82575(struct e1000_hw *hw)
111{
112 struct e1000_phy_info *phy = &hw->phy;
113 struct e1000_nvm_info *nvm = &hw->nvm;
114 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 115 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243
AK		 116 u32 eecd;
117 s32 ret_val;
118 u16 size;
119 u32 ctrl_ext = 0;
120
121 switch (hw->device_id) {
122 case E1000_DEV_ID_82575EB_COPPER:
123 case E1000_DEV_ID_82575EB_FIBER_SERDES:
124 case E1000_DEV_ID_82575GB_QUAD_COPPER:
125 mac->type = e1000_82575;
126 break;
2d064c06 127 case E1000_DEV_ID_82576:
9eb2341d 128 case E1000_DEV_ID_82576_NS:
747d49ba 129 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 130 case E1000_DEV_ID_82576_FIBER:
131 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 132 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 133 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 134 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 135 mac->type = e1000_82576;
136 break;
bb2ac47b
AD		 137 case E1000_DEV_ID_82580_COPPER:
138 case E1000_DEV_ID_82580_FIBER:
6493d24f 139 case E1000_DEV_ID_82580_QUAD_FIBER:
bb2ac47b
AD		 140 case E1000_DEV_ID_82580_SERDES:
141 case E1000_DEV_ID_82580_SGMII:
142 case E1000_DEV_ID_82580_COPPER_DUAL:
308fb39a
JG		 143 case E1000_DEV_ID_DH89XXCC_SGMII:
144 case E1000_DEV_ID_DH89XXCC_SERDES:
1b5dda33
GJ		 145 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
146 case E1000_DEV_ID_DH89XXCC_SFP:
bb2ac47b
AD		 147 mac->type = e1000_82580;
148 break;
d2ba2ed8
AD		 149 case E1000_DEV_ID_I350_COPPER:
150 case E1000_DEV_ID_I350_FIBER:
151 case E1000_DEV_ID_I350_SERDES:
152 case E1000_DEV_ID_I350_SGMII:
153 mac->type = e1000_i350;
154 break;
9d5c8243
AK		 155 default:
156 return -E1000_ERR_MAC_INIT;
157 break;
158 }
159
9d5c8243
AK		 160 /* Set media type */
161 /*
162 * The 82575 uses bits 22:23 for link mode. The mode can be changed
163 * based on the EEPROM. We cannot rely upon device ID. There
164 * is no distinguishable difference between fiber and internal
165 * SerDes mode on the 82575. There can be an external PHY attached
166 * on the SGMII interface. For this, we'll set sgmii_active to true.
167 */
168 phy->media_type = e1000_media_type_copper;
169 dev_spec->sgmii_active = false;
170
171 ctrl_ext = rd32(E1000_CTRL_EXT);
2fb02a26
AD		 172 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
173 case E1000_CTRL_EXT_LINK_MODE_SGMII:
9d5c8243 174 dev_spec->sgmii_active = true;
2fb02a26 175 break;
bb2ac47b 176 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26
AD		 177 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
178 hw->phy.media_type = e1000_media_type_internal_serdes;
2fb02a26
AD		 179 break;
180 default:
2fb02a26 181 break;
9d5c8243 182 }
2fb02a26 183
9d5c8243
AK		 184 /* Set mta register count */
185 mac->mta_reg_count = 128;
186 /* Set rar entry count */
187 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
2d064c06
AD		 188 if (mac->type == e1000_82576)
189 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
bb2ac47b
AD		 190 if (mac->type == e1000_82580)
191 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
d2ba2ed8
AD		 192 if (mac->type == e1000_i350)
193 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
bb2ac47b 194 /* reset */
d2ba2ed8 195 if (mac->type >= e1000_82580)
bb2ac47b
AD		 196 mac->ops.reset_hw = igb_reset_hw_82580;
197 else
198 mac->ops.reset_hw = igb_reset_hw_82575;
9d5c8243
AK		 199 /* Set if part includes ASF firmware */
200 mac->asf_firmware_present = true;
201 /* Set if manageability features are enabled. */
202 mac->arc_subsystem_valid =
203 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
204 ? true : false;
09b068d4
CW		 205 /* enable EEE on i350 parts */
206 if (mac->type == e1000_i350)
207 dev_spec->eee_disable = false;
208 else
209 dev_spec->eee_disable = true;
9d5c8243
AK		 210 /* physical interface link setup */
211 mac->ops.setup_physical_interface =
212 (hw->phy.media_type == e1000_media_type_copper)
213 ? igb_setup_copper_link_82575
2fb02a26 214 : igb_setup_serdes_link_82575;
9d5c8243
AK		 215
216 /* NVM initialization */
217 eecd = rd32(E1000_EECD);
218
219 nvm->opcode_bits = 8;
220 nvm->delay_usec = 1;
221 switch (nvm->override) {
222 case e1000_nvm_override_spi_large:
223 nvm->page_size = 32;
224 nvm->address_bits = 16;
225 break;
226 case e1000_nvm_override_spi_small:
227 nvm->page_size = 8;
228 nvm->address_bits = 8;
229 break;
230 default:
231 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
232 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
233 break;
234 }
235
236 nvm->type = e1000_nvm_eeprom_spi;
237
238 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
239 E1000_EECD_SIZE_EX_SHIFT);
240
241 /*
242 * Added to a constant, "size" becomes the left-shift value
243 * for setting word_size.
244 */
245 size += NVM_WORD_SIZE_BASE_SHIFT;
5c3cad75 246
9d5c8243 247 nvm->word_size = 1 << size;
4322e561
CW		 248 if (nvm->word_size == (1 << 15))
249 nvm->page_size = 128;
250
251 /* NVM Function Pointers */
252 nvm->ops.acquire = igb_acquire_nvm_82575;
253 if (nvm->word_size < (1 << 15))
254 nvm->ops.read = igb_read_nvm_eerd;
255 else
256 nvm->ops.read = igb_read_nvm_spi;
257
258 nvm->ops.release = igb_release_nvm_82575;
259 switch (hw->mac.type) {
260 case e1000_82580:
261 nvm->ops.validate = igb_validate_nvm_checksum_82580;
262 nvm->ops.update = igb_update_nvm_checksum_82580;
263 break;
264 case e1000_i350:
265 nvm->ops.validate = igb_validate_nvm_checksum_i350;
266 nvm->ops.update = igb_update_nvm_checksum_i350;
267 break;
268 default:
269 nvm->ops.validate = igb_validate_nvm_checksum;
270 nvm->ops.update = igb_update_nvm_checksum;
271 }
272 nvm->ops.write = igb_write_nvm_spi;
9d5c8243 273
6b78bb1d
CW		 274 /* if part supports SR-IOV then initialize mailbox parameters */
275 switch (mac->type) {
276 case e1000_82576:
277 case e1000_i350:
a0c98605 278 igb_init_mbx_params_pf(hw);
6b78bb1d
CW		 279 break;
280 default:
281 break;
282 }
a0c98605 283
9d5c8243
AK		 284 /* setup PHY parameters */
285 if (phy->media_type != e1000_media_type_copper) {
286 phy->type = e1000_phy_none;
287 return 0;
288 }
289
290 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
291 phy->reset_delay_us = 100;
292
99870a73
AD		 293 ctrl_ext = rd32(E1000_CTRL_EXT);
294
9d5c8243 295 /* PHY function pointers */
99870a73 296 if (igb_sgmii_active_82575(hw)) {
4085f746 297 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
99870a73
AD		 298 ctrl_ext |= E1000_CTRL_I2C_ENA;
299 } else {
4085f746 300 phy->ops.reset = igb_phy_hw_reset;
99870a73
AD		 301 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
302 }
303
304 wr32(E1000_CTRL_EXT, ctrl_ext);
305 igb_reset_mdicnfg_82580(hw);
4085f746
NN		 306
307 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
308 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
309 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
d2ba2ed8 310 } else if (hw->mac.type >= e1000_82580) {
4085f746
NN		 311 phy->ops.read_reg = igb_read_phy_reg_82580;
312 phy->ops.write_reg = igb_write_phy_reg_82580;
9d5c8243 313 } else {
4085f746
NN		 314 phy->ops.read_reg = igb_read_phy_reg_igp;
315 phy->ops.write_reg = igb_write_phy_reg_igp;
9d5c8243
AK		 316 }
317
19e588e7
AD		 318 /* set lan id */
319 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
320 E1000_STATUS_FUNC_SHIFT;
321
9d5c8243
AK		 322 /* Set phy->phy_addr and phy->id. */
323 ret_val = igb_get_phy_id_82575(hw);
324 if (ret_val)
325 return ret_val;
326
327 /* Verify phy id and set remaining function pointers */
328 switch (phy->id) {
308fb39a
JG		 329 case I347AT4_E_PHY_ID:
330 case M88E1112_E_PHY_ID:
9d5c8243
AK		 331 case M88E1111_I_PHY_ID:
332 phy->type = e1000_phy_m88;
333 phy->ops.get_phy_info = igb_get_phy_info_m88;
308fb39a
JG		 334
335 if (phy->id == I347AT4_E_PHY_ID ||
336 phy->id == M88E1112_E_PHY_ID)
337 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
338 else
339 phy->ops.get_cable_length = igb_get_cable_length_m88;
340
9d5c8243
AK		 341 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
342 break;
343 case IGP03E1000_E_PHY_ID:
344 phy->type = e1000_phy_igp_3;
345 phy->ops.get_phy_info = igb_get_phy_info_igp;
346 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
347 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
348 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
349 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
350 break;
bb2ac47b 351 case I82580_I_PHY_ID:
d2ba2ed8 352 case I350_I_PHY_ID:
bb2ac47b
AD		 353 phy->type = e1000_phy_82580;
354 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
355 phy->ops.get_cable_length = igb_get_cable_length_82580;
356 phy->ops.get_phy_info = igb_get_phy_info_82580;
357 break;
9d5c8243
AK		 358 default:
359 return -E1000_ERR_PHY;
360 }
361
362 return 0;
363}
364
365/**
733596be 366 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 367 * @hw: pointer to the HW structure
368 *
369 * Acquire access rights to the correct PHY. This is a
370 * function pointer entry point called by the api module.
371 **/
372static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
373{
008c3422 374 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 375
008c3422
AD		 376 if (hw->bus.func == E1000_FUNC_1)
377 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 378 else if (hw->bus.func == E1000_FUNC_2)
379 mask = E1000_SWFW_PHY2_SM;
380 else if (hw->bus.func == E1000_FUNC_3)
381 mask = E1000_SWFW_PHY3_SM;
9d5c8243
AK		 382
383 return igb_acquire_swfw_sync_82575(hw, mask);
384}
385
386/**
733596be 387 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 388 * @hw: pointer to the HW structure
389 *
390 * A wrapper to release access rights to the correct PHY. This is a
391 * function pointer entry point called by the api module.
392 **/
393static void igb_release_phy_82575(struct e1000_hw *hw)
394{
008c3422
AD		 395 u16 mask = E1000_SWFW_PHY0_SM;
396
397 if (hw->bus.func == E1000_FUNC_1)
398 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 399 else if (hw->bus.func == E1000_FUNC_2)
400 mask = E1000_SWFW_PHY2_SM;
401 else if (hw->bus.func == E1000_FUNC_3)
402 mask = E1000_SWFW_PHY3_SM;
9d5c8243 403
9d5c8243
AK		 404 igb_release_swfw_sync_82575(hw, mask);
405}
406
407/**
733596be 408 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 409 * @hw: pointer to the HW structure
410 * @offset: register offset to be read
411 * @data: pointer to the read data
412 *
413 * Reads the PHY register at offset using the serial gigabit media independent
414 * interface and stores the retrieved information in data.
415 **/
416static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
417 u16 *data)
418{
bf6f7a92 419 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 420
421 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 422 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 423 goto out;
9d5c8243
AK		 424 }
425
bf6f7a92
AD		 426 ret_val = hw->phy.ops.acquire(hw);
427 if (ret_val)
428 goto out;
9d5c8243 429
bf6f7a92 430 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 431
bf6f7a92
AD		 432 hw->phy.ops.release(hw);
433
434out:
435 return ret_val;
9d5c8243
AK		 436}
437
438/**
733596be 439 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 440 * @hw: pointer to the HW structure
441 * @offset: register offset to write to
442 * @data: data to write at register offset
443 *
444 * Writes the data to PHY register at the offset using the serial gigabit
445 * media independent interface.
446 **/
447static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
448 u16 data)
449{
bf6f7a92
AD		 450 s32 ret_val = -E1000_ERR_PARAM;
451
9d5c8243
AK		 452
453 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 454 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 455 goto out;
9d5c8243
AK		 456 }
457
bf6f7a92
AD		 458 ret_val = hw->phy.ops.acquire(hw);
459 if (ret_val)
460 goto out;
9d5c8243 461
bf6f7a92 462 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 463
bf6f7a92
AD		 464 hw->phy.ops.release(hw);
465
466out:
467 return ret_val;
9d5c8243
AK		 468}
469
470/**
733596be 471 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 472 * @hw: pointer to the HW structure
473 *
652fff32 474 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 475 * sgmi interface.
476 **/
477static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
478{
479 struct e1000_phy_info *phy = &hw->phy;
480 s32 ret_val = 0;
481 u16 phy_id;
2fb02a26 482 u32 ctrl_ext;
4085f746 483 u32 mdic;
9d5c8243
AK		 484
485 /*
486 * For SGMII PHYs, we try the list of possible addresses until
487 * we find one that works. For non-SGMII PHYs
488 * (e.g. integrated copper PHYs), an address of 1 should
489 * work. The result of this function should mean phy->phy_addr
490 * and phy->id are set correctly.
491 */
492 if (!(igb_sgmii_active_82575(hw))) {
493 phy->addr = 1;
494 ret_val = igb_get_phy_id(hw);
495 goto out;
496 }
497
4085f746
NN		 498 if (igb_sgmii_uses_mdio_82575(hw)) {
499 switch (hw->mac.type) {
500 case e1000_82575:
501 case e1000_82576:
502 mdic = rd32(E1000_MDIC);
503 mdic &= E1000_MDIC_PHY_MASK;
504 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
505 break;
506 case e1000_82580:
507 case e1000_i350:
508 mdic = rd32(E1000_MDICNFG);
509 mdic &= E1000_MDICNFG_PHY_MASK;
510 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
511 break;
512 default:
513 ret_val = -E1000_ERR_PHY;
514 goto out;
515 break;
516 }
517 ret_val = igb_get_phy_id(hw);
518 goto out;
519 }
520
2fb02a26
AD		 521 /* Power on sgmii phy if it is disabled */
522 ctrl_ext = rd32(E1000_CTRL_EXT);
523 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
524 wrfl();
525 msleep(300);
526
9d5c8243
AK		 527 /*
528 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
529 * Therefore, we need to test 1-7
530 */
531 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
532 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
533 if (ret_val == 0) {
652fff32
AK		 534 hw_dbg("Vendor ID 0x%08X read at address %u\n",
535 phy_id, phy->addr);
9d5c8243
AK		 536 /*
537 * At the time of this writing, The M88 part is
538 * the only supported SGMII PHY product.
539 */
540 if (phy_id == M88_VENDOR)
541 break;
542 } else {
652fff32 543 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 544 }
545 }
546
547 /* A valid PHY type couldn't be found. */
548 if (phy->addr == 8) {
549 phy->addr = 0;
550 ret_val = -E1000_ERR_PHY;
551 goto out;
2fb02a26
AD		 552 } else {
553 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 554 }
555
2fb02a26
AD		 556 /* restore previous sfp cage power state */
557 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 558
559out:
560 return ret_val;
561}
562
563/**
733596be 564 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 565 * @hw: pointer to the HW structure
566 *
567 * Resets the PHY using the serial gigabit media independent interface.
568 **/
569static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
570{
571 s32 ret_val;
572
573 /*
574 * This isn't a true "hard" reset, but is the only reset
575 * available to us at this time.
576 */
577
652fff32 578 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243
AK		 579
580 /*
581 * SFP documentation requires the following to configure the SPF module
582 * to work on SGMII. No further documentation is given.
583 */
a8d2a0c2 584 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 585 if (ret_val)
586 goto out;
587
588 ret_val = igb_phy_sw_reset(hw);
589
590out:
591 return ret_val;
592}
593
594/**
733596be 595 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 596 * @hw: pointer to the HW structure
597 * @active: true to enable LPLU, false to disable
598 *
599 * Sets the LPLU D0 state according to the active flag. When
600 * activating LPLU this function also disables smart speed
601 * and vice versa. LPLU will not be activated unless the
602 * device autonegotiation advertisement meets standards of
603 * either 10 or 10/100 or 10/100/1000 at all duplexes.
604 * This is a function pointer entry point only called by
605 * PHY setup routines.
606 **/
607static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
608{
609 struct e1000_phy_info *phy = &hw->phy;
610 s32 ret_val;
611 u16 data;
612
a8d2a0c2 613 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 614 if (ret_val)
615 goto out;
616
617 if (active) {
618 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 619 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 620 data);
9d5c8243
AK		 621 if (ret_val)
622 goto out;
623
624 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 625 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 626 &data);
9d5c8243 627 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 628 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 629 data);
9d5c8243
AK		 630 if (ret_val)
631 goto out;
632 } else {
633 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 634 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 635 data);
9d5c8243
AK		 636 /*
637 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
638 * during Dx states where the power conservation is most
639 * important. During driver activity we should enable
640 * SmartSpeed, so performance is maintained.
641 */
642 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 643 ret_val = phy->ops.read_reg(hw,
652fff32 644 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 645 if (ret_val)
646 goto out;
647
648 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 649 ret_val = phy->ops.write_reg(hw,
652fff32 650 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 651 if (ret_val)
652 goto out;
653 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 654 ret_val = phy->ops.read_reg(hw,
652fff32 655 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 656 if (ret_val)
657 goto out;
658
659 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 660 ret_val = phy->ops.write_reg(hw,
652fff32 661 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 662 if (ret_val)
663 goto out;
664 }
665 }
666
667out:
668 return ret_val;
669}
670
671/**
733596be 672 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 673 * @hw: pointer to the HW structure
674 *
652fff32 675 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 676 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
677 * Return successful if access grant bit set, else clear the request for
678 * EEPROM access and return -E1000_ERR_NVM (-1).
679 **/
680static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
681{
682 s32 ret_val;
683
684 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
685 if (ret_val)
686 goto out;
687
688 ret_val = igb_acquire_nvm(hw);
689
690 if (ret_val)
691 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
692
693out:
694 return ret_val;
695}
696
697/**
733596be 698 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 699 * @hw: pointer to the HW structure
700 *
701 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
702 * then release the semaphores acquired.
703 **/
704static void igb_release_nvm_82575(struct e1000_hw *hw)
705{
706 igb_release_nvm(hw);
707 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
708}
709
710/**
733596be 711 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 712 * @hw: pointer to the HW structure
713 * @mask: specifies which semaphore to acquire
714 *
715 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
716 * will also specify which port we're acquiring the lock for.
717 **/
718static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
719{
720 u32 swfw_sync;
721 u32 swmask = mask;
722 u32 fwmask = mask << 16;
723 s32 ret_val = 0;
724 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
725
726 while (i < timeout) {
727 if (igb_get_hw_semaphore(hw)) {
728 ret_val = -E1000_ERR_SWFW_SYNC;
729 goto out;
730 }
731
732 swfw_sync = rd32(E1000_SW_FW_SYNC);
733 if (!(swfw_sync & (fwmask | swmask)))
734 break;
735
736 /*
737 * Firmware currently using resource (fwmask)
738 * or other software thread using resource (swmask)
739 */
740 igb_put_hw_semaphore(hw);
741 mdelay(5);
742 i++;
743 }
744
745 if (i == timeout) {
652fff32 746 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 747 ret_val = -E1000_ERR_SWFW_SYNC;
748 goto out;
749 }
750
751 swfw_sync |= swmask;
752 wr32(E1000_SW_FW_SYNC, swfw_sync);
753
754 igb_put_hw_semaphore(hw);
755
756out:
757 return ret_val;
758}
759
760/**
733596be 761 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 762 * @hw: pointer to the HW structure
763 * @mask: specifies which semaphore to acquire
764 *
765 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
766 * will also specify which port we're releasing the lock for.
767 **/
768static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
769{
770 u32 swfw_sync;
771
772 while (igb_get_hw_semaphore(hw) != 0);
773 /* Empty */
774
775 swfw_sync = rd32(E1000_SW_FW_SYNC);
776 swfw_sync &= ~mask;
777 wr32(E1000_SW_FW_SYNC, swfw_sync);
778
779 igb_put_hw_semaphore(hw);
780}
781
782/**
733596be 783 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 784 * @hw: pointer to the HW structure
785 *
786 * Read the management control register for the config done bit for
787 * completion status. NOTE: silicon which is EEPROM-less will fail trying
788 * to read the config done bit, so an error is *ONLY* logged and returns
789 * 0. If we were to return with error, EEPROM-less silicon
790 * would not be able to be reset or change link.
791 **/
792static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
793{
794 s32 timeout = PHY_CFG_TIMEOUT;
795 s32 ret_val = 0;
796 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
797
798 if (hw->bus.func == 1)
799 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 800 else if (hw->bus.func == E1000_FUNC_2)
801 mask = E1000_NVM_CFG_DONE_PORT_2;
802 else if (hw->bus.func == E1000_FUNC_3)
803 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 804
805 while (timeout) {
806 if (rd32(E1000_EEMNGCTL) & mask)
807 break;
808 msleep(1);
809 timeout--;
810 }
811 if (!timeout)
652fff32 812 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 813
814 /* If EEPROM is not marked present, init the PHY manually */
815 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
816 (hw->phy.type == e1000_phy_igp_3))
817 igb_phy_init_script_igp3(hw);
818
819 return ret_val;
820}
821
822/**
733596be 823 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 824 * @hw: pointer to the HW structure
825 *
826 * If sgmii is enabled, then use the pcs register to determine link, otherwise
827 * use the generic interface for determining link.
828 **/
829static s32 igb_check_for_link_82575(struct e1000_hw *hw)
830{
831 s32 ret_val;
832 u16 speed, duplex;
833
70d92f86 834 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 835 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 836 &duplex);
5d0932a5
AD		 837 /*
838 * Use this flag to determine if link needs to be checked or
839 * not. If we have link clear the flag so that we do not
840 * continue to check for link.
841 */
842 hw->mac.get_link_status = !hw->mac.serdes_has_link;
843 } else {
9d5c8243 844 ret_val = igb_check_for_copper_link(hw);
5d0932a5 845 }
9d5c8243
AK		 846
847 return ret_val;
848}
70d92f86 849
88a268c1
NN		 850/**
851 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
852 * @hw: pointer to the HW structure
853 **/
854void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
855{
856 u32 reg;
857
858
859 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
860 !igb_sgmii_active_82575(hw))
861 return;
862
863 /* Enable PCS to turn on link */
864 reg = rd32(E1000_PCS_CFG0);
865 reg |= E1000_PCS_CFG_PCS_EN;
866 wr32(E1000_PCS_CFG0, reg);
867
868 /* Power up the laser */
869 reg = rd32(E1000_CTRL_EXT);
870 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
871 wr32(E1000_CTRL_EXT, reg);
872
873 /* flush the write to verify completion */
874 wrfl();
875 msleep(1);
876}
877
9d5c8243 878/**
733596be 879 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 880 * @hw: pointer to the HW structure
881 * @speed: stores the current speed
882 * @duplex: stores the current duplex
883 *
652fff32 884 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 885 * duplex, then store the values in the pointers provided.
886 **/
887static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
888 u16 *duplex)
889{
890 struct e1000_mac_info *mac = &hw->mac;
891 u32 pcs;
892
893 /* Set up defaults for the return values of this function */
894 mac->serdes_has_link = false;
895 *speed = 0;
896 *duplex = 0;
897
898 /*
899 * Read the PCS Status register for link state. For non-copper mode,
900 * the status register is not accurate. The PCS status register is
901 * used instead.
902 */
903 pcs = rd32(E1000_PCS_LSTAT);
904
905 /*
906 * The link up bit determines when link is up on autoneg. The sync ok
907 * gets set once both sides sync up and agree upon link. Stable link
908 * can be determined by checking for both link up and link sync ok
909 */
910 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
911 mac->serdes_has_link = true;
912
913 /* Detect and store PCS speed */
914 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
915 *speed = SPEED_1000;
916 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
917 *speed = SPEED_100;
918 } else {
919 *speed = SPEED_10;
920 }
921
922 /* Detect and store PCS duplex */
923 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
924 *duplex = FULL_DUPLEX;
925 } else {
926 *duplex = HALF_DUPLEX;
927 }
928 }
929
930 return 0;
931}
932
2d064c06 933/**
2fb02a26 934 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 935 * @hw: pointer to the HW structure
9d5c8243 936 *
2d064c06
AD		 937 * In the case of fiber serdes, shut down optics and PCS on driver unload
938 * when management pass thru is not enabled.
9d5c8243 939 **/
2fb02a26 940void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 941{
2d064c06
AD		 942 u32 reg;
943
53c992fa 944 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 945 igb_sgmii_active_82575(hw))
2d064c06
AD		 946 return;
947
53c992fa 948 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 949 /* Disable PCS to turn off link */
950 reg = rd32(E1000_PCS_CFG0);
951 reg &= ~E1000_PCS_CFG_PCS_EN;
952 wr32(E1000_PCS_CFG0, reg);
953
954 /* shutdown the laser */
955 reg = rd32(E1000_CTRL_EXT);
2fb02a26 956 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 957 wr32(E1000_CTRL_EXT, reg);
958
959 /* flush the write to verify completion */
960 wrfl();
961 msleep(1);
962 }
9d5c8243
AK		 963}
964
965/**
733596be 966 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 967 * @hw: pointer to the HW structure
968 *
969 * This resets the hardware into a known state. This is a
970 * function pointer entry point called by the api module.
971 **/
972static s32 igb_reset_hw_82575(struct e1000_hw *hw)
973{
974 u32 ctrl, icr;
975 s32 ret_val;
976
977 /*
978 * Prevent the PCI-E bus from sticking if there is no TLP connection
979 * on the last TLP read/write transaction when MAC is reset.
980 */
981 ret_val = igb_disable_pcie_master(hw);
982 if (ret_val)
652fff32 983 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 984
009bc06e
AD		 985 /* set the completion timeout for interface */
986 ret_val = igb_set_pcie_completion_timeout(hw);
987 if (ret_val) {
988 hw_dbg("PCI-E Set completion timeout has failed.\n");
989 }
990
652fff32 991 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 992 wr32(E1000_IMC, 0xffffffff);
993
994 wr32(E1000_RCTL, 0);
995 wr32(E1000_TCTL, E1000_TCTL_PSP);
996 wrfl();
997
998 msleep(10);
999
1000 ctrl = rd32(E1000_CTRL);
1001
652fff32 1002 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 1003 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1004
1005 ret_val = igb_get_auto_rd_done(hw);
1006 if (ret_val) {
1007 /*
1008 * When auto config read does not complete, do not
1009 * return with an error. This can happen in situations
1010 * where there is no eeprom and prevents getting link.
1011 */
652fff32 1012 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 1013 }
1014
1015 /* If EEPROM is not present, run manual init scripts */
1016 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1017 igb_reset_init_script_82575(hw);
1018
1019 /* Clear any pending interrupt events. */
1020 wr32(E1000_IMC, 0xffffffff);
1021 icr = rd32(E1000_ICR);
1022
5ac16659
AD		 1023 /* Install any alternate MAC address into RAR0 */
1024 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 1025
1026 return ret_val;
1027}
1028
1029/**
733596be 1030 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 1031 * @hw: pointer to the HW structure
1032 *
1033 * This inits the hardware readying it for operation.
1034 **/
1035static s32 igb_init_hw_82575(struct e1000_hw *hw)
1036{
1037 struct e1000_mac_info *mac = &hw->mac;
1038 s32 ret_val;
1039 u16 i, rar_count = mac->rar_entry_count;
1040
1041 /* Initialize identification LED */
1042 ret_val = igb_id_led_init(hw);
1043 if (ret_val) {
652fff32 1044 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 1045 /* This is not fatal and we should not stop init due to this */
1046 }
1047
1048 /* Disabling VLAN filtering */
652fff32 1049 hw_dbg("Initializing the IEEE VLAN\n");
9d5c8243
AK		 1050 igb_clear_vfta(hw);
1051
1052 /* Setup the receive address */
5ac16659
AD		 1053 igb_init_rx_addrs(hw, rar_count);
1054
9d5c8243 1055 /* Zero out the Multicast HASH table */
652fff32 1056 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1057 for (i = 0; i < mac->mta_reg_count; i++)
1058 array_wr32(E1000_MTA, i, 0);
1059
68d480c4
AD		 1060 /* Zero out the Unicast HASH table */
1061 hw_dbg("Zeroing the UTA\n");
1062 for (i = 0; i < mac->uta_reg_count; i++)
1063 array_wr32(E1000_UTA, i, 0);
1064
9d5c8243
AK		 1065 /* Setup link and flow control */
1066 ret_val = igb_setup_link(hw);
1067
1068 /*
1069 * Clear all of the statistics registers (clear on read). It is
1070 * important that we do this after we have tried to establish link
1071 * because the symbol error count will increment wildly if there
1072 * is no link.
1073 */
1074 igb_clear_hw_cntrs_82575(hw);
1075
1076 return ret_val;
1077}
1078
1079/**
733596be 1080 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1081 * @hw: pointer to the HW structure
1082 *
1083 * Configures the link for auto-neg or forced speed and duplex. Then we check
1084 * for link, once link is established calls to configure collision distance
1085 * and flow control are called.
1086 **/
1087static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1088{
12645a19 1089 u32 ctrl;
9d5c8243 1090 s32 ret_val;
9d5c8243
AK		 1091
1092 ctrl = rd32(E1000_CTRL);
1093 ctrl |= E1000_CTRL_SLU;
1094 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1095 wr32(E1000_CTRL, ctrl);
1096
2fb02a26
AD		 1097 ret_val = igb_setup_serdes_link_82575(hw);
1098 if (ret_val)
1099 goto out;
1100
1101 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1102 /* allow time for SFP cage time to power up phy */
1103 msleep(300);
1104
2fb02a26
AD		 1105 ret_val = hw->phy.ops.reset(hw);
1106 if (ret_val) {
1107 hw_dbg("Error resetting the PHY.\n");
1108 goto out;
1109 }
1110 }
9d5c8243
AK		 1111 switch (hw->phy.type) {
1112 case e1000_phy_m88:
308fb39a
JG		 1113 if (hw->phy.id == I347AT4_E_PHY_ID ||
1114 hw->phy.id == M88E1112_E_PHY_ID)
1115 ret_val = igb_copper_link_setup_m88_gen2(hw);
1116 else
1117 ret_val = igb_copper_link_setup_m88(hw);
9d5c8243
AK		 1118 break;
1119 case e1000_phy_igp_3:
1120 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1121 break;
bb2ac47b
AD		 1122 case e1000_phy_82580:
1123 ret_val = igb_copper_link_setup_82580(hw);
1124 break;
9d5c8243
AK		 1125 default:
1126 ret_val = -E1000_ERR_PHY;
1127 break;
1128 }
1129
1130 if (ret_val)
1131 goto out;
1132
81fadd81 1133 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1134out:
1135 return ret_val;
1136}
1137
1138/**
70d92f86 1139 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1140 * @hw: pointer to the HW structure
1141 *
70d92f86
AD		 1142 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1143 * used on copper connections where the serialized gigabit media independent
1144 * interface (sgmii), or serdes fiber is being used. Configures the link
1145 * for auto-negotiation or forces speed/duplex.
9d5c8243 1146 **/
2fb02a26 1147static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1148{
bb2ac47b
AD		 1149 u32 ctrl_ext, ctrl_reg, reg;
1150 bool pcs_autoneg;
2fb02a26
AD		 1151
1152 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1153 !igb_sgmii_active_82575(hw))
1154 return 0;
9d5c8243
AK		 1155
1156 /*
1157 * On the 82575, SerDes loopback mode persists until it is
1158 * explicitly turned off or a power cycle is performed. A read to
1159 * the register does not indicate its status. Therefore, we ensure
1160 * loopback mode is disabled during initialization.
1161 */
1162 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1163
2fb02a26 1164 /* power on the sfp cage if present */
bb2ac47b
AD		 1165 ctrl_ext = rd32(E1000_CTRL_EXT);
1166 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1167 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1168
1169 ctrl_reg = rd32(E1000_CTRL);
1170 ctrl_reg |= E1000_CTRL_SLU;
1171
1172 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1173 /* set both sw defined pins */
1174 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1175
1176 /* Set switch control to serdes energy detect */
1177 reg = rd32(E1000_CONNSW);
1178 reg |= E1000_CONNSW_ENRGSRC;
1179 wr32(E1000_CONNSW, reg);
1180 }
1181
1182 reg = rd32(E1000_PCS_LCTL);
1183
bb2ac47b
AD		 1184 /* default pcs_autoneg to the same setting as mac autoneg */
1185 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1186
bb2ac47b
AD		 1187 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1188 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1189 /* sgmii mode lets the phy handle forcing speed/duplex */
1190 pcs_autoneg = true;
1191 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1192 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1193 break;
1194 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1195 /* disable PCS autoneg and support parallel detect only */
1196 pcs_autoneg = false;
1197 default:
1198 /*
1199 * non-SGMII modes only supports a speed of 1000/Full for the
1200 * link so it is best to just force the MAC and let the pcs
1201 * link either autoneg or be forced to 1000/Full
1202 */
2fb02a26
AD		 1203 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1204 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1205
1206 /* set speed of 1000/Full if speed/duplex is forced */
1207 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1208 break;
921aa749
AD		 1209 }
1210
2fb02a26 1211 wr32(E1000_CTRL, ctrl_reg);
9d5c8243
AK		 1212
1213 /*
1214 * New SerDes mode allows for forcing speed or autonegotiating speed
1215 * at 1gb. Autoneg should be default set by most drivers. This is the
1216 * mode that will be compatible with older link partners and switches.
1217 * However, both are supported by the hardware and some drivers/tools.
1218 */
9d5c8243
AK		 1219 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1220 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1221
2fb02a26
AD		 1222 /*
1223 * We force flow control to prevent the CTRL register values from being
1224 * overwritten by the autonegotiated flow control values
1225 */
1226 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1227
bb2ac47b 1228 if (pcs_autoneg) {
9d5c8243 1229 /* Set PCS register for autoneg */
bb2ac47b 1230 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1231 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
bb2ac47b 1232 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1233 } else {
bb2ac47b 1234 /* Set PCS register for forced link */
d68caec6 1235 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b
AD		 1236
1237 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1238 }
726c09e7 1239
9d5c8243
AK		 1240 wr32(E1000_PCS_LCTL, reg);
1241
2fb02a26
AD		 1242 if (!igb_sgmii_active_82575(hw))
1243 igb_force_mac_fc(hw);
9d5c8243 1244
2fb02a26 1245 return 0;
9d5c8243
AK		 1246}
1247
1248/**
733596be 1249 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1250 * @hw: pointer to the HW structure
1251 *
1252 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1253 * which can be enabled for use in the embedded applications. Simply
1254 * return the current state of the sgmii interface.
1255 **/
1256static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1257{
c1889bfe 1258 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1259 return dev_spec->sgmii_active;
9d5c8243
AK		 1260}
1261
1262/**
733596be 1263 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1264 * @hw: pointer to the HW structure
1265 *
1266 * Inits recommended HW defaults after a reset when there is no EEPROM
1267 * detected. This is only for the 82575.
1268 **/
1269static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1270{
1271 if (hw->mac.type == e1000_82575) {
652fff32 1272 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1273 /* SerDes configuration via SERDESCTRL */
1274 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1275 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1276 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1277 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1278
1279 /* CCM configuration via CCMCTL register */
1280 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1281 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1282
1283 /* PCIe lanes configuration */
1284 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1285 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1286 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1287 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1288
1289 /* PCIe PLL Configuration */
1290 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1291 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1292 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1293 }
1294
1295 return 0;
1296}
1297
1298/**
733596be 1299 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1300 * @hw: pointer to the HW structure
1301 **/
1302static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1303{
1304 s32 ret_val = 0;
1305
22896639
AD		 1306 /*
1307 * If there's an alternate MAC address place it in RAR0
1308 * so that it will override the Si installed default perm
1309 * address.
1310 */
1311 ret_val = igb_check_alt_mac_addr(hw);
1312 if (ret_val)
1313 goto out;
1314
1315 ret_val = igb_read_mac_addr(hw);
9d5c8243 1316
22896639 1317out:
9d5c8243
AK		 1318 return ret_val;
1319}
1320
88a268c1
NN		 1321/**
1322 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1323 * @hw: pointer to the HW structure
1324 *
1325 * In the case of a PHY power down to save power, or to turn off link during a
1326 * driver unload, or wake on lan is not enabled, remove the link.
1327 **/
1328void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1329{
1330 /* If the management interface is not enabled, then power down */
1331 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1332 igb_power_down_phy_copper(hw);
88a268c1
NN		 1333}
1334
9d5c8243 1335/**
733596be 1336 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1337 * @hw: pointer to the HW structure
1338 *
1339 * Clears the hardware counters by reading the counter registers.
1340 **/
1341static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1342{
9d5c8243
AK		 1343 igb_clear_hw_cntrs_base(hw);
1344
cc9073bb
AD		 1345 rd32(E1000_PRC64);
1346 rd32(E1000_PRC127);
1347 rd32(E1000_PRC255);
1348 rd32(E1000_PRC511);
1349 rd32(E1000_PRC1023);
1350 rd32(E1000_PRC1522);
1351 rd32(E1000_PTC64);
1352 rd32(E1000_PTC127);
1353 rd32(E1000_PTC255);
1354 rd32(E1000_PTC511);
1355 rd32(E1000_PTC1023);
1356 rd32(E1000_PTC1522);
1357
1358 rd32(E1000_ALGNERRC);
1359 rd32(E1000_RXERRC);
1360 rd32(E1000_TNCRS);
1361 rd32(E1000_CEXTERR);
1362 rd32(E1000_TSCTC);
1363 rd32(E1000_TSCTFC);
1364
1365 rd32(E1000_MGTPRC);
1366 rd32(E1000_MGTPDC);
1367 rd32(E1000_MGTPTC);
1368
1369 rd32(E1000_IAC);
1370 rd32(E1000_ICRXOC);
1371
1372 rd32(E1000_ICRXPTC);
1373 rd32(E1000_ICRXATC);
1374 rd32(E1000_ICTXPTC);
1375 rd32(E1000_ICTXATC);
1376 rd32(E1000_ICTXQEC);
1377 rd32(E1000_ICTXQMTC);
1378 rd32(E1000_ICRXDMTC);
1379
1380 rd32(E1000_CBTMPC);
1381 rd32(E1000_HTDPMC);
1382 rd32(E1000_CBRMPC);
1383 rd32(E1000_RPTHC);
1384 rd32(E1000_HGPTC);
1385 rd32(E1000_HTCBDPC);
1386 rd32(E1000_HGORCL);
1387 rd32(E1000_HGORCH);
1388 rd32(E1000_HGOTCL);
1389 rd32(E1000_HGOTCH);
1390 rd32(E1000_LENERRS);
9d5c8243
AK		 1391
1392 /* This register should not be read in copper configurations */
2fb02a26
AD		 1393 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1394 igb_sgmii_active_82575(hw))
cc9073bb 1395 rd32(E1000_SCVPC);
9d5c8243
AK		 1396}
1397
662d7205
AD		 1398/**
1399 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1400 * @hw: pointer to the HW structure
1401 *
1402 * After rx enable if managability is enabled then there is likely some
1403 * bad data at the start of the fifo and possibly in the DMA fifo. This
1404 * function clears the fifos and flushes any packets that came in as rx was
1405 * being enabled.
1406 **/
1407void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1408{
1409 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1410 int i, ms_wait;
1411
1412 if (hw->mac.type != e1000_82575 ||
1413 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1414 return;
1415
1416 /* Disable all RX queues */
1417 for (i = 0; i < 4; i++) {
1418 rxdctl[i] = rd32(E1000_RXDCTL(i));
1419 wr32(E1000_RXDCTL(i),
1420 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1421 }
1422 /* Poll all queues to verify they have shut down */
1423 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1424 msleep(1);
1425 rx_enabled = 0;
1426 for (i = 0; i < 4; i++)
1427 rx_enabled |= rd32(E1000_RXDCTL(i));
1428 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1429 break;
1430 }
1431
1432 if (ms_wait == 10)
1433 hw_dbg("Queue disable timed out after 10ms\n");
1434
1435 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1436 * incoming packets are rejected. Set enable and wait 2ms so that
1437 * any packet that was coming in as RCTL.EN was set is flushed
1438 */
1439 rfctl = rd32(E1000_RFCTL);
1440 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1441
1442 rlpml = rd32(E1000_RLPML);
1443 wr32(E1000_RLPML, 0);
1444
1445 rctl = rd32(E1000_RCTL);
1446 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1447 temp_rctl |= E1000_RCTL_LPE;
1448
1449 wr32(E1000_RCTL, temp_rctl);
1450 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1451 wrfl();
1452 msleep(2);
1453
1454 /* Enable RX queues that were previously enabled and restore our
1455 * previous state
1456 */
1457 for (i = 0; i < 4; i++)
1458 wr32(E1000_RXDCTL(i), rxdctl[i]);
1459 wr32(E1000_RCTL, rctl);
1460 wrfl();
1461
1462 wr32(E1000_RLPML, rlpml);
1463 wr32(E1000_RFCTL, rfctl);
1464
1465 /* Flush receive errors generated by workaround */
1466 rd32(E1000_ROC);
1467 rd32(E1000_RNBC);
1468 rd32(E1000_MPC);
1469}
1470
009bc06e
AD		 1471/**
1472 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1473 * @hw: pointer to the HW structure
1474 *
1475 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1476 * however the hardware default for these parts is 500us to 1ms which is less
1477 * than the 10ms recommended by the pci-e spec. To address this we need to
1478 * increase the value to either 10ms to 200ms for capability version 1 config,
1479 * or 16ms to 55ms for version 2.
1480 **/
1481static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1482{
1483 u32 gcr = rd32(E1000_GCR);
1484 s32 ret_val = 0;
1485 u16 pcie_devctl2;
1486
1487 /* only take action if timeout value is defaulted to 0 */
1488 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1489 goto out;
1490
1491 /*
1492 * if capababilities version is type 1 we can write the
1493 * timeout of 10ms to 200ms through the GCR register
1494 */
1495 if (!(gcr & E1000_GCR_CAP_VER2)) {
1496 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1497 goto out;
1498 }
1499
1500 /*
1501 * for version 2 capabilities we need to write the config space
1502 * directly in order to set the completion timeout value for
1503 * 16ms to 55ms
1504 */
1505 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1506 &pcie_devctl2);
1507 if (ret_val)
1508 goto out;
1509
1510 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1511
1512 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1513 &pcie_devctl2);
1514out:
1515 /* disable completion timeout resend */
1516 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1517
1518 wr32(E1000_GCR, gcr);
1519 return ret_val;
1520}
1521
13800469
GR		 1522/**
1523 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1524 * @hw: pointer to the hardware struct
1525 * @enable: state to enter, either enabled or disabled
1526 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1527 *
1528 * enables/disables L2 switch anti-spoofing functionality.
1529 **/
1530void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1531{
1532 u32 dtxswc;
1533
1534 switch (hw->mac.type) {
1535 case e1000_82576:
1536 case e1000_i350:
1537 dtxswc = rd32(E1000_DTXSWC);
1538 if (enable) {
1539 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1540 E1000_DTXSWC_VLAN_SPOOF_MASK);
1541 /* The PF can spoof - it has to in order to
1542 * support emulation mode NICs */
1543 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1544 } else {
1545 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1546 E1000_DTXSWC_VLAN_SPOOF_MASK);
1547 }
1548 wr32(E1000_DTXSWC, dtxswc);
1549 break;
1550 default:
1551 break;
1552 }
1553}
1554
4ae196df
AD		 1555/**
1556 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1557 * @hw: pointer to the hardware struct
1558 * @enable: state to enter, either enabled or disabled
1559 *
1560 * enables/disables L2 switch loopback functionality.
1561 **/
1562void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1563{
1564 u32 dtxswc = rd32(E1000_DTXSWC);
1565
1566 if (enable)
1567 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1568 else
1569 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1570
1571 wr32(E1000_DTXSWC, dtxswc);
1572}
1573
1574/**
1575 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1576 * @hw: pointer to the hardware struct
1577 * @enable: state to enter, either enabled or disabled
1578 *
1579 * enables/disables replication of packets across multiple pools.
1580 **/
1581void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1582{
1583 u32 vt_ctl = rd32(E1000_VT_CTL);
1584
1585 if (enable)
1586 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1587 else
1588 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1589
1590 wr32(E1000_VT_CTL, vt_ctl);
1591}
1592
bb2ac47b
AD		 1593/**
1594 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1595 * @hw: pointer to the HW structure
1596 * @offset: register offset to be read
1597 * @data: pointer to the read data
1598 *
1599 * Reads the MDI control register in the PHY at offset and stores the
1600 * information read to data.
1601 **/
1602static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1603{
bb2ac47b
AD		 1604 s32 ret_val;
1605
1606
1607 ret_val = hw->phy.ops.acquire(hw);
1608 if (ret_val)
1609 goto out;
1610
bb2ac47b
AD		 1611 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1612
1613 hw->phy.ops.release(hw);
1614
1615out:
1616 return ret_val;
1617}
1618
1619/**
1620 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1621 * @hw: pointer to the HW structure
1622 * @offset: register offset to write to
1623 * @data: data to write to register at offset
1624 *
1625 * Writes data to MDI control register in the PHY at offset.
1626 **/
1627static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1628{
bb2ac47b
AD		 1629 s32 ret_val;
1630
1631
1632 ret_val = hw->phy.ops.acquire(hw);
1633 if (ret_val)
1634 goto out;
1635
bb2ac47b
AD		 1636 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1637
1638 hw->phy.ops.release(hw);
1639
1640out:
1641 return ret_val;
1642}
1643
08451e25
NN		 1644/**
1645 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1646 * @hw: pointer to the HW structure
1647 *
1648 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1649 * the values found in the EEPROM. This addresses an issue in which these
1650 * bits are not restored from EEPROM after reset.
1651 **/
1652static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1653{
1654 s32 ret_val = 0;
1655 u32 mdicnfg;
1b5dda33 1656 u16 nvm_data = 0;
08451e25
NN		 1657
1658 if (hw->mac.type != e1000_82580)
1659 goto out;
1660 if (!igb_sgmii_active_82575(hw))
1661 goto out;
1662
1663 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1664 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1665 &nvm_data);
1666 if (ret_val) {
1667 hw_dbg("NVM Read Error\n");
1668 goto out;
1669 }
1670
1671 mdicnfg = rd32(E1000_MDICNFG);
1672 if (nvm_data & NVM_WORD24_EXT_MDIO)
1673 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1674 if (nvm_data & NVM_WORD24_COM_MDIO)
1675 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1676 wr32(E1000_MDICNFG, mdicnfg);
1677out:
1678 return ret_val;
1679}
1680
bb2ac47b
AD		 1681/**
1682 * igb_reset_hw_82580 - Reset hardware
1683 * @hw: pointer to the HW structure
1684 *
1685 * This resets function or entire device (all ports, etc.)
1686 * to a known state.
1687 **/
1688static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1689{
1690 s32 ret_val = 0;
1691 /* BH SW mailbox bit in SW_FW_SYNC */
1692 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1693 u32 ctrl, icr;
1694 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1695
1696
1697 hw->dev_spec._82575.global_device_reset = false;
1698
1699 /* Get current control state. */
1700 ctrl = rd32(E1000_CTRL);
1701
1702 /*
1703 * Prevent the PCI-E bus from sticking if there is no TLP connection
1704 * on the last TLP read/write transaction when MAC is reset.
1705 */
1706 ret_val = igb_disable_pcie_master(hw);
1707 if (ret_val)
1708 hw_dbg("PCI-E Master disable polling has failed.\n");
1709
1710 hw_dbg("Masking off all interrupts\n");
1711 wr32(E1000_IMC, 0xffffffff);
1712 wr32(E1000_RCTL, 0);
1713 wr32(E1000_TCTL, E1000_TCTL_PSP);
1714 wrfl();
1715
1716 msleep(10);
1717
1718 /* Determine whether or not a global dev reset is requested */
1719 if (global_device_reset &&
1720 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1721 global_device_reset = false;
1722
1723 if (global_device_reset &&
1724 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1725 ctrl |= E1000_CTRL_DEV_RST;
1726 else
1727 ctrl |= E1000_CTRL_RST;
1728
1729 wr32(E1000_CTRL, ctrl);
1730
1731 /* Add delay to insure DEV_RST has time to complete */
1732 if (global_device_reset)
1733 msleep(5);
1734
1735 ret_val = igb_get_auto_rd_done(hw);
1736 if (ret_val) {
1737 /*
1738 * When auto config read does not complete, do not
1739 * return with an error. This can happen in situations
1740 * where there is no eeprom and prevents getting link.
1741 */
1742 hw_dbg("Auto Read Done did not complete\n");
1743 }
1744
1745 /* If EEPROM is not present, run manual init scripts */
1746 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1747 igb_reset_init_script_82575(hw);
1748
1749 /* clear global device reset status bit */
1750 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1751
1752 /* Clear any pending interrupt events. */
1753 wr32(E1000_IMC, 0xffffffff);
1754 icr = rd32(E1000_ICR);
1755
08451e25
NN		 1756 ret_val = igb_reset_mdicnfg_82580(hw);
1757 if (ret_val)
1758 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
1759
bb2ac47b
AD		 1760 /* Install any alternate MAC address into RAR0 */
1761 ret_val = igb_check_alt_mac_addr(hw);
1762
1763 /* Release semaphore */
1764 if (global_device_reset)
1765 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1766
1767 return ret_val;
1768}
1769
1770/**
1771 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1772 * @data: data received by reading RXPBS register
1773 *
1774 * The 82580 uses a table based approach for packet buffer allocation sizes.
1775 * This function converts the retrieved value into the correct table value
1776 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1777 * 0x0 36 72 144 1 2 4 8 16
1778 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1779 */
1780u16 igb_rxpbs_adjust_82580(u32 data)
1781{
1782 u16 ret_val = 0;
1783
1784 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1785 ret_val = e1000_82580_rxpbs_table[data];
1786
1787 return ret_val;
1788}
1789
4322e561
CW		 1790/**
1791 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
1792 * checksum
1793 * @hw: pointer to the HW structure
1794 * @offset: offset in words of the checksum protected region
1795 *
1796 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1797 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1798 **/
1799s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
1800{
1801 s32 ret_val = 0;
1802 u16 checksum = 0;
1803 u16 i, nvm_data;
1804
1805 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
1806 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1807 if (ret_val) {
1808 hw_dbg("NVM Read Error\n");
1809 goto out;
1810 }
1811 checksum += nvm_data;
1812 }
1813
1814 if (checksum != (u16) NVM_SUM) {
1815 hw_dbg("NVM Checksum Invalid\n");
1816 ret_val = -E1000_ERR_NVM;
1817 goto out;
1818 }
1819
1820out:
1821 return ret_val;
1822}
1823
1824/**
1825 * igb_update_nvm_checksum_with_offset - Update EEPROM
1826 * checksum
1827 * @hw: pointer to the HW structure
1828 * @offset: offset in words of the checksum protected region
1829 *
1830 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1831 * up to the checksum. Then calculates the EEPROM checksum and writes the
1832 * value to the EEPROM.
1833 **/
1834s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
1835{
1836 s32 ret_val;
1837 u16 checksum = 0;
1838 u16 i, nvm_data;
1839
1840 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
1841 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1842 if (ret_val) {
1843 hw_dbg("NVM Read Error while updating checksum.\n");
1844 goto out;
1845 }
1846 checksum += nvm_data;
1847 }
1848 checksum = (u16) NVM_SUM - checksum;
1849 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
1850 &checksum);
1851 if (ret_val)
1852 hw_dbg("NVM Write Error while updating checksum.\n");
1853
1854out:
1855 return ret_val;
1856}
1857
1858/**
1859 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
1860 * @hw: pointer to the HW structure
1861 *
1862 * Calculates the EEPROM section checksum by reading/adding each word of
1863 * the EEPROM and then verifies that the sum of the EEPROM is
1864 * equal to 0xBABA.
1865 **/
1866static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
1867{
1868 s32 ret_val = 0;
1869 u16 eeprom_regions_count = 1;
1870 u16 j, nvm_data;
1871 u16 nvm_offset;
1872
1873 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
1874 if (ret_val) {
1875 hw_dbg("NVM Read Error\n");
1876 goto out;
1877 }
1878
1879 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
1880 /* if chekcsums compatibility bit is set validate checksums
1881 * for all 4 ports. */
1882 eeprom_regions_count = 4;
1883 }
1884
1885 for (j = 0; j < eeprom_regions_count; j++) {
1886 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1887 ret_val = igb_validate_nvm_checksum_with_offset(hw,
1888 nvm_offset);
1889 if (ret_val != 0)
1890 goto out;
1891 }
1892
1893out:
1894 return ret_val;
1895}
1896
1897/**
1898 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
1899 * @hw: pointer to the HW structure
1900 *
1901 * Updates the EEPROM section checksums for all 4 ports by reading/adding
1902 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
1903 * checksum and writes the value to the EEPROM.
1904 **/
1905static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
1906{
1907 s32 ret_val;
1908 u16 j, nvm_data;
1909 u16 nvm_offset;
1910
1911 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
1912 if (ret_val) {
1913 hw_dbg("NVM Read Error while updating checksum"
1914 " compatibility bit.\n");
1915 goto out;
1916 }
1917
1918 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
1919 /* set compatibility bit to validate checksums appropriately */
1920 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
1921 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
1922 &nvm_data);
1923 if (ret_val) {
1924 hw_dbg("NVM Write Error while updating checksum"
1925 " compatibility bit.\n");
1926 goto out;
1927 }
1928 }
1929
1930 for (j = 0; j < 4; j++) {
1931 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1932 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
1933 if (ret_val)
1934 goto out;
1935 }
1936
1937out:
1938 return ret_val;
1939}
1940
1941/**
1942 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
1943 * @hw: pointer to the HW structure
1944 *
1945 * Calculates the EEPROM section checksum by reading/adding each word of
1946 * the EEPROM and then verifies that the sum of the EEPROM is
1947 * equal to 0xBABA.
1948 **/
1949static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
1950{
1951 s32 ret_val = 0;
1952 u16 j;
1953 u16 nvm_offset;
1954
1955 for (j = 0; j < 4; j++) {
1956 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1957 ret_val = igb_validate_nvm_checksum_with_offset(hw,
1958 nvm_offset);
1959 if (ret_val != 0)
1960 goto out;
1961 }
1962
1963out:
1964 return ret_val;
1965}
1966
1967/**
1968 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
1969 * @hw: pointer to the HW structure
1970 *
1971 * Updates the EEPROM section checksums for all 4 ports by reading/adding
1972 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
1973 * checksum and writes the value to the EEPROM.
1974 **/
1975static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
1976{
1977 s32 ret_val = 0;
1978 u16 j;
1979 u16 nvm_offset;
1980
1981 for (j = 0; j < 4; j++) {
1982 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1983 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
1984 if (ret_val != 0)
1985 goto out;
1986 }
1987
1988out:
1989 return ret_val;
1990}
09b068d4
CW		 1991/**
1992 * igb_set_eee_i350 - Enable/disable EEE support
1993 * @hw: pointer to the HW structure
1994 *
1995 * Enable/disable EEE based on setting in dev_spec structure.
1996 *
1997 **/
1998s32 igb_set_eee_i350(struct e1000_hw *hw)
1999{
2000 s32 ret_val = 0;
2001 u32 ipcnfg, eeer, ctrl_ext;
2002
2003 ctrl_ext = rd32(E1000_CTRL_EXT);
2004 if ((hw->mac.type != e1000_i350) ||
2005 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2006 goto out;
2007 ipcnfg = rd32(E1000_IPCNFG);
2008 eeer = rd32(E1000_EEER);
2009
2010 /* enable or disable per user setting */
2011 if (!(hw->dev_spec._82575.eee_disable)) {
2012 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
2013 E1000_IPCNFG_EEE_100M_AN);
2014 eeer |= (E1000_EEER_TX_LPI_EN |
2015 E1000_EEER_RX_LPI_EN |
2016 E1000_EEER_LPI_FC);
2017
2018 } else {
2019 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2020 E1000_IPCNFG_EEE_100M_AN);
2021 eeer &= ~(E1000_EEER_TX_LPI_EN |
2022 E1000_EEER_RX_LPI_EN |
2023 E1000_EEER_LPI_FC);
2024 }
2025 wr32(E1000_IPCNFG, ipcnfg);
2026 wr32(E1000_EEER, eeer);
2027out:
2028
2029 return ret_val;
2030}
4322e561 2031
9d5c8243 2032static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 2033 .init_hw = igb_init_hw_82575,
2034 .check_for_link = igb_check_for_link_82575,
2d064c06 2035 .rar_set = igb_rar_set,
9d5c8243
AK		 2036 .read_mac_addr = igb_read_mac_addr_82575,
2037 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
2038};
2039
2040static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 2041 .acquire = igb_acquire_phy_82575,
9d5c8243 2042 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 2043 .release = igb_release_phy_82575,
9d5c8243
AK		 2044};
2045
2046static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 2047 .acquire = igb_acquire_nvm_82575,
2048 .read = igb_read_nvm_eerd,
2049 .release = igb_release_nvm_82575,
2050 .write = igb_write_nvm_spi,
9d5c8243
AK		 2051};
2052
2053const struct e1000_info e1000_82575_info = {
2054 .get_invariants = igb_get_invariants_82575,
2055 .mac_ops = &e1000_mac_ops_82575,
2056 .phy_ops = &e1000_phy_ops_82575,
2057 .nvm_ops = &e1000_nvm_ops_82575,
2058};
2059
Linux kernel - Deliverables
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