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ixgbe: fix sparse warning
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 48
9a799d71 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
0b0c2b31
ET		 50static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
51static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
52static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
53static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
54static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
7b25cdba 56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
eb9c3e3e 57static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
9a799d71
AK		 58
59/**
c44ade9e 60 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 61 * @hw: pointer to hardware structure
62 *
63 * Starts the hardware by filling the bus info structure and media type, clears
64 * all on chip counters, initializes receive address registers, multicast
65 * table, VLAN filter table, calls routine to set up link and flow control
66 * settings, and leaves transmit and receive units disabled and uninitialized
67 **/
c44ade9e 68s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 69{
70 u32 ctrl_ext;
71
72 /* Set the media type */
73 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
74
75 /* Identify the PHY */
c44ade9e 76 hw->phy.ops.identify(hw);
9a799d71 77
9a799d71 78 /* Clear the VLAN filter table */
c44ade9e 79 hw->mac.ops.clear_vfta(hw);
9a799d71 80
9a799d71 81 /* Clear statistics registers */
c44ade9e 82 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 83
84 /* Set No Snoop Disable */
85 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
86 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
87 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 88 IXGBE_WRITE_FLUSH(hw);
9a799d71 89
620fa036
MC		 90 /* Setup flow control */
91 ixgbe_setup_fc(hw, 0);
92
9a799d71
AK		 93 /* Clear adapter stopped flag */
94 hw->adapter_stopped = false;
95
96 return 0;
97}
98
7184b7cf
ET		 99/**
100 * ixgbe_start_hw_gen2 - Init sequence for common device family
101 * @hw: pointer to hw structure
102 *
103 * Performs the init sequence common to the second generation
104 * of 10 GbE devices.
105 * Devices in the second generation:
106 * 82599
107 * X540
108 **/
109s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
110{
111 u32 i;
3d5c5207 112 u32 regval;
7184b7cf
ET		 113
114 /* Clear the rate limiters */
115 for (i = 0; i < hw->mac.max_tx_queues; i++) {
116 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
117 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
118 }
119 IXGBE_WRITE_FLUSH(hw);
120
3d5c5207
ET		 121 /* Disable relaxed ordering */
122 for (i = 0; i < hw->mac.max_tx_queues; i++) {
123 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
124 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
125 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
126 }
127
128 for (i = 0; i < hw->mac.max_rx_queues; i++) {
129 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
130 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
131 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
132 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
133 }
134
7184b7cf
ET		 135 return 0;
136}
137
9a799d71 138/**
c44ade9e 139 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 140 * @hw: pointer to hardware structure
141 *
c44ade9e 142 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 143 * structure and media type, clears all on chip counters, initializes receive
144 * address registers, multicast table, VLAN filter table, calls routine to set
145 * up link and flow control settings, and leaves transmit and receive units
146 * disabled and uninitialized
147 **/
c44ade9e 148s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 149{
794caeb2
PWJ		 150 s32 status;
151
9a799d71 152 /* Reset the hardware */
794caeb2 153 status = hw->mac.ops.reset_hw(hw);
9a799d71 154
794caeb2
PWJ		 155 if (status == 0) {
156 /* Start the HW */
157 status = hw->mac.ops.start_hw(hw);
158 }
9a799d71 159
794caeb2 160 return status;
9a799d71
AK		 161}
162
163/**
c44ade9e 164 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 165 * @hw: pointer to hardware structure
166 *
167 * Clears all hardware statistics counters by reading them from the hardware
168 * Statistics counters are clear on read.
169 **/
c44ade9e 170s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 171{
172 u16 i = 0;
173
174 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
175 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
176 IXGBE_READ_REG(hw, IXGBE_ERRBC);
177 IXGBE_READ_REG(hw, IXGBE_MSPDC);
178 for (i = 0; i < 8; i++)
179 IXGBE_READ_REG(hw, IXGBE_MPC(i));
180
181 IXGBE_READ_REG(hw, IXGBE_MLFC);
182 IXGBE_READ_REG(hw, IXGBE_MRFC);
183 IXGBE_READ_REG(hw, IXGBE_RLEC);
184 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 185 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 186 if (hw->mac.type >= ixgbe_mac_82599EB) {
187 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
188 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
189 } else {
190 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
191 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
192 }
9a799d71
AK		 193
194 for (i = 0; i < 8; i++) {
195 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 196 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 197 if (hw->mac.type >= ixgbe_mac_82599EB) {
198 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
199 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
200 } else {
201 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
202 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
203 }
9a799d71 204 }
667c7565
ET		 205 if (hw->mac.type >= ixgbe_mac_82599EB)
206 for (i = 0; i < 8; i++)
207 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 208 IXGBE_READ_REG(hw, IXGBE_PRC64);
209 IXGBE_READ_REG(hw, IXGBE_PRC127);
210 IXGBE_READ_REG(hw, IXGBE_PRC255);
211 IXGBE_READ_REG(hw, IXGBE_PRC511);
212 IXGBE_READ_REG(hw, IXGBE_PRC1023);
213 IXGBE_READ_REG(hw, IXGBE_PRC1522);
214 IXGBE_READ_REG(hw, IXGBE_GPRC);
215 IXGBE_READ_REG(hw, IXGBE_BPRC);
216 IXGBE_READ_REG(hw, IXGBE_MPRC);
217 IXGBE_READ_REG(hw, IXGBE_GPTC);
218 IXGBE_READ_REG(hw, IXGBE_GORCL);
219 IXGBE_READ_REG(hw, IXGBE_GORCH);
220 IXGBE_READ_REG(hw, IXGBE_GOTCL);
221 IXGBE_READ_REG(hw, IXGBE_GOTCH);
222 for (i = 0; i < 8; i++)
223 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
224 IXGBE_READ_REG(hw, IXGBE_RUC);
225 IXGBE_READ_REG(hw, IXGBE_RFC);
226 IXGBE_READ_REG(hw, IXGBE_ROC);
227 IXGBE_READ_REG(hw, IXGBE_RJC);
228 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
229 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
230 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
231 IXGBE_READ_REG(hw, IXGBE_TORL);
232 IXGBE_READ_REG(hw, IXGBE_TORH);
233 IXGBE_READ_REG(hw, IXGBE_TPR);
234 IXGBE_READ_REG(hw, IXGBE_TPT);
235 IXGBE_READ_REG(hw, IXGBE_PTC64);
236 IXGBE_READ_REG(hw, IXGBE_PTC127);
237 IXGBE_READ_REG(hw, IXGBE_PTC255);
238 IXGBE_READ_REG(hw, IXGBE_PTC511);
239 IXGBE_READ_REG(hw, IXGBE_PTC1023);
240 IXGBE_READ_REG(hw, IXGBE_PTC1522);
241 IXGBE_READ_REG(hw, IXGBE_MPTC);
242 IXGBE_READ_REG(hw, IXGBE_BPTC);
243 for (i = 0; i < 16; i++) {
244 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 245 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 246 if (hw->mac.type >= ixgbe_mac_82599EB) {
247 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
248 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
249 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
250 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
251 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
252 } else {
253 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
254 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
255 }
9a799d71
AK		 256 }
257
a3aeea0e
ET		 258 if (hw->mac.type == ixgbe_mac_X540) {
259 if (hw->phy.id == 0)
260 hw->phy.ops.identify(hw);
261 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECL, &i);
262 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECH, &i);
263 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECL, &i);
264 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECH, &i);
265 }
266
9a799d71
AK		 267 return 0;
268}
269
270/**
289700db 271 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 272 * @hw: pointer to hardware structure
289700db
DS		 273 * @pba_num: stores the part number string from the EEPROM
274 * @pba_num_size: part number string buffer length
c44ade9e 275 *
289700db 276 * Reads the part number string from the EEPROM.
c44ade9e 277 **/
289700db
DS		 278s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
279 u32 pba_num_size)
c44ade9e
JB		 280{
281 s32 ret_val;
282 u16 data;
289700db
DS		 283 u16 pba_ptr;
284 u16 offset;
285 u16 length;
286
287 if (pba_num == NULL) {
288 hw_dbg(hw, "PBA string buffer was null\n");
289 return IXGBE_ERR_INVALID_ARGUMENT;
290 }
c44ade9e
JB		 291
292 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
293 if (ret_val) {
294 hw_dbg(hw, "NVM Read Error\n");
295 return ret_val;
296 }
c44ade9e 297
289700db 298 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 299 if (ret_val) {
300 hw_dbg(hw, "NVM Read Error\n");
301 return ret_val;
302 }
289700db
DS		 303
304 /*
305 * if data is not ptr guard the PBA must be in legacy format which
306 * means pba_ptr is actually our second data word for the PBA number
307 * and we can decode it into an ascii string
308 */
309 if (data != IXGBE_PBANUM_PTR_GUARD) {
310 hw_dbg(hw, "NVM PBA number is not stored as string\n");
311
312 /* we will need 11 characters to store the PBA */
313 if (pba_num_size < 11) {
314 hw_dbg(hw, "PBA string buffer too small\n");
315 return IXGBE_ERR_NO_SPACE;
316 }
317
318 /* extract hex string from data and pba_ptr */
319 pba_num[0] = (data >> 12) & 0xF;
320 pba_num[1] = (data >> 8) & 0xF;
321 pba_num[2] = (data >> 4) & 0xF;
322 pba_num[3] = data & 0xF;
323 pba_num[4] = (pba_ptr >> 12) & 0xF;
324 pba_num[5] = (pba_ptr >> 8) & 0xF;
325 pba_num[6] = '-';
326 pba_num[7] = 0;
327 pba_num[8] = (pba_ptr >> 4) & 0xF;
328 pba_num[9] = pba_ptr & 0xF;
329
330 /* put a null character on the end of our string */
331 pba_num[10] = '\0';
332
333 /* switch all the data but the '-' to hex char */
334 for (offset = 0; offset < 10; offset++) {
335 if (pba_num[offset] < 0xA)
336 pba_num[offset] += '0';
337 else if (pba_num[offset] < 0x10)
338 pba_num[offset] += 'A' - 0xA;
339 }
340
341 return 0;
342 }
343
344 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
345 if (ret_val) {
346 hw_dbg(hw, "NVM Read Error\n");
347 return ret_val;
348 }
349
350 if (length == 0xFFFF || length == 0) {
351 hw_dbg(hw, "NVM PBA number section invalid length\n");
352 return IXGBE_ERR_PBA_SECTION;
353 }
354
355 /* check if pba_num buffer is big enough */
356 if (pba_num_size < (((u32)length * 2) - 1)) {
357 hw_dbg(hw, "PBA string buffer too small\n");
358 return IXGBE_ERR_NO_SPACE;
359 }
360
361 /* trim pba length from start of string */
362 pba_ptr++;
363 length--;
364
365 for (offset = 0; offset < length; offset++) {
366 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
367 if (ret_val) {
368 hw_dbg(hw, "NVM Read Error\n");
369 return ret_val;
370 }
371 pba_num[offset * 2] = (u8)(data >> 8);
372 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
373 }
374 pba_num[offset * 2] = '\0';
c44ade9e
JB		 375
376 return 0;
377}
378
379/**
380 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 381 * @hw: pointer to hardware structure
382 * @mac_addr: Adapter MAC address
383 *
384 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
385 * A reset of the adapter must be performed prior to calling this function
386 * in order for the MAC address to have been loaded from the EEPROM into RAR0
387 **/
c44ade9e 388s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 389{
390 u32 rar_high;
391 u32 rar_low;
392 u16 i;
393
394 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
395 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
396
397 for (i = 0; i < 4; i++)
398 mac_addr[i] = (u8)(rar_low >> (i*8));
399
400 for (i = 0; i < 2; i++)
401 mac_addr[i+4] = (u8)(rar_high >> (i*8));
402
403 return 0;
404}
405
11afc1b1
PW		 406/**
407 * ixgbe_get_bus_info_generic - Generic set PCI bus info
408 * @hw: pointer to hardware structure
409 *
410 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
411 **/
412s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
413{
414 struct ixgbe_adapter *adapter = hw->back;
415 struct ixgbe_mac_info *mac = &hw->mac;
416 u16 link_status;
417
418 hw->bus.type = ixgbe_bus_type_pci_express;
419
420 /* Get the negotiated link width and speed from PCI config space */
421 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
422 &link_status);
423
424 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
425 case IXGBE_PCI_LINK_WIDTH_1:
426 hw->bus.width = ixgbe_bus_width_pcie_x1;
427 break;
428 case IXGBE_PCI_LINK_WIDTH_2:
429 hw->bus.width = ixgbe_bus_width_pcie_x2;
430 break;
431 case IXGBE_PCI_LINK_WIDTH_4:
432 hw->bus.width = ixgbe_bus_width_pcie_x4;
433 break;
434 case IXGBE_PCI_LINK_WIDTH_8:
435 hw->bus.width = ixgbe_bus_width_pcie_x8;
436 break;
437 default:
438 hw->bus.width = ixgbe_bus_width_unknown;
439 break;
440 }
441
442 switch (link_status & IXGBE_PCI_LINK_SPEED) {
443 case IXGBE_PCI_LINK_SPEED_2500:
444 hw->bus.speed = ixgbe_bus_speed_2500;
445 break;
446 case IXGBE_PCI_LINK_SPEED_5000:
447 hw->bus.speed = ixgbe_bus_speed_5000;
448 break;
449 default:
450 hw->bus.speed = ixgbe_bus_speed_unknown;
451 break;
452 }
453
454 mac->ops.set_lan_id(hw);
455
456 return 0;
457}
458
459/**
460 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
461 * @hw: pointer to the HW structure
462 *
463 * Determines the LAN function id by reading memory-mapped registers
464 * and swaps the port value if requested.
465 **/
466void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
467{
468 struct ixgbe_bus_info *bus = &hw->bus;
469 u32 reg;
470
471 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
472 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
473 bus->lan_id = bus->func;
474
475 /* check for a port swap */
476 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
477 if (reg & IXGBE_FACTPS_LFS)
478 bus->func ^= 0x1;
479}
480
9a799d71 481/**
c44ade9e 482 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 483 * @hw: pointer to hardware structure
484 *
485 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
486 * disables transmit and receive units. The adapter_stopped flag is used by
487 * the shared code and drivers to determine if the adapter is in a stopped
488 * state and should not touch the hardware.
489 **/
c44ade9e 490s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 491{
492 u32 number_of_queues;
493 u32 reg_val;
494 u16 i;
495
496 /*
497 * Set the adapter_stopped flag so other driver functions stop touching
498 * the hardware
499 */
500 hw->adapter_stopped = true;
501
502 /* Disable the receive unit */
503 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
504 reg_val &= ~(IXGBE_RXCTRL_RXEN);
505 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 506 IXGBE_WRITE_FLUSH(hw);
032b4325 507 usleep_range(2000, 4000);
9a799d71
AK		 508
509 /* Clear interrupt mask to stop from interrupts being generated */
510 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
511
512 /* Clear any pending interrupts */
513 IXGBE_READ_REG(hw, IXGBE_EICR);
514
515 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 516 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 517 for (i = 0; i < number_of_queues; i++) {
518 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
519 if (reg_val & IXGBE_TXDCTL_ENABLE) {
520 reg_val &= ~IXGBE_TXDCTL_ENABLE;
521 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
522 }
523 }
524
c44ade9e
JB		 525 /*
526 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
527 * access and verify no pending requests
528 */
a4297dc2 529 ixgbe_disable_pcie_master(hw);
c44ade9e 530
9a799d71
AK		 531 return 0;
532}
533
534/**
c44ade9e 535 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 536 * @hw: pointer to hardware structure
537 * @index: led number to turn on
538 **/
c44ade9e 539s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 540{
541 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
542
543 /* To turn on the LED, set mode to ON. */
544 led_reg &= ~IXGBE_LED_MODE_MASK(index);
545 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
546 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 547 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 548
549 return 0;
550}
551
552/**
c44ade9e 553 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 554 * @hw: pointer to hardware structure
555 * @index: led number to turn off
556 **/
c44ade9e 557s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 558{
559 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
560
561 /* To turn off the LED, set mode to OFF. */
562 led_reg &= ~IXGBE_LED_MODE_MASK(index);
563 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
564 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 565 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 566
567 return 0;
568}
569
9a799d71 570/**
c44ade9e 571 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 572 * @hw: pointer to hardware structure
573 *
574 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
575 * ixgbe_hw struct in order to set up EEPROM access.
576 **/
c44ade9e 577s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 578{
579 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
580 u32 eec;
581 u16 eeprom_size;
582
583 if (eeprom->type == ixgbe_eeprom_uninitialized) {
584 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 585 /* Set default semaphore delay to 10ms which is a well
586 * tested value */
587 eeprom->semaphore_delay = 10;
9a799d71
AK		 588
589 /*
590 * Check for EEPROM present first.
591 * If not present leave as none
592 */
593 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
594 if (eec & IXGBE_EEC_PRES) {
595 eeprom->type = ixgbe_eeprom_spi;
596
597 /*
598 * SPI EEPROM is assumed here. This code would need to
599 * change if a future EEPROM is not SPI.
600 */
601 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
602 IXGBE_EEC_SIZE_SHIFT);
603 eeprom->word_size = 1 << (eeprom_size +
604 IXGBE_EEPROM_WORD_SIZE_SHIFT);
605 }
606
607 if (eec & IXGBE_EEC_ADDR_SIZE)
608 eeprom->address_bits = 16;
609 else
610 eeprom->address_bits = 8;
611 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
612 "%d\n", eeprom->type, eeprom->word_size,
613 eeprom->address_bits);
614 }
615
616 return 0;
617}
618
11afc1b1
PW		 619/**
620 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
621 * @hw: pointer to hardware structure
622 * @offset: offset within the EEPROM to be written to
623 * @data: 16 bit word to be written to the EEPROM
624 *
625 * If ixgbe_eeprom_update_checksum is not called after this function, the
626 * EEPROM will most likely contain an invalid checksum.
627 **/
628s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
629{
630 s32 status;
631 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
632
633 hw->eeprom.ops.init_params(hw);
634
635 if (offset >= hw->eeprom.word_size) {
636 status = IXGBE_ERR_EEPROM;
637 goto out;
638 }
639
640 /* Prepare the EEPROM for writing */
641 status = ixgbe_acquire_eeprom(hw);
642
643 if (status == 0) {
644 if (ixgbe_ready_eeprom(hw) != 0) {
645 ixgbe_release_eeprom(hw);
646 status = IXGBE_ERR_EEPROM;
647 }
648 }
649
650 if (status == 0) {
651 ixgbe_standby_eeprom(hw);
652
653 /* Send the WRITE ENABLE command (8 bit opcode ) */
654 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
655 IXGBE_EEPROM_OPCODE_BITS);
656
657 ixgbe_standby_eeprom(hw);
658
659 /*
660 * Some SPI eeproms use the 8th address bit embedded in the
661 * opcode
662 */
663 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
664 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
665
666 /* Send the Write command (8-bit opcode + addr) */
667 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
668 IXGBE_EEPROM_OPCODE_BITS);
669 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
670 hw->eeprom.address_bits);
671
672 /* Send the data */
673 data = (data >> 8) | (data << 8);
674 ixgbe_shift_out_eeprom_bits(hw, data, 16);
675 ixgbe_standby_eeprom(hw);
676
11afc1b1
PW		 677 /* Done with writing - release the EEPROM */
678 ixgbe_release_eeprom(hw);
679 }
680
681out:
682 return status;
683}
684
9a799d71 685/**
c44ade9e
JB		 686 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
687 * @hw: pointer to hardware structure
688 * @offset: offset within the EEPROM to be read
689 * @data: read 16 bit value from EEPROM
690 *
691 * Reads 16 bit value from EEPROM through bit-bang method
692 **/
693s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
694 u16 *data)
695{
696 s32 status;
697 u16 word_in;
698 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
699
700 hw->eeprom.ops.init_params(hw);
701
702 if (offset >= hw->eeprom.word_size) {
703 status = IXGBE_ERR_EEPROM;
704 goto out;
705 }
706
707 /* Prepare the EEPROM for reading */
708 status = ixgbe_acquire_eeprom(hw);
709
710 if (status == 0) {
711 if (ixgbe_ready_eeprom(hw) != 0) {
712 ixgbe_release_eeprom(hw);
713 status = IXGBE_ERR_EEPROM;
714 }
715 }
716
717 if (status == 0) {
718 ixgbe_standby_eeprom(hw);
719
720 /*
721 * Some SPI eeproms use the 8th address bit embedded in the
722 * opcode
723 */
724 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
725 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
726
727 /* Send the READ command (opcode + addr) */
728 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
729 IXGBE_EEPROM_OPCODE_BITS);
730 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
731 hw->eeprom.address_bits);
732
733 /* Read the data. */
734 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
735 *data = (word_in >> 8) | (word_in << 8);
736
737 /* End this read operation */
738 ixgbe_release_eeprom(hw);
739 }
740
741out:
742 return status;
743}
744
745/**
21ce849b 746 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
9a799d71
AK		 747 * @hw: pointer to hardware structure
748 * @offset: offset of word in the EEPROM to read
749 * @data: word read from the EEPROM
750 *
751 * Reads a 16 bit word from the EEPROM using the EERD register.
752 **/
21ce849b 753s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
9a799d71
AK		 754{
755 u32 eerd;
756 s32 status;
757
c44ade9e
JB		 758 hw->eeprom.ops.init_params(hw);
759
760 if (offset >= hw->eeprom.word_size) {
761 status = IXGBE_ERR_EEPROM;
762 goto out;
763 }
764
21ce849b
MC		 765 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
766 IXGBE_EEPROM_RW_REG_START;
9a799d71
AK		 767
768 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
21ce849b 769 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71
AK		 770
771 if (status == 0)
772 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
21ce849b 773 IXGBE_EEPROM_RW_REG_DATA);
9a799d71
AK		 774 else
775 hw_dbg(hw, "Eeprom read timed out\n");
776
c44ade9e 777out:
9a799d71
AK		 778 return status;
779}
780
eb9c3e3e
ET		 781/**
782 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
783 * @hw: pointer to hardware structure
784 * @offset: offset of word in the EEPROM to write
785 * @data: word write to the EEPROM
786 *
787 * Write a 16 bit word to the EEPROM using the EEWR register.
788 **/
789s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
790{
791 u32 eewr;
792 s32 status;
793
794 hw->eeprom.ops.init_params(hw);
795
796 if (offset >= hw->eeprom.word_size) {
797 status = IXGBE_ERR_EEPROM;
798 goto out;
799 }
800
801 eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) |
802 (data << IXGBE_EEPROM_RW_REG_DATA) | IXGBE_EEPROM_RW_REG_START;
803
804 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
805 if (status != 0) {
806 hw_dbg(hw, "Eeprom write EEWR timed out\n");
807 goto out;
808 }
809
810 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
811
812 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
813 if (status != 0) {
814 hw_dbg(hw, "Eeprom write EEWR timed out\n");
815 goto out;
816 }
817
818out:
819 return status;
820}
821
9a799d71 822/**
21ce849b 823 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 824 * @hw: pointer to hardware structure
21ce849b 825 * @ee_reg: EEPROM flag for polling
9a799d71 826 *
21ce849b
MC		 827 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
828 * read or write is done respectively.
9a799d71 829 **/
eb9c3e3e 830static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 831{
832 u32 i;
833 u32 reg;
834 s32 status = IXGBE_ERR_EEPROM;
835
21ce849b
MC		 836 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
837 if (ee_reg == IXGBE_NVM_POLL_READ)
838 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
839 else
840 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
841
842 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 843 status = 0;
844 break;
845 }
846 udelay(5);
847 }
848 return status;
849}
850
c44ade9e
JB		 851/**
852 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
853 * @hw: pointer to hardware structure
854 *
855 * Prepares EEPROM for access using bit-bang method. This function should
856 * be called before issuing a command to the EEPROM.
857 **/
858static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
859{
860 s32 status = 0;
dbf893ee 861 u32 eec;
c44ade9e
JB		 862 u32 i;
863
5e655105 864 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
c44ade9e
JB		 865 status = IXGBE_ERR_SWFW_SYNC;
866
867 if (status == 0) {
868 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
869
870 /* Request EEPROM Access */
871 eec |= IXGBE_EEC_REQ;
872 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
873
874 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
875 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
876 if (eec & IXGBE_EEC_GNT)
877 break;
878 udelay(5);
879 }
880
881 /* Release if grant not acquired */
882 if (!(eec & IXGBE_EEC_GNT)) {
883 eec &= ~IXGBE_EEC_REQ;
884 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
885 hw_dbg(hw, "Could not acquire EEPROM grant\n");
886
5e655105 887 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
c44ade9e
JB		 888 status = IXGBE_ERR_EEPROM;
889 }
c44ade9e 890
dbf893ee
ET		 891 /* Setup EEPROM for Read/Write */
892 if (status == 0) {
893 /* Clear CS and SK */
894 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
895 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
896 IXGBE_WRITE_FLUSH(hw);
897 udelay(1);
898 }
c44ade9e
JB		 899 }
900 return status;
901}
902
9a799d71
AK		 903/**
904 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
905 * @hw: pointer to hardware structure
906 *
907 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
908 **/
909static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
910{
911 s32 status = IXGBE_ERR_EEPROM;
dbf893ee 912 u32 timeout = 2000;
9a799d71
AK		 913 u32 i;
914 u32 swsm;
915
9a799d71
AK		 916 /* Get SMBI software semaphore between device drivers first */
917 for (i = 0; i < timeout; i++) {
918 /*
919 * If the SMBI bit is 0 when we read it, then the bit will be
920 * set and we have the semaphore
921 */
922 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
923 if (!(swsm & IXGBE_SWSM_SMBI)) {
924 status = 0;
925 break;
926 }
dbf893ee 927 udelay(50);
9a799d71
AK		 928 }
929
930 /* Now get the semaphore between SW/FW through the SWESMBI bit */
931 if (status == 0) {
932 for (i = 0; i < timeout; i++) {
933 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
934
935 /* Set the SW EEPROM semaphore bit to request access */
936 swsm |= IXGBE_SWSM_SWESMBI;
937 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
938
939 /*
940 * If we set the bit successfully then we got the
941 * semaphore.
942 */
943 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
944 if (swsm & IXGBE_SWSM_SWESMBI)
945 break;
946
947 udelay(50);
948 }
949
950 /*
951 * Release semaphores and return error if SW EEPROM semaphore
952 * was not granted because we don't have access to the EEPROM
953 */
954 if (i >= timeout) {
dbf893ee 955 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
b4617240 956 "not granted.\n");
9a799d71
AK		 957 ixgbe_release_eeprom_semaphore(hw);
958 status = IXGBE_ERR_EEPROM;
959 }
dbf893ee
ET		 960 } else {
961 hw_dbg(hw, "Software semaphore SMBI between device drivers "
962 "not granted.\n");
9a799d71
AK		 963 }
964
965 return status;
966}
967
968/**
969 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
970 * @hw: pointer to hardware structure
971 *
972 * This function clears hardware semaphore bits.
973 **/
974static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
975{
976 u32 swsm;
977
978 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
979
980 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
981 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
982 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 983 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 984}
985
c44ade9e
JB		 986/**
987 * ixgbe_ready_eeprom - Polls for EEPROM ready
988 * @hw: pointer to hardware structure
989 **/
990static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
991{
992 s32 status = 0;
993 u16 i;
994 u8 spi_stat_reg;
995
996 /*
997 * Read "Status Register" repeatedly until the LSB is cleared. The
998 * EEPROM will signal that the command has been completed by clearing
999 * bit 0 of the internal status register. If it's not cleared within
1000 * 5 milliseconds, then error out.
1001 */
1002 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1003 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1004 IXGBE_EEPROM_OPCODE_BITS);
1005 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1006 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1007 break;
1008
1009 udelay(5);
1010 ixgbe_standby_eeprom(hw);
1011 };
1012
1013 /*
1014 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1015 * devices (and only 0-5mSec on 5V devices)
1016 */
1017 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1018 hw_dbg(hw, "SPI EEPROM Status error\n");
1019 status = IXGBE_ERR_EEPROM;
1020 }
1021
1022 return status;
1023}
1024
1025/**
1026 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1027 * @hw: pointer to hardware structure
1028 **/
1029static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1030{
1031 u32 eec;
1032
1033 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1034
1035 /* Toggle CS to flush commands */
1036 eec |= IXGBE_EEC_CS;
1037 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1038 IXGBE_WRITE_FLUSH(hw);
1039 udelay(1);
1040 eec &= ~IXGBE_EEC_CS;
1041 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1042 IXGBE_WRITE_FLUSH(hw);
1043 udelay(1);
1044}
1045
1046/**
1047 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1048 * @hw: pointer to hardware structure
1049 * @data: data to send to the EEPROM
1050 * @count: number of bits to shift out
1051 **/
1052static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1053 u16 count)
1054{
1055 u32 eec;
1056 u32 mask;
1057 u32 i;
1058
1059 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1060
1061 /*
1062 * Mask is used to shift "count" bits of "data" out to the EEPROM
1063 * one bit at a time. Determine the starting bit based on count
1064 */
1065 mask = 0x01 << (count - 1);
1066
1067 for (i = 0; i < count; i++) {
1068 /*
1069 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1070 * "1", and then raising and then lowering the clock (the SK
1071 * bit controls the clock input to the EEPROM). A "0" is
1072 * shifted out to the EEPROM by setting "DI" to "0" and then
1073 * raising and then lowering the clock.
1074 */
1075 if (data & mask)
1076 eec |= IXGBE_EEC_DI;
1077 else
1078 eec &= ~IXGBE_EEC_DI;
1079
1080 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1081 IXGBE_WRITE_FLUSH(hw);
1082
1083 udelay(1);
1084
1085 ixgbe_raise_eeprom_clk(hw, &eec);
1086 ixgbe_lower_eeprom_clk(hw, &eec);
1087
1088 /*
1089 * Shift mask to signify next bit of data to shift in to the
1090 * EEPROM
1091 */
1092 mask = mask >> 1;
1093 };
1094
1095 /* We leave the "DI" bit set to "0" when we leave this routine. */
1096 eec &= ~IXGBE_EEC_DI;
1097 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1098 IXGBE_WRITE_FLUSH(hw);
1099}
1100
1101/**
1102 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1103 * @hw: pointer to hardware structure
1104 **/
1105static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1106{
1107 u32 eec;
1108 u32 i;
1109 u16 data = 0;
1110
1111 /*
1112 * In order to read a register from the EEPROM, we need to shift
1113 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1114 * the clock input to the EEPROM (setting the SK bit), and then reading
1115 * the value of the "DO" bit. During this "shifting in" process the
1116 * "DI" bit should always be clear.
1117 */
1118 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1119
1120 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1121
1122 for (i = 0; i < count; i++) {
1123 data = data << 1;
1124 ixgbe_raise_eeprom_clk(hw, &eec);
1125
1126 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1127
1128 eec &= ~(IXGBE_EEC_DI);
1129 if (eec & IXGBE_EEC_DO)
1130 data |= 1;
1131
1132 ixgbe_lower_eeprom_clk(hw, &eec);
1133 }
1134
1135 return data;
1136}
1137
1138/**
1139 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1140 * @hw: pointer to hardware structure
1141 * @eec: EEC register's current value
1142 **/
1143static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1144{
1145 /*
1146 * Raise the clock input to the EEPROM
1147 * (setting the SK bit), then delay
1148 */
1149 *eec = *eec | IXGBE_EEC_SK;
1150 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1151 IXGBE_WRITE_FLUSH(hw);
1152 udelay(1);
1153}
1154
1155/**
1156 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1157 * @hw: pointer to hardware structure
1158 * @eecd: EECD's current value
1159 **/
1160static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1161{
1162 /*
1163 * Lower the clock input to the EEPROM (clearing the SK bit), then
1164 * delay
1165 */
1166 *eec = *eec & ~IXGBE_EEC_SK;
1167 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1168 IXGBE_WRITE_FLUSH(hw);
1169 udelay(1);
1170}
1171
1172/**
1173 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1174 * @hw: pointer to hardware structure
1175 **/
1176static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1177{
1178 u32 eec;
1179
1180 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1181
1182 eec |= IXGBE_EEC_CS; /* Pull CS high */
1183 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1184
1185 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1186 IXGBE_WRITE_FLUSH(hw);
1187
1188 udelay(1);
1189
1190 /* Stop requesting EEPROM access */
1191 eec &= ~IXGBE_EEC_REQ;
1192 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1193
90827996 1194 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1195
032b4325
DS		 1196 /*
1197 * Delay before attempt to obtain semaphore again to allow FW
1198 * access. semaphore_delay is in ms we need us for usleep_range
1199 */
1200 usleep_range(hw->eeprom.semaphore_delay * 1000,
1201 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1202}
1203
9a799d71 1204/**
dbf893ee 1205 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1206 * @hw: pointer to hardware structure
1207 **/
a391f1d5 1208u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1209{
1210 u16 i;
1211 u16 j;
1212 u16 checksum = 0;
1213 u16 length = 0;
1214 u16 pointer = 0;
1215 u16 word = 0;
1216
1217 /* Include 0x0-0x3F in the checksum */
1218 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1219 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1220 hw_dbg(hw, "EEPROM read failed\n");
1221 break;
1222 }
1223 checksum += word;
1224 }
1225
1226 /* Include all data from pointers except for the fw pointer */
1227 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1228 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1229
1230 /* Make sure the pointer seems valid */
1231 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1232 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1233
1234 if (length != 0xFFFF && length != 0) {
1235 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1236 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1237 checksum += word;
1238 }
1239 }
1240 }
1241 }
1242
1243 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1244
1245 return checksum;
1246}
1247
1248/**
c44ade9e 1249 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1250 * @hw: pointer to hardware structure
1251 * @checksum_val: calculated checksum
1252 *
1253 * Performs checksum calculation and validates the EEPROM checksum. If the
1254 * caller does not need checksum_val, the value can be NULL.
1255 **/
c44ade9e
JB		 1256s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1257 u16 *checksum_val)
9a799d71
AK		 1258{
1259 s32 status;
1260 u16 checksum;
1261 u16 read_checksum = 0;
1262
1263 /*
1264 * Read the first word from the EEPROM. If this times out or fails, do
1265 * not continue or we could be in for a very long wait while every
1266 * EEPROM read fails
1267 */
c44ade9e 1268 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1269
1270 if (status == 0) {
a391f1d5 1271 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1272
c44ade9e 1273 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1274
1275 /*
1276 * Verify read checksum from EEPROM is the same as
1277 * calculated checksum
1278 */
1279 if (read_checksum != checksum)
1280 status = IXGBE_ERR_EEPROM_CHECKSUM;
1281
1282 /* If the user cares, return the calculated checksum */
1283 if (checksum_val)
1284 *checksum_val = checksum;
1285 } else {
1286 hw_dbg(hw, "EEPROM read failed\n");
1287 }
1288
1289 return status;
1290}
1291
c44ade9e
JB		 1292/**
1293 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1294 * @hw: pointer to hardware structure
1295 **/
1296s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1297{
1298 s32 status;
1299 u16 checksum;
1300
1301 /*
1302 * Read the first word from the EEPROM. If this times out or fails, do
1303 * not continue or we could be in for a very long wait while every
1304 * EEPROM read fails
1305 */
1306 status = hw->eeprom.ops.read(hw, 0, &checksum);
1307
1308 if (status == 0) {
a391f1d5 1309 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1310 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1311 checksum);
c44ade9e
JB		 1312 } else {
1313 hw_dbg(hw, "EEPROM read failed\n");
1314 }
1315
1316 return status;
1317}
1318
9a799d71
AK		 1319/**
1320 * ixgbe_validate_mac_addr - Validate MAC address
1321 * @mac_addr: pointer to MAC address.
1322 *
1323 * Tests a MAC address to ensure it is a valid Individual Address
1324 **/
1325s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1326{
1327 s32 status = 0;
1328
1329 /* Make sure it is not a multicast address */
1330 if (IXGBE_IS_MULTICAST(mac_addr))
1331 status = IXGBE_ERR_INVALID_MAC_ADDR;
1332 /* Not a broadcast address */
1333 else if (IXGBE_IS_BROADCAST(mac_addr))
1334 status = IXGBE_ERR_INVALID_MAC_ADDR;
1335 /* Reject the zero address */
1336 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1337 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1338 status = IXGBE_ERR_INVALID_MAC_ADDR;
1339
1340 return status;
1341}
1342
1343/**
c44ade9e 1344 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1345 * @hw: pointer to hardware structure
9a799d71 1346 * @index: Receive address register to write
c44ade9e
JB		 1347 * @addr: Address to put into receive address register
1348 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1349 * @enable_addr: set flag that address is active
1350 *
1351 * Puts an ethernet address into a receive address register.
1352 **/
c44ade9e
JB		 1353s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1354 u32 enable_addr)
9a799d71
AK		 1355{
1356 u32 rar_low, rar_high;
c44ade9e
JB		 1357 u32 rar_entries = hw->mac.num_rar_entries;
1358
c700f4e6
ET		 1359 /* Make sure we are using a valid rar index range */
1360 if (index >= rar_entries) {
1361 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1362 return IXGBE_ERR_INVALID_ARGUMENT;
1363 }
1364
c44ade9e
JB		 1365 /* setup VMDq pool selection before this RAR gets enabled */
1366 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1367
c700f4e6
ET		 1368 /*
1369 * HW expects these in little endian so we reverse the byte
1370 * order from network order (big endian) to little endian
1371 */
1372 rar_low = ((u32)addr[0] |
1373 ((u32)addr[1] << 8) |
1374 ((u32)addr[2] << 16) |
1375 ((u32)addr[3] << 24));
1376 /*
1377 * Some parts put the VMDq setting in the extra RAH bits,
1378 * so save everything except the lower 16 bits that hold part
1379 * of the address and the address valid bit.
1380 */
1381 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1382 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1383 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1384
c700f4e6
ET		 1385 if (enable_addr != 0)
1386 rar_high |= IXGBE_RAH_AV;
9a799d71 1387
c700f4e6
ET		 1388 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1389 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1390
1391 return 0;
1392}
1393
1394/**
1395 * ixgbe_clear_rar_generic - Remove Rx address register
1396 * @hw: pointer to hardware structure
1397 * @index: Receive address register to write
1398 *
1399 * Clears an ethernet address from a receive address register.
1400 **/
1401s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1402{
1403 u32 rar_high;
1404 u32 rar_entries = hw->mac.num_rar_entries;
1405
1406 /* Make sure we are using a valid rar index range */
c700f4e6 1407 if (index >= rar_entries) {
c44ade9e 1408 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1409 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1410 }
1411
c700f4e6
ET		 1412 /*
1413 * Some parts put the VMDq setting in the extra RAH bits,
1414 * so save everything except the lower 16 bits that hold part
1415 * of the address and the address valid bit.
1416 */
1417 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1418 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1419
1420 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1421 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1422
c44ade9e
JB		 1423 /* clear VMDq pool/queue selection for this RAR */
1424 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1425
1426 return 0;
1427}
1428
c44ade9e
JB		 1429/**
1430 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1431 * @hw: pointer to hardware structure
1432 *
1433 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1434 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1435 * the receiver is in reset when the routine is called.
1436 **/
c44ade9e 1437s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1438{
1439 u32 i;
2c5645cf 1440 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1441
1442 /*
1443 * If the current mac address is valid, assume it is a software override
1444 * to the permanent address.
1445 * Otherwise, use the permanent address from the eeprom.
1446 */
1447 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1448 IXGBE_ERR_INVALID_MAC_ADDR) {
1449 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1450 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1451
ce7194d8 1452 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1453 } else {
1454 /* Setup the receive address. */
1455 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1456 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1457
c44ade9e 1458 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1459
1460 /* clear VMDq pool/queue selection for RAR 0 */
1461 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1462 }
c44ade9e 1463 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1464
1465 hw->addr_ctrl.rar_used_count = 1;
1466
1467 /* Zero out the other receive addresses. */
c44ade9e 1468 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1469 for (i = 1; i < rar_entries; i++) {
1470 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1471 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1472 }
1473
1474 /* Clear the MTA */
9a799d71
AK		 1475 hw->addr_ctrl.mta_in_use = 0;
1476 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1477
1478 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1479 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1480 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1481
c44ade9e
JB		 1482 if (hw->mac.ops.init_uta_tables)
1483 hw->mac.ops.init_uta_tables(hw);
1484
9a799d71
AK		 1485 return 0;
1486}
1487
1488/**
1489 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1490 * @hw: pointer to hardware structure
1491 * @mc_addr: the multicast address
1492 *
1493 * Extracts the 12 bits, from a multicast address, to determine which
1494 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1495 * incoming rx multicast addresses, to determine the bit-vector to check in
1496 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1497 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1498 * to mc_filter_type.
1499 **/
1500static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1501{
1502 u32 vector = 0;
1503
1504 switch (hw->mac.mc_filter_type) {
b4617240 1505 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1506 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1507 break;
b4617240 1508 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1509 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1510 break;
b4617240 1511 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1512 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1513 break;
b4617240 1514 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1515 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1516 break;
b4617240 1517 default: /* Invalid mc_filter_type */
9a799d71
AK		 1518 hw_dbg(hw, "MC filter type param set incorrectly\n");
1519 break;
1520 }
1521
1522 /* vector can only be 12-bits or boundary will be exceeded */
1523 vector &= 0xFFF;
1524 return vector;
1525}
1526
1527/**
1528 * ixgbe_set_mta - Set bit-vector in multicast table
1529 * @hw: pointer to hardware structure
1530 * @hash_value: Multicast address hash value
1531 *
1532 * Sets the bit-vector in the multicast table.
1533 **/
1534static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1535{
1536 u32 vector;
1537 u32 vector_bit;
1538 u32 vector_reg;
9a799d71
AK		 1539
1540 hw->addr_ctrl.mta_in_use++;
1541
1542 vector = ixgbe_mta_vector(hw, mc_addr);
1543 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1544
1545 /*
1546 * The MTA is a register array of 128 32-bit registers. It is treated
1547 * like an array of 4096 bits. We want to set bit
1548 * BitArray[vector_value]. So we figure out what register the bit is
1549 * in, read it, OR in the new bit, then write back the new value. The
1550 * register is determined by the upper 7 bits of the vector value and
1551 * the bit within that register are determined by the lower 5 bits of
1552 * the value.
1553 */
1554 vector_reg = (vector >> 5) & 0x7F;
1555 vector_bit = vector & 0x1F;
80960ab0 1556 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1557}
1558
9a799d71 1559/**
c44ade9e 1560 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1561 * @hw: pointer to hardware structure
2853eb89 1562 * @netdev: pointer to net device structure
9a799d71
AK		 1563 *
1564 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1565 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1566 * registers for the first multicast addresses, and hashes the rest into the
1567 * multicast table.
1568 **/
2853eb89
JP		 1569s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1570 struct net_device *netdev)
9a799d71 1571{
22bedad3 1572 struct netdev_hw_addr *ha;
9a799d71 1573 u32 i;
9a799d71
AK		 1574
1575 /*
1576 * Set the new number of MC addresses that we are being requested to
1577 * use.
1578 */
2853eb89 1579 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1580 hw->addr_ctrl.mta_in_use = 0;
1581
80960ab0 1582 /* Clear mta_shadow */
9a799d71 1583 hw_dbg(hw, " Clearing MTA\n");
80960ab0 1584 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 1585
80960ab0 1586 /* Update mta shadow */
22bedad3 1587 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 1588 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 1589 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 1590 }
1591
1592 /* Enable mta */
80960ab0
ET		 1593 for (i = 0; i < hw->mac.mcft_size; i++)
1594 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1595 hw->mac.mta_shadow[i]);
1596
9a799d71
AK		 1597 if (hw->addr_ctrl.mta_in_use > 0)
1598 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1599 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1600
c44ade9e 1601 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1602 return 0;
1603}
1604
1605/**
c44ade9e 1606 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1607 * @hw: pointer to hardware structure
1608 *
c44ade9e 1609 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1610 **/
c44ade9e 1611s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1612{
c44ade9e 1613 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1614
c44ade9e
JB		 1615 if (a->mta_in_use > 0)
1616 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1617 hw->mac.mc_filter_type);
9a799d71
AK		 1618
1619 return 0;
1620}
1621
1622/**
c44ade9e 1623 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1624 * @hw: pointer to hardware structure
9a799d71 1625 *
c44ade9e 1626 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1627 **/
c44ade9e 1628s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1629{
c44ade9e 1630 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1631
c44ade9e
JB		 1632 if (a->mta_in_use > 0)
1633 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1634
1635 return 0;
1636}
1637
11afc1b1 1638/**
620fa036 1639 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1640 * @hw: pointer to hardware structure
1641 * @packetbuf_num: packet buffer number (0-7)
1642 *
1643 * Enable flow control according to the current settings.
1644 **/
620fa036 1645s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1646{
1647 s32 ret_val = 0;
620fa036 1648 u32 mflcn_reg, fccfg_reg;
11afc1b1 1649 u32 reg;
70b77628 1650 u32 rx_pba_size;
16b61beb 1651 u32 fcrtl, fcrth;
70b77628
PWJ		 1652
1653#ifdef CONFIG_DCB
1654 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1655 goto out;
1656
1657#endif /* CONFIG_DCB */
620fa036
MC		 1658 /* Negotiate the fc mode to use */
1659 ret_val = ixgbe_fc_autoneg(hw);
0b0c2b31 1660 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
620fa036 1661 goto out;
11afc1b1 1662
620fa036 1663 /* Disable any previous flow control settings */
11afc1b1
PW		 1664 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1665 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1666
1667 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1668 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1669
1670 /*
1671 * The possible values of fc.current_mode are:
1672 * 0: Flow control is completely disabled
1673 * 1: Rx flow control is enabled (we can receive pause frames,
1674 * but not send pause frames).
bb3daa4a
PW		 1675 * 2: Tx flow control is enabled (we can send pause frames but
1676 * we do not support receiving pause frames).
11afc1b1 1677 * 3: Both Rx and Tx flow control (symmetric) are enabled.
8c7bea32 1678#ifdef CONFIG_DCB
bb3daa4a 1679 * 4: Priority Flow Control is enabled.
8c7bea32 1680#endif
11afc1b1
PW		 1681 * other: Invalid.
1682 */
1683 switch (hw->fc.current_mode) {
1684 case ixgbe_fc_none:
620fa036
MC		 1685 /*
1686 * Flow control is disabled by software override or autoneg.
1687 * The code below will actually disable it in the HW.
1688 */
11afc1b1
PW		 1689 break;
1690 case ixgbe_fc_rx_pause:
1691 /*
1692 * Rx Flow control is enabled and Tx Flow control is
1693 * disabled by software override. Since there really
1694 * isn't a way to advertise that we are capable of RX
1695 * Pause ONLY, we will advertise that we support both
1696 * symmetric and asymmetric Rx PAUSE. Later, we will
1697 * disable the adapter's ability to send PAUSE frames.
1698 */
1699 mflcn_reg |= IXGBE_MFLCN_RFCE;
1700 break;
1701 case ixgbe_fc_tx_pause:
1702 /*
1703 * Tx Flow control is enabled, and Rx Flow control is
1704 * disabled by software override.
1705 */
1706 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1707 break;
1708 case ixgbe_fc_full:
1709 /* Flow control (both Rx and Tx) is enabled by SW override. */
1710 mflcn_reg |= IXGBE_MFLCN_RFCE;
1711 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1712 break;
bb3daa4a
PW		 1713#ifdef CONFIG_DCB
1714 case ixgbe_fc_pfc:
1715 goto out;
1716 break;
620fa036 1717#endif /* CONFIG_DCB */
11afc1b1
PW		 1718 default:
1719 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1720 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 1721 goto out;
1722 break;
1723 }
1724
620fa036 1725 /* Set 802.3x based flow control settings. */
2132d381 1726 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 1727 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1728 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1729
16b61beb
JF		 1730 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1731 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
620fa036 1732
16b61beb
JF		 1733 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
1734 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
264857b8 1735
16b61beb
JF		 1736 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1737 fcrth |= IXGBE_FCRTH_FCEN;
1738 if (hw->fc.send_xon)
1739 fcrtl |= IXGBE_FCRTL_XONE;
11afc1b1
PW		 1740 }
1741
16b61beb
JF		 1742 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
1743 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
1744
11afc1b1 1745 /* Configure pause time (2 TCs per register) */
70b77628 1746 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 1747 if ((packetbuf_num & 1) == 0)
1748 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1749 else
1750 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1751 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1752
1753 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1754
1755out:
1756 return ret_val;
1757}
1758
0ecc061d
PWJ		 1759/**
1760 * ixgbe_fc_autoneg - Configure flow control
1761 * @hw: pointer to hardware structure
1762 *
620fa036
MC		 1763 * Compares our advertised flow control capabilities to those advertised by
1764 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 1765 **/
1766s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1767{
0b0c2b31 1768 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
620fa036 1769 ixgbe_link_speed speed;
620fa036 1770 bool link_up;
0ecc061d 1771
0b0c2b31
ET		 1772 if (hw->fc.disable_fc_autoneg)
1773 goto out;
1774
0ecc061d 1775 /*
620fa036
MC		 1776 * AN should have completed when the cable was plugged in.
1777 * Look for reasons to bail out. Bail out if:
1778 * - FC autoneg is disabled, or if
539e5f02 1779 * - link is not up.
620fa036 1780 *
539e5f02 1781 * Since we're being called from an LSC, link is already known to be up.
620fa036 1782 * So use link_up_wait_to_complete=false.
0ecc061d 1783 */
620fa036 1784 hw->mac.ops.check_link(hw, &speed, &link_up, false);
0b0c2b31
ET		 1785 if (!link_up) {
1786 ret_val = IXGBE_ERR_FLOW_CONTROL;
0ecc061d
PWJ		 1787 goto out;
1788 }
1789
0b0c2b31
ET		 1790 switch (hw->phy.media_type) {
1791 /* Autoneg flow control on fiber adapters */
1792 case ixgbe_media_type_fiber:
1793 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
1794 ret_val = ixgbe_fc_autoneg_fiber(hw);
1795 break;
000c486d 1796
0b0c2b31
ET		 1797 /* Autoneg flow control on backplane adapters */
1798 case ixgbe_media_type_backplane:
1799 ret_val = ixgbe_fc_autoneg_backplane(hw);
1800 break;
1801
1802 /* Autoneg flow control on copper adapters */
1803 case ixgbe_media_type_copper:
1804 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
1805 ret_val = ixgbe_fc_autoneg_copper(hw);
1806 break;
1807
1808 default:
1809 break;
1810 }
1811
1812out:
1813 if (ret_val == 0) {
1814 hw->fc.fc_was_autonegged = true;
1815 } else {
1816 hw->fc.fc_was_autonegged = false;
1817 hw->fc.current_mode = hw->fc.requested_mode;
539e5f02 1818 }
0b0c2b31
ET		 1819 return ret_val;
1820}
1821
1822/**
1823 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1824 * @hw: pointer to hardware structure
1825 *
1826 * Enable flow control according on 1 gig fiber.
1827 **/
1828static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
1829{
1830 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1831 s32 ret_val;
539e5f02
PWJ		 1832
1833 /*
1834 * On multispeed fiber at 1g, bail out if
1835 * - link is up but AN did not complete, or if
1836 * - link is up and AN completed but timed out
1837 */
0b0c2b31
ET		 1838
1839 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1840 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1841 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1842 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
1843 goto out;
539e5f02
PWJ		 1844 }
1845
0b0c2b31
ET		 1846 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1847 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1848
1849 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
1850 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
1851 IXGBE_PCS1GANA_ASM_PAUSE,
1852 IXGBE_PCS1GANA_SYM_PAUSE,
1853 IXGBE_PCS1GANA_ASM_PAUSE);
1854
1855out:
1856 return ret_val;
1857}
1858
1859/**
1860 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1861 * @hw: pointer to hardware structure
1862 *
1863 * Enable flow control according to IEEE clause 37.
1864 **/
1865static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
1866{
1867 u32 links2, anlp1_reg, autoc_reg, links;
1868 s32 ret_val;
1869
9bbe3a57 1870 /*
0b0c2b31
ET		 1871 * On backplane, bail out if
1872 * - backplane autoneg was not completed, or if
1873 * - we are 82599 and link partner is not AN enabled
9bbe3a57 1874 */
0b0c2b31
ET		 1875 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
1876 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
9bbe3a57
PW		 1877 hw->fc.fc_was_autonegged = false;
1878 hw->fc.current_mode = hw->fc.requested_mode;
0b0c2b31 1879 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57
PW		 1880 goto out;
1881 }
1882
0b0c2b31
ET		 1883 if (hw->mac.type == ixgbe_mac_82599EB) {
1884 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1885 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1886 hw->fc.fc_was_autonegged = false;
1887 hw->fc.current_mode = hw->fc.requested_mode;
1888 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
1889 goto out;
1890 }
1891 }
0ecc061d 1892 /*
0b0c2b31 1893 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 1894 * local flow control settings accordingly
1895 */
0b0c2b31
ET		 1896 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1897 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 1898
0b0c2b31
ET		 1899 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
1900 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
1901 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
1902
1903out:
1904 return ret_val;
1905}
1906
1907/**
1908 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1909 * @hw: pointer to hardware structure
1910 *
1911 * Enable flow control according to IEEE clause 37.
1912 **/
1913static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
1914{
1915 u16 technology_ability_reg = 0;
1916 u16 lp_technology_ability_reg = 0;
1917
1918 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1919 MDIO_MMD_AN,
1920 &technology_ability_reg);
1921 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
1922 MDIO_MMD_AN,
1923 &lp_technology_ability_reg);
1924
1925 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1926 (u32)lp_technology_ability_reg,
1927 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
1928 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
1929}
1930
1931/**
1932 * ixgbe_negotiate_fc - Negotiate flow control
1933 * @hw: pointer to hardware structure
1934 * @adv_reg: flow control advertised settings
1935 * @lp_reg: link partner's flow control settings
1936 * @adv_sym: symmetric pause bit in advertisement
1937 * @adv_asm: asymmetric pause bit in advertisement
1938 * @lp_sym: symmetric pause bit in link partner advertisement
1939 * @lp_asm: asymmetric pause bit in link partner advertisement
1940 *
1941 * Find the intersection between advertised settings and link partner's
1942 * advertised settings
1943 **/
1944static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1945 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
1946{
1947 if ((!(adv_reg)) || (!(lp_reg)))
1948 return IXGBE_ERR_FC_NOT_NEGOTIATED;
1949
1950 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
0ecc061d 1951 /*
0b0c2b31
ET		 1952 * Now we need to check if the user selected Rx ONLY
1953 * of pause frames. In this case, we had to advertise
1954 * FULL flow control because we could not advertise RX
1955 * ONLY. Hence, we must now check to see if we need to
1956 * turn OFF the TRANSMISSION of PAUSE frames.
0ecc061d 1957 */
0b0c2b31
ET		 1958 if (hw->fc.requested_mode == ixgbe_fc_full) {
1959 hw->fc.current_mode = ixgbe_fc_full;
1960 hw_dbg(hw, "Flow Control = FULL.\n");
539e5f02 1961 } else {
0b0c2b31
ET		 1962 hw->fc.current_mode = ixgbe_fc_rx_pause;
1963 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
0ecc061d 1964 }
0b0c2b31
ET		 1965 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1966 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1967 hw->fc.current_mode = ixgbe_fc_tx_pause;
1968 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1969 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1970 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1971 hw->fc.current_mode = ixgbe_fc_rx_pause;
1972 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1973 } else {
1974 hw->fc.current_mode = ixgbe_fc_none;
1975 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 1976 }
0b0c2b31 1977 return 0;
0ecc061d
PWJ		 1978}
1979
11afc1b1 1980/**
620fa036 1981 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 1982 * @hw: pointer to hardware structure
1983 *
620fa036 1984 * Called at init time to set up flow control.
11afc1b1 1985 **/
7b25cdba 1986static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1987{
1988 s32 ret_val = 0;
0b0c2b31
ET		 1989 u32 reg = 0, reg_bp = 0;
1990 u16 reg_cu = 0;
11afc1b1 1991
bb3daa4a
PW		 1992#ifdef CONFIG_DCB
1993 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1994 hw->fc.current_mode = hw->fc.requested_mode;
1995 goto out;
1996 }
1997
0b0c2b31 1998#endif /* CONFIG_DCB */
11afc1b1
PW		 1999 /* Validate the packetbuf configuration */
2000 if (packetbuf_num < 0 || packetbuf_num > 7) {
2001 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
2002 "is 0-7\n", packetbuf_num);
2003 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2004 goto out;
2005 }
2006
2007 /*
2008 * Validate the water mark configuration. Zero water marks are invalid
2009 * because it causes the controller to just blast out fc packets.
2010 */
2011 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
620fa036
MC		 2012 hw_dbg(hw, "Invalid water mark configuration\n");
2013 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2014 goto out;
11afc1b1
PW		 2015 }
2016
2017 /*
2018 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 2019 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 2020 */
2021 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2022 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
2023 "IEEE mode\n");
2024 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2025 goto out;
2026 }
2027
2028 /*
2029 * 10gig parts do not have a word in the EEPROM to determine the
2030 * default flow control setting, so we explicitly set it to full.
2031 */
2032 if (hw->fc.requested_mode == ixgbe_fc_default)
2033 hw->fc.requested_mode = ixgbe_fc_full;
2034
2035 /*
0b0c2b31
ET		 2036 * Set up the 1G and 10G flow control advertisement registers so the
2037 * HW will be able to do fc autoneg once the cable is plugged in. If
2038 * we link at 10G, the 1G advertisement is harmless and vice versa.
11afc1b1 2039 */
0b0c2b31
ET		 2040
2041 switch (hw->phy.media_type) {
2042 case ixgbe_media_type_fiber:
2043 case ixgbe_media_type_backplane:
2044 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2045 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2046 break;
2047
2048 case ixgbe_media_type_copper:
2049 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2050 MDIO_MMD_AN, &reg_cu);
2051 break;
2052
2053 default:
2054 ;
2055 }
11afc1b1 2056
620fa036
MC		 2057 /*
2058 * The possible values of fc.requested_mode are:
2059 * 0: Flow control is completely disabled
2060 * 1: Rx flow control is enabled (we can receive pause frames,
2061 * but not send pause frames).
2062 * 2: Tx flow control is enabled (we can send pause frames but
2063 * we do not support receiving pause frames).
2064 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2065#ifdef CONFIG_DCB
2066 * 4: Priority Flow Control is enabled.
2067#endif
2068 * other: Invalid.
2069 */
2070 switch (hw->fc.requested_mode) {
2071 case ixgbe_fc_none:
2072 /* Flow control completely disabled by software override. */
2073 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2074 if (hw->phy.media_type == ixgbe_media_type_backplane)
2075 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
2076 IXGBE_AUTOC_ASM_PAUSE);
2077 else if (hw->phy.media_type == ixgbe_media_type_copper)
2078 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2079 break;
2080 case ixgbe_fc_rx_pause:
2081 /*
2082 * Rx Flow control is enabled and Tx Flow control is
2083 * disabled by software override. Since there really
2084 * isn't a way to advertise that we are capable of RX
2085 * Pause ONLY, we will advertise that we support both
2086 * symmetric and asymmetric Rx PAUSE. Later, we will
2087 * disable the adapter's ability to send PAUSE frames.
2088 */
2089 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2090 if (hw->phy.media_type == ixgbe_media_type_backplane)
2091 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2092 IXGBE_AUTOC_ASM_PAUSE);
2093 else if (hw->phy.media_type == ixgbe_media_type_copper)
2094 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2095 break;
2096 case ixgbe_fc_tx_pause:
2097 /*
2098 * Tx Flow control is enabled, and Rx Flow control is
2099 * disabled by software override.
2100 */
2101 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2102 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
0b0c2b31
ET		 2103 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2104 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
2105 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
2106 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
2107 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
2108 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
2109 }
620fa036
MC		 2110 break;
2111 case ixgbe_fc_full:
2112 /* Flow control (both Rx and Tx) is enabled by SW override. */
2113 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2114 if (hw->phy.media_type == ixgbe_media_type_backplane)
2115 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2116 IXGBE_AUTOC_ASM_PAUSE);
2117 else if (hw->phy.media_type == ixgbe_media_type_copper)
2118 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2119 break;
2120#ifdef CONFIG_DCB
2121 case ixgbe_fc_pfc:
11afc1b1 2122 goto out;
620fa036
MC		 2123 break;
2124#endif /* CONFIG_DCB */
2125 default:
2126 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2127 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 2128 goto out;
2129 break;
2130 }
2131
0b0c2b31
ET		 2132 if (hw->mac.type != ixgbe_mac_X540) {
2133 /*
2134 * Enable auto-negotiation between the MAC & PHY;
2135 * the MAC will advertise clause 37 flow control.
2136 */
2137 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2138 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
620fa036 2139
0b0c2b31
ET		 2140 /* Disable AN timeout */
2141 if (hw->fc.strict_ieee)
2142 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
11afc1b1 2143
0b0c2b31
ET		 2144 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2145 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2146 }
539e5f02
PWJ		 2147
2148 /*
0b0c2b31
ET		 2149 * AUTOC restart handles negotiation of 1G and 10G on backplane
2150 * and copper. There is no need to set the PCS1GCTL register.
2151 *
539e5f02 2152 */
0b0c2b31
ET		 2153 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2154 reg_bp |= IXGBE_AUTOC_AN_RESTART;
2155 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
2156 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
2157 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
2158 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
2159 MDIO_MMD_AN, reg_cu);
539e5f02 2160 }
539e5f02 2161
0b0c2b31 2162 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
11afc1b1
PW		 2163out:
2164 return ret_val;
2165}
2166
9a799d71
AK		 2167/**
2168 * ixgbe_disable_pcie_master - Disable PCI-express master access
2169 * @hw: pointer to hardware structure
2170 *
2171 * Disables PCI-Express master access and verifies there are no pending
2172 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2173 * bit hasn't caused the master requests to be disabled, else 0
2174 * is returned signifying master requests disabled.
2175 **/
2176s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2177{
a4297dc2 2178 struct ixgbe_adapter *adapter = hw->back;
c44ade9e
JB		 2179 u32 i;
2180 u32 reg_val;
2181 u32 number_of_queues;
a4297dc2
ET		 2182 s32 status = 0;
2183 u16 dev_status = 0;
2184
2185 /* Just jump out if bus mastering is already disabled */
2186 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2187 goto out;
9a799d71 2188
c44ade9e
JB		 2189 /* Disable the receive unit by stopping each queue */
2190 number_of_queues = hw->mac.max_rx_queues;
2191 for (i = 0; i < number_of_queues; i++) {
2192 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2193 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2194 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2195 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2196 }
2197 }
2198
2199 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2200 reg_val |= IXGBE_CTRL_GIO_DIS;
2201 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 2202
2203 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2
ET		 2204 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2205 goto check_device_status;
2206 udelay(100);
2207 }
2208
2209 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2210 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2211
2212 /*
2213 * Before proceeding, make sure that the PCIe block does not have
2214 * transactions pending.
2215 */
2216check_device_status:
2217 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2218 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2219 &dev_status);
2220 if (!(dev_status & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
9a799d71 2221 break;
9a799d71
AK		 2222 udelay(100);
2223 }
2224
a4297dc2
ET		 2225 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2226 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2227 else
2228 goto out;
2229
2230 /*
2231 * Two consecutive resets are required via CTRL.RST per datasheet
2232 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2233 * of this need. The first reset prevents new master requests from
2234 * being issued by our device. We then must wait 1usec for any
2235 * remaining completions from the PCIe bus to trickle in, and then reset
2236 * again to clear out any effects they may have had on our device.
2237 */
2238 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2239
2240out:
9a799d71
AK		 2241 return status;
2242}
2243
2244
2245/**
c44ade9e 2246 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2247 * @hw: pointer to hardware structure
c44ade9e 2248 * @mask: Mask to specify which semaphore to acquire
9a799d71 2249 *
da74cd4a 2250 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2251 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2252 **/
2253s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2254{
2255 u32 gssr;
2256 u32 swmask = mask;
2257 u32 fwmask = mask << 5;
2258 s32 timeout = 200;
2259
2260 while (timeout) {
dbf893ee
ET		 2261 /*
2262 * SW EEPROM semaphore bit is used for access to all
2263 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2264 */
9a799d71 2265 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2266 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2267
2268 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2269 if (!(gssr & (fwmask | swmask)))
2270 break;
2271
2272 /*
2273 * Firmware currently using resource (fwmask) or other software
2274 * thread currently using resource (swmask)
2275 */
2276 ixgbe_release_eeprom_semaphore(hw);
032b4325 2277 usleep_range(5000, 10000);
9a799d71
AK		 2278 timeout--;
2279 }
2280
2281 if (!timeout) {
dbf893ee 2282 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
539e5f02 2283 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2284 }
2285
2286 gssr |= swmask;
2287 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2288
2289 ixgbe_release_eeprom_semaphore(hw);
2290 return 0;
2291}
2292
2293/**
2294 * ixgbe_release_swfw_sync - Release SWFW semaphore
2295 * @hw: pointer to hardware structure
c44ade9e 2296 * @mask: Mask to specify which semaphore to release
9a799d71 2297 *
da74cd4a 2298 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2299 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2300 **/
2301void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2302{
2303 u32 gssr;
2304 u32 swmask = mask;
2305
2306 ixgbe_get_eeprom_semaphore(hw);
2307
2308 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2309 gssr &= ~swmask;
2310 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2311
2312 ixgbe_release_eeprom_semaphore(hw);
2313}
2314
11afc1b1
PW		 2315/**
2316 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2317 * @hw: pointer to hardware structure
2318 * @regval: register value to write to RXCTRL
2319 *
2320 * Enables the Rx DMA unit
2321 **/
2322s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2323{
2324 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2325
2326 return 0;
2327}
87c12017
PW		 2328
2329/**
2330 * ixgbe_blink_led_start_generic - Blink LED based on index.
2331 * @hw: pointer to hardware structure
2332 * @index: led number to blink
2333 **/
2334s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2335{
2336 ixgbe_link_speed speed = 0;
2337 bool link_up = 0;
2338 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2339 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2340
2341 /*
2342 * Link must be up to auto-blink the LEDs;
2343 * Force it if link is down.
2344 */
2345 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2346
2347 if (!link_up) {
50ac58ba 2348 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2349 autoc_reg |= IXGBE_AUTOC_FLU;
2350 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
032b4325 2351 usleep_range(10000, 20000);
87c12017
PW		 2352 }
2353
2354 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2355 led_reg |= IXGBE_LED_BLINK(index);
2356 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2357 IXGBE_WRITE_FLUSH(hw);
2358
2359 return 0;
2360}
2361
2362/**
2363 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2364 * @hw: pointer to hardware structure
2365 * @index: led number to stop blinking
2366 **/
2367s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2368{
2369 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2370 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2371
2372 autoc_reg &= ~IXGBE_AUTOC_FLU;
2373 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2374 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2375
2376 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2377 led_reg &= ~IXGBE_LED_BLINK(index);
2378 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2379 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2380 IXGBE_WRITE_FLUSH(hw);
2381
2382 return 0;
2383}
21ce849b
MC		 2384
2385/**
2386 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2387 * @hw: pointer to hardware structure
2388 * @san_mac_offset: SAN MAC address offset
2389 *
2390 * This function will read the EEPROM location for the SAN MAC address
2391 * pointer, and returns the value at that location. This is used in both
2392 * get and set mac_addr routines.
2393 **/
2394static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2395 u16 *san_mac_offset)
2396{
2397 /*
2398 * First read the EEPROM pointer to see if the MAC addresses are
2399 * available.
2400 */
2401 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2402
2403 return 0;
2404}
2405
2406/**
2407 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2408 * @hw: pointer to hardware structure
2409 * @san_mac_addr: SAN MAC address
2410 *
2411 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2412 * per-port, so set_lan_id() must be called before reading the addresses.
2413 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2414 * upon for non-SFP connections, so we must call it here.
2415 **/
2416s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2417{
2418 u16 san_mac_data, san_mac_offset;
2419 u8 i;
2420
2421 /*
2422 * First read the EEPROM pointer to see if the MAC addresses are
2423 * available. If they're not, no point in calling set_lan_id() here.
2424 */
2425 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2426
2427 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2428 /*
2429 * No addresses available in this EEPROM. It's not an
2430 * error though, so just wipe the local address and return.
2431 */
2432 for (i = 0; i < 6; i++)
2433 san_mac_addr[i] = 0xFF;
2434
2435 goto san_mac_addr_out;
2436 }
2437
2438 /* make sure we know which port we need to program */
2439 hw->mac.ops.set_lan_id(hw);
2440 /* apply the port offset to the address offset */
2441 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2442 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2443 for (i = 0; i < 3; i++) {
2444 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2445 san_mac_addr[i * 2] = (u8)(san_mac_data);
2446 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2447 san_mac_offset++;
2448 }
2449
2450san_mac_addr_out:
2451 return 0;
2452}
2453
2454/**
2455 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2456 * @hw: pointer to hardware structure
2457 *
2458 * Read PCIe configuration space, and get the MSI-X vector count from
2459 * the capabilities table.
2460 **/
2461u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2462{
2463 struct ixgbe_adapter *adapter = hw->back;
2464 u16 msix_count;
2465 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2466 &msix_count);
2467 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2468
2469 /* MSI-X count is zero-based in HW, so increment to give proper value */
2470 msix_count++;
2471
2472 return msix_count;
2473}
2474
2475/**
2476 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2477 * @hw: pointer to hardware struct
2478 * @rar: receive address register index to disassociate
2479 * @vmdq: VMDq pool index to remove from the rar
2480 **/
2481s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2482{
2483 u32 mpsar_lo, mpsar_hi;
2484 u32 rar_entries = hw->mac.num_rar_entries;
2485
c700f4e6
ET		 2486 /* Make sure we are using a valid rar index range */
2487 if (rar >= rar_entries) {
2488 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2489 return IXGBE_ERR_INVALID_ARGUMENT;
2490 }
21ce849b 2491
c700f4e6
ET		 2492 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2493 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2494
c700f4e6
ET		 2495 if (!mpsar_lo && !mpsar_hi)
2496 goto done;
21ce849b 2497
c700f4e6
ET		 2498 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2499 if (mpsar_lo) {
2500 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2501 mpsar_lo = 0;
2502 }
2503 if (mpsar_hi) {
2504 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2505 mpsar_hi = 0;
2506 }
2507 } else if (vmdq < 32) {
2508 mpsar_lo &= ~(1 << vmdq);
2509 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2510 } else {
c700f4e6
ET		 2511 mpsar_hi &= ~(1 << (vmdq - 32));
2512 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2513 }
2514
c700f4e6
ET		 2515 /* was that the last pool using this rar? */
2516 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2517 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2518done:
2519 return 0;
2520}
2521
2522/**
2523 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2524 * @hw: pointer to hardware struct
2525 * @rar: receive address register index to associate with a VMDq index
2526 * @vmdq: VMDq pool index
2527 **/
2528s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2529{
2530 u32 mpsar;
2531 u32 rar_entries = hw->mac.num_rar_entries;
2532
c700f4e6
ET		 2533 /* Make sure we are using a valid rar index range */
2534 if (rar >= rar_entries) {
21ce849b 2535 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2536 return IXGBE_ERR_INVALID_ARGUMENT;
2537 }
2538
2539 if (vmdq < 32) {
2540 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2541 mpsar |= 1 << vmdq;
2542 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2543 } else {
2544 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2545 mpsar |= 1 << (vmdq - 32);
2546 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2547 }
2548 return 0;
2549}
2550
2551/**
2552 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2553 * @hw: pointer to hardware structure
2554 **/
2555s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2556{
2557 int i;
2558
21ce849b
MC		 2559 for (i = 0; i < 128; i++)
2560 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2561
2562 return 0;
2563}
2564
2565/**
2566 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2567 * @hw: pointer to hardware structure
2568 * @vlan: VLAN id to write to VLAN filter
2569 *
2570 * return the VLVF index where this VLAN id should be placed
2571 *
2572 **/
5d5b7c39 2573static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2574{
2575 u32 bits = 0;
2576 u32 first_empty_slot = 0;
2577 s32 regindex;
2578
2579 /* short cut the special case */
2580 if (vlan == 0)
2581 return 0;
2582
2583 /*
2584 * Search for the vlan id in the VLVF entries. Save off the first empty
2585 * slot found along the way
2586 */
2587 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2588 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2589 if (!bits && !(first_empty_slot))
2590 first_empty_slot = regindex;
2591 else if ((bits & 0x0FFF) == vlan)
2592 break;
2593 }
2594
2595 /*
2596 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2597 * in the VLVF. Else use the first empty VLVF register for this
2598 * vlan id.
2599 */
2600 if (regindex >= IXGBE_VLVF_ENTRIES) {
2601 if (first_empty_slot)
2602 regindex = first_empty_slot;
2603 else {
2604 hw_dbg(hw, "No space in VLVF.\n");
2605 regindex = IXGBE_ERR_NO_SPACE;
2606 }
2607 }
2608
2609 return regindex;
2610}
2611
2612/**
2613 * ixgbe_set_vfta_generic - Set VLAN filter table
2614 * @hw: pointer to hardware structure
2615 * @vlan: VLAN id to write to VLAN filter
2616 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2617 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2618 *
2619 * Turn on/off specified VLAN in the VLAN filter table.
2620 **/
2621s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2622 bool vlan_on)
2623{
2624 s32 regindex;
2625 u32 bitindex;
2626 u32 vfta;
2627 u32 bits;
2628 u32 vt;
2629 u32 targetbit;
2630 bool vfta_changed = false;
2631
2632 if (vlan > 4095)
2633 return IXGBE_ERR_PARAM;
2634
2635 /*
2636 * this is a 2 part operation - first the VFTA, then the
2637 * VLVF and VLVFB if VT Mode is set
2638 * We don't write the VFTA until we know the VLVF part succeeded.
2639 */
2640
2641 /* Part 1
2642 * The VFTA is a bitstring made up of 128 32-bit registers
2643 * that enable the particular VLAN id, much like the MTA:
2644 * bits[11-5]: which register
2645 * bits[4-0]: which bit in the register
2646 */
2647 regindex = (vlan >> 5) & 0x7F;
2648 bitindex = vlan & 0x1F;
2649 targetbit = (1 << bitindex);
2650 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2651
2652 if (vlan_on) {
2653 if (!(vfta & targetbit)) {
2654 vfta |= targetbit;
2655 vfta_changed = true;
2656 }
2657 } else {
2658 if ((vfta & targetbit)) {
2659 vfta &= ~targetbit;
2660 vfta_changed = true;
2661 }
2662 }
2663
2664 /* Part 2
2665 * If VT Mode is set
2666 * Either vlan_on
2667 * make sure the vlan is in VLVF
2668 * set the vind bit in the matching VLVFB
2669 * Or !vlan_on
2670 * clear the pool bit and possibly the vind
2671 */
2672 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2673 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2674 s32 vlvf_index;
2675
2676 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2677 if (vlvf_index < 0)
2678 return vlvf_index;
2679
2680 if (vlan_on) {
2681 /* set the pool bit */
2682 if (vind < 32) {
2683 bits = IXGBE_READ_REG(hw,
2684 IXGBE_VLVFB(vlvf_index*2));
2685 bits |= (1 << vind);
2686 IXGBE_WRITE_REG(hw,
2687 IXGBE_VLVFB(vlvf_index*2),
2688 bits);
2689 } else {
2690 bits = IXGBE_READ_REG(hw,
2691 IXGBE_VLVFB((vlvf_index*2)+1));
2692 bits |= (1 << (vind-32));
2693 IXGBE_WRITE_REG(hw,
2694 IXGBE_VLVFB((vlvf_index*2)+1),
2695 bits);
2696 }
2697 } else {
2698 /* clear the pool bit */
2699 if (vind < 32) {
2700 bits = IXGBE_READ_REG(hw,
2701 IXGBE_VLVFB(vlvf_index*2));
2702 bits &= ~(1 << vind);
2703 IXGBE_WRITE_REG(hw,
2704 IXGBE_VLVFB(vlvf_index*2),
2705 bits);
2706 bits |= IXGBE_READ_REG(hw,
2707 IXGBE_VLVFB((vlvf_index*2)+1));
2708 } else {
2709 bits = IXGBE_READ_REG(hw,
2710 IXGBE_VLVFB((vlvf_index*2)+1));
2711 bits &= ~(1 << (vind-32));
2712 IXGBE_WRITE_REG(hw,
2713 IXGBE_VLVFB((vlvf_index*2)+1),
2714 bits);
2715 bits |= IXGBE_READ_REG(hw,
2716 IXGBE_VLVFB(vlvf_index*2));
2717 }
2718 }
2719
2720 /*
2721 * If there are still bits set in the VLVFB registers
2722 * for the VLAN ID indicated we need to see if the
2723 * caller is requesting that we clear the VFTA entry bit.
2724 * If the caller has requested that we clear the VFTA
2725 * entry bit but there are still pools/VFs using this VLAN
2726 * ID entry then ignore the request. We're not worried
2727 * about the case where we're turning the VFTA VLAN ID
2728 * entry bit on, only when requested to turn it off as
2729 * there may be multiple pools and/or VFs using the
2730 * VLAN ID entry. In that case we cannot clear the
2731 * VFTA bit until all pools/VFs using that VLAN ID have also
2732 * been cleared. This will be indicated by "bits" being
2733 * zero.
2734 */
2735 if (bits) {
2736 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
2737 (IXGBE_VLVF_VIEN | vlan));
2738 if (!vlan_on) {
2739 /* someone wants to clear the vfta entry
2740 * but some pools/VFs are still using it.
2741 * Ignore it. */
2742 vfta_changed = false;
2743 }
2744 }
2745 else
2746 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
2747 }
2748
2749 if (vfta_changed)
2750 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
2751
2752 return 0;
2753}
2754
2755/**
2756 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2757 * @hw: pointer to hardware structure
2758 *
2759 * Clears the VLAN filer table, and the VMDq index associated with the filter
2760 **/
2761s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2762{
2763 u32 offset;
2764
2765 for (offset = 0; offset < hw->mac.vft_size; offset++)
2766 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2767
2768 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2769 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2770 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2771 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2772 }
2773
2774 return 0;
2775}
2776
2777/**
2778 * ixgbe_check_mac_link_generic - Determine link and speed status
2779 * @hw: pointer to hardware structure
2780 * @speed: pointer to link speed
2781 * @link_up: true when link is up
2782 * @link_up_wait_to_complete: bool used to wait for link up or not
2783 *
2784 * Reads the links register to determine if link is up and the current speed
2785 **/
2786s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 2787 bool *link_up, bool link_up_wait_to_complete)
21ce849b 2788{
48de36c5 2789 u32 links_reg, links_orig;
21ce849b
MC		 2790 u32 i;
2791
48de36c5
ET		 2792 /* clear the old state */
2793 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
2794
21ce849b 2795 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 2796
2797 if (links_orig != links_reg) {
2798 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
2799 links_orig, links_reg);
2800 }
2801
21ce849b
MC		 2802 if (link_up_wait_to_complete) {
2803 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2804 if (links_reg & IXGBE_LINKS_UP) {
2805 *link_up = true;
2806 break;
2807 } else {
2808 *link_up = false;
2809 }
2810 msleep(100);
2811 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2812 }
2813 } else {
2814 if (links_reg & IXGBE_LINKS_UP)
2815 *link_up = true;
2816 else
2817 *link_up = false;
2818 }
2819
2820 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2821 IXGBE_LINKS_SPEED_10G_82599)
2822 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2823 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
63d778df 2824 IXGBE_LINKS_SPEED_1G_82599)
21ce849b 2825 *speed = IXGBE_LINK_SPEED_1GB_FULL;
63d778df
ET		 2826 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2827 IXGBE_LINKS_SPEED_100_82599)
21ce849b 2828 *speed = IXGBE_LINK_SPEED_100_FULL;
63d778df
ET		 2829 else
2830 *speed = IXGBE_LINK_SPEED_UNKNOWN;
21ce849b
MC		 2831
2832 /* if link is down, zero out the current_mode */
2833 if (*link_up == false) {
2834 hw->fc.current_mode = ixgbe_fc_none;
2835 hw->fc.fc_was_autonegged = false;
2836 }
2837
2838 return 0;
2839}
a391f1d5
DS		 2840
2841/**
2842 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
2843 * the EEPROM
2844 * @hw: pointer to hardware structure
2845 * @wwnn_prefix: the alternative WWNN prefix
2846 * @wwpn_prefix: the alternative WWPN prefix
2847 *
2848 * This function will read the EEPROM from the alternative SAN MAC address
2849 * block to check the support for the alternative WWNN/WWPN prefix support.
2850 **/
2851s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2852 u16 *wwpn_prefix)
2853{
2854 u16 offset, caps;
2855 u16 alt_san_mac_blk_offset;
2856
2857 /* clear output first */
2858 *wwnn_prefix = 0xFFFF;
2859 *wwpn_prefix = 0xFFFF;
2860
2861 /* check if alternative SAN MAC is supported */
2862 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2863 &alt_san_mac_blk_offset);
2864
2865 if ((alt_san_mac_blk_offset == 0) ||
2866 (alt_san_mac_blk_offset == 0xFFFF))
2867 goto wwn_prefix_out;
2868
2869 /* check capability in alternative san mac address block */
2870 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2871 hw->eeprom.ops.read(hw, offset, &caps);
2872 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2873 goto wwn_prefix_out;
2874
2875 /* get the corresponding prefix for WWNN/WWPN */
2876 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2877 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2878
2879 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2880 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2881
2882wwn_prefix_out:
2883 return 0;
2884}
a985b6c3 2885
0b0c2b31
ET		 2886/**
2887 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
2888 * control
2889 * @hw: pointer to hardware structure
2890 *
2891 * There are several phys that do not support autoneg flow control. This
2892 * function check the device id to see if the associated phy supports
2893 * autoneg flow control.
2894 **/
2895static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
2896{
2897
2898 switch (hw->device_id) {
2899 case IXGBE_DEV_ID_X540T:
2900 return 0;
2901 case IXGBE_DEV_ID_82599_T3_LOM:
2902 return 0;
2903 default:
2904 return IXGBE_ERR_FC_NOT_SUPPORTED;
2905 }
2906}
2907
a985b6c3
GR		 2908/**
2909 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2910 * @hw: pointer to hardware structure
2911 * @enable: enable or disable switch for anti-spoofing
2912 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
2913 *
2914 **/
2915void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
2916{
2917 int j;
2918 int pf_target_reg = pf >> 3;
2919 int pf_target_shift = pf % 8;
2920 u32 pfvfspoof = 0;
2921
2922 if (hw->mac.type == ixgbe_mac_82598EB)
2923 return;
2924
2925 if (enable)
2926 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
2927
2928 /*
2929 * PFVFSPOOF register array is size 8 with 8 bits assigned to
2930 * MAC anti-spoof enables in each register array element.
2931 */
2932 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
2933 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
2934
2935 /* If not enabling anti-spoofing then done */
2936 if (!enable)
2937 return;
2938
2939 /*
2940 * The PF should be allowed to spoof so that it can support
2941 * emulation mode NICs. Reset the bit assigned to the PF
2942 */
2943 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
2944 pfvfspoof ^= (1 << pf_target_shift);
2945 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
2946}
2947
2948/**
2949 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
2950 * @hw: pointer to hardware structure
2951 * @enable: enable or disable switch for VLAN anti-spoofing
2952 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
2953 *
2954 **/
2955void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
2956{
2957 int vf_target_reg = vf >> 3;
2958 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
2959 u32 pfvfspoof;
2960
2961 if (hw->mac.type == ixgbe_mac_82598EB)
2962 return;
2963
2964 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2965 if (enable)
2966 pfvfspoof |= (1 << vf_target_shift);
2967 else
2968 pfvfspoof &= ~(1 << vf_target_shift);
2969 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2970}
b776d104
ET		 2971
2972/**
2973 * ixgbe_get_device_caps_generic - Get additional device capabilities
2974 * @hw: pointer to hardware structure
2975 * @device_caps: the EEPROM word with the extra device capabilities
2976 *
2977 * This function will read the EEPROM location for the device capabilities,
2978 * and return the word through device_caps.
2979 **/
2980s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
2981{
2982 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2983
2984 return 0;
2985}
Linux kernel - Deliverables
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