Commit | Line | Data |
---|---|---|
9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
4 | Copyright(c) 1999 - 2007 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/pci.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/sched.h> | |
32 | ||
33 | #include "ixgbe_common.h" | |
34 | #include "ixgbe_phy.h" | |
35 | ||
36 | static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw); | |
37 | ||
38 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); | |
39 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); | |
40 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); | |
41 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); | |
42 | ||
43 | static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw); | |
44 | static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw); | |
45 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); | |
46 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); | |
47 | ||
48 | /** | |
49 | * ixgbe_start_hw - Prepare hardware for TX/RX | |
50 | * @hw: pointer to hardware structure | |
51 | * | |
52 | * Starts the hardware by filling the bus info structure and media type, clears | |
53 | * all on chip counters, initializes receive address registers, multicast | |
54 | * table, VLAN filter table, calls routine to set up link and flow control | |
55 | * settings, and leaves transmit and receive units disabled and uninitialized | |
56 | **/ | |
57 | s32 ixgbe_start_hw(struct ixgbe_hw *hw) | |
58 | { | |
59 | u32 ctrl_ext; | |
60 | ||
61 | /* Set the media type */ | |
62 | hw->phy.media_type = hw->mac.ops.get_media_type(hw); | |
63 | ||
64 | /* Identify the PHY */ | |
65 | ixgbe_identify_phy(hw); | |
66 | ||
67 | /* | |
68 | * Store MAC address from RAR0, clear receive address registers, and | |
69 | * clear the multicast table | |
70 | */ | |
71 | ixgbe_init_rx_addrs(hw); | |
72 | ||
73 | /* Clear the VLAN filter table */ | |
74 | ixgbe_clear_vfta(hw); | |
75 | ||
76 | /* Set up link */ | |
3957d63d | 77 | hw->mac.ops.setup_link(hw); |
9a799d71 AK |
78 | |
79 | /* Clear statistics registers */ | |
80 | ixgbe_clear_hw_cntrs(hw); | |
81 | ||
82 | /* Set No Snoop Disable */ | |
83 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
84 | ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; | |
85 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3957d63d | 86 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
87 | |
88 | /* Clear adapter stopped flag */ | |
89 | hw->adapter_stopped = false; | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
94 | /** | |
95 | * ixgbe_init_hw - Generic hardware initialization | |
96 | * @hw: pointer to hardware structure | |
97 | * | |
98 | * Initialize the hardware by reseting the hardware, filling the bus info | |
99 | * structure and media type, clears all on chip counters, initializes receive | |
100 | * address registers, multicast table, VLAN filter table, calls routine to set | |
101 | * up link and flow control settings, and leaves transmit and receive units | |
102 | * disabled and uninitialized | |
103 | **/ | |
104 | s32 ixgbe_init_hw(struct ixgbe_hw *hw) | |
105 | { | |
106 | /* Reset the hardware */ | |
107 | hw->mac.ops.reset(hw); | |
108 | ||
109 | /* Start the HW */ | |
110 | ixgbe_start_hw(hw); | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | /** | |
116 | * ixgbe_clear_hw_cntrs - Generic clear hardware counters | |
117 | * @hw: pointer to hardware structure | |
118 | * | |
119 | * Clears all hardware statistics counters by reading them from the hardware | |
120 | * Statistics counters are clear on read. | |
121 | **/ | |
122 | static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) | |
123 | { | |
124 | u16 i = 0; | |
125 | ||
126 | IXGBE_READ_REG(hw, IXGBE_CRCERRS); | |
127 | IXGBE_READ_REG(hw, IXGBE_ILLERRC); | |
128 | IXGBE_READ_REG(hw, IXGBE_ERRBC); | |
129 | IXGBE_READ_REG(hw, IXGBE_MSPDC); | |
130 | for (i = 0; i < 8; i++) | |
131 | IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
132 | ||
133 | IXGBE_READ_REG(hw, IXGBE_MLFC); | |
134 | IXGBE_READ_REG(hw, IXGBE_MRFC); | |
135 | IXGBE_READ_REG(hw, IXGBE_RLEC); | |
136 | IXGBE_READ_REG(hw, IXGBE_LXONTXC); | |
137 | IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
138 | IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
139 | IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
140 | ||
141 | for (i = 0; i < 8; i++) { | |
142 | IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); | |
143 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
144 | IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
145 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
146 | } | |
147 | ||
148 | IXGBE_READ_REG(hw, IXGBE_PRC64); | |
149 | IXGBE_READ_REG(hw, IXGBE_PRC127); | |
150 | IXGBE_READ_REG(hw, IXGBE_PRC255); | |
151 | IXGBE_READ_REG(hw, IXGBE_PRC511); | |
152 | IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
153 | IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
154 | IXGBE_READ_REG(hw, IXGBE_GPRC); | |
155 | IXGBE_READ_REG(hw, IXGBE_BPRC); | |
156 | IXGBE_READ_REG(hw, IXGBE_MPRC); | |
157 | IXGBE_READ_REG(hw, IXGBE_GPTC); | |
158 | IXGBE_READ_REG(hw, IXGBE_GORCL); | |
159 | IXGBE_READ_REG(hw, IXGBE_GORCH); | |
160 | IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
161 | IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
162 | for (i = 0; i < 8; i++) | |
163 | IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
164 | IXGBE_READ_REG(hw, IXGBE_RUC); | |
165 | IXGBE_READ_REG(hw, IXGBE_RFC); | |
166 | IXGBE_READ_REG(hw, IXGBE_ROC); | |
167 | IXGBE_READ_REG(hw, IXGBE_RJC); | |
168 | IXGBE_READ_REG(hw, IXGBE_MNGPRC); | |
169 | IXGBE_READ_REG(hw, IXGBE_MNGPDC); | |
170 | IXGBE_READ_REG(hw, IXGBE_MNGPTC); | |
171 | IXGBE_READ_REG(hw, IXGBE_TORL); | |
172 | IXGBE_READ_REG(hw, IXGBE_TORH); | |
173 | IXGBE_READ_REG(hw, IXGBE_TPR); | |
174 | IXGBE_READ_REG(hw, IXGBE_TPT); | |
175 | IXGBE_READ_REG(hw, IXGBE_PTC64); | |
176 | IXGBE_READ_REG(hw, IXGBE_PTC127); | |
177 | IXGBE_READ_REG(hw, IXGBE_PTC255); | |
178 | IXGBE_READ_REG(hw, IXGBE_PTC511); | |
179 | IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
180 | IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
181 | IXGBE_READ_REG(hw, IXGBE_MPTC); | |
182 | IXGBE_READ_REG(hw, IXGBE_BPTC); | |
183 | for (i = 0; i < 16; i++) { | |
184 | IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
185 | IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
186 | IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
187 | IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
188 | } | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | /** | |
194 | * ixgbe_get_mac_addr - Generic get MAC address | |
195 | * @hw: pointer to hardware structure | |
196 | * @mac_addr: Adapter MAC address | |
197 | * | |
198 | * Reads the adapter's MAC address from first Receive Address Register (RAR0) | |
199 | * A reset of the adapter must be performed prior to calling this function | |
200 | * in order for the MAC address to have been loaded from the EEPROM into RAR0 | |
201 | **/ | |
202 | s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) | |
203 | { | |
204 | u32 rar_high; | |
205 | u32 rar_low; | |
206 | u16 i; | |
207 | ||
208 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); | |
209 | rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); | |
210 | ||
211 | for (i = 0; i < 4; i++) | |
212 | mac_addr[i] = (u8)(rar_low >> (i*8)); | |
213 | ||
214 | for (i = 0; i < 2; i++) | |
215 | mac_addr[i+4] = (u8)(rar_high >> (i*8)); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num) | |
221 | { | |
222 | s32 ret_val; | |
223 | u16 data; | |
224 | ||
225 | ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM0_PTR, &data); | |
226 | if (ret_val) { | |
227 | hw_dbg(hw, "NVM Read Error\n"); | |
228 | return ret_val; | |
229 | } | |
230 | *part_num = (u32)(data << 16); | |
231 | ||
232 | ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM1_PTR, &data); | |
233 | if (ret_val) { | |
234 | hw_dbg(hw, "NVM Read Error\n"); | |
235 | return ret_val; | |
236 | } | |
237 | *part_num |= data; | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | /** | |
243 | * ixgbe_stop_adapter - Generic stop TX/RX units | |
244 | * @hw: pointer to hardware structure | |
245 | * | |
246 | * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, | |
247 | * disables transmit and receive units. The adapter_stopped flag is used by | |
248 | * the shared code and drivers to determine if the adapter is in a stopped | |
249 | * state and should not touch the hardware. | |
250 | **/ | |
251 | s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) | |
252 | { | |
253 | u32 number_of_queues; | |
254 | u32 reg_val; | |
255 | u16 i; | |
256 | ||
257 | /* | |
258 | * Set the adapter_stopped flag so other driver functions stop touching | |
259 | * the hardware | |
260 | */ | |
261 | hw->adapter_stopped = true; | |
262 | ||
263 | /* Disable the receive unit */ | |
264 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
265 | reg_val &= ~(IXGBE_RXCTRL_RXEN); | |
266 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); | |
267 | msleep(2); | |
268 | ||
269 | /* Clear interrupt mask to stop from interrupts being generated */ | |
270 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
271 | ||
272 | /* Clear any pending interrupts */ | |
273 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
274 | ||
275 | /* Disable the transmit unit. Each queue must be disabled. */ | |
276 | number_of_queues = hw->mac.num_tx_queues; | |
277 | for (i = 0; i < number_of_queues; i++) { | |
278 | reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
279 | if (reg_val & IXGBE_TXDCTL_ENABLE) { | |
280 | reg_val &= ~IXGBE_TXDCTL_ENABLE; | |
281 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); | |
282 | } | |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | /** | |
289 | * ixgbe_led_on - Turns on the software controllable LEDs. | |
290 | * @hw: pointer to hardware structure | |
291 | * @index: led number to turn on | |
292 | **/ | |
293 | s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) | |
294 | { | |
295 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
296 | ||
297 | /* To turn on the LED, set mode to ON. */ | |
298 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
299 | led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); | |
300 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
3957d63d | 301 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
302 | |
303 | return 0; | |
304 | } | |
305 | ||
306 | /** | |
307 | * ixgbe_led_off - Turns off the software controllable LEDs. | |
308 | * @hw: pointer to hardware structure | |
309 | * @index: led number to turn off | |
310 | **/ | |
311 | s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) | |
312 | { | |
313 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
314 | ||
315 | /* To turn off the LED, set mode to OFF. */ | |
316 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
317 | led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); | |
318 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
3957d63d | 319 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
324 | ||
325 | /** | |
326 | * ixgbe_init_eeprom - Initialize EEPROM params | |
327 | * @hw: pointer to hardware structure | |
328 | * | |
329 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | |
330 | * ixgbe_hw struct in order to set up EEPROM access. | |
331 | **/ | |
332 | s32 ixgbe_init_eeprom(struct ixgbe_hw *hw) | |
333 | { | |
334 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | |
335 | u32 eec; | |
336 | u16 eeprom_size; | |
337 | ||
338 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | |
339 | eeprom->type = ixgbe_eeprom_none; | |
340 | ||
341 | /* | |
342 | * Check for EEPROM present first. | |
343 | * If not present leave as none | |
344 | */ | |
345 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
346 | if (eec & IXGBE_EEC_PRES) { | |
347 | eeprom->type = ixgbe_eeprom_spi; | |
348 | ||
349 | /* | |
350 | * SPI EEPROM is assumed here. This code would need to | |
351 | * change if a future EEPROM is not SPI. | |
352 | */ | |
353 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | |
354 | IXGBE_EEC_SIZE_SHIFT); | |
355 | eeprom->word_size = 1 << (eeprom_size + | |
356 | IXGBE_EEPROM_WORD_SIZE_SHIFT); | |
357 | } | |
358 | ||
359 | if (eec & IXGBE_EEC_ADDR_SIZE) | |
360 | eeprom->address_bits = 16; | |
361 | else | |
362 | eeprom->address_bits = 8; | |
363 | hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " | |
364 | "%d\n", eeprom->type, eeprom->word_size, | |
365 | eeprom->address_bits); | |
366 | } | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
371 | /** | |
372 | * ixgbe_read_eeprom - Read EEPROM word using EERD | |
373 | * @hw: pointer to hardware structure | |
374 | * @offset: offset of word in the EEPROM to read | |
375 | * @data: word read from the EEPROM | |
376 | * | |
377 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
378 | **/ | |
379 | s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) | |
380 | { | |
381 | u32 eerd; | |
382 | s32 status; | |
383 | ||
384 | eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + | |
385 | IXGBE_EEPROM_READ_REG_START; | |
386 | ||
387 | IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); | |
388 | status = ixgbe_poll_eeprom_eerd_done(hw); | |
389 | ||
390 | if (status == 0) | |
391 | *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> | |
392 | IXGBE_EEPROM_READ_REG_DATA); | |
393 | else | |
394 | hw_dbg(hw, "Eeprom read timed out\n"); | |
395 | ||
396 | return status; | |
397 | } | |
398 | ||
399 | /** | |
400 | * ixgbe_poll_eeprom_eerd_done - Poll EERD status | |
401 | * @hw: pointer to hardware structure | |
402 | * | |
403 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
404 | **/ | |
405 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) | |
406 | { | |
407 | u32 i; | |
408 | u32 reg; | |
409 | s32 status = IXGBE_ERR_EEPROM; | |
410 | ||
411 | for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { | |
412 | reg = IXGBE_READ_REG(hw, IXGBE_EERD); | |
413 | if (reg & IXGBE_EEPROM_READ_REG_DONE) { | |
414 | status = 0; | |
415 | break; | |
416 | } | |
417 | udelay(5); | |
418 | } | |
419 | return status; | |
420 | } | |
421 | ||
422 | /** | |
423 | * ixgbe_get_eeprom_semaphore - Get hardware semaphore | |
424 | * @hw: pointer to hardware structure | |
425 | * | |
426 | * Sets the hardware semaphores so EEPROM access can occur for bit-bang method | |
427 | **/ | |
428 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) | |
429 | { | |
430 | s32 status = IXGBE_ERR_EEPROM; | |
431 | u32 timeout; | |
432 | u32 i; | |
433 | u32 swsm; | |
434 | ||
435 | /* Set timeout value based on size of EEPROM */ | |
436 | timeout = hw->eeprom.word_size + 1; | |
437 | ||
438 | /* Get SMBI software semaphore between device drivers first */ | |
439 | for (i = 0; i < timeout; i++) { | |
440 | /* | |
441 | * If the SMBI bit is 0 when we read it, then the bit will be | |
442 | * set and we have the semaphore | |
443 | */ | |
444 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
445 | if (!(swsm & IXGBE_SWSM_SMBI)) { | |
446 | status = 0; | |
447 | break; | |
448 | } | |
449 | msleep(1); | |
450 | } | |
451 | ||
452 | /* Now get the semaphore between SW/FW through the SWESMBI bit */ | |
453 | if (status == 0) { | |
454 | for (i = 0; i < timeout; i++) { | |
455 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
456 | ||
457 | /* Set the SW EEPROM semaphore bit to request access */ | |
458 | swsm |= IXGBE_SWSM_SWESMBI; | |
459 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | |
460 | ||
461 | /* | |
462 | * If we set the bit successfully then we got the | |
463 | * semaphore. | |
464 | */ | |
465 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
466 | if (swsm & IXGBE_SWSM_SWESMBI) | |
467 | break; | |
468 | ||
469 | udelay(50); | |
470 | } | |
471 | ||
472 | /* | |
473 | * Release semaphores and return error if SW EEPROM semaphore | |
474 | * was not granted because we don't have access to the EEPROM | |
475 | */ | |
476 | if (i >= timeout) { | |
477 | hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " | |
478 | "not granted.\n"); | |
479 | ixgbe_release_eeprom_semaphore(hw); | |
480 | status = IXGBE_ERR_EEPROM; | |
481 | } | |
482 | } | |
483 | ||
484 | return status; | |
485 | } | |
486 | ||
487 | /** | |
488 | * ixgbe_release_eeprom_semaphore - Release hardware semaphore | |
489 | * @hw: pointer to hardware structure | |
490 | * | |
491 | * This function clears hardware semaphore bits. | |
492 | **/ | |
493 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) | |
494 | { | |
495 | u32 swsm; | |
496 | ||
497 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
498 | ||
499 | /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ | |
500 | swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); | |
501 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | |
3957d63d | 502 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
503 | } |
504 | ||
505 | /** | |
506 | * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum | |
507 | * @hw: pointer to hardware structure | |
508 | **/ | |
509 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) | |
510 | { | |
511 | u16 i; | |
512 | u16 j; | |
513 | u16 checksum = 0; | |
514 | u16 length = 0; | |
515 | u16 pointer = 0; | |
516 | u16 word = 0; | |
517 | ||
518 | /* Include 0x0-0x3F in the checksum */ | |
519 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { | |
520 | if (ixgbe_read_eeprom(hw, i, &word) != 0) { | |
521 | hw_dbg(hw, "EEPROM read failed\n"); | |
522 | break; | |
523 | } | |
524 | checksum += word; | |
525 | } | |
526 | ||
527 | /* Include all data from pointers except for the fw pointer */ | |
528 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { | |
529 | ixgbe_read_eeprom(hw, i, &pointer); | |
530 | ||
531 | /* Make sure the pointer seems valid */ | |
532 | if (pointer != 0xFFFF && pointer != 0) { | |
533 | ixgbe_read_eeprom(hw, pointer, &length); | |
534 | ||
535 | if (length != 0xFFFF && length != 0) { | |
536 | for (j = pointer+1; j <= pointer+length; j++) { | |
537 | ixgbe_read_eeprom(hw, j, &word); | |
538 | checksum += word; | |
539 | } | |
540 | } | |
541 | } | |
542 | } | |
543 | ||
544 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; | |
545 | ||
546 | return checksum; | |
547 | } | |
548 | ||
549 | /** | |
550 | * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum | |
551 | * @hw: pointer to hardware structure | |
552 | * @checksum_val: calculated checksum | |
553 | * | |
554 | * Performs checksum calculation and validates the EEPROM checksum. If the | |
555 | * caller does not need checksum_val, the value can be NULL. | |
556 | **/ | |
557 | s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) | |
558 | { | |
559 | s32 status; | |
560 | u16 checksum; | |
561 | u16 read_checksum = 0; | |
562 | ||
563 | /* | |
564 | * Read the first word from the EEPROM. If this times out or fails, do | |
565 | * not continue or we could be in for a very long wait while every | |
566 | * EEPROM read fails | |
567 | */ | |
568 | status = ixgbe_read_eeprom(hw, 0, &checksum); | |
569 | ||
570 | if (status == 0) { | |
571 | checksum = ixgbe_calc_eeprom_checksum(hw); | |
572 | ||
573 | ixgbe_read_eeprom(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); | |
574 | ||
575 | /* | |
576 | * Verify read checksum from EEPROM is the same as | |
577 | * calculated checksum | |
578 | */ | |
579 | if (read_checksum != checksum) | |
580 | status = IXGBE_ERR_EEPROM_CHECKSUM; | |
581 | ||
582 | /* If the user cares, return the calculated checksum */ | |
583 | if (checksum_val) | |
584 | *checksum_val = checksum; | |
585 | } else { | |
586 | hw_dbg(hw, "EEPROM read failed\n"); | |
587 | } | |
588 | ||
589 | return status; | |
590 | } | |
591 | ||
592 | /** | |
593 | * ixgbe_validate_mac_addr - Validate MAC address | |
594 | * @mac_addr: pointer to MAC address. | |
595 | * | |
596 | * Tests a MAC address to ensure it is a valid Individual Address | |
597 | **/ | |
598 | s32 ixgbe_validate_mac_addr(u8 *mac_addr) | |
599 | { | |
600 | s32 status = 0; | |
601 | ||
602 | /* Make sure it is not a multicast address */ | |
603 | if (IXGBE_IS_MULTICAST(mac_addr)) | |
604 | status = IXGBE_ERR_INVALID_MAC_ADDR; | |
605 | /* Not a broadcast address */ | |
606 | else if (IXGBE_IS_BROADCAST(mac_addr)) | |
607 | status = IXGBE_ERR_INVALID_MAC_ADDR; | |
608 | /* Reject the zero address */ | |
609 | else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && | |
610 | mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) | |
611 | status = IXGBE_ERR_INVALID_MAC_ADDR; | |
612 | ||
613 | return status; | |
614 | } | |
615 | ||
616 | /** | |
617 | * ixgbe_set_rar - Set RX address register | |
618 | * @hw: pointer to hardware structure | |
619 | * @addr: Address to put into receive address register | |
620 | * @index: Receive address register to write | |
621 | * @vind: Vind to set RAR to | |
622 | * @enable_addr: set flag that address is active | |
623 | * | |
624 | * Puts an ethernet address into a receive address register. | |
625 | **/ | |
626 | s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind, | |
627 | u32 enable_addr) | |
628 | { | |
629 | u32 rar_low, rar_high; | |
630 | ||
631 | /* | |
632 | * HW expects these in little endian so we reverse the byte order from | |
633 | * network order (big endian) to little endian | |
634 | */ | |
635 | rar_low = ((u32)addr[0] | | |
636 | ((u32)addr[1] << 8) | | |
637 | ((u32)addr[2] << 16) | | |
638 | ((u32)addr[3] << 24)); | |
639 | ||
640 | rar_high = ((u32)addr[4] | | |
641 | ((u32)addr[5] << 8) | | |
642 | ((vind << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK)); | |
643 | ||
644 | if (enable_addr != 0) | |
645 | rar_high |= IXGBE_RAH_AV; | |
646 | ||
647 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); | |
648 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | /** | |
654 | * ixgbe_init_rx_addrs - Initializes receive address filters. | |
655 | * @hw: pointer to hardware structure | |
656 | * | |
657 | * Places the MAC address in receive address register 0 and clears the rest | |
658 | * of the receive addresss registers. Clears the multicast table. Assumes | |
659 | * the receiver is in reset when the routine is called. | |
660 | **/ | |
661 | static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) | |
662 | { | |
663 | u32 i; | |
664 | u32 rar_entries = hw->mac.num_rx_addrs; | |
665 | ||
666 | /* | |
667 | * If the current mac address is valid, assume it is a software override | |
668 | * to the permanent address. | |
669 | * Otherwise, use the permanent address from the eeprom. | |
670 | */ | |
671 | if (ixgbe_validate_mac_addr(hw->mac.addr) == | |
672 | IXGBE_ERR_INVALID_MAC_ADDR) { | |
673 | /* Get the MAC address from the RAR0 for later reference */ | |
674 | ixgbe_get_mac_addr(hw, hw->mac.addr); | |
675 | ||
676 | hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ", | |
677 | hw->mac.addr[0], hw->mac.addr[1], | |
678 | hw->mac.addr[2]); | |
679 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], | |
680 | hw->mac.addr[4], hw->mac.addr[5]); | |
681 | } else { | |
682 | /* Setup the receive address. */ | |
683 | hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); | |
684 | hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ", | |
685 | hw->mac.addr[0], hw->mac.addr[1], | |
686 | hw->mac.addr[2]); | |
687 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], | |
688 | hw->mac.addr[4], hw->mac.addr[5]); | |
689 | ||
690 | ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); | |
691 | } | |
692 | ||
693 | hw->addr_ctrl.rar_used_count = 1; | |
694 | ||
695 | /* Zero out the other receive addresses. */ | |
696 | hw_dbg(hw, "Clearing RAR[1-15]\n"); | |
697 | for (i = 1; i < rar_entries; i++) { | |
698 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | |
699 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | |
700 | } | |
701 | ||
702 | /* Clear the MTA */ | |
703 | hw->addr_ctrl.mc_addr_in_rar_count = 0; | |
704 | hw->addr_ctrl.mta_in_use = 0; | |
705 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); | |
706 | ||
707 | hw_dbg(hw, " Clearing MTA\n"); | |
708 | for (i = 0; i < IXGBE_MC_TBL_SIZE; i++) | |
709 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
714 | /** | |
715 | * ixgbe_mta_vector - Determines bit-vector in multicast table to set | |
716 | * @hw: pointer to hardware structure | |
717 | * @mc_addr: the multicast address | |
718 | * | |
719 | * Extracts the 12 bits, from a multicast address, to determine which | |
720 | * bit-vector to set in the multicast table. The hardware uses 12 bits, from | |
721 | * incoming rx multicast addresses, to determine the bit-vector to check in | |
722 | * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set | |
723 | * by the MO field of the MCSTCTRL. The MO field is set during initalization | |
724 | * to mc_filter_type. | |
725 | **/ | |
726 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) | |
727 | { | |
728 | u32 vector = 0; | |
729 | ||
730 | switch (hw->mac.mc_filter_type) { | |
731 | case 0: /* use bits [47:36] of the address */ | |
732 | vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); | |
733 | break; | |
734 | case 1: /* use bits [46:35] of the address */ | |
735 | vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); | |
736 | break; | |
737 | case 2: /* use bits [45:34] of the address */ | |
738 | vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); | |
739 | break; | |
740 | case 3: /* use bits [43:32] of the address */ | |
741 | vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); | |
742 | break; | |
743 | default: /* Invalid mc_filter_type */ | |
744 | hw_dbg(hw, "MC filter type param set incorrectly\n"); | |
745 | break; | |
746 | } | |
747 | ||
748 | /* vector can only be 12-bits or boundary will be exceeded */ | |
749 | vector &= 0xFFF; | |
750 | return vector; | |
751 | } | |
752 | ||
753 | /** | |
754 | * ixgbe_set_mta - Set bit-vector in multicast table | |
755 | * @hw: pointer to hardware structure | |
756 | * @hash_value: Multicast address hash value | |
757 | * | |
758 | * Sets the bit-vector in the multicast table. | |
759 | **/ | |
760 | static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) | |
761 | { | |
762 | u32 vector; | |
763 | u32 vector_bit; | |
764 | u32 vector_reg; | |
765 | u32 mta_reg; | |
766 | ||
767 | hw->addr_ctrl.mta_in_use++; | |
768 | ||
769 | vector = ixgbe_mta_vector(hw, mc_addr); | |
770 | hw_dbg(hw, " bit-vector = 0x%03X\n", vector); | |
771 | ||
772 | /* | |
773 | * The MTA is a register array of 128 32-bit registers. It is treated | |
774 | * like an array of 4096 bits. We want to set bit | |
775 | * BitArray[vector_value]. So we figure out what register the bit is | |
776 | * in, read it, OR in the new bit, then write back the new value. The | |
777 | * register is determined by the upper 7 bits of the vector value and | |
778 | * the bit within that register are determined by the lower 5 bits of | |
779 | * the value. | |
780 | */ | |
781 | vector_reg = (vector >> 5) & 0x7F; | |
782 | vector_bit = vector & 0x1F; | |
783 | mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); | |
784 | mta_reg |= (1 << vector_bit); | |
785 | IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); | |
786 | } | |
787 | ||
788 | /** | |
789 | * ixgbe_add_mc_addr - Adds a multicast address. | |
790 | * @hw: pointer to hardware structure | |
791 | * @mc_addr: new multicast address | |
792 | * | |
793 | * Adds it to unused receive address register or to the multicast table. | |
794 | **/ | |
795 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) | |
796 | { | |
797 | u32 rar_entries = hw->mac.num_rx_addrs; | |
798 | ||
799 | hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", | |
800 | mc_addr[0], mc_addr[1], mc_addr[2], | |
801 | mc_addr[3], mc_addr[4], mc_addr[5]); | |
802 | ||
803 | /* | |
804 | * Place this multicast address in the RAR if there is room, | |
805 | * else put it in the MTA | |
806 | */ | |
807 | if (hw->addr_ctrl.rar_used_count < rar_entries) { | |
808 | ixgbe_set_rar(hw, hw->addr_ctrl.rar_used_count, | |
809 | mc_addr, 0, IXGBE_RAH_AV); | |
810 | hw_dbg(hw, "Added a multicast address to RAR[%d]\n", | |
811 | hw->addr_ctrl.rar_used_count); | |
812 | hw->addr_ctrl.rar_used_count++; | |
813 | hw->addr_ctrl.mc_addr_in_rar_count++; | |
814 | } else { | |
815 | ixgbe_set_mta(hw, mc_addr); | |
816 | } | |
817 | ||
818 | hw_dbg(hw, "ixgbe_add_mc_addr Complete\n"); | |
819 | } | |
820 | ||
821 | /** | |
822 | * ixgbe_update_mc_addr_list - Updates MAC list of multicast addresses | |
823 | * @hw: pointer to hardware structure | |
824 | * @mc_addr_list: the list of new multicast addresses | |
825 | * @mc_addr_count: number of addresses | |
826 | * @pad: number of bytes between addresses in the list | |
827 | * | |
828 | * The given list replaces any existing list. Clears the MC addrs from receive | |
829 | * address registers and the multicast table. Uses unsed receive address | |
830 | * registers for the first multicast addresses, and hashes the rest into the | |
831 | * multicast table. | |
832 | **/ | |
833 | s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, | |
834 | u32 mc_addr_count, u32 pad) | |
835 | { | |
836 | u32 i; | |
837 | u32 rar_entries = hw->mac.num_rx_addrs; | |
838 | ||
839 | /* | |
840 | * Set the new number of MC addresses that we are being requested to | |
841 | * use. | |
842 | */ | |
843 | hw->addr_ctrl.num_mc_addrs = mc_addr_count; | |
844 | hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; | |
845 | hw->addr_ctrl.mc_addr_in_rar_count = 0; | |
846 | hw->addr_ctrl.mta_in_use = 0; | |
847 | ||
848 | /* Zero out the other receive addresses. */ | |
849 | hw_dbg(hw, "Clearing RAR[1-15]\n"); | |
850 | for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { | |
851 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | |
852 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | |
853 | } | |
854 | ||
855 | /* Clear the MTA */ | |
856 | hw_dbg(hw, " Clearing MTA\n"); | |
857 | for (i = 0; i < IXGBE_MC_TBL_SIZE; i++) | |
858 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); | |
859 | ||
860 | /* Add the new addresses */ | |
861 | for (i = 0; i < mc_addr_count; i++) { | |
862 | hw_dbg(hw, " Adding the multicast addresses:\n"); | |
863 | ixgbe_add_mc_addr(hw, mc_addr_list + | |
864 | (i * (IXGBE_ETH_LENGTH_OF_ADDRESS + pad))); | |
865 | } | |
866 | ||
867 | /* Enable mta */ | |
868 | if (hw->addr_ctrl.mta_in_use > 0) | |
869 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, | |
870 | IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); | |
871 | ||
872 | hw_dbg(hw, "ixgbe_update_mc_addr_list Complete\n"); | |
873 | return 0; | |
874 | } | |
875 | ||
876 | /** | |
877 | * ixgbe_clear_vfta - Clear VLAN filter table | |
878 | * @hw: pointer to hardware structure | |
879 | * | |
880 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
881 | **/ | |
882 | static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) | |
883 | { | |
884 | u32 offset; | |
885 | u32 vlanbyte; | |
886 | ||
887 | for (offset = 0; offset < IXGBE_VLAN_FILTER_TBL_SIZE; offset++) | |
888 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
889 | ||
890 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | |
891 | for (offset = 0; offset < IXGBE_VLAN_FILTER_TBL_SIZE; offset++) | |
892 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | |
893 | 0); | |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
898 | /** | |
899 | * ixgbe_set_vfta - Set VLAN filter table | |
900 | * @hw: pointer to hardware structure | |
901 | * @vlan: VLAN id to write to VLAN filter | |
902 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | |
903 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | |
904 | * | |
905 | * Turn on/off specified VLAN in the VLAN filter table. | |
906 | **/ | |
907 | s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, | |
908 | bool vlan_on) | |
909 | { | |
910 | u32 VftaIndex; | |
911 | u32 BitOffset; | |
912 | u32 VftaReg; | |
913 | u32 VftaByte; | |
914 | ||
915 | /* Determine 32-bit word position in array */ | |
916 | VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */ | |
917 | ||
918 | /* Determine the location of the (VMD) queue index */ | |
919 | VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | |
920 | BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | |
921 | ||
922 | /* Set the nibble for VMD queue index */ | |
923 | VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex)); | |
924 | VftaReg &= (~(0x0F << BitOffset)); | |
925 | VftaReg |= (vind << BitOffset); | |
926 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg); | |
927 | ||
928 | /* Determine the location of the bit for this VLAN id */ | |
929 | BitOffset = vlan & 0x1F; /* lower five bits */ | |
930 | ||
931 | VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex)); | |
932 | if (vlan_on) | |
933 | /* Turn on this VLAN id */ | |
934 | VftaReg |= (1 << BitOffset); | |
935 | else | |
936 | /* Turn off this VLAN id */ | |
937 | VftaReg &= ~(1 << BitOffset); | |
938 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg); | |
939 | ||
940 | return 0; | |
941 | } | |
942 | ||
943 | /** | |
944 | * ixgbe_setup_fc - Configure flow control settings | |
945 | * @hw: pointer to hardware structure | |
946 | * @packetbuf_num: packet buffer number (0-7) | |
947 | * | |
948 | * Configures the flow control settings based on SW configuration. | |
949 | * This function is used for 802.3x flow control configuration only. | |
950 | **/ | |
951 | s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |
952 | { | |
953 | u32 frctl_reg; | |
954 | u32 rmcs_reg; | |
955 | ||
956 | if (packetbuf_num < 0 || packetbuf_num > 7) | |
8c5863a4 | 957 | hw_dbg(hw, "Invalid packet buffer number [%d], expected range " |
9a799d71 AK |
958 | "is 0-7\n", packetbuf_num); |
959 | ||
960 | frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
961 | frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | |
962 | ||
963 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
964 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | |
965 | ||
966 | /* | |
967 | * We want to save off the original Flow Control configuration just in | |
968 | * case we get disconnected and then reconnected into a different hub | |
969 | * or switch with different Flow Control capabilities. | |
970 | */ | |
971 | hw->fc.type = hw->fc.original_type; | |
972 | ||
973 | /* | |
974 | * The possible values of the "flow_control" parameter are: | |
975 | * 0: Flow control is completely disabled | |
976 | * 1: Rx flow control is enabled (we can receive pause frames but not | |
977 | * send pause frames). | |
978 | * 2: Tx flow control is enabled (we can send pause frames but we do not | |
979 | * support receiving pause frames) | |
980 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
981 | * other: Invalid. | |
982 | */ | |
983 | switch (hw->fc.type) { | |
984 | case ixgbe_fc_none: | |
985 | break; | |
986 | case ixgbe_fc_rx_pause: | |
987 | /* | |
988 | * RX Flow control is enabled, | |
989 | * and TX Flow control is disabled. | |
990 | */ | |
991 | frctl_reg |= IXGBE_FCTRL_RFCE; | |
992 | break; | |
993 | case ixgbe_fc_tx_pause: | |
994 | /* | |
995 | * TX Flow control is enabled, and RX Flow control is disabled, | |
996 | * by a software over-ride. | |
997 | */ | |
998 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
999 | break; | |
1000 | case ixgbe_fc_full: | |
1001 | /* | |
1002 | * Flow control (both RX and TX) is enabled by a software | |
1003 | * over-ride. | |
1004 | */ | |
1005 | frctl_reg |= IXGBE_FCTRL_RFCE; | |
1006 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
1007 | break; | |
1008 | default: | |
1009 | /* We should never get here. The value should be 0-3. */ | |
1010 | hw_dbg(hw, "Flow control param set incorrectly\n"); | |
1011 | break; | |
1012 | } | |
1013 | ||
1014 | /* Enable 802.3x based flow control settings. */ | |
1015 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); | |
1016 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); | |
1017 | ||
1018 | /* | |
1019 | * We need to set up the Receive Threshold high and low water | |
1020 | * marks as well as (optionally) enabling the transmission of | |
1021 | * XON frames. | |
1022 | */ | |
1023 | if (hw->fc.type & ixgbe_fc_tx_pause) { | |
1024 | if (hw->fc.send_xon) { | |
1025 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), | |
1026 | (hw->fc.low_water | IXGBE_FCRTL_XONE)); | |
1027 | } else { | |
1028 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), | |
1029 | hw->fc.low_water); | |
1030 | } | |
1031 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), | |
1032 | (hw->fc.high_water)|IXGBE_FCRTH_FCEN); | |
1033 | } | |
1034 | ||
1035 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); | |
1036 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); | |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | ||
1041 | /** | |
1042 | * ixgbe_disable_pcie_master - Disable PCI-express master access | |
1043 | * @hw: pointer to hardware structure | |
1044 | * | |
1045 | * Disables PCI-Express master access and verifies there are no pending | |
1046 | * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable | |
1047 | * bit hasn't caused the master requests to be disabled, else 0 | |
1048 | * is returned signifying master requests disabled. | |
1049 | **/ | |
1050 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) | |
1051 | { | |
1052 | u32 ctrl; | |
1053 | s32 i; | |
1054 | s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; | |
1055 | ||
1056 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
1057 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
1058 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
1059 | ||
1060 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { | |
1061 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { | |
1062 | status = 0; | |
1063 | break; | |
1064 | } | |
1065 | udelay(100); | |
1066 | } | |
1067 | ||
1068 | return status; | |
1069 | } | |
1070 | ||
1071 | ||
1072 | /** | |
1073 | * ixgbe_acquire_swfw_sync - Aquire SWFW semaphore | |
1074 | * @hw: pointer to hardware structure | |
1075 | * @mask: Mask to specify wich semaphore to acquire | |
1076 | * | |
1077 | * Aquires the SWFW semaphore throught the GSSR register for the specified | |
1078 | * function (CSR, PHY0, PHY1, EEPROM, Flash) | |
1079 | **/ | |
1080 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |
1081 | { | |
1082 | u32 gssr; | |
1083 | u32 swmask = mask; | |
1084 | u32 fwmask = mask << 5; | |
1085 | s32 timeout = 200; | |
1086 | ||
1087 | while (timeout) { | |
1088 | if (ixgbe_get_eeprom_semaphore(hw)) | |
1089 | return -IXGBE_ERR_SWFW_SYNC; | |
1090 | ||
1091 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | |
1092 | if (!(gssr & (fwmask | swmask))) | |
1093 | break; | |
1094 | ||
1095 | /* | |
1096 | * Firmware currently using resource (fwmask) or other software | |
1097 | * thread currently using resource (swmask) | |
1098 | */ | |
1099 | ixgbe_release_eeprom_semaphore(hw); | |
1100 | msleep(5); | |
1101 | timeout--; | |
1102 | } | |
1103 | ||
1104 | if (!timeout) { | |
1105 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); | |
1106 | return -IXGBE_ERR_SWFW_SYNC; | |
1107 | } | |
1108 | ||
1109 | gssr |= swmask; | |
1110 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); | |
1111 | ||
1112 | ixgbe_release_eeprom_semaphore(hw); | |
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | /** | |
1117 | * ixgbe_release_swfw_sync - Release SWFW semaphore | |
1118 | * @hw: pointer to hardware structure | |
1119 | * @mask: Mask to specify wich semaphore to release | |
1120 | * | |
1121 | * Releases the SWFW semaphore throught the GSSR register for the specified | |
1122 | * function (CSR, PHY0, PHY1, EEPROM, Flash) | |
1123 | **/ | |
1124 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |
1125 | { | |
1126 | u32 gssr; | |
1127 | u32 swmask = mask; | |
1128 | ||
1129 | ixgbe_get_eeprom_semaphore(hw); | |
1130 | ||
1131 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | |
1132 | gssr &= ~swmask; | |
1133 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); | |
1134 | ||
1135 | ixgbe_release_eeprom_semaphore(hw); | |
1136 | } | |
1137 | ||
1138 | /** | |
3957d63d | 1139 | * ixgbe_read_analog_reg8 - Reads 8 bit Atlas analog register |
9a799d71 AK |
1140 | * @hw: pointer to hardware structure |
1141 | * @reg: analog register to read | |
1142 | * @val: read value | |
1143 | * | |
1144 | * Performs write operation to analog register specified. | |
1145 | **/ | |
1146 | s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) | |
1147 | { | |
1148 | u32 atlas_ctl; | |
1149 | ||
1150 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | |
1151 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); | |
1152 | IXGBE_WRITE_FLUSH(hw); | |
1153 | udelay(10); | |
1154 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
1155 | *val = (u8)atlas_ctl; | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | /** | |
3957d63d | 1161 | * ixgbe_write_analog_reg8 - Writes 8 bit Atlas analog register |
9a799d71 AK |
1162 | * @hw: pointer to hardware structure |
1163 | * @reg: atlas register to write | |
1164 | * @val: value to write | |
1165 | * | |
1166 | * Performs write operation to Atlas analog register specified. | |
1167 | **/ | |
1168 | s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) | |
1169 | { | |
1170 | u32 atlas_ctl; | |
1171 | ||
1172 | atlas_ctl = (reg << 8) | val; | |
1173 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | |
1174 | IXGBE_WRITE_FLUSH(hw); | |
1175 | udelay(10); | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 |