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ixgbe: merge reset task into service task
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
30#include <linux/types.h>
31#include <linux/module.h>
5a0e3ad6 32#include <linux/slab.h>
9a799d71
AK		 33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/ethtool.h>
36#include <linux/vmalloc.h>
37#include <linux/uaccess.h>
38
39#include "ixgbe.h"
40
41
42#define IXGBE_ALL_RAR_ENTRIES 16
43
29c3a050
AK		 44enum {NETDEV_STATS, IXGBE_STATS};
45
9a799d71
AK		 46struct ixgbe_stats {
47 char stat_string[ETH_GSTRING_LEN];
29c3a050 48 int type;
9a799d71
AK		 49 int sizeof_stat;
50 int stat_offset;
51};
52
29c3a050
AK		 53#define IXGBE_STAT(m) IXGBE_STATS, \
54 sizeof(((struct ixgbe_adapter *)0)->m), \
55 offsetof(struct ixgbe_adapter, m)
56#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 57 sizeof(((struct rtnl_link_stats64 *)0)->m), \
58 offsetof(struct rtnl_link_stats64, m)
29c3a050 59
9a799d71 60static struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 61 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
62 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
63 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
64 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 65 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
66 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
67 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
68 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 69 {"lsc_int", IXGBE_STAT(lsc_int)},
70 {"tx_busy", IXGBE_STAT(tx_busy)},
71 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 72 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
73 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
74 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
75 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
76 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 77 {"broadcast", IXGBE_STAT(stats.bprc)},
78 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 79 {"collisions", IXGBE_NETDEV_STAT(collisions)},
80 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
81 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
82 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 83 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
84 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 85 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
86 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
55bad823
ED		 87 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
88 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
89 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
90 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
91 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
92 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 93 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
94 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
95 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
96 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 97 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
98 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
99 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
100 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 101 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 102 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
103 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 104 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 105 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
106 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
107 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
108 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 109#ifdef IXGBE_FCOE
110 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
111 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
112 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
113 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
114 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
115 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
116#endif /* IXGBE_FCOE */
9a799d71
AK		 117};
118
119#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 120 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
121 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
122 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 123#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 124#define IXGBE_PB_STATS_LEN ( \
9d2f4720 125 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 126 IXGBE_FLAG_DCB_ENABLED) ? \
127 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
128 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
129 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
130 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
131 / sizeof(u64) : 0)
132#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
133 IXGBE_PB_STATS_LEN + \
134 IXGBE_QUEUE_STATS_LEN)
9a799d71 135
da4dd0f7
PWJ		 136static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
137 "Register test (offline)", "Eeprom test (offline)",
138 "Interrupt test (offline)", "Loopback test (offline)",
139 "Link test (on/offline)"
140};
141#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
142
9a799d71 143static int ixgbe_get_settings(struct net_device *netdev,
b4617240 144 struct ethtool_cmd *ecmd)
9a799d71
AK		 145{
146 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 link_speed = 0;
149 bool link_up;
9a799d71 150
735441fb
AV		 151 ecmd->supported = SUPPORTED_10000baseT_Full;
152 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 153 ecmd->transceiver = XCVR_EXTERNAL;
74766013 154 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 155 (hw->phy.multispeed_fiber)) {
735441fb 156 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 157 SUPPORTED_Autoneg);
735441fb 158
1b1c0a48
AS		 159 switch (hw->mac.type) {
160 case ixgbe_mac_X540:
161 ecmd->supported |= SUPPORTED_100baseT_Full;
162 break;
163 default:
164 break;
165 }
166
74766013 167 ecmd->advertising = ADVERTISED_Autoneg;
2b642ca5
ET		 168 if (hw->phy.autoneg_advertised) {
169 if (hw->phy.autoneg_advertised &
170 IXGBE_LINK_SPEED_100_FULL)
171 ecmd->advertising |= ADVERTISED_100baseT_Full;
172 if (hw->phy.autoneg_advertised &
173 IXGBE_LINK_SPEED_10GB_FULL)
174 ecmd->advertising |= ADVERTISED_10000baseT_Full;
175 if (hw->phy.autoneg_advertised &
176 IXGBE_LINK_SPEED_1GB_FULL)
177 ecmd->advertising |= ADVERTISED_1000baseT_Full;
178 } else {
179 /*
180 * Default advertised modes in case
181 * phy.autoneg_advertised isn't set.
182 */
7c5b8323
DS		 183 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
184 ADVERTISED_1000baseT_Full);
2b642ca5
ET		 185 if (hw->mac.type == ixgbe_mac_X540)
186 ecmd->advertising |= ADVERTISED_100baseT_Full;
1b1c0a48
AS		 187 }
188
74766013
MC		 189 if (hw->phy.media_type == ixgbe_media_type_copper) {
190 ecmd->supported |= SUPPORTED_TP;
191 ecmd->advertising |= ADVERTISED_TP;
192 ecmd->port = PORT_TP;
193 } else {
194 ecmd->supported |= SUPPORTED_FIBRE;
195 ecmd->advertising |= ADVERTISED_FIBRE;
196 ecmd->port = PORT_FIBRE;
197 }
1e336d0f
DS		 198 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
199 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 200 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 201 ecmd->supported = (SUPPORTED_1000baseT_Full |
202 SUPPORTED_FIBRE);
203 ecmd->advertising = (ADVERTISED_1000baseT_Full |
204 ADVERTISED_FIBRE);
205 ecmd->port = PORT_FIBRE;
206 ecmd->autoneg = AUTONEG_DISABLE;
50d6c681
AD		 207 } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE) ||
208 (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) {
209 ecmd->supported |= (SUPPORTED_1000baseT_Full |
210 SUPPORTED_Autoneg |
211 SUPPORTED_FIBRE);
212 ecmd->advertising = (ADVERTISED_10000baseT_Full |
213 ADVERTISED_1000baseT_Full |
214 ADVERTISED_Autoneg |
215 ADVERTISED_FIBRE);
216 ecmd->port = PORT_FIBRE;
46a72b35
MC		 217 } else {
218 ecmd->supported |= (SUPPORTED_1000baseT_Full |
219 SUPPORTED_FIBRE);
220 ecmd->advertising = (ADVERTISED_10000baseT_Full |
221 ADVERTISED_1000baseT_Full |
222 ADVERTISED_FIBRE);
223 ecmd->port = PORT_FIBRE;
1e336d0f 224 }
735441fb
AV		 225 } else {
226 ecmd->supported |= SUPPORTED_FIBRE;
227 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 228 ADVERTISED_FIBRE);
735441fb 229 ecmd->port = PORT_FIBRE;
c44ade9e 230 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 231 }
9a799d71 232
3b8626ba
PW		 233 /* Get PHY type */
234 switch (adapter->hw.phy.type) {
235 case ixgbe_phy_tn:
fe15e8e1 236 case ixgbe_phy_aq:
3b8626ba
PW		 237 case ixgbe_phy_cu_unknown:
238 /* Copper 10G-BASET */
239 ecmd->port = PORT_TP;
240 break;
241 case ixgbe_phy_qt:
242 ecmd->port = PORT_FIBRE;
243 break;
244 case ixgbe_phy_nl:
ea0a04df
DS		 245 case ixgbe_phy_sfp_passive_tyco:
246 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 247 case ixgbe_phy_sfp_ftl:
248 case ixgbe_phy_sfp_avago:
249 case ixgbe_phy_sfp_intel:
250 case ixgbe_phy_sfp_unknown:
251 switch (adapter->hw.phy.sfp_type) {
252 /* SFP+ devices, further checking needed */
253 case ixgbe_sfp_type_da_cu:
254 case ixgbe_sfp_type_da_cu_core0:
255 case ixgbe_sfp_type_da_cu_core1:
256 ecmd->port = PORT_DA;
257 break;
258 case ixgbe_sfp_type_sr:
259 case ixgbe_sfp_type_lr:
260 case ixgbe_sfp_type_srlr_core0:
261 case ixgbe_sfp_type_srlr_core1:
262 ecmd->port = PORT_FIBRE;
263 break;
264 case ixgbe_sfp_type_not_present:
265 ecmd->port = PORT_NONE;
266 break;
cb836a97
DS		 267 case ixgbe_sfp_type_1g_cu_core0:
268 case ixgbe_sfp_type_1g_cu_core1:
269 ecmd->port = PORT_TP;
270 ecmd->supported = SUPPORTED_TP;
271 ecmd->advertising = (ADVERTISED_1000baseT_Full |
272 ADVERTISED_TP);
273 break;
3b8626ba
PW		 274 case ixgbe_sfp_type_unknown:
275 default:
276 ecmd->port = PORT_OTHER;
277 break;
278 }
279 break;
280 case ixgbe_phy_xaui:
281 ecmd->port = PORT_NONE;
282 break;
283 case ixgbe_phy_unknown:
284 case ixgbe_phy_generic:
285 case ixgbe_phy_sfp_unsupported:
286 default:
287 ecmd->port = PORT_OTHER;
288 break;
289 }
290
c44ade9e 291 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 292 if (link_up) {
1b1c0a48
AS		 293 switch (link_speed) {
294 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 295 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48
AS		 296 break;
297 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 298 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 299 break;
300 case IXGBE_LINK_SPEED_100_FULL:
70739497 301 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 302 break;
303 default:
304 break;
305 }
9a799d71
AK		 306 ecmd->duplex = DUPLEX_FULL;
307 } else {
70739497 308 ethtool_cmd_speed_set(ecmd, -1);
9a799d71
AK		 309 ecmd->duplex = -1;
310 }
311
9a799d71
AK		 312 return 0;
313}
314
315static int ixgbe_set_settings(struct net_device *netdev,
b4617240 316 struct ethtool_cmd *ecmd)
9a799d71
AK		 317{
318 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 319 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 320 u32 advertised, old;
74766013 321 s32 err = 0;
9a799d71 322
74766013 323 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 324 (hw->phy.multispeed_fiber)) {
0befdb3e
JB		 325 /* 10000/copper and 1000/copper must autoneg
326 * this function does not support any duplex forcing, but can
327 * limit the advertising of the adapter to only 10000 or 1000 */
328 if (ecmd->autoneg == AUTONEG_DISABLE)
329 return -EINVAL;
330
331 old = hw->phy.autoneg_advertised;
332 advertised = 0;
333 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
334 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
335
336 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
337 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
338
2b642ca5
ET		 339 if (ecmd->advertising & ADVERTISED_100baseT_Full)
340 advertised |= IXGBE_LINK_SPEED_100_FULL;
341
0befdb3e 342 if (old == advertised)
74766013 343 return err;
0befdb3e 344 /* this sets the link speed and restarts auto-neg */
74766013 345 hw->mac.autotry_restart = true;
8620a103 346 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e 347 if (err) {
396e799c 348 e_info(probe, "setup link failed with code %d\n", err);
8620a103 349 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 350 }
74766013
MC		 351 } else {
352 /* in this case we currently only support 10Gb/FULL */
25db0338 353 u32 speed = ethtool_cmd_speed(ecmd);
74766013 354 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 355 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 356 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 357 return -EINVAL;
9a799d71
AK		 358 }
359
74766013 360 return err;
9a799d71
AK		 361}
362
363static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 364 struct ethtool_pauseparam *pause)
9a799d71
AK		 365{
366 struct ixgbe_adapter *adapter = netdev_priv(netdev);
367 struct ixgbe_hw *hw = &adapter->hw;
368
71fd570b
DS		 369 /*
370 * Flow Control Autoneg isn't on if
371 * - we didn't ask for it OR
372 * - it failed, we know this by tx & rx being off
373 */
374 if (hw->fc.disable_fc_autoneg ||
375 (hw->fc.current_mode == ixgbe_fc_none))
376 pause->autoneg = 0;
377 else
378 pause->autoneg = 1;
9a799d71 379
0ecc061d 380 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 381 pause->rx_pause = 1;
0ecc061d 382 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 383 pause->tx_pause = 1;
0ecc061d 384 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 385 pause->rx_pause = 1;
386 pause->tx_pause = 1;
673ac604
AD		 387#ifdef CONFIG_DCB
388 } else if (hw->fc.current_mode == ixgbe_fc_pfc) {
389 pause->rx_pause = 0;
390 pause->tx_pause = 0;
391#endif
9a799d71
AK		 392 }
393}
394
395static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 396 struct ethtool_pauseparam *pause)
9a799d71
AK		 397{
398 struct ixgbe_adapter *adapter = netdev_priv(netdev);
399 struct ixgbe_hw *hw = &adapter->hw;
620fa036 400 struct ixgbe_fc_info fc;
9a799d71 401
264857b8
PWJ		 402#ifdef CONFIG_DCB
403 if (adapter->dcb_cfg.pfc_mode_enable ||
404 ((hw->mac.type == ixgbe_mac_82598EB) &&
405 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
406 return -EINVAL;
407
408#endif
620fa036
MC		 409 fc = hw->fc;
410
71fd570b 411 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 412 fc.disable_fc_autoneg = true;
71fd570b 413 else
620fa036 414 fc.disable_fc_autoneg = false;
71fd570b 415
1c4f0ef8 416 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 417 fc.requested_mode = ixgbe_fc_full;
9a799d71 418 else if (pause->rx_pause && !pause->tx_pause)
620fa036 419 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 420 else if (!pause->rx_pause && pause->tx_pause)
620fa036 421 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 422 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 423 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 424 else
425 return -EINVAL;
9a799d71 426
264857b8 427#ifdef CONFIG_DCB
620fa036 428 adapter->last_lfc_mode = fc.requested_mode;
264857b8 429#endif
620fa036
MC		 430
431 /* if the thing changed then we'll update and use new autoneg */
432 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
433 hw->fc = fc;
434 if (netif_running(netdev))
435 ixgbe_reinit_locked(adapter);
436 else
437 ixgbe_reset(adapter);
438 }
9a799d71
AK		 439
440 return 0;
441}
442
443static u32 ixgbe_get_rx_csum(struct net_device *netdev)
444{
445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
807540ba 446 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
9a799d71
AK		 447}
448
449static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
450{
451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
452 if (data)
453 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
454 else
455 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
456
9a799d71
AK		 457 return 0;
458}
459
460static u32 ixgbe_get_tx_csum(struct net_device *netdev)
461{
22f32b7a 462 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 463}
464
465static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
466{
45a5ead0 467 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b93a2226 468 u32 feature_list;
45a5ead0 469
b93a2226
DS		 470 feature_list = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
471 switch (adapter->hw.mac.type) {
472 case ixgbe_mac_82599EB:
473 case ixgbe_mac_X540:
474 feature_list |= NETIF_F_SCTP_CSUM;
475 break;
476 default:
477 break;
45a5ead0 478 }
b93a2226
DS		 479 if (data)
480 netdev->features |= feature_list;
481 else
482 netdev->features &= ~feature_list;
9a799d71
AK		 483
484 return 0;
485}
486
487static int ixgbe_set_tso(struct net_device *netdev, u32 data)
488{
9a799d71
AK		 489 if (data) {
490 netdev->features |= NETIF_F_TSO;
491 netdev->features |= NETIF_F_TSO6;
492 } else {
493 netdev->features &= ~NETIF_F_TSO;
494 netdev->features &= ~NETIF_F_TSO6;
495 }
496 return 0;
497}
498
499static u32 ixgbe_get_msglevel(struct net_device *netdev)
500{
501 struct ixgbe_adapter *adapter = netdev_priv(netdev);
502 return adapter->msg_enable;
503}
504
505static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
506{
507 struct ixgbe_adapter *adapter = netdev_priv(netdev);
508 adapter->msg_enable = data;
509}
510
511static int ixgbe_get_regs_len(struct net_device *netdev)
512{
513#define IXGBE_REGS_LEN 1128
514 return IXGBE_REGS_LEN * sizeof(u32);
515}
516
517#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
518
519static void ixgbe_get_regs(struct net_device *netdev,
b4617240 520 struct ethtool_regs *regs, void *p)
9a799d71
AK		 521{
522 struct ixgbe_adapter *adapter = netdev_priv(netdev);
523 struct ixgbe_hw *hw = &adapter->hw;
524 u32 *regs_buff = p;
525 u8 i;
526
527 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
528
529 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
530
531 /* General Registers */
532 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
533 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
534 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
535 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
536 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
537 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
538 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
539 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
540
541 /* NVM Register */
542 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
543 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
544 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
545 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
546 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
547 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
548 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
549 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
550 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
551 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
552
553 /* Interrupt */
98c00a1c
JB		 554 /* don't read EICR because it can clear interrupt causes, instead
555 * read EICS which is a shadow but doesn't clear EICR */
556 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 557 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
558 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
559 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
560 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
561 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
562 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
563 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
564 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
565 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 566 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 567 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
568
569 /* Flow Control */
570 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
571 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
572 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
573 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
574 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 575 for (i = 0; i < 8; i++) {
576 switch (hw->mac.type) {
577 case ixgbe_mac_82598EB:
578 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
579 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
580 break;
581 case ixgbe_mac_82599EB:
582 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
583 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
584 break;
585 default:
586 break;
587 }
588 }
9a799d71
AK		 589 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
590 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
591
592 /* Receive DMA */
593 for (i = 0; i < 64; i++)
594 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
595 for (i = 0; i < 64; i++)
596 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
597 for (i = 0; i < 64; i++)
598 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
599 for (i = 0; i < 64; i++)
600 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
601 for (i = 0; i < 64; i++)
602 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
603 for (i = 0; i < 64; i++)
604 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
605 for (i = 0; i < 16; i++)
606 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
607 for (i = 0; i < 16; i++)
608 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
609 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
610 for (i = 0; i < 8; i++)
611 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
612 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
613 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
614
615 /* Receive */
616 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
617 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
618 for (i = 0; i < 16; i++)
619 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
620 for (i = 0; i < 16; i++)
621 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 622 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 623 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
624 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
625 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
626 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
627 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
628 for (i = 0; i < 8; i++)
629 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
630 for (i = 0; i < 8; i++)
631 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
632 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
633
634 /* Transmit */
635 for (i = 0; i < 32; i++)
636 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
637 for (i = 0; i < 32; i++)
638 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
639 for (i = 0; i < 32; i++)
640 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
641 for (i = 0; i < 32; i++)
642 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
643 for (i = 0; i < 32; i++)
644 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
645 for (i = 0; i < 32; i++)
646 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
647 for (i = 0; i < 32; i++)
648 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
649 for (i = 0; i < 32; i++)
650 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
651 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
652 for (i = 0; i < 16; i++)
653 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
654 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
655 for (i = 0; i < 8; i++)
656 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
657 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
658
659 /* Wake Up */
660 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
661 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
662 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
663 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
664 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
665 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
666 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
667 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 668 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 669
673ac604 670 /* DCB */
9a799d71
AK		 671 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
672 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
673 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
674 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
675 for (i = 0; i < 8; i++)
676 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
677 for (i = 0; i < 8; i++)
678 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
679 for (i = 0; i < 8; i++)
680 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
681 for (i = 0; i < 8; i++)
682 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
683 for (i = 0; i < 8; i++)
684 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
685 for (i = 0; i < 8; i++)
686 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
687
688 /* Statistics */
689 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
690 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
691 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
692 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
693 for (i = 0; i < 8; i++)
694 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
695 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
696 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
697 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
698 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
699 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
700 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
701 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
702 for (i = 0; i < 8; i++)
703 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
704 for (i = 0; i < 8; i++)
705 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
706 for (i = 0; i < 8; i++)
707 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
708 for (i = 0; i < 8; i++)
709 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
710 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
711 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
712 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
713 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
714 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
715 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
716 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
717 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
718 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
719 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
720 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
721 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
722 for (i = 0; i < 8; i++)
723 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
724 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
725 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
726 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
727 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
728 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
729 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
730 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
731 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
732 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
733 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
734 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
735 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
736 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
737 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
738 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
739 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
740 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
741 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
742 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
743 for (i = 0; i < 16; i++)
744 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
745 for (i = 0; i < 16; i++)
746 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
747 for (i = 0; i < 16; i++)
748 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
749 for (i = 0; i < 16; i++)
750 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
751
752 /* MAC */
753 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
754 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
755 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
756 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
757 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
758 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
759 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
760 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
761 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
762 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
763 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
764 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
765 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
766 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
767 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
768 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
769 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
770 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
771 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
772 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
773 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
774 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
775 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
776 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
777 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
778 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
779 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
780 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
781 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
782 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
783 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
784 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
785 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
786
787 /* Diagnostic */
788 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
789 for (i = 0; i < 8; i++)
98c00a1c 790 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 791 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 792 for (i = 0; i < 4; i++)
793 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 794 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
795 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
796 for (i = 0; i < 8; i++)
98c00a1c 797 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 798 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 799 for (i = 0; i < 4; i++)
800 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 801 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
802 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
803 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
804 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
805 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
806 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
807 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
808 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
809 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
810 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
811 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
812 for (i = 0; i < 8; i++)
98c00a1c 813 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 814 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
815 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
816 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
817 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
818 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
819 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
820 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
821 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
822 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
823}
824
825static int ixgbe_get_eeprom_len(struct net_device *netdev)
826{
827 struct ixgbe_adapter *adapter = netdev_priv(netdev);
828 return adapter->hw.eeprom.word_size * 2;
829}
830
831static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 832 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 833{
834 struct ixgbe_adapter *adapter = netdev_priv(netdev);
835 struct ixgbe_hw *hw = &adapter->hw;
836 u16 *eeprom_buff;
837 int first_word, last_word, eeprom_len;
838 int ret_val = 0;
839 u16 i;
840
841 if (eeprom->len == 0)
842 return -EINVAL;
843
844 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
845
846 first_word = eeprom->offset >> 1;
847 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
848 eeprom_len = last_word - first_word + 1;
849
850 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
851 if (!eeprom_buff)
852 return -ENOMEM;
853
68c7005d
ET		 854 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
855 eeprom_buff);
9a799d71
AK		 856
857 /* Device's eeprom is always little-endian, word addressable */
858 for (i = 0; i < eeprom_len; i++)
859 le16_to_cpus(&eeprom_buff[i]);
860
861 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
862 kfree(eeprom_buff);
863
864 return ret_val;
865}
866
867static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 868 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 869{
870 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 871 char firmware_version[32];
9a799d71 872
9fe93afd
DS		 873 strncpy(drvinfo->driver, ixgbe_driver_name,
874 sizeof(drvinfo->driver) - 1);
083fc582 875 strncpy(drvinfo->version, ixgbe_driver_version,
9fe93afd 876 sizeof(drvinfo->version) - 1);
083fc582
DS		 877
878 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
879 (adapter->eeprom_version & 0xF000) >> 12,
880 (adapter->eeprom_version & 0x0FF0) >> 4,
881 adapter->eeprom_version & 0x000F);
882
883 strncpy(drvinfo->fw_version, firmware_version,
884 sizeof(drvinfo->fw_version));
885 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
886 sizeof(drvinfo->bus_info));
9a799d71 887 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 888 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 889 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
890}
891
892static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 893 struct ethtool_ringparam *ring)
9a799d71
AK		 894{
895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 896 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
897 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 898
899 ring->rx_max_pending = IXGBE_MAX_RXD;
900 ring->tx_max_pending = IXGBE_MAX_TXD;
901 ring->rx_mini_max_pending = 0;
902 ring->rx_jumbo_max_pending = 0;
903 ring->rx_pending = rx_ring->count;
904 ring->tx_pending = tx_ring->count;
905 ring->rx_mini_pending = 0;
906 ring->rx_jumbo_pending = 0;
907}
908
909static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 910 struct ethtool_ringparam *ring)
9a799d71
AK		 911{
912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 913 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 914 int i, err = 0;
c431f97e 915 u32 new_rx_count, new_tx_count;
f9ed8854 916 bool need_update = false;
9a799d71
AK		 917
918 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
919 return -EINVAL;
920
921 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
922 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
923 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
924
925 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
926 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
927 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
928
4a0b9ca0
PW		 929 if ((new_tx_count == adapter->tx_ring[0]->count) &&
930 (new_rx_count == adapter->rx_ring[0]->count)) {
9a799d71
AK		 931 /* nothing to do */
932 return 0;
933 }
934
d4f80882 935 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 936 usleep_range(1000, 2000);
d4f80882 937
759884b4
AD		 938 if (!netif_running(adapter->netdev)) {
939 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 940 adapter->tx_ring[i]->count = new_tx_count;
759884b4 941 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 942 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 943 adapter->tx_ring_count = new_tx_count;
944 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 945 goto clear_reset;
759884b4
AD		 946 }
947
4a0b9ca0 948 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
f9ed8854
MC		 949 if (!temp_tx_ring) {
950 err = -ENOMEM;
4a0b9ca0 951 goto clear_reset;
f9ed8854
MC		 952 }
953
954 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 955 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 956 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
957 sizeof(struct ixgbe_ring));
f9ed8854 958 temp_tx_ring[i].count = new_tx_count;
b6ec895e 959 err = ixgbe_setup_tx_resources(&temp_tx_ring[i]);
9a799d71 960 if (err) {
c431f97e
JB		 961 while (i) {
962 i--;
b6ec895e 963 ixgbe_free_tx_resources(&temp_tx_ring[i]);
c431f97e 964 }
4a0b9ca0 965 goto clear_reset;
9a799d71 966 }
9a799d71 967 }
f9ed8854 968 need_update = true;
9a799d71
AK		 969 }
970
4a0b9ca0
PW		 971 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
972 if (!temp_rx_ring) {
f9ed8854
MC		 973 err = -ENOMEM;
974 goto err_setup;
d3fa4721 975 }
9a799d71 976
f9ed8854 977 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 978 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 979 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
980 sizeof(struct ixgbe_ring));
f9ed8854 981 temp_rx_ring[i].count = new_rx_count;
b6ec895e 982 err = ixgbe_setup_rx_resources(&temp_rx_ring[i]);
9a799d71 983 if (err) {
c431f97e
JB		 984 while (i) {
985 i--;
b6ec895e 986 ixgbe_free_rx_resources(&temp_rx_ring[i]);
c431f97e 987 }
9a799d71
AK		 988 goto err_setup;
989 }
9a799d71 990 }
f9ed8854
MC		 991 need_update = true;
992 }
993
994 /* if rings need to be updated, here's the place to do it in one shot */
995 if (need_update) {
759884b4 996 ixgbe_down(adapter);
f9ed8854
MC		 997
998 /* tx */
999 if (new_tx_count != adapter->tx_ring_count) {
4a0b9ca0 1000 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 1001 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4a0b9ca0
PW		 1002 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
1003 sizeof(struct ixgbe_ring));
1004 }
f9ed8854
MC		 1005 adapter->tx_ring_count = new_tx_count;
1006 }
1007
1008 /* rx */
1009 if (new_rx_count != adapter->rx_ring_count) {
4a0b9ca0 1010 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 1011 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4a0b9ca0
PW		 1012 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
1013 sizeof(struct ixgbe_ring));
1014 }
f9ed8854
MC		 1015 adapter->rx_ring_count = new_rx_count;
1016 }
f9ed8854 1017 ixgbe_up(adapter);
759884b4 1018 }
4a0b9ca0
PW		 1019
1020 vfree(temp_rx_ring);
f9ed8854 1021err_setup:
4a0b9ca0
PW		 1022 vfree(temp_tx_ring);
1023clear_reset:
d4f80882 1024 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1025 return err;
1026}
1027
b9f2c044 1028static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1029{
b9f2c044 1030 switch (sset) {
da4dd0f7
PWJ		 1031 case ETH_SS_TEST:
1032 return IXGBE_TEST_LEN;
b9f2c044
JG		 1033 case ETH_SS_STATS:
1034 return IXGBE_STATS_LEN;
1035 default:
1036 return -EOPNOTSUPP;
1037 }
9a799d71
AK		 1038}
1039
1040static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 1041 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1042{
1043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1044 struct rtnl_link_stats64 temp;
1045 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1046 unsigned int start;
1047 struct ixgbe_ring *ring;
1048 int i, j;
29c3a050 1049 char *p = NULL;
9a799d71
AK		 1050
1051 ixgbe_update_stats(adapter);
28172739 1052 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1053 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1054 switch (ixgbe_gstrings_stats[i].type) {
1055 case NETDEV_STATS:
28172739 1056 p = (char *) net_stats +
29c3a050
AK		 1057 ixgbe_gstrings_stats[i].stat_offset;
1058 break;
1059 case IXGBE_STATS:
1060 p = (char *) adapter +
1061 ixgbe_gstrings_stats[i].stat_offset;
1062 break;
1063 }
1064
9a799d71 1065 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1066 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1067 }
1068 for (j = 0; j < adapter->num_tx_queues; j++) {
de1036b1
ED		 1069 ring = adapter->tx_ring[j];
1070 do {
1071 start = u64_stats_fetch_begin_bh(&ring->syncp);
1072 data[i] = ring->stats.packets;
1073 data[i+1] = ring->stats.bytes;
1074 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1075 i += 2;
9a799d71
AK		 1076 }
1077 for (j = 0; j < adapter->num_rx_queues; j++) {
de1036b1
ED		 1078 ring = adapter->rx_ring[j];
1079 do {
1080 start = u64_stats_fetch_begin_bh(&ring->syncp);
1081 data[i] = ring->stats.packets;
1082 data[i+1] = ring->stats.bytes;
1083 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1084 i += 2;
9a799d71 1085 }
2f90b865
AD		 1086 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1087 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1088 data[i++] = adapter->stats.pxontxc[j];
1089 data[i++] = adapter->stats.pxofftxc[j];
1090 }
1091 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1092 data[i++] = adapter->stats.pxonrxc[j];
1093 data[i++] = adapter->stats.pxoffrxc[j];
1094 }
1095 }
9a799d71
AK		 1096}
1097
1098static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1099 u8 *data)
9a799d71
AK		 1100{
1101 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1102 char *p = (char *)data;
9a799d71
AK		 1103 int i;
1104
1105 switch (stringset) {
da4dd0f7
PWJ		 1106 case ETH_SS_TEST:
1107 memcpy(data, *ixgbe_gstrings_test,
1108 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1109 break;
9a799d71
AK		 1110 case ETH_SS_STATS:
1111 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1112 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1113 ETH_GSTRING_LEN);
1114 p += ETH_GSTRING_LEN;
1115 }
1116 for (i = 0; i < adapter->num_tx_queues; i++) {
1117 sprintf(p, "tx_queue_%u_packets", i);
1118 p += ETH_GSTRING_LEN;
1119 sprintf(p, "tx_queue_%u_bytes", i);
1120 p += ETH_GSTRING_LEN;
1121 }
1122 for (i = 0; i < adapter->num_rx_queues; i++) {
1123 sprintf(p, "rx_queue_%u_packets", i);
1124 p += ETH_GSTRING_LEN;
1125 sprintf(p, "rx_queue_%u_bytes", i);
1126 p += ETH_GSTRING_LEN;
1127 }
2f90b865
AD		 1128 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1129 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1130 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1131 p += ETH_GSTRING_LEN;
1132 sprintf(p, "tx_pb_%u_pxoff", i);
1133 p += ETH_GSTRING_LEN;
2f90b865
AD		 1134 }
1135 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1136 sprintf(p, "rx_pb_%u_pxon", i);
1137 p += ETH_GSTRING_LEN;
1138 sprintf(p, "rx_pb_%u_pxoff", i);
1139 p += ETH_GSTRING_LEN;
2f90b865
AD		 1140 }
1141 }
b4617240 1142 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1143 break;
1144 }
1145}
1146
da4dd0f7
PWJ		 1147static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1148{
1149 struct ixgbe_hw *hw = &adapter->hw;
1150 bool link_up;
1151 u32 link_speed = 0;
1152 *data = 0;
1153
1154 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1155 if (link_up)
1156 return *data;
1157 else
1158 *data = 1;
1159 return *data;
1160}
1161
1162/* ethtool register test data */
1163struct ixgbe_reg_test {
1164 u16 reg;
1165 u8 array_len;
1166 u8 test_type;
1167 u32 mask;
1168 u32 write;
1169};
1170
1171/* In the hardware, registers are laid out either singly, in arrays
1172 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1173 * most tests take place on arrays or single registers (handled
1174 * as a single-element array) and special-case the tables.
1175 * Table tests are always pattern tests.
1176 *
1177 * We also make provision for some required setup steps by specifying
1178 * registers to be written without any read-back testing.
1179 */
1180
1181#define PATTERN_TEST 1
1182#define SET_READ_TEST 2
1183#define WRITE_NO_TEST 3
1184#define TABLE32_TEST 4
1185#define TABLE64_TEST_LO 5
1186#define TABLE64_TEST_HI 6
1187
1188/* default 82599 register test */
66744500 1189static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1190 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1191 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1192 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1193 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1194 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1195 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1196 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1197 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1198 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1199 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1200 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1201 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1202 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1203 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1204 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1205 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1206 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1207 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1208 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1209 { 0, 0, 0, 0 }
1210};
1211
1212/* default 82598 register test */
66744500 1213static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1214 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1215 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1216 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1217 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1218 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1219 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1220 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1221 /* Enable all four RX queues before testing. */
1222 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1223 /* RDH is read-only for 82598, only test RDT. */
1224 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1225 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1226 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1227 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1228 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1229 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1230 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1231 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1232 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1233 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1234 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1235 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1236 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1237 { 0, 0, 0, 0 }
1238};
1239
95a46011
ET		 1240static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1241 u32 mask, u32 write)
1242{
1243 u32 pat, val, before;
1244 static const u32 test_pattern[] = {
1245 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1246
1247 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1248 before = readl(adapter->hw.hw_addr + reg);
1249 writel((test_pattern[pat] & write),
1250 (adapter->hw.hw_addr + reg));
1251 val = readl(adapter->hw.hw_addr + reg);
1252 if (val != (test_pattern[pat] & write & mask)) {
1253 e_err(drv, "pattern test reg %04X failed: got "
1254 "0x%08X expected 0x%08X\n",
1255 reg, val, (test_pattern[pat] & write & mask));
1256 *data = reg;
1257 writel(before, adapter->hw.hw_addr + reg);
1258 return 1;
1259 }
1260 writel(before, adapter->hw.hw_addr + reg);
1261 }
1262 return 0;
da4dd0f7
PWJ		 1263}
1264
95a46011
ET		 1265static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1266 u32 mask, u32 write)
1267{
1268 u32 val, before;
1269 before = readl(adapter->hw.hw_addr + reg);
1270 writel((write & mask), (adapter->hw.hw_addr + reg));
1271 val = readl(adapter->hw.hw_addr + reg);
1272 if ((write & mask) != (val & mask)) {
1273 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1274 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1275 *data = reg;
1276 writel(before, (adapter->hw.hw_addr + reg));
1277 return 1;
1278 }
1279 writel(before, (adapter->hw.hw_addr + reg));
1280 return 0;
da4dd0f7
PWJ		 1281}
1282
95a46011
ET		 1283#define REG_PATTERN_TEST(reg, mask, write) \
1284 do { \
1285 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1286 return 1; \
1287 } while (0) \
1288
1289
1290#define REG_SET_AND_CHECK(reg, mask, write) \
1291 do { \
1292 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1293 return 1; \
1294 } while (0) \
1295
da4dd0f7
PWJ		 1296static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1297{
66744500 1298 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1299 u32 value, before, after;
1300 u32 i, toggle;
1301
bd508178
AD		 1302 switch (adapter->hw.mac.type) {
1303 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1304 toggle = 0x7FFFF3FF;
1305 test = reg_test_82598;
bd508178
AD		 1306 break;
1307 case ixgbe_mac_82599EB:
b93a2226 1308 case ixgbe_mac_X540:
bd508178
AD		 1309 toggle = 0x7FFFF30F;
1310 test = reg_test_82599;
1311 break;
1312 default:
1313 *data = 1;
1314 return 1;
1315 break;
da4dd0f7
PWJ		 1316 }
1317
1318 /*
1319 * Because the status register is such a special case,
1320 * we handle it separately from the rest of the register
1321 * tests. Some bits are read-only, some toggle, and some
1322 * are writeable on newer MACs.
1323 */
1324 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1325 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1327 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1328 if (value != after) {
396e799c
ET		 1329 e_err(drv, "failed STATUS register test got: 0x%08X "
1330 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1331 *data = 1;
1332 return 1;
1333 }
1334 /* restore previous status */
1335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1336
1337 /*
1338 * Perform the remainder of the register test, looping through
1339 * the test table until we either fail or reach the null entry.
1340 */
1341 while (test->reg) {
1342 for (i = 0; i < test->array_len; i++) {
1343 switch (test->test_type) {
1344 case PATTERN_TEST:
1345 REG_PATTERN_TEST(test->reg + (i * 0x40),
95a46011
ET		 1346 test->mask,
1347 test->write);
da4dd0f7
PWJ		 1348 break;
1349 case SET_READ_TEST:
1350 REG_SET_AND_CHECK(test->reg + (i * 0x40),
95a46011
ET		 1351 test->mask,
1352 test->write);
da4dd0f7
PWJ		 1353 break;
1354 case WRITE_NO_TEST:
1355 writel(test->write,
1356 (adapter->hw.hw_addr + test->reg)
1357 + (i * 0x40));
1358 break;
1359 case TABLE32_TEST:
1360 REG_PATTERN_TEST(test->reg + (i * 4),
95a46011
ET		 1361 test->mask,
1362 test->write);
da4dd0f7
PWJ		 1363 break;
1364 case TABLE64_TEST_LO:
1365 REG_PATTERN_TEST(test->reg + (i * 8),
95a46011
ET		 1366 test->mask,
1367 test->write);
da4dd0f7
PWJ		 1368 break;
1369 case TABLE64_TEST_HI:
1370 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
95a46011
ET		 1371 test->mask,
1372 test->write);
da4dd0f7
PWJ		 1373 break;
1374 }
1375 }
1376 test++;
1377 }
1378
1379 *data = 0;
1380 return 0;
1381}
1382
1383static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1384{
1385 struct ixgbe_hw *hw = &adapter->hw;
1386 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1387 *data = 1;
1388 else
1389 *data = 0;
1390 return *data;
1391}
1392
1393static irqreturn_t ixgbe_test_intr(int irq, void *data)
1394{
1395 struct net_device *netdev = (struct net_device *) data;
1396 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1397
1398 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1399
1400 return IRQ_HANDLED;
1401}
1402
1403static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1404{
1405 struct net_device *netdev = adapter->netdev;
1406 u32 mask, i = 0, shared_int = true;
1407 u32 irq = adapter->pdev->irq;
1408
1409 *data = 0;
1410
1411 /* Hook up test interrupt handler just for this test */
1412 if (adapter->msix_entries) {
1413 /* NOTE: we don't test MSI-X interrupts here, yet */
1414 return 0;
1415 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1416 shared_int = false;
a0607fd3 1417 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1418 netdev)) {
1419 *data = 1;
1420 return -1;
1421 }
a0607fd3 1422 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1423 netdev->name, netdev)) {
1424 shared_int = false;
a0607fd3 1425 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1426 netdev->name, netdev)) {
1427 *data = 1;
1428 return -1;
1429 }
396e799c
ET		 1430 e_info(hw, "testing %s interrupt\n", shared_int ?
1431 "shared" : "unshared");
da4dd0f7
PWJ		 1432
1433 /* Disable all the interrupts */
1434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
032b4325 1435 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1436
1437 /* Test each interrupt */
1438 for (; i < 10; i++) {
1439 /* Interrupt to test */
1440 mask = 1 << i;
1441
1442 if (!shared_int) {
1443 /*
1444 * Disable the interrupts to be reported in
1445 * the cause register and then force the same
1446 * interrupt and see if one gets posted. If
1447 * an interrupt was posted to the bus, the
1448 * test failed.
1449 */
1450 adapter->test_icr = 0;
1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1452 ~mask & 0x00007FFF);
1453 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1454 ~mask & 0x00007FFF);
032b4325 1455 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1456
1457 if (adapter->test_icr & mask) {
1458 *data = 3;
1459 break;
1460 }
1461 }
1462
1463 /*
1464 * Enable the interrupt to be reported in the cause
1465 * register and then force the same interrupt and see
1466 * if one gets posted. If an interrupt was not posted
1467 * to the bus, the test failed.
1468 */
1469 adapter->test_icr = 0;
1470 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
032b4325 1472 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1473
1474 if (!(adapter->test_icr &mask)) {
1475 *data = 4;
1476 break;
1477 }
1478
1479 if (!shared_int) {
1480 /*
1481 * Disable the other interrupts to be reported in
1482 * the cause register and then force the other
1483 * interrupts and see if any get posted. If
1484 * an interrupt was posted to the bus, the
1485 * test failed.
1486 */
1487 adapter->test_icr = 0;
1488 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1489 ~mask & 0x00007FFF);
1490 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1491 ~mask & 0x00007FFF);
032b4325 1492 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1493
1494 if (adapter->test_icr) {
1495 *data = 5;
1496 break;
1497 }
1498 }
1499 }
1500
1501 /* Disable all the interrupts */
1502 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
032b4325 1503 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1504
1505 /* Unhook test interrupt handler */
1506 free_irq(irq, netdev);
1507
1508 return *data;
1509}
1510
1511static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1512{
1513 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1514 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1515 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1516 u32 reg_ctl;
da4dd0f7
PWJ		 1517
1518 /* shut down the DMA engines now so they can be reinitialized later */
1519
1520 /* first Rx */
1521 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1522 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1523 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
2d39d576 1524 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1525
1526 /* now Tx */
84418e3b 1527 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1528 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1529 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1530
bd508178
AD		 1531 switch (hw->mac.type) {
1532 case ixgbe_mac_82599EB:
b93a2226 1533 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1534 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1535 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1536 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1537 break;
1538 default:
1539 break;
da4dd0f7
PWJ		 1540 }
1541
1542 ixgbe_reset(adapter);
1543
b6ec895e
AD		 1544 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1545 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1546}
1547
1548static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1549{
1550 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1551 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1552 u32 rctl, reg_data;
84418e3b
AD		 1553 int ret_val;
1554 int err;
da4dd0f7
PWJ		 1555
1556 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1557 tx_ring->count = IXGBE_DEFAULT_TXD;
1558 tx_ring->queue_index = 0;
b6ec895e 1559 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1560 tx_ring->netdev = adapter->netdev;
84418e3b
AD		 1561 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1562 tx_ring->numa_node = adapter->node;
da4dd0f7 1563
b6ec895e 1564 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1565 if (err)
1566 return 1;
da4dd0f7 1567
bd508178
AD		 1568 switch (adapter->hw.mac.type) {
1569 case ixgbe_mac_82599EB:
b93a2226 1570 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1571 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1572 reg_data |= IXGBE_DMATXCTL_TE;
1573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1574 break;
1575 default:
1576 break;
da4dd0f7 1577 }
f4ec443b 1578
84418e3b 1579 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1580
1581 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1582 rx_ring->count = IXGBE_DEFAULT_RXD;
1583 rx_ring->queue_index = 0;
b6ec895e 1584 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1585 rx_ring->netdev = adapter->netdev;
84418e3b
AD		 1586 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1587 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048;
1588 rx_ring->numa_node = adapter->node;
1589
b6ec895e 1590 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1591 if (err) {
da4dd0f7
PWJ		 1592 ret_val = 4;
1593 goto err_nomem;
1594 }
1595
da4dd0f7
PWJ		 1596 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1598
84418e3b 1599 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1600
1601 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1603
da4dd0f7
PWJ		 1604 return 0;
1605
1606err_nomem:
1607 ixgbe_free_desc_rings(adapter);
1608 return ret_val;
1609}
1610
1611static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1612{
1613 struct ixgbe_hw *hw = &adapter->hw;
1614 u32 reg_data;
1615
e7fd9253
DS		 1616 /* X540 needs to set the MACC.FLU bit to force link up */
1617 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1618 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MACC);
1619 reg_data |= IXGBE_MACC_FLU;
1620 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MACC, reg_data);
1621 }
1622
da4dd0f7 1623 /* right now we only support MAC loopback in the driver */
da4dd0f7 1624 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
84418e3b 1625 /* Setup MAC loopback */
da4dd0f7
PWJ		 1626 reg_data |= IXGBE_HLREG0_LPBK;
1627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1628
84418e3b
AD		 1629 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1630 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1631 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1632
da4dd0f7
PWJ		 1633 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1634 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1635 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
84418e3b 1637 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1638 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1639
1640 /* Disable Atlas Tx lanes; re-enabled in reset path */
1641 if (hw->mac.type == ixgbe_mac_82598EB) {
1642 u8 atlas;
1643
1644 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1645 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1646 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1647
1648 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1649 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1650 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1651
1652 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1653 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1654 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1655
1656 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1657 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1658 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1659 }
1660
1661 return 0;
1662}
1663
1664static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1665{
1666 u32 reg_data;
1667
1668 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1669 reg_data &= ~IXGBE_HLREG0_LPBK;
1670 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1671}
1672
1673static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1674 unsigned int frame_size)
1675{
1676 memset(skb->data, 0xFF, frame_size);
1677 frame_size &= ~1;
1678 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1679 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1680 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1681}
1682
1683static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1684 unsigned int frame_size)
1685{
1686 frame_size &= ~1;
1687 if (*(skb->data + 3) == 0xFF) {
1688 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1689 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1690 return 0;
1691 }
1692 }
1693 return 13;
1694}
1695
fc77dc3c 1696static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
84418e3b
AD		 1697 struct ixgbe_ring *tx_ring,
1698 unsigned int size)
1699{
1700 union ixgbe_adv_rx_desc *rx_desc;
1701 struct ixgbe_rx_buffer *rx_buffer_info;
1702 struct ixgbe_tx_buffer *tx_buffer_info;
1703 const int bufsz = rx_ring->rx_buf_len;
1704 u32 staterr;
1705 u16 rx_ntc, tx_ntc, count = 0;
1706
1707 /* initialize next to clean and descriptor values */
1708 rx_ntc = rx_ring->next_to_clean;
1709 tx_ntc = tx_ring->next_to_clean;
1710 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1711 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1712
1713 while (staterr & IXGBE_RXD_STAT_DD) {
1714 /* check Rx buffer */
1715 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1716
1717 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
b6ec895e 1718 dma_unmap_single(rx_ring->dev,
84418e3b
AD		 1719 rx_buffer_info->dma,
1720 bufsz,
1721 DMA_FROM_DEVICE);
1722 rx_buffer_info->dma = 0;
1723
1724 /* verify contents of skb */
1725 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1726 count++;
1727
1728 /* unmap buffer on Tx side */
1729 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
b6ec895e 1730 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
84418e3b
AD		 1731
1732 /* increment Rx/Tx next to clean counters */
1733 rx_ntc++;
1734 if (rx_ntc == rx_ring->count)
1735 rx_ntc = 0;
1736 tx_ntc++;
1737 if (tx_ntc == tx_ring->count)
1738 tx_ntc = 0;
1739
1740 /* fetch next descriptor */
1741 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1742 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1743 }
1744
1745 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1746 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1747 rx_ring->next_to_clean = rx_ntc;
1748 tx_ring->next_to_clean = tx_ntc;
1749
1750 return count;
1751}
1752
da4dd0f7
PWJ		 1753static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1754{
1755 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1756 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1757 int i, j, lc, good_cnt, ret_val = 0;
1758 unsigned int size = 1024;
1759 netdev_tx_t tx_ret_val;
1760 struct sk_buff *skb;
1761
1762 /* allocate test skb */
1763 skb = alloc_skb(size, GFP_KERNEL);
1764 if (!skb)
1765 return 11;
da4dd0f7 1766
84418e3b
AD		 1767 /* place data into test skb */
1768 ixgbe_create_lbtest_frame(skb, size);
1769 skb_put(skb, size);
da4dd0f7
PWJ		 1770
1771 /*
1772 * Calculate the loop count based on the largest descriptor ring
1773 * The idea is to wrap the largest ring a number of times using 64
1774 * send/receive pairs during each loop
1775 */
1776
1777 if (rx_ring->count <= tx_ring->count)
1778 lc = ((tx_ring->count / 64) * 2) + 1;
1779 else
1780 lc = ((rx_ring->count / 64) * 2) + 1;
1781
da4dd0f7 1782 for (j = 0; j <= lc; j++) {
84418e3b 1783 /* reset count of good packets */
da4dd0f7 1784 good_cnt = 0;
84418e3b
AD		 1785
1786 /* place 64 packets on the transmit queue*/
1787 for (i = 0; i < 64; i++) {
1788 skb_get(skb);
1789 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1790 adapter,
1791 tx_ring);
1792 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1793 good_cnt++;
84418e3b
AD		 1794 }
1795
da4dd0f7 1796 if (good_cnt != 64) {
84418e3b 1797 ret_val = 12;
da4dd0f7
PWJ		 1798 break;
1799 }
84418e3b
AD		 1800
1801 /* allow 200 milliseconds for packets to go from Tx to Rx */
1802 msleep(200);
1803
fc77dc3c 1804 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1805 if (good_cnt != 64) {
1806 ret_val = 13;
da4dd0f7
PWJ		 1807 break;
1808 }
1809 }
1810
84418e3b
AD		 1811 /* free the original skb */
1812 kfree_skb(skb);
1813
da4dd0f7
PWJ		 1814 return ret_val;
1815}
1816
1817static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1818{
1819 *data = ixgbe_setup_desc_rings(adapter);
1820 if (*data)
1821 goto out;
1822 *data = ixgbe_setup_loopback_test(adapter);
1823 if (*data)
1824 goto err_loopback;
1825 *data = ixgbe_run_loopback_test(adapter);
1826 ixgbe_loopback_cleanup(adapter);
1827
1828err_loopback:
1829 ixgbe_free_desc_rings(adapter);
1830out:
1831 return *data;
1832}
1833
1834static void ixgbe_diag_test(struct net_device *netdev,
1835 struct ethtool_test *eth_test, u64 *data)
1836{
1837 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1838 bool if_running = netif_running(netdev);
1839
1840 set_bit(__IXGBE_TESTING, &adapter->state);
1841 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1842 /* Offline tests */
1843
396e799c 1844 e_info(hw, "offline testing starting\n");
da4dd0f7
PWJ		 1845
1846 /* Link test performed before hardware reset so autoneg doesn't
1847 * interfere with test result */
1848 if (ixgbe_link_test(adapter, &data[4]))
1849 eth_test->flags |= ETH_TEST_FL_FAILED;
1850
e7d481a6
GR		 1851 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1852 int i;
1853 for (i = 0; i < adapter->num_vfs; i++) {
1854 if (adapter->vfinfo[i].clear_to_send) {
1855 netdev_warn(netdev, "%s",
1856 "offline diagnostic is not "
1857 "supported when VFs are "
1858 "present\n");
1859 data[0] = 1;
1860 data[1] = 1;
1861 data[2] = 1;
1862 data[3] = 1;
1863 eth_test->flags |= ETH_TEST_FL_FAILED;
1864 clear_bit(__IXGBE_TESTING,
1865 &adapter->state);
1866 goto skip_ol_tests;
1867 }
1868 }
1869 }
1870
da4dd0f7
PWJ		 1871 if (if_running)
1872 /* indicate we're in test mode */
1873 dev_close(netdev);
1874 else
1875 ixgbe_reset(adapter);
1876
396e799c 1877 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1878 if (ixgbe_reg_test(adapter, &data[0]))
1879 eth_test->flags |= ETH_TEST_FL_FAILED;
1880
1881 ixgbe_reset(adapter);
396e799c 1882 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1883 if (ixgbe_eeprom_test(adapter, &data[1]))
1884 eth_test->flags |= ETH_TEST_FL_FAILED;
1885
1886 ixgbe_reset(adapter);
396e799c 1887 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1888 if (ixgbe_intr_test(adapter, &data[2]))
1889 eth_test->flags |= ETH_TEST_FL_FAILED;
1890
bdbec4b8
GR		 1891 /* If SRIOV or VMDq is enabled then skip MAC
1892 * loopback diagnostic. */
1893 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1894 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1895 e_info(hw, "Skip MAC loopback diagnostic in VT "
1896 "mode\n");
bdbec4b8
GR		 1897 data[3] = 0;
1898 goto skip_loopback;
1899 }
1900
da4dd0f7 1901 ixgbe_reset(adapter);
396e799c 1902 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1903 if (ixgbe_loopback_test(adapter, &data[3]))
1904 eth_test->flags |= ETH_TEST_FL_FAILED;
1905
bdbec4b8 1906skip_loopback:
da4dd0f7
PWJ		 1907 ixgbe_reset(adapter);
1908
1909 clear_bit(__IXGBE_TESTING, &adapter->state);
1910 if (if_running)
1911 dev_open(netdev);
1912 } else {
396e799c 1913 e_info(hw, "online testing starting\n");
da4dd0f7
PWJ		 1914 /* Online tests */
1915 if (ixgbe_link_test(adapter, &data[4]))
1916 eth_test->flags |= ETH_TEST_FL_FAILED;
1917
1918 /* Online tests aren't run; pass by default */
1919 data[0] = 0;
1920 data[1] = 0;
1921 data[2] = 0;
1922 data[3] = 0;
1923
1924 clear_bit(__IXGBE_TESTING, &adapter->state);
1925 }
e7d481a6 1926skip_ol_tests:
da4dd0f7
PWJ		 1927 msleep_interruptible(4 * 1000);
1928}
9a799d71 1929
d6c519e1
AD		 1930static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1931 struct ethtool_wolinfo *wol)
1932{
1933 struct ixgbe_hw *hw = &adapter->hw;
1934 int retval = 1;
1935
0b077fea 1936 /* WOL not supported except for the following */
d6c519e1 1937 switch(hw->device_id) {
0b077fea
DS		 1938 case IXGBE_DEV_ID_82599_SFP:
1939 /* Only this subdevice supports WOL */
1940 if (hw->subsystem_device_id != IXGBE_SUBDEV_ID_82599_SFP) {
1941 wol->supported = 0;
1942 break;
1943 }
1944 retval = 0;
1945 break;
50d6c681
AD		 1946 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1947 /* All except this subdevice support WOL */
1948 if (hw->subsystem_device_id ==
1949 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
1950 wol->supported = 0;
1951 break;
1952 }
0b077fea
DS		 1953 retval = 0;
1954 break;
d6c519e1
AD		 1955 case IXGBE_DEV_ID_82599_KX4:
1956 retval = 0;
1957 break;
1958 default:
1959 wol->supported = 0;
d6c519e1
AD		 1960 }
1961
1962 return retval;
1963}
1964
9a799d71 1965static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1966 struct ethtool_wolinfo *wol)
9a799d71 1967{
e63d9762
PW		 1968 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1969
1970 wol->supported = WAKE_UCAST | WAKE_MCAST |
1971 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1972 wol->wolopts = 0;
1973
d6c519e1
AD		 1974 if (ixgbe_wol_exclusion(adapter, wol) ||
1975 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1976 return;
1977
1978 if (adapter->wol & IXGBE_WUFC_EX)
1979 wol->wolopts |= WAKE_UCAST;
1980 if (adapter->wol & IXGBE_WUFC_MC)
1981 wol->wolopts |= WAKE_MCAST;
1982 if (adapter->wol & IXGBE_WUFC_BC)
1983 wol->wolopts |= WAKE_BCAST;
1984 if (adapter->wol & IXGBE_WUFC_MAG)
1985 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 1986}
1987
e63d9762
PW		 1988static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1989{
1990 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1991
1992 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1993 return -EOPNOTSUPP;
1994
d6c519e1
AD		 1995 if (ixgbe_wol_exclusion(adapter, wol))
1996 return wol->wolopts ? -EOPNOTSUPP : 0;
1997
e63d9762
PW		 1998 adapter->wol = 0;
1999
2000 if (wol->wolopts & WAKE_UCAST)
2001 adapter->wol |= IXGBE_WUFC_EX;
2002 if (wol->wolopts & WAKE_MCAST)
2003 adapter->wol |= IXGBE_WUFC_MC;
2004 if (wol->wolopts & WAKE_BCAST)
2005 adapter->wol |= IXGBE_WUFC_BC;
2006 if (wol->wolopts & WAKE_MAGIC)
2007 adapter->wol |= IXGBE_WUFC_MAG;
2008
2009 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2010
2011 return 0;
2012}
2013
9a799d71
AK		 2014static int ixgbe_nway_reset(struct net_device *netdev)
2015{
2016 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2017
d4f80882
AV		 2018 if (netif_running(netdev))
2019 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2020
2021 return 0;
2022}
2023
66e6961c
ET		 2024static int ixgbe_set_phys_id(struct net_device *netdev,
2025 enum ethtool_phys_id_state state)
9a799d71
AK		 2026{
2027 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2028 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2029
66e6961c
ET		 2030 switch (state) {
2031 case ETHTOOL_ID_ACTIVE:
2032 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2033 return 2;
9a799d71 2034
66e6961c 2035 case ETHTOOL_ID_ON:
c44ade9e 2036 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 2037 break;
2038
2039 case ETHTOOL_ID_OFF:
c44ade9e 2040 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 2041 break;
9a799d71 2042
66e6961c
ET		 2043 case ETHTOOL_ID_INACTIVE:
2044 /* Restore LED settings */
2045 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2046 break;
2047 }
9a799d71
AK		 2048
2049 return 0;
2050}
2051
2052static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 2053 struct ethtool_coalesce *ec)
9a799d71
AK		 2054{
2055 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2056
4a0b9ca0 2057 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
30efa5a3
JB		 2058
2059 /* only valid if in constant ITR mode */
f7554a2b 2060 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 2061 case 0:
2062 /* throttling disabled */
2063 ec->rx_coalesce_usecs = 0;
2064 break;
2065 case 1:
2066 /* dynamic ITR mode */
2067 ec->rx_coalesce_usecs = 1;
2068 break;
2069 default:
2070 /* fixed interrupt rate mode */
f7554a2b 2071 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 2072 break;
2073 }
f7554a2b 2074
cfb3f91a
SN		 2075 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2076 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2077 return 0;
2078
f7554a2b
NS		 2079 /* only valid if in constant ITR mode */
2080 switch (adapter->tx_itr_setting) {
2081 case 0:
2082 /* throttling disabled */
2083 ec->tx_coalesce_usecs = 0;
2084 break;
2085 case 1:
2086 /* dynamic ITR mode */
2087 ec->tx_coalesce_usecs = 1;
2088 break;
2089 default:
2090 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2091 break;
2092 }
2093
9a799d71
AK		 2094 return 0;
2095}
2096
80fba3f4
AD		 2097/*
2098 * this function must be called before setting the new value of
2099 * rx_itr_setting
2100 */
2101static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter,
2102 struct ethtool_coalesce *ec)
2103{
2104 struct net_device *netdev = adapter->netdev;
2105
2106 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2107 return false;
2108
2109 /* if interrupt rate is too high then disable RSC */
2110 if (ec->rx_coalesce_usecs != 1 &&
2111 ec->rx_coalesce_usecs <= 1000000/IXGBE_MAX_RSC_INT_RATE) {
2112 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2113 e_info(probe, "rx-usecs set too low, "
2114 "disabling RSC\n");
2115 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2116 return true;
2117 }
2118 } else {
2119 /* check the feature flag value and enable RSC if necessary */
2120 if ((netdev->features & NETIF_F_LRO) &&
2121 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2122 e_info(probe, "rx-usecs set to %d, "
2123 "re-enabling RSC\n",
2124 ec->rx_coalesce_usecs);
2125 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2126 return true;
2127 }
2128 }
2129 return false;
2130}
2131
9a799d71 2132static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2133 struct ethtool_coalesce *ec)
9a799d71
AK		 2134{
2135 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2136 struct ixgbe_q_vector *q_vector;
30efa5a3 2137 int i;
ef021194 2138 bool need_reset = false;
9a799d71 2139
cfb3f91a
SN		 2140 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2141 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2142 && ec->tx_coalesce_usecs)
f7554a2b
NS		 2143 return -EINVAL;
2144
9a799d71 2145 if (ec->tx_max_coalesced_frames_irq)
4a0b9ca0 2146 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
30efa5a3
JB		 2147
2148 if (ec->rx_coalesce_usecs > 1) {
509ee935 2149 /* check the limits */
80fba3f4 2150 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
509ee935
JB		 2151 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2152 return -EINVAL;
2153
80fba3f4
AD		 2154 /* check the old value and enable RSC if necessary */
2155 need_reset = ixgbe_update_rsc(adapter, ec);
2156
30efa5a3 2157 /* store the value in ints/second */
f7554a2b 2158 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2159
2160 /* static value of interrupt rate */
f7554a2b 2161 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2162 /* clear the lower bit as its used for dynamic state */
f7554a2b 2163 adapter->rx_itr_setting &= ~1;
30efa5a3 2164 } else if (ec->rx_coalesce_usecs == 1) {
80fba3f4
AD		 2165 /* check the old value and enable RSC if necessary */
2166 need_reset = ixgbe_update_rsc(adapter, ec);
2167
30efa5a3 2168 /* 1 means dynamic mode */
f7554a2b
NS		 2169 adapter->rx_eitr_param = 20000;
2170 adapter->rx_itr_setting = 1;
30efa5a3 2171 } else {
80fba3f4
AD		 2172 /* check the old value and enable RSC if necessary */
2173 need_reset = ixgbe_update_rsc(adapter, ec);
509ee935
JB		 2174 /*
2175 * any other value means disable eitr, which is best
2176 * served by setting the interrupt rate very high
2177 */
f8d1dcaf 2178 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
f7554a2b
NS		 2179 adapter->rx_itr_setting = 0;
2180 }
2181
2182 if (ec->tx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2183 /*
2184 * don't have to worry about max_int as above because
2185 * tx vectors don't do hardware RSC (an rx function)
2186 */
f7554a2b
NS		 2187 /* check the limits */
2188 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2189 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2190 return -EINVAL;
2191
2192 /* store the value in ints/second */
2193 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2194
2195 /* static value of interrupt rate */
2196 adapter->tx_itr_setting = adapter->tx_eitr_param;
2197
2198 /* clear the lower bit as its used for dynamic state */
2199 adapter->tx_itr_setting &= ~1;
2200 } else if (ec->tx_coalesce_usecs == 1) {
2201 /* 1 means dynamic mode */
2202 adapter->tx_eitr_param = 10000;
2203 adapter->tx_itr_setting = 1;
2204 } else {
2205 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2206 adapter->tx_itr_setting = 0;
30efa5a3 2207 }
9a799d71 2208
237057ad
DS		 2209 /* MSI/MSIx Interrupt Mode */
2210 if (adapter->flags &
2211 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2212 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2213 for (i = 0; i < num_vectors; i++) {
2214 q_vector = adapter->q_vector[i];
2215 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 2216 /* tx only */
2217 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2218 else
2219 /* rx only or mixed */
f7554a2b 2220 q_vector->eitr = adapter->rx_eitr_param;
237057ad
DS		 2221 ixgbe_write_eitr(q_vector);
2222 }
2223 /* Legacy Interrupt Mode */
2224 } else {
2225 q_vector = adapter->q_vector[0];
f7554a2b 2226 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 2227 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2228 }
2229
ef021194
JB		 2230 /*
2231 * do reset here at the end to make sure EITR==0 case is handled
2232 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2233 * also locks in RSC enable/disable which requires reset
2234 */
2235 if (need_reset) {
2236 if (netif_running(netdev))
2237 ixgbe_reinit_locked(adapter);
2238 else
2239 ixgbe_reset(adapter);
2240 }
2241
9a799d71
AK		 2242 return 0;
2243}
2244
f8212f97
AD		 2245static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2246{
2247 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a713e7c 2248 bool need_reset = false;
1437ce39 2249 int rc;
f8212f97 2250
f62bbb5e
JG		 2251#ifdef CONFIG_IXGBE_DCB
2252 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
2253 !(data & ETH_FLAG_RXVLAN))
2254 return -EINVAL;
2255#endif
2256
2257 need_reset = (data & ETH_FLAG_RXVLAN) !=
2258 (netdev->features & NETIF_F_HW_VLAN_RX);
2259
67a74ee2
ET		 2260 if ((data & ETH_FLAG_RXHASH) &&
2261 !(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
2262 return -EOPNOTSUPP;
2263
5136cad3 2264 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO | ETH_FLAG_NTUPLE |
67a74ee2
ET		 2265 ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN |
2266 ETH_FLAG_RXHASH);
1437ce39
BH		 2267 if (rc)
2268 return rc;
f8212f97 2269
f8212f97 2270 /* if state changes we need to update adapter->flags and reset */
80fba3f4
AD		 2271 if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
2272 (!!(data & ETH_FLAG_LRO) !=
2273 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2274 if ((data & ETH_FLAG_LRO) &&
2275 (!adapter->rx_itr_setting ||
2276 (adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE))) {
2277 e_info(probe, "rx-usecs set too low, "
2278 "not enabling RSC.\n");
2279 } else {
f8d1dcaf
JB		 2280 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2281 switch (adapter->hw.mac.type) {
2282 case ixgbe_mac_82599EB:
2283 need_reset = true;
2284 break;
b93a2226
DS		 2285 case ixgbe_mac_X540: {
2286 int i;
2287 for (i = 0; i < adapter->num_rx_queues; i++) {
2288 struct ixgbe_ring *ring =
2289 adapter->rx_ring[i];
2290 if (adapter->flags2 &
2291 IXGBE_FLAG2_RSC_ENABLED) {
2292 ixgbe_configure_rscctl(adapter,
2293 ring);
2294 } else {
2295 ixgbe_clear_rscctl(adapter,
2296 ring);
2297 }
2298 }
2299 }
2300 break;
f8d1dcaf
JB		 2301 default:
2302 break;
2303 }
f8d1dcaf 2304 }
9a713e7c
PW		 2305 }
2306
2307 /*
2308 * Check if Flow Director n-tuple support was enabled or disabled. If
2309 * the state changed, we need to reset.
2310 */
2311 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2312 (!(data & ETH_FLAG_NTUPLE))) {
2313 /* turn off Flow Director perfect, set hash and reset */
2314 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2315 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2316 need_reset = true;
2317 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2318 (data & ETH_FLAG_NTUPLE)) {
2319 /* turn off Flow Director hash, enable perfect and reset */
2320 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2321 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2322 need_reset = true;
2323 } else {
2324 /* no state change */
2325 }
2326
2327 if (need_reset) {
f8212f97
AD		 2328 if (netif_running(netdev))
2329 ixgbe_reinit_locked(adapter);
2330 else
2331 ixgbe_reset(adapter);
2332 }
9a713e7c 2333
f8212f97 2334 return 0;
9a713e7c
PW		 2335}
2336
2337static int ixgbe_set_rx_ntuple(struct net_device *dev,
2338 struct ethtool_rx_ntuple *cmd)
2339{
2340 struct ixgbe_adapter *adapter = netdev_priv(dev);
45b9f509 2341 struct ethtool_rx_ntuple_flow_spec *fs = &cmd->fs;
905e4a41 2342 union ixgbe_atr_input input_struct;
9a713e7c
PW		 2343 struct ixgbe_atr_input_masks input_masks;
2344 int target_queue;
45b9f509 2345 int err;
9a713e7c
PW		 2346
2347 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2348 return -EOPNOTSUPP;
2349
2350 /*
2351 * Don't allow programming if the action is a queue greater than
2352 * the number of online Tx queues.
2353 */
45b9f509
AD		 2354 if ((fs->action >= adapter->num_tx_queues) ||
2355 (fs->action < ETHTOOL_RXNTUPLE_ACTION_DROP))
9a713e7c
PW		 2356 return -EINVAL;
2357
905e4a41 2358 memset(&input_struct, 0, sizeof(union ixgbe_atr_input));
9a713e7c
PW		 2359 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2360
45b9f509
AD		 2361 /* record flow type */
2362 switch (fs->flow_type) {
2363 case IPV4_FLOW:
2364 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2365 break;
9a713e7c 2366 case TCP_V4_FLOW:
45b9f509 2367 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
9a713e7c
PW		 2368 break;
2369 case UDP_V4_FLOW:
45b9f509 2370 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
9a713e7c
PW		 2371 break;
2372 case SCTP_V4_FLOW:
45b9f509 2373 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
9a713e7c
PW		 2374 break;
2375 default:
2376 return -1;
2377 }
f8212f97 2378
45b9f509
AD		 2379 /* copy vlan tag minus the CFI bit */
2380 if ((fs->vlan_tag & 0xEFFF) || (~fs->vlan_tag_mask & 0xEFFF)) {
2381 input_struct.formatted.vlan_id = htons(fs->vlan_tag & 0xEFFF);
2382 if (!fs->vlan_tag_mask) {
2383 input_masks.vlan_id_mask = htons(0xEFFF);
2384 } else {
2385 switch (~fs->vlan_tag_mask & 0xEFFF) {
2386 /* all of these are valid vlan-mask values */
2387 case 0xEFFF:
2388 case 0xE000:
2389 case 0x0FFF:
2390 case 0x0000:
2391 input_masks.vlan_id_mask =
2392 htons(~fs->vlan_tag_mask);
2393 break;
2394 /* exit with error if vlan-mask is invalid */
2395 default:
2396 e_err(drv, "Partial VLAN ID or "
2397 "priority mask in vlan-mask is not "
2398 "supported by hardware\n");
2399 return -1;
2400 }
2401 }
2402 }
2403
2404 /* make sure we only use the first 2 bytes of user data */
2405 if ((fs->data & 0xFFFF) || (~fs->data_mask & 0xFFFF)) {
2406 input_struct.formatted.flex_bytes = htons(fs->data & 0xFFFF);
2407 if (!(fs->data_mask & 0xFFFF)) {
2408 input_masks.flex_mask = 0xFFFF;
2409 } else if (~fs->data_mask & 0xFFFF) {
2410 e_err(drv, "Partial user-def-mask is not "
2411 "supported by hardware\n");
2412 return -1;
2413 }
2414 }
2415
2416 /*
2417 * Copy input into formatted structures
2418 *
2419 * These assignments are based on the following logic
2420 * If neither input or mask are set assume value is masked out.
2421 * If input is set, but mask is not mask should default to accept all.
2422 * If input is not set, but mask is set then mask likely results in 0.
2423 * If input is set and mask is set then assign both.
2424 */
2425 if (fs->h_u.tcp_ip4_spec.ip4src || ~fs->m_u.tcp_ip4_spec.ip4src) {
2426 input_struct.formatted.src_ip[0] = fs->h_u.tcp_ip4_spec.ip4src;
2427 if (!fs->m_u.tcp_ip4_spec.ip4src)
2428 input_masks.src_ip_mask[0] = 0xFFFFFFFF;
2429 else
2430 input_masks.src_ip_mask[0] =
2431 ~fs->m_u.tcp_ip4_spec.ip4src;
2432 }
2433 if (fs->h_u.tcp_ip4_spec.ip4dst || ~fs->m_u.tcp_ip4_spec.ip4dst) {
2434 input_struct.formatted.dst_ip[0] = fs->h_u.tcp_ip4_spec.ip4dst;
2435 if (!fs->m_u.tcp_ip4_spec.ip4dst)
2436 input_masks.dst_ip_mask[0] = 0xFFFFFFFF;
2437 else
2438 input_masks.dst_ip_mask[0] =
2439 ~fs->m_u.tcp_ip4_spec.ip4dst;
2440 }
2441 if (fs->h_u.tcp_ip4_spec.psrc || ~fs->m_u.tcp_ip4_spec.psrc) {
2442 input_struct.formatted.src_port = fs->h_u.tcp_ip4_spec.psrc;
2443 if (!fs->m_u.tcp_ip4_spec.psrc)
2444 input_masks.src_port_mask = 0xFFFF;
2445 else
2446 input_masks.src_port_mask = ~fs->m_u.tcp_ip4_spec.psrc;
2447 }
2448 if (fs->h_u.tcp_ip4_spec.pdst || ~fs->m_u.tcp_ip4_spec.pdst) {
2449 input_struct.formatted.dst_port = fs->h_u.tcp_ip4_spec.pdst;
2450 if (!fs->m_u.tcp_ip4_spec.pdst)
2451 input_masks.dst_port_mask = 0xFFFF;
2452 else
2453 input_masks.dst_port_mask = ~fs->m_u.tcp_ip4_spec.pdst;
2454 }
9a713e7c
PW		 2455
2456 /* determine if we need to drop or route the packet */
45b9f509 2457 if (fs->action == ETHTOOL_RXNTUPLE_ACTION_DROP)
9a713e7c
PW		 2458 target_queue = MAX_RX_QUEUES - 1;
2459 else
45b9f509 2460 target_queue = fs->action;
9a713e7c
PW		 2461
2462 spin_lock(&adapter->fdir_perfect_lock);
45b9f509
AD		 2463 err = ixgbe_fdir_add_perfect_filter_82599(&adapter->hw,
2464 &input_struct,
2465 &input_masks, 0,
2466 target_queue);
9a713e7c
PW		 2467 spin_unlock(&adapter->fdir_perfect_lock);
2468
45b9f509 2469 return err ? -1 : 0;
f8212f97 2470}
9a799d71 2471
b9804972 2472static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2473 .get_settings = ixgbe_get_settings,
2474 .set_settings = ixgbe_set_settings,
2475 .get_drvinfo = ixgbe_get_drvinfo,
2476 .get_regs_len = ixgbe_get_regs_len,
2477 .get_regs = ixgbe_get_regs,
2478 .get_wol = ixgbe_get_wol,
e63d9762 2479 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2480 .nway_reset = ixgbe_nway_reset,
2481 .get_link = ethtool_op_get_link,
2482 .get_eeprom_len = ixgbe_get_eeprom_len,
2483 .get_eeprom = ixgbe_get_eeprom,
2484 .get_ringparam = ixgbe_get_ringparam,
2485 .set_ringparam = ixgbe_set_ringparam,
2486 .get_pauseparam = ixgbe_get_pauseparam,
2487 .set_pauseparam = ixgbe_set_pauseparam,
2488 .get_rx_csum = ixgbe_get_rx_csum,
2489 .set_rx_csum = ixgbe_set_rx_csum,
2490 .get_tx_csum = ixgbe_get_tx_csum,
2491 .set_tx_csum = ixgbe_set_tx_csum,
2492 .get_sg = ethtool_op_get_sg,
2493 .set_sg = ethtool_op_set_sg,
2494 .get_msglevel = ixgbe_get_msglevel,
2495 .set_msglevel = ixgbe_set_msglevel,
2496 .get_tso = ethtool_op_get_tso,
2497 .set_tso = ixgbe_set_tso,
da4dd0f7 2498 .self_test = ixgbe_diag_test,
9a799d71 2499 .get_strings = ixgbe_get_strings,
66e6961c 2500 .set_phys_id = ixgbe_set_phys_id,
b4617240 2501 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2502 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2503 .get_coalesce = ixgbe_get_coalesce,
2504 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2505 .get_flags = ethtool_op_get_flags,
f8212f97 2506 .set_flags = ixgbe_set_flags,
9a713e7c 2507 .set_rx_ntuple = ixgbe_set_rx_ntuple,
9a799d71
AK		 2508};
2509
2510void ixgbe_set_ethtool_ops(struct net_device *netdev)
2511{
2512 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2513}
Linux kernel - Deliverables
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