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d3a2ae6d YZ |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a52055e0 | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
d3a2ae6d YZ |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
d3a2ae6d YZ |
28 | #include "ixgbe.h" |
29 | #include <linux/if_ether.h> | |
5a0e3ad6 | 30 | #include <linux/gfp.h> |
be5d507d | 31 | #include <linux/if_vlan.h> |
d3a2ae6d YZ |
32 | #include <scsi/scsi_cmnd.h> |
33 | #include <scsi/scsi_device.h> | |
34 | #include <scsi/fc/fc_fs.h> | |
35 | #include <scsi/fc/fc_fcoe.h> | |
36 | #include <scsi/libfc.h> | |
37 | #include <scsi/libfcoe.h> | |
38 | ||
d0ed8937 YZ |
39 | /** |
40 | * ixgbe_fcoe_clear_ddp - clear the given ddp context | |
41 | * @ddp - ptr to the ixgbe_fcoe_ddp | |
42 | * | |
43 | * Returns : none | |
44 | * | |
45 | */ | |
46 | static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp) | |
47 | { | |
48 | ddp->len = 0; | |
8ca371e4 | 49 | ddp->err = 1; |
d0ed8937 YZ |
50 | ddp->udl = NULL; |
51 | ddp->udp = 0UL; | |
52 | ddp->sgl = NULL; | |
53 | ddp->sgc = 0; | |
54 | } | |
55 | ||
56 | /** | |
57 | * ixgbe_fcoe_ddp_put - free the ddp context for a given xid | |
58 | * @netdev: the corresponding net_device | |
59 | * @xid: the xid that corresponding ddp will be freed | |
60 | * | |
61 | * This is the implementation of net_device_ops.ndo_fcoe_ddp_done | |
62 | * and it is expected to be called by ULD, i.e., FCP layer of libfc | |
63 | * to release the corresponding ddp context when the I/O is done. | |
64 | * | |
65 | * Returns : data length already ddp-ed in bytes | |
66 | */ | |
67 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid) | |
68 | { | |
69 | int len = 0; | |
70 | struct ixgbe_fcoe *fcoe; | |
71 | struct ixgbe_adapter *adapter; | |
72 | struct ixgbe_fcoe_ddp *ddp; | |
9b55bb03 | 73 | u32 fcbuff; |
d0ed8937 YZ |
74 | |
75 | if (!netdev) | |
76 | goto out_ddp_put; | |
77 | ||
78 | if (xid >= IXGBE_FCOE_DDP_MAX) | |
79 | goto out_ddp_put; | |
80 | ||
81 | adapter = netdev_priv(netdev); | |
82 | fcoe = &adapter->fcoe; | |
83 | ddp = &fcoe->ddp[xid]; | |
84 | if (!ddp->udl) | |
85 | goto out_ddp_put; | |
86 | ||
87 | len = ddp->len; | |
88 | /* if there an error, force to invalidate ddp context */ | |
89 | if (ddp->err) { | |
90 | spin_lock_bh(&fcoe->lock); | |
91 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLT, 0); | |
92 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLTRW, | |
93 | (xid | IXGBE_FCFLTRW_WE)); | |
94 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0); | |
95 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW, | |
96 | (xid | IXGBE_FCDMARW_WE)); | |
9b55bb03 YZ |
97 | |
98 | /* guaranteed to be invalidated after 100us */ | |
99 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW, | |
100 | (xid | IXGBE_FCDMARW_RE)); | |
101 | fcbuff = IXGBE_READ_REG(&adapter->hw, IXGBE_FCBUFF); | |
d0ed8937 | 102 | spin_unlock_bh(&fcoe->lock); |
9b55bb03 YZ |
103 | if (fcbuff & IXGBE_FCBUFF_VALID) |
104 | udelay(100); | |
d0ed8937 YZ |
105 | } |
106 | if (ddp->sgl) | |
107 | pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc, | |
108 | DMA_FROM_DEVICE); | |
dadbe85a VD |
109 | if (ddp->pool) { |
110 | pci_pool_free(ddp->pool, ddp->udl, ddp->udp); | |
111 | ddp->pool = NULL; | |
112 | } | |
113 | ||
d0ed8937 YZ |
114 | ixgbe_fcoe_clear_ddp(ddp); |
115 | ||
116 | out_ddp_put: | |
117 | return len; | |
118 | } | |
119 | ||
120 | /** | |
68a683cf | 121 | * ixgbe_fcoe_ddp_setup - called to set up ddp context |
d0ed8937 YZ |
122 | * @netdev: the corresponding net_device |
123 | * @xid: the exchange id requesting ddp | |
124 | * @sgl: the scatter-gather list for this request | |
125 | * @sgc: the number of scatter-gather items | |
126 | * | |
d0ed8937 YZ |
127 | * Returns : 1 for success and 0 for no ddp |
128 | */ | |
68a683cf YZ |
129 | static int ixgbe_fcoe_ddp_setup(struct net_device *netdev, u16 xid, |
130 | struct scatterlist *sgl, unsigned int sgc, | |
131 | int target_mode) | |
d0ed8937 YZ |
132 | { |
133 | struct ixgbe_adapter *adapter; | |
134 | struct ixgbe_hw *hw; | |
135 | struct ixgbe_fcoe *fcoe; | |
136 | struct ixgbe_fcoe_ddp *ddp; | |
137 | struct scatterlist *sg; | |
138 | unsigned int i, j, dmacount; | |
139 | unsigned int len; | |
c600636b | 140 | static const unsigned int bufflen = IXGBE_FCBUFF_MIN; |
d0ed8937 YZ |
141 | unsigned int firstoff = 0; |
142 | unsigned int lastsize; | |
143 | unsigned int thisoff = 0; | |
144 | unsigned int thislen = 0; | |
68a683cf | 145 | u32 fcbuff, fcdmarw, fcfltrw, fcrxctl; |
fbbea32b | 146 | dma_addr_t addr = 0; |
dadbe85a | 147 | struct pci_pool *pool; |
d0ed8937 YZ |
148 | |
149 | if (!netdev || !sgl) | |
150 | return 0; | |
151 | ||
152 | adapter = netdev_priv(netdev); | |
153 | if (xid >= IXGBE_FCOE_DDP_MAX) { | |
396e799c | 154 | e_warn(drv, "xid=0x%x out-of-range\n", xid); |
d0ed8937 YZ |
155 | return 0; |
156 | } | |
157 | ||
a41c0597 YZ |
158 | /* no DDP if we are already down or resetting */ |
159 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
160 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
161 | return 0; | |
162 | ||
d0ed8937 YZ |
163 | fcoe = &adapter->fcoe; |
164 | if (!fcoe->pool) { | |
396e799c | 165 | e_warn(drv, "xid=0x%x no ddp pool for fcoe\n", xid); |
d0ed8937 YZ |
166 | return 0; |
167 | } | |
168 | ||
169 | ddp = &fcoe->ddp[xid]; | |
170 | if (ddp->sgl) { | |
396e799c ET |
171 | e_err(drv, "xid 0x%x w/ non-null sgl=%p nents=%d\n", |
172 | xid, ddp->sgl, ddp->sgc); | |
d0ed8937 YZ |
173 | return 0; |
174 | } | |
175 | ixgbe_fcoe_clear_ddp(ddp); | |
176 | ||
177 | /* setup dma from scsi command sgl */ | |
178 | dmacount = pci_map_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE); | |
179 | if (dmacount == 0) { | |
396e799c | 180 | e_err(drv, "xid 0x%x DMA map error\n", xid); |
d0ed8937 YZ |
181 | return 0; |
182 | } | |
183 | ||
dadbe85a VD |
184 | /* alloc the udl from per cpu ddp pool */ |
185 | pool = *per_cpu_ptr(fcoe->pool, get_cpu()); | |
186 | ddp->udl = pci_pool_alloc(pool, GFP_ATOMIC, &ddp->udp); | |
d0ed8937 | 187 | if (!ddp->udl) { |
396e799c | 188 | e_err(drv, "failed allocated ddp context\n"); |
d0ed8937 YZ |
189 | goto out_noddp_unmap; |
190 | } | |
dadbe85a | 191 | ddp->pool = pool; |
d0ed8937 YZ |
192 | ddp->sgl = sgl; |
193 | ddp->sgc = sgc; | |
194 | ||
195 | j = 0; | |
196 | for_each_sg(sgl, sg, dmacount, i) { | |
197 | addr = sg_dma_address(sg); | |
198 | len = sg_dma_len(sg); | |
199 | while (len) { | |
a7551b75 RL |
200 | /* max number of buffers allowed in one DDP context */ |
201 | if (j >= IXGBE_BUFFCNT_MAX) { | |
396e799c | 202 | e_err(drv, "xid=%x:%d,%d,%d:addr=%llx " |
849c4542 ET |
203 | "not enough descriptors\n", |
204 | xid, i, j, dmacount, (u64)addr); | |
a7551b75 RL |
205 | goto out_noddp_free; |
206 | } | |
207 | ||
d0ed8937 YZ |
208 | /* get the offset of length of current buffer */ |
209 | thisoff = addr & ((dma_addr_t)bufflen - 1); | |
210 | thislen = min((bufflen - thisoff), len); | |
211 | /* | |
212 | * all but the 1st buffer (j == 0) | |
213 | * must be aligned on bufflen | |
214 | */ | |
215 | if ((j != 0) && (thisoff)) | |
216 | goto out_noddp_free; | |
217 | /* | |
218 | * all but the last buffer | |
219 | * ((i == (dmacount - 1)) && (thislen == len)) | |
220 | * must end at bufflen | |
221 | */ | |
222 | if (((i != (dmacount - 1)) || (thislen != len)) | |
223 | && ((thislen + thisoff) != bufflen)) | |
224 | goto out_noddp_free; | |
225 | ||
226 | ddp->udl[j] = (u64)(addr - thisoff); | |
227 | /* only the first buffer may have none-zero offset */ | |
228 | if (j == 0) | |
229 | firstoff = thisoff; | |
230 | len -= thislen; | |
231 | addr += thislen; | |
232 | j++; | |
d0ed8937 YZ |
233 | } |
234 | } | |
235 | /* only the last buffer may have non-full bufflen */ | |
236 | lastsize = thisoff + thislen; | |
237 | ||
c600636b AH |
238 | /* |
239 | * lastsize can not be buffer len. | |
240 | * If it is then adding another buffer with lastsize = 1. | |
241 | */ | |
242 | if (lastsize == bufflen) { | |
243 | if (j >= IXGBE_BUFFCNT_MAX) { | |
244 | e_err(drv, "xid=%x:%d,%d,%d:addr=%llx " | |
245 | "not enough user buffers. We need an extra " | |
246 | "buffer because lastsize is bufflen.\n", | |
247 | xid, i, j, dmacount, (u64)addr); | |
248 | goto out_noddp_free; | |
249 | } | |
250 | ||
251 | ddp->udl[j] = (u64)(fcoe->extra_ddp_buffer_dma); | |
252 | j++; | |
253 | lastsize = 1; | |
254 | } | |
dadbe85a | 255 | put_cpu(); |
c600636b | 256 | |
d0ed8937 | 257 | fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT); |
a7551b75 | 258 | fcbuff |= ((j & 0xff) << IXGBE_FCBUFF_BUFFCNT_SHIFT); |
d0ed8937 | 259 | fcbuff |= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT); |
68a683cf YZ |
260 | /* Set WRCONTX bit to allow DDP for target */ |
261 | if (target_mode) | |
262 | fcbuff |= (IXGBE_FCBUFF_WRCONTX); | |
d0ed8937 YZ |
263 | fcbuff |= (IXGBE_FCBUFF_VALID); |
264 | ||
265 | fcdmarw = xid; | |
266 | fcdmarw |= IXGBE_FCDMARW_WE; | |
267 | fcdmarw |= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT); | |
268 | ||
269 | fcfltrw = xid; | |
270 | fcfltrw |= IXGBE_FCFLTRW_WE; | |
271 | ||
272 | /* program DMA context */ | |
273 | hw = &adapter->hw; | |
274 | spin_lock_bh(&fcoe->lock); | |
68a683cf YZ |
275 | |
276 | /* turn on last frame indication for target mode as FCP_RSPtarget is | |
277 | * supposed to send FCP_RSP when it is done. */ | |
278 | if (target_mode && !test_bit(__IXGBE_FCOE_TARGET, &fcoe->mode)) { | |
279 | set_bit(__IXGBE_FCOE_TARGET, &fcoe->mode); | |
280 | fcrxctl = IXGBE_READ_REG(hw, IXGBE_FCRXCTRL); | |
281 | fcrxctl |= IXGBE_FCRXCTRL_LASTSEQH; | |
282 | IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL, fcrxctl); | |
283 | } | |
284 | ||
8e20ce94 | 285 | IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_BIT_MASK(32)); |
d0ed8937 YZ |
286 | IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32); |
287 | IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff); | |
288 | IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw); | |
289 | /* program filter context */ | |
290 | IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0); | |
291 | IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID); | |
292 | IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw); | |
68a683cf | 293 | |
d0ed8937 YZ |
294 | spin_unlock_bh(&fcoe->lock); |
295 | ||
296 | return 1; | |
297 | ||
298 | out_noddp_free: | |
dadbe85a | 299 | pci_pool_free(pool, ddp->udl, ddp->udp); |
d0ed8937 YZ |
300 | ixgbe_fcoe_clear_ddp(ddp); |
301 | ||
302 | out_noddp_unmap: | |
303 | pci_unmap_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE); | |
dadbe85a | 304 | put_cpu(); |
d0ed8937 YZ |
305 | return 0; |
306 | } | |
307 | ||
68a683cf YZ |
308 | /** |
309 | * ixgbe_fcoe_ddp_get - called to set up ddp context in initiator mode | |
310 | * @netdev: the corresponding net_device | |
311 | * @xid: the exchange id requesting ddp | |
312 | * @sgl: the scatter-gather list for this request | |
313 | * @sgc: the number of scatter-gather items | |
314 | * | |
315 | * This is the implementation of net_device_ops.ndo_fcoe_ddp_setup | |
316 | * and is expected to be called from ULD, e.g., FCP layer of libfc | |
317 | * to set up ddp for the corresponding xid of the given sglist for | |
318 | * the corresponding I/O. | |
319 | * | |
320 | * Returns : 1 for success and 0 for no ddp | |
321 | */ | |
322 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
323 | struct scatterlist *sgl, unsigned int sgc) | |
324 | { | |
325 | return ixgbe_fcoe_ddp_setup(netdev, xid, sgl, sgc, 0); | |
326 | } | |
327 | ||
328 | /** | |
329 | * ixgbe_fcoe_ddp_target - called to set up ddp context in target mode | |
330 | * @netdev: the corresponding net_device | |
331 | * @xid: the exchange id requesting ddp | |
332 | * @sgl: the scatter-gather list for this request | |
333 | * @sgc: the number of scatter-gather items | |
334 | * | |
335 | * This is the implementation of net_device_ops.ndo_fcoe_ddp_target | |
336 | * and is expected to be called from ULD, e.g., FCP layer of libfc | |
337 | * to set up ddp for the corresponding xid of the given sglist for | |
338 | * the corresponding I/O. The DDP in target mode is a write I/O request | |
339 | * from the initiator. | |
340 | * | |
341 | * Returns : 1 for success and 0 for no ddp | |
342 | */ | |
343 | int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, | |
344 | struct scatterlist *sgl, unsigned int sgc) | |
345 | { | |
346 | return ixgbe_fcoe_ddp_setup(netdev, xid, sgl, sgc, 1); | |
347 | } | |
348 | ||
d0ed8937 YZ |
349 | /** |
350 | * ixgbe_fcoe_ddp - check ddp status and mark it done | |
351 | * @adapter: ixgbe adapter | |
352 | * @rx_desc: advanced rx descriptor | |
353 | * @skb: the skb holding the received data | |
354 | * | |
355 | * This checks ddp status. | |
356 | * | |
3d8fd385 YZ |
357 | * Returns : < 0 indicates an error or not a FCiE ddp, 0 indicates |
358 | * not passing the skb to ULD, > 0 indicates is the length of data | |
359 | * being ddped. | |
d0ed8937 YZ |
360 | */ |
361 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
362 | union ixgbe_adv_rx_desc *rx_desc, | |
ff886dfc AD |
363 | struct sk_buff *skb, |
364 | u32 staterr) | |
d0ed8937 YZ |
365 | { |
366 | u16 xid; | |
d4ab8819 | 367 | u32 fctl; |
ff886dfc | 368 | u32 fceofe, fcerr, fcstat; |
d0ed8937 YZ |
369 | int rc = -EINVAL; |
370 | struct ixgbe_fcoe *fcoe; | |
371 | struct ixgbe_fcoe_ddp *ddp; | |
372 | struct fc_frame_header *fh; | |
68a683cf | 373 | struct fcoe_crc_eof *crc; |
d0ed8937 | 374 | |
ff886dfc AD |
375 | fcerr = (staterr & IXGBE_RXDADV_ERR_FCERR); |
376 | fceofe = (staterr & IXGBE_RXDADV_ERR_FCEOFE); | |
d0ed8937 | 377 | if (fcerr == IXGBE_FCERR_BADCRC) |
bc8acf2c ED |
378 | skb_checksum_none_assert(skb); |
379 | else | |
380 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
d0ed8937 | 381 | |
be5d507d YZ |
382 | if (eth_hdr(skb)->h_proto == htons(ETH_P_8021Q)) |
383 | fh = (struct fc_frame_header *)(skb->data + | |
384 | sizeof(struct vlan_hdr) + sizeof(struct fcoe_hdr)); | |
385 | else | |
386 | fh = (struct fc_frame_header *)(skb->data + | |
387 | sizeof(struct fcoe_hdr)); | |
d4ab8819 YZ |
388 | fctl = ntoh24(fh->fh_f_ctl); |
389 | if (fctl & FC_FC_EX_CTX) | |
390 | xid = be16_to_cpu(fh->fh_ox_id); | |
391 | else | |
392 | xid = be16_to_cpu(fh->fh_rx_id); | |
393 | ||
d0ed8937 YZ |
394 | if (xid >= IXGBE_FCOE_DDP_MAX) |
395 | goto ddp_out; | |
396 | ||
397 | fcoe = &adapter->fcoe; | |
398 | ddp = &fcoe->ddp[xid]; | |
399 | if (!ddp->udl) | |
400 | goto ddp_out; | |
401 | ||
7aba7b07 | 402 | if (fcerr | fceofe) |
d0ed8937 YZ |
403 | goto ddp_out; |
404 | ||
ff886dfc | 405 | fcstat = (staterr & IXGBE_RXDADV_STAT_FCSTAT); |
d0ed8937 YZ |
406 | if (fcstat) { |
407 | /* update length of DDPed data */ | |
408 | ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
409 | /* unmap the sg list when FCP_RSP is received */ | |
410 | if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_FCPRSP) { | |
411 | pci_unmap_sg(adapter->pdev, ddp->sgl, | |
412 | ddp->sgc, DMA_FROM_DEVICE); | |
7aba7b07 | 413 | ddp->err = (fcerr | fceofe); |
d0ed8937 YZ |
414 | ddp->sgl = NULL; |
415 | ddp->sgc = 0; | |
416 | } | |
417 | /* return 0 to bypass going to ULD for DDPed data */ | |
418 | if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP) | |
419 | rc = 0; | |
17e78b06 | 420 | else if (ddp->len) |
3d8fd385 | 421 | rc = ddp->len; |
d0ed8937 | 422 | } |
68a683cf YZ |
423 | /* In target mode, check the last data frame of the sequence. |
424 | * For DDP in target mode, data is already DDPed but the header | |
425 | * indication of the last data frame ould allow is to tell if we | |
426 | * got all the data and the ULP can send FCP_RSP back, as this is | |
427 | * not a full fcoe frame, we fill the trailer here so it won't be | |
428 | * dropped by the ULP stack. | |
429 | */ | |
430 | if ((fh->fh_r_ctl == FC_RCTL_DD_SOL_DATA) && | |
431 | (fctl & FC_FC_END_SEQ)) { | |
432 | crc = (struct fcoe_crc_eof *)skb_put(skb, sizeof(*crc)); | |
433 | crc->fcoe_eof = FC_EOF_T; | |
434 | } | |
d0ed8937 YZ |
435 | ddp_out: |
436 | return rc; | |
437 | } | |
438 | ||
bc079228 YZ |
439 | /** |
440 | * ixgbe_fso - ixgbe FCoE Sequence Offload (FSO) | |
441 | * @adapter: ixgbe adapter | |
442 | * @tx_ring: tx desc ring | |
443 | * @skb: associated skb | |
444 | * @tx_flags: tx flags | |
445 | * @hdr_len: hdr_len to be returned | |
446 | * | |
447 | * This sets up large send offload for FCoE | |
448 | * | |
449 | * Returns : 0 indicates no FSO, > 0 for FSO, < 0 for error | |
450 | */ | |
897ab156 | 451 | int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
bc079228 YZ |
452 | u32 tx_flags, u8 *hdr_len) |
453 | { | |
897ab156 | 454 | struct fc_frame_header *fh; |
bc079228 | 455 | u32 vlan_macip_lens; |
897ab156 | 456 | u32 fcoe_sof_eof = 0; |
bc079228 | 457 | u32 mss_l4len_idx; |
897ab156 | 458 | u8 sof, eof; |
bc079228 YZ |
459 | |
460 | if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) { | |
897ab156 AD |
461 | dev_err(tx_ring->dev, "Wrong gso type %d:expecting SKB_GSO_FCOE\n", |
462 | skb_shinfo(skb)->gso_type); | |
bc079228 YZ |
463 | return -EINVAL; |
464 | } | |
465 | ||
466 | /* resets the header to point fcoe/fc */ | |
467 | skb_set_network_header(skb, skb->mac_len); | |
468 | skb_set_transport_header(skb, skb->mac_len + | |
469 | sizeof(struct fcoe_hdr)); | |
470 | ||
471 | /* sets up SOF and ORIS */ | |
bc079228 YZ |
472 | sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof; |
473 | switch (sof) { | |
474 | case FC_SOF_I2: | |
897ab156 | 475 | fcoe_sof_eof = IXGBE_ADVTXD_FCOEF_ORIS; |
bc079228 YZ |
476 | break; |
477 | case FC_SOF_I3: | |
897ab156 AD |
478 | fcoe_sof_eof = IXGBE_ADVTXD_FCOEF_SOF | |
479 | IXGBE_ADVTXD_FCOEF_ORIS; | |
bc079228 YZ |
480 | break; |
481 | case FC_SOF_N2: | |
482 | break; | |
483 | case FC_SOF_N3: | |
897ab156 | 484 | fcoe_sof_eof = IXGBE_ADVTXD_FCOEF_SOF; |
bc079228 YZ |
485 | break; |
486 | default: | |
897ab156 | 487 | dev_warn(tx_ring->dev, "unknown sof = 0x%x\n", sof); |
bc079228 YZ |
488 | return -EINVAL; |
489 | } | |
490 | ||
491 | /* the first byte of the last dword is EOF */ | |
492 | skb_copy_bits(skb, skb->len - 4, &eof, 1); | |
493 | /* sets up EOF and ORIE */ | |
494 | switch (eof) { | |
495 | case FC_EOF_N: | |
496 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N; | |
497 | break; | |
498 | case FC_EOF_T: | |
499 | /* lso needs ORIE */ | |
897ab156 AD |
500 | if (skb_is_gso(skb)) |
501 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N | | |
502 | IXGBE_ADVTXD_FCOEF_ORIE; | |
503 | else | |
bc079228 | 504 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_T; |
bc079228 YZ |
505 | break; |
506 | case FC_EOF_NI: | |
507 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_NI; | |
508 | break; | |
509 | case FC_EOF_A: | |
510 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_A; | |
511 | break; | |
512 | default: | |
897ab156 | 513 | dev_warn(tx_ring->dev, "unknown eof = 0x%x\n", eof); |
bc079228 YZ |
514 | return -EINVAL; |
515 | } | |
516 | ||
517 | /* sets up PARINC indicating data offset */ | |
518 | fh = (struct fc_frame_header *)skb_transport_header(skb); | |
519 | if (fh->fh_f_ctl[2] & FC_FC_REL_OFF) | |
520 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_PARINC; | |
521 | ||
897ab156 | 522 | /* include trailer in headlen as it is replicated per frame */ |
bc079228 | 523 | *hdr_len = sizeof(struct fcoe_crc_eof); |
897ab156 AD |
524 | |
525 | /* hdr_len includes fc_hdr if FCoE LSO is enabled */ | |
bc079228 YZ |
526 | if (skb_is_gso(skb)) |
527 | *hdr_len += (skb_transport_offset(skb) + | |
528 | sizeof(struct fc_frame_header)); | |
897ab156 | 529 | |
bc079228 | 530 | /* mss_l4len_id: use 1 for FSO as TSO, no need for L4LEN */ |
897ab156 AD |
531 | mss_l4len_idx = skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; |
532 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
533 | ||
534 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
535 | vlan_macip_lens = skb_transport_offset(skb) + | |
536 | sizeof(struct fc_frame_header); | |
537 | vlan_macip_lens |= (skb_transport_offset(skb) - 4) | |
538 | << IXGBE_ADVTXD_MACLEN_SHIFT; | |
539 | vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; | |
bc079228 YZ |
540 | |
541 | /* write context desc */ | |
897ab156 AD |
542 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fcoe_sof_eof, |
543 | IXGBE_ADVTXT_TUCMD_FCOE, mss_l4len_idx); | |
bc079228 YZ |
544 | |
545 | return skb_is_gso(skb); | |
546 | } | |
547 | ||
dadbe85a VD |
548 | static void ixgbe_fcoe_ddp_pools_free(struct ixgbe_fcoe *fcoe) |
549 | { | |
550 | unsigned int cpu; | |
551 | struct pci_pool **pool; | |
552 | ||
553 | for_each_possible_cpu(cpu) { | |
554 | pool = per_cpu_ptr(fcoe->pool, cpu); | |
555 | if (*pool) | |
556 | pci_pool_destroy(*pool); | |
557 | } | |
558 | free_percpu(fcoe->pool); | |
559 | fcoe->pool = NULL; | |
560 | } | |
561 | ||
562 | static void ixgbe_fcoe_ddp_pools_alloc(struct ixgbe_adapter *adapter) | |
563 | { | |
564 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
565 | unsigned int cpu; | |
566 | struct pci_pool **pool; | |
567 | char pool_name[32]; | |
568 | ||
569 | fcoe->pool = alloc_percpu(struct pci_pool *); | |
570 | if (!fcoe->pool) | |
571 | return; | |
572 | ||
573 | /* allocate pci pool for each cpu */ | |
574 | for_each_possible_cpu(cpu) { | |
575 | snprintf(pool_name, 32, "ixgbe_fcoe_ddp_%d", cpu); | |
576 | pool = per_cpu_ptr(fcoe->pool, cpu); | |
577 | *pool = pci_pool_create(pool_name, | |
578 | adapter->pdev, IXGBE_FCPTR_MAX, | |
579 | IXGBE_FCPTR_ALIGN, PAGE_SIZE); | |
580 | if (!*pool) { | |
581 | e_err(drv, "failed to alloc DDP pool on cpu:%d\n", cpu); | |
582 | ixgbe_fcoe_ddp_pools_free(fcoe); | |
583 | return; | |
584 | } | |
585 | } | |
586 | } | |
587 | ||
d3a2ae6d YZ |
588 | /** |
589 | * ixgbe_configure_fcoe - configures registers for fcoe at start | |
590 | * @adapter: ptr to ixgbe adapter | |
591 | * | |
592 | * This sets up FCoE related registers | |
593 | * | |
594 | * Returns : none | |
595 | */ | |
596 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter) | |
597 | { | |
29ebf6f8 | 598 | int i, fcoe_q, fcoe_i; |
d3a2ae6d | 599 | struct ixgbe_hw *hw = &adapter->hw; |
d0ed8937 | 600 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
29ebf6f8 | 601 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
d0ed8937 | 602 | |
d0ed8937 | 603 | if (!fcoe->pool) { |
d0ed8937 | 604 | spin_lock_init(&fcoe->lock); |
c600636b | 605 | |
dadbe85a VD |
606 | ixgbe_fcoe_ddp_pools_alloc(adapter); |
607 | if (!fcoe->pool) { | |
608 | e_err(drv, "failed to alloc percpu fcoe DDP pools\n"); | |
609 | return; | |
610 | } | |
611 | ||
c600636b AH |
612 | /* Extra buffer to be shared by all DDPs for HW work around */ |
613 | fcoe->extra_ddp_buffer = kmalloc(IXGBE_FCBUFF_MIN, GFP_ATOMIC); | |
614 | if (fcoe->extra_ddp_buffer == NULL) { | |
615 | e_err(drv, "failed to allocated extra DDP buffer\n"); | |
dadbe85a | 616 | goto out_ddp_pools; |
c600636b AH |
617 | } |
618 | ||
619 | fcoe->extra_ddp_buffer_dma = | |
620 | dma_map_single(&adapter->pdev->dev, | |
621 | fcoe->extra_ddp_buffer, | |
622 | IXGBE_FCBUFF_MIN, | |
623 | DMA_FROM_DEVICE); | |
624 | if (dma_mapping_error(&adapter->pdev->dev, | |
625 | fcoe->extra_ddp_buffer_dma)) { | |
626 | e_err(drv, "failed to map extra DDP buffer\n"); | |
dadbe85a | 627 | goto out_extra_ddp_buffer; |
c600636b | 628 | } |
d0ed8937 | 629 | } |
29ebf6f8 YZ |
630 | |
631 | /* Enable L2 eth type filter for FCoE */ | |
d3a2ae6d YZ |
632 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE), |
633 | (ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN)); | |
af06393b CL |
634 | /* Enable L2 eth type filter for FIP */ |
635 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FIP), | |
636 | (ETH_P_FIP | IXGBE_ETQF_FILTER_EN)); | |
29ebf6f8 YZ |
637 | if (adapter->ring_feature[RING_F_FCOE].indices) { |
638 | /* Use multiple rx queues for FCoE by redirection table */ | |
639 | for (i = 0; i < IXGBE_FCRETA_SIZE; i++) { | |
640 | fcoe_i = f->mask + i % f->indices; | |
641 | fcoe_i &= IXGBE_FCRETA_ENTRY_MASK; | |
4a0b9ca0 | 642 | fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx; |
29ebf6f8 YZ |
643 | IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q); |
644 | } | |
645 | IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA); | |
646 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0); | |
647 | } else { | |
648 | /* Use single rx queue for FCoE */ | |
649 | fcoe_i = f->mask; | |
4a0b9ca0 | 650 | fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx; |
29ebf6f8 YZ |
651 | IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0); |
652 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), | |
653 | IXGBE_ETQS_QUEUE_EN | | |
654 | (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT)); | |
655 | } | |
af06393b CL |
656 | /* send FIP frames to the first FCoE queue */ |
657 | fcoe_i = f->mask; | |
658 | fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx; | |
659 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FIP), | |
660 | IXGBE_ETQS_QUEUE_EN | | |
661 | (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT)); | |
29ebf6f8 | 662 | |
d3a2ae6d YZ |
663 | IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL, |
664 | IXGBE_FCRXCTRL_FCOELLI | | |
665 | IXGBE_FCRXCTRL_FCCRCBO | | |
666 | (FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT)); | |
c600636b AH |
667 | return; |
668 | ||
dadbe85a | 669 | out_extra_ddp_buffer: |
c600636b | 670 | kfree(fcoe->extra_ddp_buffer); |
dadbe85a VD |
671 | out_ddp_pools: |
672 | ixgbe_fcoe_ddp_pools_free(fcoe); | |
d3a2ae6d | 673 | } |
d0ed8937 YZ |
674 | |
675 | /** | |
676 | * ixgbe_cleanup_fcoe - release all fcoe ddp context resources | |
677 | * @adapter : ixgbe adapter | |
678 | * | |
679 | * Cleans up outstanding ddp context resources | |
680 | * | |
681 | * Returns : none | |
682 | */ | |
683 | void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter) | |
684 | { | |
685 | int i; | |
686 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
687 | ||
dadbe85a VD |
688 | if (!fcoe->pool) |
689 | return; | |
690 | ||
691 | for (i = 0; i < IXGBE_FCOE_DDP_MAX; i++) | |
692 | ixgbe_fcoe_ddp_put(adapter->netdev, i); | |
693 | dma_unmap_single(&adapter->pdev->dev, | |
694 | fcoe->extra_ddp_buffer_dma, | |
695 | IXGBE_FCBUFF_MIN, | |
696 | DMA_FROM_DEVICE); | |
697 | kfree(fcoe->extra_ddp_buffer); | |
698 | ixgbe_fcoe_ddp_pools_free(fcoe); | |
d0ed8937 | 699 | } |
8450ff8c YZ |
700 | |
701 | /** | |
702 | * ixgbe_fcoe_enable - turn on FCoE offload feature | |
703 | * @netdev: the corresponding netdev | |
704 | * | |
705 | * Turns on FCoE offload feature in 82599. | |
706 | * | |
707 | * Returns : 0 indicates success or -EINVAL on failure | |
708 | */ | |
709 | int ixgbe_fcoe_enable(struct net_device *netdev) | |
710 | { | |
711 | int rc = -EINVAL; | |
712 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
27ab7606 | 713 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
8450ff8c YZ |
714 | |
715 | ||
716 | if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE)) | |
717 | goto out_enable; | |
718 | ||
27ab7606 | 719 | atomic_inc(&fcoe->refcnt); |
8450ff8c YZ |
720 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) |
721 | goto out_enable; | |
722 | ||
396e799c | 723 | e_info(drv, "Enabling FCoE offload features.\n"); |
8450ff8c YZ |
724 | if (netif_running(netdev)) |
725 | netdev->netdev_ops->ndo_stop(netdev); | |
726 | ||
727 | ixgbe_clear_interrupt_scheme(adapter); | |
728 | ||
729 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | |
730 | adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE; | |
731 | netdev->features |= NETIF_F_FCOE_CRC; | |
732 | netdev->features |= NETIF_F_FSO; | |
733 | netdev->features |= NETIF_F_FCOE_MTU; | |
8450ff8c | 734 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; |
8450ff8c YZ |
735 | |
736 | ixgbe_init_interrupt_scheme(adapter); | |
936332b8 | 737 | netdev_features_change(netdev); |
8450ff8c YZ |
738 | |
739 | if (netif_running(netdev)) | |
740 | netdev->netdev_ops->ndo_open(netdev); | |
741 | rc = 0; | |
742 | ||
743 | out_enable: | |
744 | return rc; | |
745 | } | |
746 | ||
747 | /** | |
748 | * ixgbe_fcoe_disable - turn off FCoE offload feature | |
749 | * @netdev: the corresponding netdev | |
750 | * | |
751 | * Turns off FCoE offload feature in 82599. | |
752 | * | |
753 | * Returns : 0 indicates success or -EINVAL on failure | |
754 | */ | |
755 | int ixgbe_fcoe_disable(struct net_device *netdev) | |
756 | { | |
757 | int rc = -EINVAL; | |
758 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
27ab7606 | 759 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
8450ff8c YZ |
760 | |
761 | if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE)) | |
762 | goto out_disable; | |
763 | ||
764 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
765 | goto out_disable; | |
27ab7606 YZ |
766 | |
767 | if (!atomic_dec_and_test(&fcoe->refcnt)) | |
768 | goto out_disable; | |
8450ff8c | 769 | |
396e799c | 770 | e_info(drv, "Disabling FCoE offload features.\n"); |
5e09d7f6 YZ |
771 | netdev->features &= ~NETIF_F_FCOE_CRC; |
772 | netdev->features &= ~NETIF_F_FSO; | |
773 | netdev->features &= ~NETIF_F_FCOE_MTU; | |
774 | netdev->fcoe_ddp_xid = 0; | |
775 | netdev_features_change(netdev); | |
776 | ||
8450ff8c YZ |
777 | if (netif_running(netdev)) |
778 | netdev->netdev_ops->ndo_stop(netdev); | |
779 | ||
780 | ixgbe_clear_interrupt_scheme(adapter); | |
8450ff8c YZ |
781 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; |
782 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
8450ff8c | 783 | ixgbe_cleanup_fcoe(adapter); |
8450ff8c | 784 | ixgbe_init_interrupt_scheme(adapter); |
936332b8 | 785 | |
8450ff8c YZ |
786 | if (netif_running(netdev)) |
787 | netdev->netdev_ops->ndo_open(netdev); | |
788 | rc = 0; | |
789 | ||
790 | out_disable: | |
791 | return rc; | |
792 | } | |
6ee16520 | 793 | |
61a1fa10 YZ |
794 | /** |
795 | * ixgbe_fcoe_get_wwn - get world wide name for the node or the port | |
796 | * @netdev : ixgbe adapter | |
797 | * @wwn : the world wide name | |
798 | * @type: the type of world wide name | |
799 | * | |
800 | * Returns the node or port world wide name if both the prefix and the san | |
801 | * mac address are valid, then the wwn is formed based on the NAA-2 for | |
802 | * IEEE Extended name identifier (ref. to T10 FC-LS Spec., Sec. 15.3). | |
803 | * | |
804 | * Returns : 0 on success | |
805 | */ | |
806 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type) | |
807 | { | |
808 | int rc = -EINVAL; | |
809 | u16 prefix = 0xffff; | |
810 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
811 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
812 | ||
813 | switch (type) { | |
814 | case NETDEV_FCOE_WWNN: | |
815 | prefix = mac->wwnn_prefix; | |
816 | break; | |
817 | case NETDEV_FCOE_WWPN: | |
818 | prefix = mac->wwpn_prefix; | |
819 | break; | |
820 | default: | |
821 | break; | |
822 | } | |
823 | ||
824 | if ((prefix != 0xffff) && | |
825 | is_valid_ether_addr(mac->san_addr)) { | |
826 | *wwn = ((u64) prefix << 48) | | |
827 | ((u64) mac->san_addr[0] << 40) | | |
828 | ((u64) mac->san_addr[1] << 32) | | |
829 | ((u64) mac->san_addr[2] << 24) | | |
830 | ((u64) mac->san_addr[3] << 16) | | |
831 | ((u64) mac->san_addr[4] << 8) | | |
832 | ((u64) mac->san_addr[5]); | |
833 | rc = 0; | |
834 | } | |
835 | return rc; | |
836 | } |