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cdc_ncm: fix endianness problem.
[deliverable/linux.git] / drivers / net / macb.c
CommitLineData
89e5785f
HS		 1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/slab.h>
17#include <linux/init.h>
a6b7a407 18#include <linux/interrupt.h>
89e5785f
HS		 19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
89e5785f 21#include <linux/dma-mapping.h>
89e5785f 22#include <linux/platform_device.h>
6c36a707 23#include <linux/phy.h>
89e5785f 24
a09e64fb
RK		 25#include <mach/board.h>
26#include <mach/cpu.h>
89e5785f
HS		 27
28#include "macb.h"
29
89e5785f
HS		 30#define RX_BUFFER_SIZE 128
31#define RX_RING_SIZE 512
32#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
33
34/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
35#define RX_OFFSET 2
36
37#define TX_RING_SIZE 128
38#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
39#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
40
41#define TX_RING_GAP(bp) \
42 (TX_RING_SIZE - (bp)->tx_pending)
43#define TX_BUFFS_AVAIL(bp) \
44 (((bp)->tx_tail <= (bp)->tx_head) ? \
45 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
46 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
47#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
48
49#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
50
51/* minimum number of free TX descriptors before waking up TX process */
52#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
53
54#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
55 | MACB_BIT(ISR_ROVR))
56
57static void __macb_set_hwaddr(struct macb *bp)
58{
59 u32 bottom;
60 u16 top;
61
62 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
63 macb_writel(bp, SA1B, bottom);
64 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
65 macb_writel(bp, SA1T, top);
66}
67
68static void __init macb_get_hwaddr(struct macb *bp)
69{
70 u32 bottom;
71 u16 top;
72 u8 addr[6];
73
74 bottom = macb_readl(bp, SA1B);
75 top = macb_readl(bp, SA1T);
76
77 addr[0] = bottom & 0xff;
78 addr[1] = (bottom >> 8) & 0xff;
79 addr[2] = (bottom >> 16) & 0xff;
80 addr[3] = (bottom >> 24) & 0xff;
81 addr[4] = top & 0xff;
82 addr[5] = (top >> 8) & 0xff;
83
d1d5741d 84 if (is_valid_ether_addr(addr)) {
89e5785f 85 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
d1d5741d
SS		 86 } else {
87 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
88 random_ether_addr(bp->dev->dev_addr);
89 }
89e5785f
HS		 90}
91
6c36a707 92static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 93{
6c36a707 94 struct macb *bp = bus->priv;
89e5785f
HS		 95 int value;
96
89e5785f
HS		 97 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
98 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 99 | MACB_BF(PHYA, mii_id)
100 | MACB_BF(REGA, regnum)
89e5785f
HS		 101 | MACB_BF(CODE, MACB_MAN_CODE)));
102
6c36a707
R		 103 /* wait for end of transfer */
104 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
105 cpu_relax();
89e5785f
HS		 106
107 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 108
109 return value;
110}
111
6c36a707
R		 112static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
113 u16 value)
89e5785f 114{
6c36a707 115 struct macb *bp = bus->priv;
89e5785f
HS		 116
117 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
118 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 119 | MACB_BF(PHYA, mii_id)
120 | MACB_BF(REGA, regnum)
89e5785f 121 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 122 | MACB_BF(DATA, value)));
89e5785f 123
6c36a707
R		 124 /* wait for end of transfer */
125 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
126 cpu_relax();
127
128 return 0;
129}
89e5785f 130
6c36a707
R		 131static int macb_mdio_reset(struct mii_bus *bus)
132{
133 return 0;
89e5785f
HS		 134}
135
6c36a707 136static void macb_handle_link_change(struct net_device *dev)
89e5785f 137{
6c36a707
R		 138 struct macb *bp = netdev_priv(dev);
139 struct phy_device *phydev = bp->phy_dev;
140 unsigned long flags;
89e5785f 141
6c36a707 142 int status_change = 0;
89e5785f 143
6c36a707
R		 144 spin_lock_irqsave(&bp->lock, flags);
145
146 if (phydev->link) {
147 if ((bp->speed != phydev->speed) ||
148 (bp->duplex != phydev->duplex)) {
149 u32 reg;
150
151 reg = macb_readl(bp, NCFGR);
152 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
153
154 if (phydev->duplex)
155 reg |= MACB_BIT(FD);
179956f4 156 if (phydev->speed == SPEED_100)
6c36a707
R		 157 reg |= MACB_BIT(SPD);
158
159 macb_writel(bp, NCFGR, reg);
160
161 bp->speed = phydev->speed;
162 bp->duplex = phydev->duplex;
163 status_change = 1;
164 }
89e5785f
HS		 165 }
166
6c36a707 167 if (phydev->link != bp->link) {
c8f15686 168 if (!phydev->link) {
6c36a707
R		 169 bp->speed = 0;
170 bp->duplex = -1;
171 }
172 bp->link = phydev->link;
89e5785f 173
6c36a707
R		 174 status_change = 1;
175 }
89e5785f 176
6c36a707
R		 177 spin_unlock_irqrestore(&bp->lock, flags);
178
179 if (status_change) {
180 if (phydev->link)
181 printk(KERN_INFO "%s: link up (%d/%s)\n",
182 dev->name, phydev->speed,
183 DUPLEX_FULL == phydev->duplex ? "Full":"Half");
184 else
185 printk(KERN_INFO "%s: link down\n", dev->name);
186 }
89e5785f
HS		 187}
188
6c36a707
R		 189/* based on au1000_eth. c*/
190static int macb_mii_probe(struct net_device *dev)
89e5785f 191{
6c36a707 192 struct macb *bp = netdev_priv(dev);
7455a76f 193 struct phy_device *phydev;
6c36a707 194 struct eth_platform_data *pdata;
7455a76f 195 int ret;
6c36a707 196
7455a76f 197 phydev = phy_find_first(bp->mii_bus);
6c36a707
R		 198 if (!phydev) {
199 printk (KERN_ERR "%s: no PHY found\n", dev->name);
200 return -1;
201 }
202
203 pdata = bp->pdev->dev.platform_data;
204 /* TODO : add pin_irq */
205
206 /* attach the mac to the phy */
7455a76f
JP		 207 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
208 pdata && pdata->is_rmii ?
209 PHY_INTERFACE_MODE_RMII :
210 PHY_INTERFACE_MODE_MII);
211 if (ret) {
6c36a707 212 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
7455a76f 213 return ret;
6c36a707
R		 214 }
215
216 /* mask with MAC supported features */
217 phydev->supported &= PHY_BASIC_FEATURES;
218
219 phydev->advertising = phydev->supported;
220
221 bp->link = 0;
222 bp->speed = 0;
223 bp->duplex = -1;
224 bp->phy_dev = phydev;
225
226 return 0;
89e5785f
HS		 227}
228
6c36a707 229static int macb_mii_init(struct macb *bp)
89e5785f 230{
6c36a707
R		 231 struct eth_platform_data *pdata;
232 int err = -ENXIO, i;
89e5785f 233
3dbda77e 234 /* Enable management port */
6c36a707 235 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 236
298cf9be
LB		 237 bp->mii_bus = mdiobus_alloc();
238 if (bp->mii_bus == NULL) {
239 err = -ENOMEM;
240 goto err_out;
241 }
242
243 bp->mii_bus->name = "MACB_mii_bus";
244 bp->mii_bus->read = &macb_mdio_read;
245 bp->mii_bus->write = &macb_mdio_write;
246 bp->mii_bus->reset = &macb_mdio_reset;
247 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
248 bp->mii_bus->priv = bp;
249 bp->mii_bus->parent = &bp->dev->dev;
6c36a707 250 pdata = bp->pdev->dev.platform_data;
89e5785f 251
6c36a707 252 if (pdata)
298cf9be 253 bp->mii_bus->phy_mask = pdata->phy_mask;
89e5785f 254
298cf9be
LB		 255 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
256 if (!bp->mii_bus->irq) {
6c36a707 257 err = -ENOMEM;
298cf9be 258 goto err_out_free_mdiobus;
89e5785f
HS		 259 }
260
6c36a707 261 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 262 bp->mii_bus->irq[i] = PHY_POLL;
89e5785f 263
91523947 264 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 265
298cf9be 266 if (mdiobus_register(bp->mii_bus))
6c36a707 267 goto err_out_free_mdio_irq;
89e5785f 268
6c36a707
R		 269 if (macb_mii_probe(bp->dev) != 0) {
270 goto err_out_unregister_bus;
271 }
89e5785f 272
6c36a707 273 return 0;
89e5785f 274
6c36a707 275err_out_unregister_bus:
298cf9be 276 mdiobus_unregister(bp->mii_bus);
6c36a707 277err_out_free_mdio_irq:
298cf9be
LB		 278 kfree(bp->mii_bus->irq);
279err_out_free_mdiobus:
280 mdiobus_free(bp->mii_bus);
6c36a707
R		 281err_out:
282 return err;
89e5785f
HS		 283}
284
285static void macb_update_stats(struct macb *bp)
286{
287 u32 __iomem *reg = bp->regs + MACB_PFR;
288 u32 *p = &bp->hw_stats.rx_pause_frames;
289 u32 *end = &bp->hw_stats.tx_pause_frames + 1;
290
291 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
292
293 for(; p < end; p++, reg++)
0f0d84e5 294 *p += __raw_readl(reg);
89e5785f
HS		 295}
296
89e5785f
HS		 297static void macb_tx(struct macb *bp)
298{
299 unsigned int tail;
300 unsigned int head;
301 u32 status;
302
303 status = macb_readl(bp, TSR);
304 macb_writel(bp, TSR, status);
305
306 dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
307 (unsigned long)status);
308
ee33c585 309 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
bdcba151 310 int i;
ee33c585
EW		 311 printk(KERN_ERR "%s: TX %s, resetting buffers\n",
312 bp->dev->name, status & MACB_BIT(UND) ?
313 "underrun" : "retry limit exceeded");
bdcba151 314
39eddb4c
RR		 315 /* Transfer ongoing, disable transmitter, to avoid confusion */
316 if (status & MACB_BIT(TGO))
317 macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
318
bdcba151
GC		 319 head = bp->tx_head;
320
321 /*Mark all the buffer as used to avoid sending a lost buffer*/
322 for (i = 0; i < TX_RING_SIZE; i++)
323 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
324
325 /* free transmit buffer in upper layer*/
326 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
327 struct ring_info *rp = &bp->tx_skb[tail];
328 struct sk_buff *skb = rp->skb;
329
330 BUG_ON(skb == NULL);
331
332 rmb();
333
334 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
335 DMA_TO_DEVICE);
336 rp->skb = NULL;
337 dev_kfree_skb_irq(skb);
338 }
339
89e5785f 340 bp->tx_head = bp->tx_tail = 0;
39eddb4c
RR		 341
342 /* Enable the transmitter again */
343 if (status & MACB_BIT(TGO))
344 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
89e5785f
HS		 345 }
346
347 if (!(status & MACB_BIT(COMP)))
348 /*
349 * This may happen when a buffer becomes complete
350 * between reading the ISR and scanning the
351 * descriptors. Nothing to worry about.
352 */
353 return;
354
355 head = bp->tx_head;
356 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
357 struct ring_info *rp = &bp->tx_skb[tail];
358 struct sk_buff *skb = rp->skb;
359 u32 bufstat;
360
361 BUG_ON(skb == NULL);
362
363 rmb();
364 bufstat = bp->tx_ring[tail].ctrl;
365
366 if (!(bufstat & MACB_BIT(TX_USED)))
367 break;
368
369 dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
370 tail, skb->data);
371 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
372 DMA_TO_DEVICE);
373 bp->stats.tx_packets++;
374 bp->stats.tx_bytes += skb->len;
375 rp->skb = NULL;
376 dev_kfree_skb_irq(skb);
377 }
378
379 bp->tx_tail = tail;
380 if (netif_queue_stopped(bp->dev) &&
381 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
382 netif_wake_queue(bp->dev);
383}
384
385static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
386 unsigned int last_frag)
387{
388 unsigned int len;
389 unsigned int frag;
390 unsigned int offset = 0;
391 struct sk_buff *skb;
392
393 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
394
395 dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
396 first_frag, last_frag, len);
397
398 skb = dev_alloc_skb(len + RX_OFFSET);
399 if (!skb) {
400 bp->stats.rx_dropped++;
401 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
402 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
403 if (frag == last_frag)
404 break;
405 }
406 wmb();
407 return 1;
408 }
409
410 skb_reserve(skb, RX_OFFSET);
bc8acf2c 411 skb_checksum_none_assert(skb);
89e5785f
HS		 412 skb_put(skb, len);
413
414 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
415 unsigned int frag_len = RX_BUFFER_SIZE;
416
417 if (offset + frag_len > len) {
418 BUG_ON(frag != last_frag);
419 frag_len = len - offset;
420 }
27d7ff46
ACM		 421 skb_copy_to_linear_data_offset(skb, offset,
422 (bp->rx_buffers +
423 (RX_BUFFER_SIZE * frag)),
424 frag_len);
89e5785f
HS		 425 offset += RX_BUFFER_SIZE;
426 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
427 wmb();
428
429 if (frag == last_frag)
430 break;
431 }
432
433 skb->protocol = eth_type_trans(skb, bp->dev);
434
435 bp->stats.rx_packets++;
436 bp->stats.rx_bytes += len;
89e5785f
HS		 437 dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
438 skb->len, skb->csum);
439 netif_receive_skb(skb);
440
441 return 0;
442}
443
444/* Mark DMA descriptors from begin up to and not including end as unused */
445static void discard_partial_frame(struct macb *bp, unsigned int begin,
446 unsigned int end)
447{
448 unsigned int frag;
449
450 for (frag = begin; frag != end; frag = NEXT_RX(frag))
451 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
452 wmb();
453
454 /*
455 * When this happens, the hardware stats registers for
456 * whatever caused this is updated, so we don't have to record
457 * anything.
458 */
459}
460
461static int macb_rx(struct macb *bp, int budget)
462{
463 int received = 0;
464 unsigned int tail = bp->rx_tail;
465 int first_frag = -1;
466
467 for (; budget > 0; tail = NEXT_RX(tail)) {
468 u32 addr, ctrl;
469
470 rmb();
471 addr = bp->rx_ring[tail].addr;
472 ctrl = bp->rx_ring[tail].ctrl;
473
474 if (!(addr & MACB_BIT(RX_USED)))
475 break;
476
477 if (ctrl & MACB_BIT(RX_SOF)) {
478 if (first_frag != -1)
479 discard_partial_frame(bp, first_frag, tail);
480 first_frag = tail;
481 }
482
483 if (ctrl & MACB_BIT(RX_EOF)) {
484 int dropped;
485 BUG_ON(first_frag == -1);
486
487 dropped = macb_rx_frame(bp, first_frag, tail);
488 first_frag = -1;
489 if (!dropped) {
490 received++;
491 budget--;
492 }
493 }
494 }
495
496 if (first_frag != -1)
497 bp->rx_tail = first_frag;
498 else
499 bp->rx_tail = tail;
500
501 return received;
502}
503
bea3348e 504static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 505{
bea3348e 506 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 507 int work_done;
89e5785f
HS		 508 u32 status;
509
510 status = macb_readl(bp, RSR);
511 macb_writel(bp, RSR, status);
512
bea3348e 513 work_done = 0;
89e5785f
HS		 514
515 dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
bea3348e 516 (unsigned long)status, budget);
89e5785f 517
bea3348e 518 work_done = macb_rx(bp, budget);
b336369c 519 if (work_done < budget) {
288379f0 520 napi_complete(napi);
89e5785f 521
b336369c
JH		 522 /*
523 * We've done what we can to clean the buffers. Make sure we
524 * get notified when new packets arrive.
525 */
526 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
527 }
89e5785f
HS		 528
529 /* TODO: Handle errors */
530
bea3348e 531 return work_done;
89e5785f
HS		 532}
533
534static irqreturn_t macb_interrupt(int irq, void *dev_id)
535{
536 struct net_device *dev = dev_id;
537 struct macb *bp = netdev_priv(dev);
538 u32 status;
539
540 status = macb_readl(bp, ISR);
541
542 if (unlikely(!status))
543 return IRQ_NONE;
544
545 spin_lock(&bp->lock);
546
547 while (status) {
89e5785f
HS		 548 /* close possible race with dev_close */
549 if (unlikely(!netif_running(dev))) {
550 macb_writel(bp, IDR, ~0UL);
551 break;
552 }
553
554 if (status & MACB_RX_INT_FLAGS) {
b336369c
JH		 555 /*
556 * There's no point taking any more interrupts
557 * until we have processed the buffers. The
558 * scheduling call may fail if the poll routine
559 * is already scheduled, so disable interrupts
560 * now.
561 */
562 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
563
288379f0 564 if (napi_schedule_prep(&bp->napi)) {
6c36a707
R		 565 dev_dbg(&bp->pdev->dev,
566 "scheduling RX softirq\n");
288379f0 567 __napi_schedule(&bp->napi);
89e5785f
HS		 568 }
569 }
570
ee33c585
EW		 571 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
572 MACB_BIT(ISR_RLE)))
89e5785f
HS		 573 macb_tx(bp);
574
575 /*
576 * Link change detection isn't possible with RMII, so we'll
577 * add that if/when we get our hands on a full-blown MII PHY.
578 */
579
b19f7f71
AS		 580 if (status & MACB_BIT(ISR_ROVR)) {
581 /* We missed at least one packet */
582 bp->hw_stats.rx_overruns++;
583 }
584
89e5785f
HS		 585 if (status & MACB_BIT(HRESP)) {
586 /*
587 * TODO: Reset the hardware, and maybe move the printk
588 * to a lower-priority context as well (work queue?)
589 */
590 printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
591 dev->name);
592 }
593
594 status = macb_readl(bp, ISR);
595 }
596
597 spin_unlock(&bp->lock);
598
599 return IRQ_HANDLED;
600}
601
6e8cf5c0
TP		 602#ifdef CONFIG_NET_POLL_CONTROLLER
603/*
604 * Polling receive - used by netconsole and other diagnostic tools
605 * to allow network i/o with interrupts disabled.
606 */
607static void macb_poll_controller(struct net_device *dev)
608{
609 unsigned long flags;
610
611 local_irq_save(flags);
612 macb_interrupt(dev->irq, dev);
613 local_irq_restore(flags);
614}
615#endif
616
89e5785f
HS		 617static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
618{
619 struct macb *bp = netdev_priv(dev);
620 dma_addr_t mapping;
621 unsigned int len, entry;
622 u32 ctrl;
4871953c 623 unsigned long flags;
89e5785f
HS		 624
625#ifdef DEBUG
626 int i;
627 dev_dbg(&bp->pdev->dev,
628 "start_xmit: len %u head %p data %p tail %p end %p\n",
27a884dc 629 skb->len, skb->head, skb->data,
4305b541 630 skb_tail_pointer(skb), skb_end_pointer(skb));
89e5785f
HS		 631 dev_dbg(&bp->pdev->dev,
632 "data:");
633 for (i = 0; i < 16; i++)
634 printk(" %02x", (unsigned int)skb->data[i]);
635 printk("\n");
636#endif
637
638 len = skb->len;
4871953c 639 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS		 640
641 /* This is a hard error, log it. */
642 if (TX_BUFFS_AVAIL(bp) < 1) {
643 netif_stop_queue(dev);
4871953c 644 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f
HS		 645 dev_err(&bp->pdev->dev,
646 "BUG! Tx Ring full when queue awake!\n");
647 dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
648 bp->tx_head, bp->tx_tail);
5b548140 649 return NETDEV_TX_BUSY;
89e5785f
HS		 650 }
651
652 entry = bp->tx_head;
653 dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
654 mapping = dma_map_single(&bp->pdev->dev, skb->data,
655 len, DMA_TO_DEVICE);
656 bp->tx_skb[entry].skb = skb;
657 bp->tx_skb[entry].mapping = mapping;
658 dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
659 skb->data, (unsigned long)mapping);
660
661 ctrl = MACB_BF(TX_FRMLEN, len);
662 ctrl |= MACB_BIT(TX_LAST);
663 if (entry == (TX_RING_SIZE - 1))
664 ctrl |= MACB_BIT(TX_WRAP);
665
666 bp->tx_ring[entry].addr = mapping;
667 bp->tx_ring[entry].ctrl = ctrl;
668 wmb();
669
670 entry = NEXT_TX(entry);
671 bp->tx_head = entry;
672
e072092f
RC		 673 skb_tx_timestamp(skb);
674
89e5785f
HS		 675 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
676
677 if (TX_BUFFS_AVAIL(bp) < 1)
678 netif_stop_queue(dev);
679
4871953c 680 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 681
6ed10654 682 return NETDEV_TX_OK;
89e5785f
HS		 683}
684
685static void macb_free_consistent(struct macb *bp)
686{
687 if (bp->tx_skb) {
688 kfree(bp->tx_skb);
689 bp->tx_skb = NULL;
690 }
691 if (bp->rx_ring) {
692 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
693 bp->rx_ring, bp->rx_ring_dma);
694 bp->rx_ring = NULL;
695 }
696 if (bp->tx_ring) {
697 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
698 bp->tx_ring, bp->tx_ring_dma);
699 bp->tx_ring = NULL;
700 }
701 if (bp->rx_buffers) {
702 dma_free_coherent(&bp->pdev->dev,
703 RX_RING_SIZE * RX_BUFFER_SIZE,
704 bp->rx_buffers, bp->rx_buffers_dma);
705 bp->rx_buffers = NULL;
706 }
707}
708
709static int macb_alloc_consistent(struct macb *bp)
710{
711 int size;
712
713 size = TX_RING_SIZE * sizeof(struct ring_info);
714 bp->tx_skb = kmalloc(size, GFP_KERNEL);
715 if (!bp->tx_skb)
716 goto out_err;
717
718 size = RX_RING_BYTES;
719 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
720 &bp->rx_ring_dma, GFP_KERNEL);
721 if (!bp->rx_ring)
722 goto out_err;
723 dev_dbg(&bp->pdev->dev,
724 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
725 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
726
727 size = TX_RING_BYTES;
728 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
729 &bp->tx_ring_dma, GFP_KERNEL);
730 if (!bp->tx_ring)
731 goto out_err;
732 dev_dbg(&bp->pdev->dev,
733 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
734 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
735
736 size = RX_RING_SIZE * RX_BUFFER_SIZE;
737 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
738 &bp->rx_buffers_dma, GFP_KERNEL);
739 if (!bp->rx_buffers)
740 goto out_err;
741 dev_dbg(&bp->pdev->dev,
742 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
743 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
744
745 return 0;
746
747out_err:
748 macb_free_consistent(bp);
749 return -ENOMEM;
750}
751
752static void macb_init_rings(struct macb *bp)
753{
754 int i;
755 dma_addr_t addr;
756
757 addr = bp->rx_buffers_dma;
758 for (i = 0; i < RX_RING_SIZE; i++) {
759 bp->rx_ring[i].addr = addr;
760 bp->rx_ring[i].ctrl = 0;
761 addr += RX_BUFFER_SIZE;
762 }
763 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
764
765 for (i = 0; i < TX_RING_SIZE; i++) {
766 bp->tx_ring[i].addr = 0;
767 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
768 }
769 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
770
771 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
772}
773
774static void macb_reset_hw(struct macb *bp)
775{
776 /* Make sure we have the write buffer for ourselves */
777 wmb();
778
779 /*
780 * Disable RX and TX (XXX: Should we halt the transmission
781 * more gracefully?)
782 */
783 macb_writel(bp, NCR, 0);
784
785 /* Clear the stats registers (XXX: Update stats first?) */
786 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
787
788 /* Clear all status flags */
789 macb_writel(bp, TSR, ~0UL);
790 macb_writel(bp, RSR, ~0UL);
791
792 /* Disable all interrupts */
793 macb_writel(bp, IDR, ~0UL);
794 macb_readl(bp, ISR);
795}
796
797static void macb_init_hw(struct macb *bp)
798{
799 u32 config;
800
801 macb_reset_hw(bp);
802 __macb_set_hwaddr(bp);
803
804 config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
805 config |= MACB_BIT(PAE); /* PAuse Enable */
806 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
8dd4bd00 807 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS		 808 if (bp->dev->flags & IFF_PROMISC)
809 config |= MACB_BIT(CAF); /* Copy All Frames */
810 if (!(bp->dev->flags & IFF_BROADCAST))
811 config |= MACB_BIT(NBC); /* No BroadCast */
812 macb_writel(bp, NCFGR, config);
813
814 /* Initialize TX and RX buffers */
815 macb_writel(bp, RBQP, bp->rx_ring_dma);
816 macb_writel(bp, TBQP, bp->tx_ring_dma);
817
818 /* Enable TX and RX */
6c36a707 819 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 820
821 /* Enable interrupts */
822 macb_writel(bp, IER, (MACB_BIT(RCOMP)
823 | MACB_BIT(RXUBR)
824 | MACB_BIT(ISR_TUND)
825 | MACB_BIT(ISR_RLE)
826 | MACB_BIT(TXERR)
827 | MACB_BIT(TCOMP)
828 | MACB_BIT(ISR_ROVR)
829 | MACB_BIT(HRESP)));
89e5785f 830
89e5785f
HS		 831}
832
446ebd01
PV		 833/*
834 * The hash address register is 64 bits long and takes up two
835 * locations in the memory map. The least significant bits are stored
836 * in EMAC_HSL and the most significant bits in EMAC_HSH.
837 *
838 * The unicast hash enable and the multicast hash enable bits in the
839 * network configuration register enable the reception of hash matched
840 * frames. The destination address is reduced to a 6 bit index into
841 * the 64 bit hash register using the following hash function. The
842 * hash function is an exclusive or of every sixth bit of the
843 * destination address.
844 *
845 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
846 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
847 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
848 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
849 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
850 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
851 *
852 * da[0] represents the least significant bit of the first byte
853 * received, that is, the multicast/unicast indicator, and da[47]
854 * represents the most significant bit of the last byte received. If
855 * the hash index, hi[n], points to a bit that is set in the hash
856 * register then the frame will be matched according to whether the
857 * frame is multicast or unicast. A multicast match will be signalled
858 * if the multicast hash enable bit is set, da[0] is 1 and the hash
859 * index points to a bit set in the hash register. A unicast match
860 * will be signalled if the unicast hash enable bit is set, da[0] is 0
861 * and the hash index points to a bit set in the hash register. To
862 * receive all multicast frames, the hash register should be set with
863 * all ones and the multicast hash enable bit should be set in the
864 * network configuration register.
865 */
866
867static inline int hash_bit_value(int bitnr, __u8 *addr)
868{
869 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
870 return 1;
871 return 0;
872}
873
874/*
875 * Return the hash index value for the specified address.
876 */
877static int hash_get_index(__u8 *addr)
878{
879 int i, j, bitval;
880 int hash_index = 0;
881
882 for (j = 0; j < 6; j++) {
883 for (i = 0, bitval = 0; i < 8; i++)
884 bitval ^= hash_bit_value(i*6 + j, addr);
885
886 hash_index |= (bitval << j);
887 }
888
889 return hash_index;
890}
891
892/*
893 * Add multicast addresses to the internal multicast-hash table.
894 */
895static void macb_sethashtable(struct net_device *dev)
896{
22bedad3 897 struct netdev_hw_addr *ha;
446ebd01 898 unsigned long mc_filter[2];
f9dcbcc9 899 unsigned int bitnr;
446ebd01
PV		 900 struct macb *bp = netdev_priv(dev);
901
902 mc_filter[0] = mc_filter[1] = 0;
903
22bedad3
JP		 904 netdev_for_each_mc_addr(ha, dev) {
905 bitnr = hash_get_index(ha->addr);
446ebd01
PV		 906 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
907 }
908
909 macb_writel(bp, HRB, mc_filter[0]);
910 macb_writel(bp, HRT, mc_filter[1]);
911}
912
913/*
914 * Enable/Disable promiscuous and multicast modes.
915 */
916static void macb_set_rx_mode(struct net_device *dev)
917{
918 unsigned long cfg;
919 struct macb *bp = netdev_priv(dev);
920
921 cfg = macb_readl(bp, NCFGR);
922
923 if (dev->flags & IFF_PROMISC)
924 /* Enable promiscuous mode */
925 cfg |= MACB_BIT(CAF);
926 else if (dev->flags & (~IFF_PROMISC))
927 /* Disable promiscuous mode */
928 cfg &= ~MACB_BIT(CAF);
929
930 if (dev->flags & IFF_ALLMULTI) {
931 /* Enable all multicast mode */
932 macb_writel(bp, HRB, -1);
933 macb_writel(bp, HRT, -1);
934 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 935 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV		 936 /* Enable specific multicasts */
937 macb_sethashtable(dev);
938 cfg |= MACB_BIT(NCFGR_MTI);
939 } else if (dev->flags & (~IFF_ALLMULTI)) {
940 /* Disable all multicast mode */
941 macb_writel(bp, HRB, 0);
942 macb_writel(bp, HRT, 0);
943 cfg &= ~MACB_BIT(NCFGR_MTI);
944 }
945
946 macb_writel(bp, NCFGR, cfg);
947}
948
89e5785f
HS		 949static int macb_open(struct net_device *dev)
950{
951 struct macb *bp = netdev_priv(dev);
952 int err;
953
954 dev_dbg(&bp->pdev->dev, "open\n");
955
6c36a707
R		 956 /* if the phy is not yet register, retry later*/
957 if (!bp->phy_dev)
958 return -EAGAIN;
959
89e5785f
HS		 960 if (!is_valid_ether_addr(dev->dev_addr))
961 return -EADDRNOTAVAIL;
962
963 err = macb_alloc_consistent(bp);
964 if (err) {
965 printk(KERN_ERR
966 "%s: Unable to allocate DMA memory (error %d)\n",
967 dev->name, err);
968 return err;
969 }
970
bea3348e
SH		 971 napi_enable(&bp->napi);
972
89e5785f
HS		 973 macb_init_rings(bp);
974 macb_init_hw(bp);
89e5785f 975
6c36a707
R		 976 /* schedule a link state check */
977 phy_start(bp->phy_dev);
89e5785f 978
6c36a707 979 netif_start_queue(dev);
89e5785f
HS		 980
981 return 0;
982}
983
984static int macb_close(struct net_device *dev)
985{
986 struct macb *bp = netdev_priv(dev);
987 unsigned long flags;
988
89e5785f 989 netif_stop_queue(dev);
bea3348e 990 napi_disable(&bp->napi);
89e5785f 991
6c36a707
R		 992 if (bp->phy_dev)
993 phy_stop(bp->phy_dev);
994
89e5785f
HS		 995 spin_lock_irqsave(&bp->lock, flags);
996 macb_reset_hw(bp);
997 netif_carrier_off(dev);
998 spin_unlock_irqrestore(&bp->lock, flags);
999
1000 macb_free_consistent(bp);
1001
1002 return 0;
1003}
1004
1005static struct net_device_stats *macb_get_stats(struct net_device *dev)
1006{
1007 struct macb *bp = netdev_priv(dev);
1008 struct net_device_stats *nstat = &bp->stats;
1009 struct macb_stats *hwstat = &bp->hw_stats;
1010
6c36a707
R		 1011 /* read stats from hardware */
1012 macb_update_stats(bp);
1013
89e5785f
HS		 1014 /* Convert HW stats into netdevice stats */
1015 nstat->rx_errors = (hwstat->rx_fcs_errors +
1016 hwstat->rx_align_errors +
1017 hwstat->rx_resource_errors +
1018 hwstat->rx_overruns +
1019 hwstat->rx_oversize_pkts +
1020 hwstat->rx_jabbers +
1021 hwstat->rx_undersize_pkts +
1022 hwstat->sqe_test_errors +
1023 hwstat->rx_length_mismatch);
1024 nstat->tx_errors = (hwstat->tx_late_cols +
1025 hwstat->tx_excessive_cols +
1026 hwstat->tx_underruns +
1027 hwstat->tx_carrier_errors);
1028 nstat->collisions = (hwstat->tx_single_cols +
1029 hwstat->tx_multiple_cols +
1030 hwstat->tx_excessive_cols);
1031 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1032 hwstat->rx_jabbers +
1033 hwstat->rx_undersize_pkts +
1034 hwstat->rx_length_mismatch);
b19f7f71
AS		 1035 nstat->rx_over_errors = hwstat->rx_resource_errors +
1036 hwstat->rx_overruns;
89e5785f
HS		 1037 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1038 nstat->rx_frame_errors = hwstat->rx_align_errors;
1039 nstat->rx_fifo_errors = hwstat->rx_overruns;
1040 /* XXX: What does "missed" mean? */
1041 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1042 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1043 nstat->tx_fifo_errors = hwstat->tx_underruns;
1044 /* Don't know about heartbeat or window errors... */
1045
1046 return nstat;
1047}
1048
1049static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1050{
1051 struct macb *bp = netdev_priv(dev);
6c36a707
R		 1052 struct phy_device *phydev = bp->phy_dev;
1053
1054 if (!phydev)
1055 return -ENODEV;
89e5785f 1056
6c36a707 1057 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 1058}
1059
1060static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1061{
1062 struct macb *bp = netdev_priv(dev);
6c36a707 1063 struct phy_device *phydev = bp->phy_dev;
89e5785f 1064
6c36a707
R		 1065 if (!phydev)
1066 return -ENODEV;
1067
1068 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 1069}
1070
6c36a707
R		 1071static void macb_get_drvinfo(struct net_device *dev,
1072 struct ethtool_drvinfo *info)
89e5785f
HS		 1073{
1074 struct macb *bp = netdev_priv(dev);
1075
1076 strcpy(info->driver, bp->pdev->dev.driver->name);
1077 strcpy(info->version, "$Revision: 1.14 $");
db1d7bf7 1078 strcpy(info->bus_info, dev_name(&bp->pdev->dev));
89e5785f
HS		 1079}
1080
0fc0b732 1081static const struct ethtool_ops macb_ethtool_ops = {
89e5785f
HS		 1082 .get_settings = macb_get_settings,
1083 .set_settings = macb_set_settings,
1084 .get_drvinfo = macb_get_drvinfo,
89e5785f
HS		 1085 .get_link = ethtool_op_get_link,
1086};
1087
1088static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1089{
1090 struct macb *bp = netdev_priv(dev);
6c36a707 1091 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 1092
1093 if (!netif_running(dev))
1094 return -EINVAL;
1095
6c36a707
R		 1096 if (!phydev)
1097 return -ENODEV;
89e5785f 1098
28b04113 1099 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f
HS		 1100}
1101
5f1fa992
AB		 1102static const struct net_device_ops macb_netdev_ops = {
1103 .ndo_open = macb_open,
1104 .ndo_stop = macb_close,
1105 .ndo_start_xmit = macb_start_xmit,
1106 .ndo_set_multicast_list = macb_set_rx_mode,
1107 .ndo_get_stats = macb_get_stats,
1108 .ndo_do_ioctl = macb_ioctl,
1109 .ndo_validate_addr = eth_validate_addr,
1110 .ndo_change_mtu = eth_change_mtu,
1111 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP		 1112#ifdef CONFIG_NET_POLL_CONTROLLER
1113 .ndo_poll_controller = macb_poll_controller,
1114#endif
5f1fa992
AB		 1115};
1116
06c3fd6a 1117static int __init macb_probe(struct platform_device *pdev)
89e5785f
HS		 1118{
1119 struct eth_platform_data *pdata;
1120 struct resource *regs;
1121 struct net_device *dev;
1122 struct macb *bp;
6c36a707 1123 struct phy_device *phydev;
89e5785f
HS		 1124 unsigned long pclk_hz;
1125 u32 config;
1126 int err = -ENXIO;
1127
1128 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1129 if (!regs) {
1130 dev_err(&pdev->dev, "no mmio resource defined\n");
1131 goto err_out;
1132 }
1133
1134 err = -ENOMEM;
1135 dev = alloc_etherdev(sizeof(*bp));
1136 if (!dev) {
1137 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
1138 goto err_out;
1139 }
1140
89e5785f
HS		 1141 SET_NETDEV_DEV(dev, &pdev->dev);
1142
1143 /* TODO: Actually, we have some interesting features... */
1144 dev->features |= 0;
1145
1146 bp = netdev_priv(dev);
1147 bp->pdev = pdev;
1148 bp->dev = dev;
1149
1150 spin_lock_init(&bp->lock);
1151
0cc8674f
AV		 1152#if defined(CONFIG_ARCH_AT91)
1153 bp->pclk = clk_get(&pdev->dev, "macb_clk");
1154 if (IS_ERR(bp->pclk)) {
1155 dev_err(&pdev->dev, "failed to get macb_clk\n");
1156 goto err_out_free_dev;
1157 }
1158 clk_enable(bp->pclk);
1159#else
89e5785f
HS		 1160 bp->pclk = clk_get(&pdev->dev, "pclk");
1161 if (IS_ERR(bp->pclk)) {
1162 dev_err(&pdev->dev, "failed to get pclk\n");
1163 goto err_out_free_dev;
1164 }
1165 bp->hclk = clk_get(&pdev->dev, "hclk");
1166 if (IS_ERR(bp->hclk)) {
1167 dev_err(&pdev->dev, "failed to get hclk\n");
1168 goto err_out_put_pclk;
1169 }
1170
1171 clk_enable(bp->pclk);
1172 clk_enable(bp->hclk);
0cc8674f 1173#endif
89e5785f 1174
28f65c11 1175 bp->regs = ioremap(regs->start, resource_size(regs));
89e5785f
HS		 1176 if (!bp->regs) {
1177 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1178 err = -ENOMEM;
1179 goto err_out_disable_clocks;
1180 }
1181
1182 dev->irq = platform_get_irq(pdev, 0);
ab392d2d 1183 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
89e5785f
HS		 1184 if (err) {
1185 printk(KERN_ERR
1186 "%s: Unable to request IRQ %d (error %d)\n",
1187 dev->name, dev->irq, err);
1188 goto err_out_iounmap;
1189 }
1190
5f1fa992 1191 dev->netdev_ops = &macb_netdev_ops;
bea3348e 1192 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS		 1193 dev->ethtool_ops = &macb_ethtool_ops;
1194
1195 dev->base_addr = regs->start;
1196
89e5785f
HS		 1197 /* Set MII management clock divider */
1198 pclk_hz = clk_get_rate(bp->pclk);
1199 if (pclk_hz <= 20000000)
1200 config = MACB_BF(CLK, MACB_CLK_DIV8);
1201 else if (pclk_hz <= 40000000)
1202 config = MACB_BF(CLK, MACB_CLK_DIV16);
1203 else if (pclk_hz <= 80000000)
1204 config = MACB_BF(CLK, MACB_CLK_DIV32);
1205 else
1206 config = MACB_BF(CLK, MACB_CLK_DIV64);
1207 macb_writel(bp, NCFGR, config);
1208
89e5785f 1209 macb_get_hwaddr(bp);
89e5785f 1210 pdata = pdev->dev.platform_data;
6c36a707 1211
89e5785f 1212 if (pdata && pdata->is_rmii)
0cc8674f
AV		 1213#if defined(CONFIG_ARCH_AT91)
1214 macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
1215#else
89e5785f 1216 macb_writel(bp, USRIO, 0);
0cc8674f 1217#endif
89e5785f 1218 else
0cc8674f
AV		 1219#if defined(CONFIG_ARCH_AT91)
1220 macb_writel(bp, USRIO, MACB_BIT(CLKEN));
1221#else
89e5785f 1222 macb_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 1223#endif
89e5785f
HS		 1224
1225 bp->tx_pending = DEF_TX_RING_PENDING;
1226
1227 err = register_netdev(dev);
1228 if (err) {
1229 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1230 goto err_out_free_irq;
1231 }
1232
6c36a707
R		 1233 if (macb_mii_init(bp) != 0) {
1234 goto err_out_unregister_netdev;
1235 }
89e5785f 1236
6c36a707 1237 platform_set_drvdata(pdev, dev);
89e5785f 1238
e174961c
JB		 1239 printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d (%pM)\n",
1240 dev->name, dev->base_addr, dev->irq, dev->dev_addr);
89e5785f 1241
6c36a707
R		 1242 phydev = bp->phy_dev;
1243 printk(KERN_INFO "%s: attached PHY driver [%s] "
db1d7bf7
KS		 1244 "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
1245 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
6c36a707 1246
89e5785f
HS		 1247 return 0;
1248
6c36a707
R		 1249err_out_unregister_netdev:
1250 unregister_netdev(dev);
89e5785f
HS		 1251err_out_free_irq:
1252 free_irq(dev->irq, dev);
1253err_out_iounmap:
1254 iounmap(bp->regs);
1255err_out_disable_clocks:
0cc8674f 1256#ifndef CONFIG_ARCH_AT91
89e5785f 1257 clk_disable(bp->hclk);
89e5785f 1258 clk_put(bp->hclk);
0cc8674f
AV		 1259#endif
1260 clk_disable(bp->pclk);
6c36a707 1261#ifndef CONFIG_ARCH_AT91
89e5785f 1262err_out_put_pclk:
6c36a707 1263#endif
89e5785f
HS		 1264 clk_put(bp->pclk);
1265err_out_free_dev:
1266 free_netdev(dev);
1267err_out:
1268 platform_set_drvdata(pdev, NULL);
1269 return err;
1270}
1271
06c3fd6a 1272static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS		 1273{
1274 struct net_device *dev;
1275 struct macb *bp;
1276
1277 dev = platform_get_drvdata(pdev);
1278
1279 if (dev) {
1280 bp = netdev_priv(dev);
84b7901f
AN		 1281 if (bp->phy_dev)
1282 phy_disconnect(bp->phy_dev);
298cf9be
LB		 1283 mdiobus_unregister(bp->mii_bus);
1284 kfree(bp->mii_bus->irq);
1285 mdiobus_free(bp->mii_bus);
89e5785f
HS		 1286 unregister_netdev(dev);
1287 free_irq(dev->irq, dev);
1288 iounmap(bp->regs);
0cc8674f 1289#ifndef CONFIG_ARCH_AT91
89e5785f 1290 clk_disable(bp->hclk);
89e5785f 1291 clk_put(bp->hclk);
0cc8674f
AV		 1292#endif
1293 clk_disable(bp->pclk);
89e5785f
HS		 1294 clk_put(bp->pclk);
1295 free_netdev(dev);
1296 platform_set_drvdata(pdev, NULL);
1297 }
1298
1299 return 0;
1300}
1301
c1f598fd
HS		 1302#ifdef CONFIG_PM
1303static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1304{
1305 struct net_device *netdev = platform_get_drvdata(pdev);
1306 struct macb *bp = netdev_priv(netdev);
1307
1308 netif_device_detach(netdev);
1309
1310#ifndef CONFIG_ARCH_AT91
1311 clk_disable(bp->hclk);
1312#endif
1313 clk_disable(bp->pclk);
1314
1315 return 0;
1316}
1317
1318static int macb_resume(struct platform_device *pdev)
1319{
1320 struct net_device *netdev = platform_get_drvdata(pdev);
1321 struct macb *bp = netdev_priv(netdev);
1322
1323 clk_enable(bp->pclk);
1324#ifndef CONFIG_ARCH_AT91
1325 clk_enable(bp->hclk);
1326#endif
1327
1328 netif_device_attach(netdev);
1329
1330 return 0;
1331}
1332#else
1333#define macb_suspend NULL
1334#define macb_resume NULL
1335#endif
1336
89e5785f 1337static struct platform_driver macb_driver = {
06c3fd6a 1338 .remove = __exit_p(macb_remove),
c1f598fd
HS		 1339 .suspend = macb_suspend,
1340 .resume = macb_resume,
89e5785f
HS		 1341 .driver = {
1342 .name = "macb",
72abb461 1343 .owner = THIS_MODULE,
89e5785f
HS		 1344 },
1345};
1346
1347static int __init macb_init(void)
1348{
06c3fd6a 1349 return platform_driver_probe(&macb_driver, macb_probe);
89e5785f
HS		 1350}
1351
1352static void __exit macb_exit(void)
1353{
1354 platform_driver_unregister(&macb_driver);
1355}
1356
1357module_init(macb_init);
1358module_exit(macb_exit);
1359
1360MODULE_LICENSE("GPL");
1361MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
e05503ef 1362MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 1363MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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