[deliverable/linux.git] / drivers / net / sfc / io.h

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2010 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#ifndef EFX_IO_H
#define EFX_IO_H

#include <linux/io.h>
#include <linux/spinlock.h>

/**************************************************************************
 *
 * NIC register I/O
 *
 **************************************************************************
 *
 * Notes on locking strategy:
 *
 * Most CSRs are 128-bit (oword) and therefore cannot be read or
 * written atomically.  Access from the host is buffered by the Bus
 * Interface Unit (BIU).  Whenever the host reads from the lowest
 * address of such a register, or from the address of a different such
 * register, the BIU latches the register's value.  Subsequent reads
 * from higher addresses of the same register will read the latched
 * value.  Whenever the host writes part of such a register, the BIU
 * collects the written value and does not write to the underlying
 * register until all 4 dwords have been written.  A similar buffering
 * scheme applies to host access to the NIC's 64-bit SRAM.
 *
 * Access to different CSRs and 64-bit SRAM words must be serialised,
 * since interleaved access can result in lost writes or lost
 * information from read-to-clear fields.  We use efx_nic::biu_lock
 * for this.  (We could use separate locks for read and write, but
 * this is not normally a performance bottleneck.)
 *
 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 * 128-bit but are special-cased in the BIU to avoid the need for
 * locking in the host:
 *
 * - They are write-only.
 * - The semantics of writing to these registers are such that
 *   replacing the low 96 bits with zero does not affect functionality.
 * - If the host writes to the last dword address of such a register
 *   (i.e. the high 32 bits) the underlying register will always be
 *   written.  If the collector and the current write together do not
 *   provide values for all 128 bits of the register, the low 96 bits
 *   will be written as zero.
 * - If the host writes to the address of any other part of such a
 *   register while the collector already holds values for some other
 *   register, the write is discarded and the collector maintains its
 *   current state.
 */

#if BITS_PER_LONG == 64
#define EFX_USE_QWORD_IO 1
#endif

#ifdef EFX_USE_QWORD_IO
static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
				  unsigned int reg)
{
	__raw_writeq((__force u64)value, efx->membase + reg);
}
static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le64)__raw_readq(efx->membase + reg);
}
#endif

static inline void _efx_writed(struct efx_nic *efx, __le32 value,
				  unsigned int reg)
{
	__raw_writel((__force u32)value, efx->membase + reg);
}
static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le32)__raw_readl(efx->membase + reg);
}

/* Write a normal 128-bit CSR, locking as appropriate. */
static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
			      unsigned int reg)
{
	unsigned long flags __attribute__ ((unused));

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	_efx_writeq(efx, value->u64[0], reg + 0);
	_efx_writeq(efx, value->u64[1], reg + 8);
#else
	_efx_writed(efx, value->u32[0], reg + 0);
	_efx_writed(efx, value->u32[1], reg + 4);
	_efx_writed(efx, value->u32[2], reg + 8);
	_efx_writed(efx, value->u32[3], reg + 12);
#endif
	wmb();
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
				   efx_qword_t *value, unsigned int index)
{
	unsigned int addr = index * sizeof(*value);
	unsigned long flags __attribute__ ((unused));

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing SRAM address %x with " EFX_QWORD_FMT "\n",
		   addr, EFX_QWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	__raw_writeq((__force u64)value->u64[0], membase + addr);
#else
	__raw_writel((__force u32)value->u32[0], membase + addr);
	__raw_writel((__force u32)value->u32[1], membase + addr + 4);
#endif
	wmb();
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value,
			      unsigned int reg)
{
	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with "EFX_DWORD_FMT"\n",
		   reg, EFX_DWORD_VAL(*value));

	/* No lock required */
	_efx_writed(efx, value->u32[0], reg);
	wmb();
}

/* Read a 128-bit CSR, locking as appropriate. */
static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
			     unsigned int reg)
{
	unsigned long flags __attribute__ ((unused));

	spin_lock_irqsave(&efx->biu_lock, flags);
	value->u32[0] = _efx_readd(efx, reg + 0);
	rmb();
	value->u32[1] = _efx_readd(efx, reg + 4);
	value->u32[2] = _efx_readd(efx, reg + 8);
	value->u32[3] = _efx_readd(efx, reg + 12);
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	netif_vdbg(efx, hw, efx->net_dev,
		   "read from register %x, got " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));
}

/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
				  efx_qword_t *value, unsigned int index)
{
	unsigned int addr = index * sizeof(*value);
	unsigned long flags __attribute__ ((unused));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef EFX_USE_QWORD_IO
	value->u64[0] = (__force __le64)__raw_readq(membase + addr);
#else
	value->u32[0] = (__force __le32)__raw_readl(membase + addr);
	rmb();
	value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
#endif
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	netif_vdbg(efx, hw, efx->net_dev,
		   "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
		   addr, EFX_QWORD_VAL(*value));
}

/* Read a 32-bit CSR or SRAM */
static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
				unsigned int reg)
{
	value->u32[0] = _efx_readd(efx, reg);
	netif_vdbg(efx, hw, efx->net_dev,
		   "read from register %x, got "EFX_DWORD_FMT"\n",
		   reg, EFX_DWORD_VAL(*value));
}

/* Write a 128-bit CSR forming part of a table */
static inline void efx_writeo_table(struct efx_nic *efx, efx_oword_t *value,
				      unsigned int reg, unsigned int index)
{
	efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Read a 128-bit CSR forming part of a table */
static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
				     unsigned int reg, unsigned int index)
{
	efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Write a 32-bit CSR forming part of a table, or 32-bit SRAM */
static inline void efx_writed_table(struct efx_nic *efx, efx_dword_t *value,
				       unsigned int reg, unsigned int index)
{
	efx_writed(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Read a 32-bit CSR forming part of a table, or 32-bit SRAM */
static inline void efx_readd_table(struct efx_nic *efx, efx_dword_t *value,
				   unsigned int reg, unsigned int index)
{
	efx_readd(efx, value, reg + index * sizeof(efx_dword_t));
}

/* Page-mapped register block size */
#define EFX_PAGE_BLOCK_SIZE 0x2000

/* Calculate offset to page-mapped register block */
#define EFX_PAGED_REG(page, reg) \
	((page) * EFX_PAGE_BLOCK_SIZE + (reg))

/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
				    unsigned int reg, unsigned int page)
{
	reg = EFX_PAGED_REG(page, reg);

	netif_vdbg(efx, hw, efx->net_dev,
		   "writing register %x with " EFX_OWORD_FMT "\n", reg,
		   EFX_OWORD_VAL(*value));

#ifdef EFX_USE_QWORD_IO
	_efx_writeq(efx, value->u64[0], reg + 0);
	_efx_writeq(efx, value->u64[1], reg + 8);
#else
	_efx_writed(efx, value->u32[0], reg + 0);
	_efx_writed(efx, value->u32[1], reg + 4);
	_efx_writed(efx, value->u32[2], reg + 8);
	_efx_writed(efx, value->u32[3], reg + 12);
#endif
	wmb();
}
#define efx_writeo_page(efx, value, reg, page)				\
	_efx_writeo_page(efx, value,					\
			 reg +						\
			 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
			 page)

/* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of
 * RX_DESC_UPD or TX_DESC_UPD)
 */
static inline void _efx_writed_page(struct efx_nic *efx, efx_dword_t *value,
				    unsigned int reg, unsigned int page)
{
	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
}
#define efx_writed_page(efx, value, reg, page)				\
	_efx_writed_page(efx, value,					\
			 reg +						\
			 BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \
					   && (reg) != 0xa1c),		\
			 page)

/* Write TIMER_COMMAND.  This is a page-mapped 32-bit CSR, but a bug
 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
 * collector register.
 */
static inline void _efx_writed_page_locked(struct efx_nic *efx,
					   efx_dword_t *value,
					   unsigned int reg,
					   unsigned int page)
{
	unsigned long flags __attribute__ ((unused));

	if (page == 0) {
		spin_lock_irqsave(&efx->biu_lock, flags);
		efx_writed(efx, value, EFX_PAGED_REG(page, reg));
		spin_unlock_irqrestore(&efx->biu_lock, flags);
	} else {
		efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	}
}
#define efx_writed_page_locked(efx, value, reg, page)			\
	_efx_writed_page_locked(efx, value,				\
				reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
				page)

#endif /* EFX_IO_H */
Commit	Line	Data
12d00cad BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6	4	* Copyright 2006-2010 Solarflare Communications Inc.
12d00cad BH	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#ifndef EFX_IO_H
	12	#define EFX_IO_H
	13
	14	#include <linux/io.h>
	15	#include <linux/spinlock.h>
	16
	17	/**************************************************************************
	18	*
	19	* NIC register I/O
	20	*
	21	**************************************************************************
	22	*
	23	* Notes on locking strategy:
	24	*
9f2f6cd0 BH	25	* Most CSRs are 128-bit (oword) and therefore cannot be read or
	26	* written atomically. Access from the host is buffered by the Bus
	27	* Interface Unit (BIU). Whenever the host reads from the lowest
	28	* address of such a register, or from the address of a different such
	29	* register, the BIU latches the register's value. Subsequent reads
	30	* from higher addresses of the same register will read the latched
	31	* value. Whenever the host writes part of such a register, the BIU
	32	* collects the written value and does not write to the underlying
	33	* register until all 4 dwords have been written. A similar buffering
	34	* scheme applies to host access to the NIC's 64-bit SRAM.
12d00cad	35	*
9f2f6cd0 BH	36	* Access to different CSRs and 64-bit SRAM words must be serialised,
	37	* since interleaved access can result in lost writes or lost
	38	* information from read-to-clear fields. We use efx_nic::biu_lock
	39	* for this. (We could use separate locks for read and write, but
	40	* this is not normally a performance bottleneck.)
12d00cad	41	*
9f2f6cd0 BH	42	* The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
	43	* 128-bit but are special-cased in the BIU to avoid the need for
	44	* locking in the host:
12d00cad	45	*
9f2f6cd0 BH	46	* - They are write-only.
	47	* - The semantics of writing to these registers are such that
	48	* replacing the low 96 bits with zero does not affect functionality.
	49	* - If the host writes to the last dword address of such a register
	50	* (i.e. the high 32 bits) the underlying register will always be
65f0b417 BH	51	* written. If the collector and the current write together do not
	52	* provide values for all 128 bits of the register, the low 96 bits
	53	* will be written as zero.
9f2f6cd0 BH	54	* - If the host writes to the address of any other part of such a
	55	* register while the collector already holds values for some other
	56	* register, the write is discarded and the collector maintains its
	57	* current state.
12d00cad BH	58	*/
	59
	60	#if BITS_PER_LONG == 64
	61	#define EFX_USE_QWORD_IO 1
	62	#endif
	63
	64	#ifdef EFX_USE_QWORD_IO
	65	static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
	66	unsigned int reg)
	67	{
	68	__raw_writeq((__force u64)value, efx->membase + reg);
	69	}
	70	static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
	71	{
	72	return (__force __le64)__raw_readq(efx->membase + reg);
	73	}
	74	#endif
	75
	76	static inline void _efx_writed(struct efx_nic *efx, __le32 value,
	77	unsigned int reg)
	78	{
	79	__raw_writel((__force u32)value, efx->membase + reg);
	80	}
	81	static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
	82	{
	83	return (__force __le32)__raw_readl(efx->membase + reg);
	84	}
	85
9f2f6cd0	86	/* Write a normal 128-bit CSR, locking as appropriate. */
12d00cad BH	87	static inline void efx_writeo(struct efx_nic efx, efx_oword_t value,
	88	unsigned int reg)
	89	{
	90	unsigned long flags __attribute__ ((unused));
	91
62776d03 BH	92	netif_vdbg(efx, hw, efx->net_dev,
	93	"writing register %x with " EFX_OWORD_FMT "\n", reg,
	94	EFX_OWORD_VAL(*value));
12d00cad BH	95
	96	spin_lock_irqsave(&efx->biu_lock, flags);
	97	#ifdef EFX_USE_QWORD_IO
	98	_efx_writeq(efx, value->u64[0], reg + 0);
12d00cad BH	99	_efx_writeq(efx, value->u64[1], reg + 8);
	100	#else
	101	_efx_writed(efx, value->u32[0], reg + 0);
	102	_efx_writed(efx, value->u32[1], reg + 4);
	103	_efx_writed(efx, value->u32[2], reg + 8);
12d00cad BH	104	_efx_writed(efx, value->u32[3], reg + 12);
12d00cad BH	105	#endif
65f0b417	106	wmb();
12d00cad BH	107	mmiowb();
	108	spin_unlock_irqrestore(&efx->biu_lock, flags);
	109	}
	110
9f2f6cd0	111	/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
12d00cad BH	112	static inline void efx_sram_writeq(struct efx_nic efx, void __iomem membase,
	113	efx_qword_t *value, unsigned int index)
	114	{
	115	unsigned int addr = index * sizeof(*value);
	116	unsigned long flags __attribute__ ((unused));
	117
62776d03 BH	118	netif_vdbg(efx, hw, efx->net_dev,
	119	"writing SRAM address %x with " EFX_QWORD_FMT "\n",
	120	addr, EFX_QWORD_VAL(*value));
12d00cad BH	121
	122	spin_lock_irqsave(&efx->biu_lock, flags);
	123	#ifdef EFX_USE_QWORD_IO
	124	__raw_writeq((__force u64)value->u64[0], membase + addr);
	125	#else
	126	__raw_writel((__force u32)value->u32[0], membase + addr);
12d00cad BH	127	__raw_writel((__force u32)value->u32[1], membase + addr + 4);
12d00cad BH	128	#endif
65f0b417	129	wmb();
12d00cad BH	130	mmiowb();
	131	spin_unlock_irqrestore(&efx->biu_lock, flags);
	132	}
	133
9f2f6cd0	134	/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
12d00cad BH	135	static inline void efx_writed(struct efx_nic efx, efx_dword_t value,
	136	unsigned int reg)
	137	{
62776d03	138	netif_vdbg(efx, hw, efx->net_dev,
9f2f6cd0	139	"writing register %x with "EFX_DWORD_FMT"\n",
62776d03	140	reg, EFX_DWORD_VAL(*value));
12d00cad BH	141
	142	/* No lock required */
	143	_efx_writed(efx, value->u32[0], reg);
65f0b417	144	wmb();
12d00cad BH	145	}
12d00cad BH	146
9f2f6cd0	147	/* Read a 128-bit CSR, locking as appropriate. */
12d00cad BH	148	static inline void efx_reado(struct efx_nic efx, efx_oword_t value,
	149	unsigned int reg)
	150	{
	151	unsigned long flags __attribute__ ((unused));
	152
	153	spin_lock_irqsave(&efx->biu_lock, flags);
	154	value->u32[0] = _efx_readd(efx, reg + 0);
fcfa0604	155	rmb();
12d00cad BH	156	value->u32[1] = _efx_readd(efx, reg + 4);
	157	value->u32[2] = _efx_readd(efx, reg + 8);
	158	value->u32[3] = _efx_readd(efx, reg + 12);
	159	spin_unlock_irqrestore(&efx->biu_lock, flags);
	160
62776d03 BH	161	netif_vdbg(efx, hw, efx->net_dev,
	162	"read from register %x, got " EFX_OWORD_FMT "\n", reg,
	163	EFX_OWORD_VAL(*value));
12d00cad BH	164	}
12d00cad BH	165
9f2f6cd0	166	/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
12d00cad BH	167	static inline void efx_sram_readq(struct efx_nic efx, void __iomem membase,
	168	efx_qword_t *value, unsigned int index)
	169	{
	170	unsigned int addr = index * sizeof(*value);
	171	unsigned long flags __attribute__ ((unused));
	172
	173	spin_lock_irqsave(&efx->biu_lock, flags);
	174	#ifdef EFX_USE_QWORD_IO
	175	value->u64[0] = (__force __le64)__raw_readq(membase + addr);
	176	#else
	177	value->u32[0] = (__force __le32)__raw_readl(membase + addr);
fcfa0604	178	rmb();
12d00cad BH	179	value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
	180	#endif
	181	spin_unlock_irqrestore(&efx->biu_lock, flags);
	182
62776d03 BH	183	netif_vdbg(efx, hw, efx->net_dev,
	184	"read from SRAM address %x, got "EFX_QWORD_FMT"\n",
	185	addr, EFX_QWORD_VAL(*value));
12d00cad BH	186	}
12d00cad BH	187
9f2f6cd0	188	/* Read a 32-bit CSR or SRAM */
12d00cad BH	189	static inline void efx_readd(struct efx_nic efx, efx_dword_t value,
	190	unsigned int reg)
	191	{
	192	value->u32[0] = _efx_readd(efx, reg);
62776d03 BH	193	netif_vdbg(efx, hw, efx->net_dev,
	194	"read from register %x, got "EFX_DWORD_FMT"\n",
	195	reg, EFX_DWORD_VAL(*value));
12d00cad BH	196	}
12d00cad BH	197
9f2f6cd0	198	/* Write a 128-bit CSR forming part of a table */
12d00cad BH	199	static inline void efx_writeo_table(struct efx_nic efx, efx_oword_t value,
	200	unsigned int reg, unsigned int index)
	201	{
	202	efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
	203	}
	204
9f2f6cd0	205	/* Read a 128-bit CSR forming part of a table */
12d00cad BH	206	static inline void efx_reado_table(struct efx_nic efx, efx_oword_t value,
	207	unsigned int reg, unsigned int index)
	208	{
	209	efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
	210	}
	211
9f2f6cd0	212	/* Write a 32-bit CSR forming part of a table, or 32-bit SRAM */
12d00cad BH	213	static inline void efx_writed_table(struct efx_nic efx, efx_dword_t value,
	214	unsigned int reg, unsigned int index)
	215	{
	216	efx_writed(efx, value, reg + index * sizeof(efx_oword_t));
	217	}
	218
9f2f6cd0	219	/* Read a 32-bit CSR forming part of a table, or 32-bit SRAM */
5b98c1bf BH	220	static inline void efx_readd_table(struct efx_nic efx, efx_dword_t value,
	221	unsigned int reg, unsigned int index)
	222	{
	223	efx_readd(efx, value, reg + index * sizeof(efx_dword_t));
	224	}
	225
12d00cad BH	226	/* Page-mapped register block size */
	227	#define EFX_PAGE_BLOCK_SIZE 0x2000
	228
	229	/* Calculate offset to page-mapped register block */
	230	#define EFX_PAGED_REG(page, reg) \
	231	((page) * EFX_PAGE_BLOCK_SIZE + (reg))
	232
9f2f6cd0	233	/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
1a29cc40 BH	234	static inline void _efx_writeo_page(struct efx_nic efx, efx_oword_t value,
1a29cc40 BH	235	unsigned int reg, unsigned int page)
12d00cad	236	{
e5061472 BH	237	reg = EFX_PAGED_REG(page, reg);
	238
	239	netif_vdbg(efx, hw, efx->net_dev,
	240	"writing register %x with " EFX_OWORD_FMT "\n", reg,
	241	EFX_OWORD_VAL(*value));
	242
	243	#ifdef EFX_USE_QWORD_IO
	244	_efx_writeq(efx, value->u64[0], reg + 0);
65f0b417	245	_efx_writeq(efx, value->u64[1], reg + 8);
e5061472 BH	246	#else
	247	_efx_writed(efx, value->u32[0], reg + 0);
	248	_efx_writed(efx, value->u32[1], reg + 4);
e5061472 BH	249	_efx_writed(efx, value->u32[2], reg + 8);
e5061472 BH	250	_efx_writed(efx, value->u32[3], reg + 12);
65f0b417 BH	251	#endif
65f0b417 BH	252	wmb();
12d00cad	253	}
1a29cc40 BH	254	#define efx_writeo_page(efx, value, reg, page) \
	255	_efx_writeo_page(efx, value, \
	256	reg + \
	257	BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
	258	page)
12d00cad	259
9f2f6cd0 BH	260	/* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of
	261	* RX_DESC_UPD or TX_DESC_UPD)
	262	*/
1a29cc40 BH	263	static inline void _efx_writed_page(struct efx_nic efx, efx_dword_t value,
1a29cc40 BH	264	unsigned int reg, unsigned int page)
12d00cad BH	265	{
	266	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	267	}
1a29cc40 BH	268	#define efx_writed_page(efx, value, reg, page) \
	269	_efx_writed_page(efx, value, \
	270	reg + \
	271	BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \
	272	&& (reg) != 0xa1c), \
	273	page)
12d00cad	274
9f2f6cd0 BH	275	/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
	276	* in the BIU means that writes to TIMER_COMMAND[0] invalidate the
	277	* collector register.
	278	*/
1a29cc40 BH	279	static inline void _efx_writed_page_locked(struct efx_nic *efx,
	280	efx_dword_t *value,
	281	unsigned int reg,
	282	unsigned int page)
12d00cad BH	283	{
	284	unsigned long flags __attribute__ ((unused));
	285
	286	if (page == 0) {
	287	spin_lock_irqsave(&efx->biu_lock, flags);
	288	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	289	spin_unlock_irqrestore(&efx->biu_lock, flags);
	290	} else {
	291	efx_writed(efx, value, EFX_PAGED_REG(page, reg));
	292	}
	293	}
1a29cc40 BH	294	#define efx_writed_page_locked(efx, value, reg, page) \
	295	_efx_writed_page_locked(efx, value, \
	296	reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
	297	page)
12d00cad BH	298
12d00cad BH	299	#endif /* EFX_IO_H */