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Fix common misspellings
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
5a0e3ad6 36#include <linux/slab.h>
c9bdd4b5 37#include <net/ip.h>
cd28ab6a
SH		 38#include <linux/tcp.h>
39#include <linux/in.h>
40#include <linux/delay.h>
91c86df5 41#include <linux/workqueue.h>
d1f13708 42#include <linux/if_vlan.h>
d70cd51a 43#include <linux/prefetch.h>
3cf26753 44#include <linux/debugfs.h>
ef743d33 45#include <linux/mii.h>
cd28ab6a
SH		 46
47#include <asm/irq.h>
48
49#include "sky2.h"
50
51#define DRV_NAME "sky2"
e0a67e2d 52#define DRV_VERSION "1.28"
cd28ab6a
SH		 53
54/*
55 * The Yukon II chipset takes 64 bit command blocks (called list elements)
56 * that are organized into three (receive, transmit, status) different rings
14d0263f 57 * similar to Tigon3.
cd28ab6a
SH		 58 */
59
14d0263f 60#define RX_LE_SIZE 1024
cd28ab6a 61#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 62#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 63#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 64
ee5f68fe 65/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 66 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
67#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 68#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
efe91932 69#define TX_MAX_PENDING 1024
ee5f68fe 70#define TX_DEF_PENDING 127
cd28ab6a 71
cd28ab6a
SH		 72#define TX_WATCHDOG (5 * HZ)
73#define NAPI_WEIGHT 64
74#define PHY_RETRIES 1000
75
f4331a6d
SH		 76#define SKY2_EEPROM_MAGIC 0x9955aabb
77
060b946c 78#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
cb5d9547 79
cd28ab6a 80static const u32 default_msg =
793b883e
SH		 81 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
82 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 83 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 84
793b883e 85static int debug = -1; /* defaults above */
cd28ab6a
SH		 86module_param(debug, int, 0);
87MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
14d0263f 89static int copybreak __read_mostly = 128;
bdb5c58e
SH		 90module_param(copybreak, int, 0);
91MODULE_PARM_DESC(copybreak, "Receive copy threshold");
92
fb2690a9
SH		 93static int disable_msi = 0;
94module_param(disable_msi, int, 0);
95MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
96
e6cac9ba 97static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 98 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 101 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
d1b139c0
SH		 149static void sky2_set_multicast(struct net_device *dev);
150
af043aa5 151/* Access to PHY via serial interconnect */
ef743d33 152static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 153{
154 int i;
155
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159
160 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 161 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
162 if (ctrl == 0xffff)
163 goto io_error;
164
165 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 166 return 0;
af043aa5
SH		 167
168 udelay(10);
cd28ab6a 169 }
ef743d33 170
060b946c 171 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 172 return -ETIMEDOUT;
af043aa5
SH		 173
174io_error:
175 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
176 return -EIO;
cd28ab6a
SH		 177}
178
ef743d33 179static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 180{
181 int i;
182
793b883e 183 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 184 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
185
186 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 187 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
188 if (ctrl == 0xffff)
189 goto io_error;
190
191 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 192 *val = gma_read16(hw, port, GM_SMI_DATA);
193 return 0;
194 }
195
af043aa5 196 udelay(10);
cd28ab6a
SH		 197 }
198
af043aa5 199 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 200 return -ETIMEDOUT;
af043aa5
SH		 201io_error:
202 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
203 return -EIO;
ef743d33 204}
205
af043aa5 206static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 207{
208 u16 v;
af043aa5 209 __gm_phy_read(hw, port, reg, &v);
ef743d33 210 return v;
cd28ab6a
SH		 211}
212
5afa0a9c 213
ae306cca
SH		 214static void sky2_power_on(struct sky2_hw *hw)
215{
216 /* switch power to VCC (WA for VAUX problem) */
217 sky2_write8(hw, B0_POWER_CTRL,
218 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 219
ae306cca
SH		 220 /* disable Core Clock Division, */
221 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 222
4b7c47aa 223 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 224 /* enable bits are inverted */
225 sky2_write8(hw, B2_Y2_CLK_GATE,
226 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
227 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
228 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
229 else
230 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 231
ea76e635 232 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 233 u32 reg;
5afa0a9c 234
b32f40c4 235 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 236
b32f40c4 237 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 238 /* set all bits to 0 except bits 15..12 and 8 */
239 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 240 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 241
b32f40c4 242 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 243 /* set all bits to 0 except bits 28 & 27 */
244 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 246
b32f40c4 247 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 248
5f8ae5c5 249 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
250
8f70920f
SH		 251 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
252 reg = sky2_read32(hw, B2_GP_IO);
253 reg |= GLB_GPIO_STAT_RACE_DIS;
254 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 255
256 sky2_read32(hw, B2_GP_IO);
5afa0a9c 257 }
10547ae2
SH		 258
259 /* Turn on "driver loaded" LED */
260 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 261}
5afa0a9c 262
ae306cca
SH		 263static void sky2_power_aux(struct sky2_hw *hw)
264{
4b7c47aa 265 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 266 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
267 else
268 /* enable bits are inverted */
269 sky2_write8(hw, B2_Y2_CLK_GATE,
270 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
271 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
272 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
273
c23ddf8f
SH		 274 /* switch power to VAUX if supported and PME from D3cold */
275 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
276 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 277 sky2_write8(hw, B0_POWER_CTRL,
278 (PC_VAUX_ENA | PC_VCC_ENA |
279 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 280
281 /* turn off "driver loaded LED" */
282 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 283}
284
d3bcfbeb 285static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 286{
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 291
cd28ab6a
SH		 292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300}
301
16ad91e1
SH		 302/* flow control to advertise bits */
303static const u16 copper_fc_adv[] = {
304 [FC_NONE] = 0,
305 [FC_TX] = PHY_M_AN_ASP,
306 [FC_RX] = PHY_M_AN_PC,
307 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
308};
309
310/* flow control to advertise bits when using 1000BaseX */
311static const u16 fiber_fc_adv[] = {
df3fe1f3 312 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 313 [FC_TX] = PHY_M_P_ASYM_MD_X,
314 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 315 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 316};
317
318/* flow control to GMA disable bits */
319static const u16 gm_fc_disable[] = {
320 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
321 [FC_TX] = GM_GPCR_FC_RX_DIS,
322 [FC_RX] = GM_GPCR_FC_TX_DIS,
323 [FC_BOTH] = 0,
324};
325
326
cd28ab6a
SH		 327static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
328{
329 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 330 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 331
0ea065e5 332 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 333 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 334 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
335
336 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 337 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 338 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
339
53419c68 340 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 341 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 342 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
344 else
53419c68
SH		 345 /* set master & slave downshift counter to 1x */
346 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 347
348 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 352 if (sky2_is_copper(hw)) {
05745c4a 353 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 354 /* enable automatic crossover */
355 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 356
357 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
358 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
359 u16 spec;
360
361 /* Enable Class A driver for FE+ A0 */
362 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 spec |= PHY_M_FESC_SEL_CL_A;
364 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
365 }
cd28ab6a
SH		 366 } else {
367 /* disable energy detect */
368 ctrl &= ~PHY_M_PC_EN_DET_MSK;
369
370 /* enable automatic crossover */
371 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
372
53419c68 373 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 374 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
375 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 376 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 377 ctrl &= ~PHY_M_PC_DSC_MSK;
378 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
379 }
380 }
cd28ab6a
SH		 381 } else {
382 /* workaround for deviation #4.88 (CRC errors) */
383 /* disable Automatic Crossover */
384
385 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 386 }
cd28ab6a 387
b89165f2
SH		 388 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
389
390 /* special setup for PHY 88E1112 Fiber */
ea76e635 391 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 392 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 393
b89165f2
SH		 394 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
396 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
397 ctrl &= ~PHY_M_MAC_MD_MSK;
398 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
399 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400
401 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 402 /* select page 1 to access Fiber registers */
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 404
405 /* for SFP-module set SIGDET polarity to low */
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 409 }
b89165f2
SH		 410
411 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 412 }
413
7800fddc 414 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 415 ct1000 = 0;
416 adv = PHY_AN_CSMA;
2eaba1a2 417 reg = 0;
cd28ab6a 418
0ea065e5 419 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 420 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 ct1000 |= PHY_M_1000C_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 ct1000 |= PHY_M_1000C_AHD;
425 if (sky2->advertising & ADVERTISED_100baseT_Full)
426 adv |= PHY_M_AN_100_FD;
427 if (sky2->advertising & ADVERTISED_100baseT_Half)
428 adv |= PHY_M_AN_100_HD;
429 if (sky2->advertising & ADVERTISED_10baseT_Full)
430 adv |= PHY_M_AN_10_FD;
431 if (sky2->advertising & ADVERTISED_10baseT_Half)
432 adv |= PHY_M_AN_10_HD;
709c6e7b 433
b89165f2
SH		 434 } else { /* special defines for FIBER (88E1040S only) */
435 if (sky2->advertising & ADVERTISED_1000baseT_Full)
436 adv |= PHY_M_AN_1000X_AFD;
437 if (sky2->advertising & ADVERTISED_1000baseT_Half)
438 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 439 }
cd28ab6a
SH		 440
441 /* Restart Auto-negotiation */
442 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
443 } else {
444 /* forced speed/duplex settings */
445 ct1000 = PHY_M_1000C_MSE;
446
0ea065e5
SH		 447 /* Disable auto update for duplex flow control and duplex */
448 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 449
450 switch (sky2->speed) {
451 case SPEED_1000:
452 ctrl |= PHY_CT_SP1000;
2eaba1a2 453 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 454 break;
455 case SPEED_100:
456 ctrl |= PHY_CT_SP100;
2eaba1a2 457 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 458 break;
459 }
460
2eaba1a2
SH		 461 if (sky2->duplex == DUPLEX_FULL) {
462 reg |= GM_GPCR_DUP_FULL;
463 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 464 } else if (sky2->speed < SPEED_1000)
465 sky2->flow_mode = FC_NONE;
0ea065e5 466 }
2eaba1a2 467
0ea065e5
SH		 468 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
469 if (sky2_is_copper(hw))
470 adv |= copper_fc_adv[sky2->flow_mode];
471 else
472 adv |= fiber_fc_adv[sky2->flow_mode];
473 } else {
474 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 475 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 476
477 /* Forward pause packets to GMAC? */
16ad91e1 478 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
480 else
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 482 }
483
2eaba1a2
SH		 484 gma_write16(hw, port, GM_GP_CTRL, reg);
485
05745c4a 486 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 487 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
488
489 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
490 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
491
492 /* Setup Phy LED's */
493 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
494 ledover = 0;
495
496 switch (hw->chip_id) {
497 case CHIP_ID_YUKON_FE:
498 /* on 88E3082 these bits are at 11..9 (shifted left) */
499 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
500
501 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
502
503 /* delete ACT LED control bits */
504 ctrl &= ~PHY_M_FELP_LED1_MSK;
505 /* change ACT LED control to blink mode */
506 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
507 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 break;
509
05745c4a
SH		 510 case CHIP_ID_YUKON_FE_P:
511 /* Enable Link Partner Next Page */
512 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
513 ctrl |= PHY_M_PC_ENA_LIP_NP;
514
515 /* disable Energy Detect and enable scrambler */
516 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
518
519 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
520 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
521 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
522 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
523
524 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
525 break;
526
cd28ab6a 527 case CHIP_ID_YUKON_XL:
793b883e 528 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 529
530 /* select page 3 to access LED control register */
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
532
533 /* set LED Function Control register */
ed6d32c7
SH		 534 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
535 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
536 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
537 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
538 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 539
540 /* set Polarity Control register */
541 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 542 (PHY_M_POLC_LS1_P_MIX(4) |
543 PHY_M_POLC_IS0_P_MIX(4) |
544 PHY_M_POLC_LOS_CTRL(2) |
545 PHY_M_POLC_INIT_CTRL(2) |
546 PHY_M_POLC_STA1_CTRL(2) |
547 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 548
549 /* restore page register */
793b883e 550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 551 break;
93745494 552
ed6d32c7 553 case CHIP_ID_YUKON_EC_U:
93745494 554 case CHIP_ID_YUKON_EX:
ed4d4161 555 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 556 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
557
558 /* select page 3 to access LED control register */
559 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
560
561 /* set LED Function Control register */
562 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
563 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
564 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
565 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
566 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
567
568 /* set Blink Rate in LED Timer Control Register */
569 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
570 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
571 /* restore page register */
572 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
573 break;
cd28ab6a
SH		 574
575 default:
576 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
577 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 578
cd28ab6a 579 /* turn off the Rx LED (LED_RX) */
a84d0a3d 580 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 581 }
582
0ce8b98d 583 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 584 /* apply fixes in PHY AFE */
ed6d32c7
SH		 585 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
586
977bdf06 587 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 588 gm_phy_write(hw, port, 0x18, 0xaa99);
589 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 590
0ce8b98d
SH		 591 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
592 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
593 gm_phy_write(hw, port, 0x18, 0xa204);
594 gm_phy_write(hw, port, 0x17, 0x2002);
595 }
977bdf06
SH		 596
597 /* set page register to 0 */
9467a8fc 598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 599 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
600 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
601 /* apply workaround for integrated resistors calibration */
602 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
603 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 604 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
605 /* apply fixes in PHY AFE */
606 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
607
608 /* apply RDAC termination workaround */
609 gm_phy_write(hw, port, 24, 0x2800);
610 gm_phy_write(hw, port, 23, 0x2001);
611
612 /* set page register back to 0 */
613 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 614 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
615 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 616 /* no effect on Yukon-XL */
977bdf06 617 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 618
8e95a202
JP		 619 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
620 sky2->speed == SPEED_100) {
977bdf06 621 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 622 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 623 }
cd28ab6a 624
977bdf06
SH		 625 if (ledover)
626 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
627
628 }
2eaba1a2 629
d571b694 630 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 631 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 632 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
633 else
634 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
635}
636
b96936da
SH		 637static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
638static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
639
640static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 641{
642 u32 reg1;
d3bcfbeb 643
a40ccc68 644 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 645 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 646 reg1 &= ~phy_power[port];
d3bcfbeb 647
4b7c47aa 648 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 649 reg1 |= coma_mode[port];
650
b32f40c4 651 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 652 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 653 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 654
655 if (hw->chip_id == CHIP_ID_YUKON_FE)
656 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
657 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
658 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 659}
167f53d0 660
b96936da
SH		 661static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
662{
663 u32 reg1;
db99b988
SH		 664 u16 ctrl;
665
666 /* release GPHY Control reset */
667 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
668
669 /* release GMAC reset */
670 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
671
672 if (hw->flags & SKY2_HW_NEWER_PHY) {
673 /* select page 2 to access MAC control register */
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
675
676 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
677 /* allow GMII Power Down */
678 ctrl &= ~PHY_M_MAC_GMIF_PUP;
679 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
680
681 /* set page register back to 0 */
682 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
683 }
684
685 /* setup General Purpose Control Register */
686 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 687 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
688 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
689 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 690
691 if (hw->chip_id != CHIP_ID_YUKON_EC) {
692 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 693 /* select page 2 to access MAC control register */
694 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 695
e484d5f5 696 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 697 /* enable Power Down */
698 ctrl |= PHY_M_PC_POW_D_ENA;
699 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 700
701 /* set page register back to 0 */
702 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 703 }
704
705 /* set IEEE compatible Power Down Mode (dev. #4.99) */
706 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
707 }
b96936da 708
a40ccc68 709 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 710 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 711 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 712 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 714}
715
38000a94
BP		 716/* Enable Rx/Tx */
717static void sky2_enable_rx_tx(struct sky2_port *sky2)
718{
719 struct sky2_hw *hw = sky2->hw;
720 unsigned port = sky2->port;
721 u16 reg;
722
723 reg = gma_read16(hw, port, GM_GP_CTRL);
724 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
725 gma_write16(hw, port, GM_GP_CTRL, reg);
726}
727
1b537565
SH		 728/* Force a renegotiation */
729static void sky2_phy_reinit(struct sky2_port *sky2)
730{
e07b1aa8 731 spin_lock_bh(&sky2->phy_lock);
1b537565 732 sky2_phy_init(sky2->hw, sky2->port);
38000a94 733 sky2_enable_rx_tx(sky2);
e07b1aa8 734 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 735}
736
e3173832
SH		 737/* Put device in state to listen for Wake On Lan */
738static void sky2_wol_init(struct sky2_port *sky2)
739{
740 struct sky2_hw *hw = sky2->hw;
741 unsigned port = sky2->port;
742 enum flow_control save_mode;
743 u16 ctrl;
e3173832
SH		 744
745 /* Bring hardware out of reset */
746 sky2_write16(hw, B0_CTST, CS_RST_CLR);
747 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
748
749 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
750 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
751
752 /* Force to 10/100
753 * sky2_reset will re-enable on resume
754 */
755 save_mode = sky2->flow_mode;
756 ctrl = sky2->advertising;
757
758 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
759 sky2->flow_mode = FC_NONE;
b96936da
SH		 760
761 spin_lock_bh(&sky2->phy_lock);
762 sky2_phy_power_up(hw, port);
763 sky2_phy_init(hw, port);
764 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 765
766 sky2->flow_mode = save_mode;
767 sky2->advertising = ctrl;
768
769 /* Set GMAC to no flow control and auto update for speed/duplex */
770 gma_write16(hw, port, GM_GP_CTRL,
771 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
772 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
773
774 /* Set WOL address */
775 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
776 sky2->netdev->dev_addr, ETH_ALEN);
777
778 /* Turn on appropriate WOL control bits */
779 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
780 ctrl = 0;
781 if (sky2->wol & WAKE_PHY)
782 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
783 else
784 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
785
786 if (sky2->wol & WAKE_MAGIC)
787 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
788 else
a419aef8 789 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 790
791 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
792 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
793
5f8ae5c5 794 /* Disable PiG firmware */
795 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
796
e3173832
SH		 797 /* block receiver */
798 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 799}
800
69161611
SH		 801static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
802{
05745c4a
SH		 803 struct net_device *dev = hw->dev[port];
804
ed4d4161
SH		 805 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
806 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 807 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 808 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
810 } else if (dev->mtu > ETH_DATA_LEN) {
811 /* set Tx GMAC FIFO Almost Empty Threshold */
812 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
813 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 814
44dde56d 815 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
816 } else
817 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 818}
819
cd28ab6a
SH		 820static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
821{
822 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
823 u16 reg;
25cccecc 824 u32 rx_reg;
cd28ab6a
SH		 825 int i;
826 const u8 *addr = hw->dev[port]->dev_addr;
827
f350339c
SH		 828 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
829 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 830
831 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
832
4b7c47aa 833 if (hw->chip_id == CHIP_ID_YUKON_XL &&
834 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
835 port == 1) {
cd28ab6a
SH		 836 /* WA DEV_472 -- looks like crossed wires on port 2 */
837 /* clear GMAC 1 Control reset */
838 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
839 do {
840 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
841 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
842 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
843 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
844 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
845 }
846
793b883e 847 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 848
2eaba1a2
SH		 849 /* Enable Transmit FIFO Underrun */
850 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
851
e07b1aa8 852 spin_lock_bh(&sky2->phy_lock);
b96936da 853 sky2_phy_power_up(hw, port);
cd28ab6a 854 sky2_phy_init(hw, port);
e07b1aa8 855 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 856
857 /* MIB clear */
858 reg = gma_read16(hw, port, GM_PHY_ADDR);
859 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
860
43f2f104
SH		 861 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
862 gma_read16(hw, port, i);
cd28ab6a
SH		 863 gma_write16(hw, port, GM_PHY_ADDR, reg);
864
865 /* transmit control */
866 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
867
868 /* receive control reg: unicast + multicast + no FCS */
869 gma_write16(hw, port, GM_RX_CTRL,
793b883e 870 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 871
872 /* transmit flow control */
873 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
874
875 /* transmit parameter */
876 gma_write16(hw, port, GM_TX_PARAM,
877 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
878 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
879 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
880 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
881
882 /* serial mode register */
883 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 884 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 885
6b1a3aef 886 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 887 reg |= GM_SMOD_JUMBO_ENA;
888
c1cd0a85 889 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
890 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
891 reg |= GM_NEW_FLOW_CTRL;
892
cd28ab6a
SH		 893 gma_write16(hw, port, GM_SERIAL_MODE, reg);
894
cd28ab6a
SH		 895 /* virtual address for data */
896 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
897
793b883e
SH		 898 /* physical address: used for pause frames */
899 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
900
901 /* ignore counter overflows */
cd28ab6a
SH		 902 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
903 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
904 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
905
906 /* Configure Rx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 908 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 909 if (hw->chip_id == CHIP_ID_YUKON_EX ||
910 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 911 rx_reg |= GMF_RX_OVER_ON;
69161611 912
25cccecc 913 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 914
798fdd07
SH		 915 if (hw->chip_id == CHIP_ID_YUKON_XL) {
916 /* Hardware errata - clear flush mask */
917 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
918 } else {
919 /* Flush Rx MAC FIFO on any flow control or error */
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
921 }
cd28ab6a 922
8df9a876 923 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 924 reg = RX_GMF_FL_THR_DEF + 1;
925 /* Another magic mystery workaround from sk98lin */
926 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
927 hw->chip_rev == CHIP_REV_YU_FE2_A0)
928 reg = 0x178;
929 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 930
931 /* Configure Tx MAC FIFO */
932 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
933 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 934
25985edc 935 /* On chips without ram buffer, pause is controlled by MAC level */
39dbd958 936 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 937 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 938 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
939 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 940 reg = 1568 / 8;
941 else
942 reg = 1024 / 8;
943 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
944 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 945
69161611 946 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 947 }
948
e970d1f8
SH		 949 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
950 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
951 /* disable dynamic watermark */
952 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
953 reg &= ~TX_DYN_WM_ENA;
954 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
955 }
cd28ab6a
SH		 956}
957
67712901
SH		 958/* Assign Ram Buffer allocation to queue */
959static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 960{
67712901
SH		 961 u32 end;
962
963 /* convert from K bytes to qwords used for hw register */
964 start *= 1024/8;
965 space *= 1024/8;
966 end = start + space - 1;
793b883e 967
cd28ab6a
SH		 968 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
969 sky2_write32(hw, RB_ADDR(q, RB_START), start);
970 sky2_write32(hw, RB_ADDR(q, RB_END), end);
971 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
972 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
973
974 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 975 u32 tp = space - space/4;
793b883e 976
1c28f6ba
SH		 977 /* On receive queue's set the thresholds
978 * give receiver priority when > 3/4 full
979 * send pause when down to 2K
980 */
981 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
982 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 983
1c28f6ba
SH		 984 tp = space - 2048/8;
985 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
986 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 987 } else {
988 /* Enable store & forward on Tx queue's because
989 * Tx FIFO is only 1K on Yukon
990 */
991 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
992 }
993
994 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 995 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 996}
997
cd28ab6a 998/* Setup Bus Memory Interface */
af4ed7e6 999static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1000{
1001 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1002 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1004 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1005}
1006
cd28ab6a
SH		 1007/* Setup prefetch unit registers. This is the interface between
1008 * hardware and driver list elements
1009 */
8cc048e3 1010static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1011 dma_addr_t addr, u32 last)
cd28ab6a 1012{
cd28ab6a
SH		 1013 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1014 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1017 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1019
1020 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1021}
1022
9b289c33 1023static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1024{
9b289c33 1025 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1026
ee5f68fe 1027 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1028 le->ctrl = 0;
793b883e
SH		 1029 return le;
1030}
cd28ab6a 1031
88f5f0ca
SH		 1032static void tx_init(struct sky2_port *sky2)
1033{
1034 struct sky2_tx_le *le;
1035
1036 sky2->tx_prod = sky2->tx_cons = 0;
1037 sky2->tx_tcpsum = 0;
1038 sky2->tx_last_mss = 0;
1039
9b289c33 1040 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1041 le->addr = 0;
1042 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1043 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1044}
1045
290d4de5
SH		 1046/* Update chip's next pointer */
1047static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1048{
50432cb5 1049 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1050 wmb();
50432cb5
SH		 1051 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1052
1053 /* Synchronize I/O on since next processor may write to tail */
1054 mmiowb();
cd28ab6a
SH		 1055}
1056
793b883e 1057
cd28ab6a
SH		 1058static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1059{
1060 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1061 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1062 le->ctrl = 0;
cd28ab6a
SH		 1063 return le;
1064}
1065
060b946c 1066static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
39ef110b
MM		 1067{
1068 unsigned size;
1069
1070 /* Space needed for frame data + headers rounded up */
1071 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1072
1073 /* Stopping point for hardware truncation */
1074 return (size - 8) / sizeof(u32);
1075}
1076
060b946c 1077static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
39ef110b
MM		 1078{
1079 struct rx_ring_info *re;
1080 unsigned size;
1081
1082 /* Space needed for frame data + headers rounded up */
1083 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1084
1085 sky2->rx_nfrags = size >> PAGE_SHIFT;
1086 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1087
1088 /* Compute residue after pages */
1089 size -= sky2->rx_nfrags << PAGE_SHIFT;
1090
1091 /* Optimize to handle small packets and headers */
1092 if (size < copybreak)
1093 size = copybreak;
1094 if (size < ETH_HLEN)
1095 size = ETH_HLEN;
1096
1097 return size;
1098}
1099
14d0263f 1100/* Build description to hardware for one receive segment */
060b946c 1101static void sky2_rx_add(struct sky2_port *sky2, u8 op,
14d0263f 1102 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1103{
1104 struct sky2_rx_le *le;
1105
86c6887e 1106 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1107 le = sky2_next_rx(sky2);
86c6887e 1108 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1109 le->opcode = OP_ADDR64 | HW_OWNER;
1110 }
793b883e 1111
cd28ab6a 1112 le = sky2_next_rx(sky2);
d6e74b6b 1113 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1114 le->length = cpu_to_le16(len);
14d0263f 1115 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1116}
1117
14d0263f
SH		 1118/* Build description to hardware for one possibly fragmented skb */
1119static void sky2_rx_submit(struct sky2_port *sky2,
1120 const struct rx_ring_info *re)
1121{
1122 int i;
1123
1124 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1125
1126 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1127 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1128}
1129
1130
454e6cb6 1131static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1132 unsigned size)
1133{
1134 struct sk_buff *skb = re->skb;
1135 int i;
1136
1137 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1138 if (pci_dma_mapping_error(pdev, re->data_addr))
1139 goto mapping_error;
454e6cb6 1140
7cd26ce5 1141 dma_unmap_len_set(re, data_size, size);
14d0263f 1142
3fbd9187 1143 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1144 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1145
1146 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1147 frag->page_offset,
1148 frag->size,
14d0263f 1149 PCI_DMA_FROMDEVICE);
3fbd9187 1150
1151 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1152 goto map_page_error;
1153 }
454e6cb6 1154 return 0;
3fbd9187 1155
1156map_page_error:
1157 while (--i >= 0) {
1158 pci_unmap_page(pdev, re->frag_addr[i],
1159 skb_shinfo(skb)->frags[i].size,
1160 PCI_DMA_FROMDEVICE);
1161 }
1162
7cd26ce5 1163 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
3fbd9187 1164 PCI_DMA_FROMDEVICE);
1165
1166mapping_error:
1167 if (net_ratelimit())
1168 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1169 skb->dev->name);
1170 return -EIO;
14d0263f
SH		 1171}
1172
1173static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1174{
1175 struct sk_buff *skb = re->skb;
1176 int i;
1177
7cd26ce5 1178 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
14d0263f
SH		 1179 PCI_DMA_FROMDEVICE);
1180
1181 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1182 pci_unmap_page(pdev, re->frag_addr[i],
1183 skb_shinfo(skb)->frags[i].size,
1184 PCI_DMA_FROMDEVICE);
1185}
793b883e 1186
cd28ab6a
SH		 1187/* Tell chip where to start receive checksum.
1188 * Actually has two checksums, but set both same to avoid possible byte
1189 * order problems.
1190 */
793b883e 1191static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1192{
ea76e635 1193 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1194
ea76e635
SH		 1195 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1196 le->ctrl = 0;
1197 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1198
ea76e635
SH		 1199 sky2_write32(sky2->hw,
1200 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1201 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1202 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1203}
1204
bf73130d
SH		 1205/* Enable/disable receive hash calculation (RSS) */
1206static void rx_set_rss(struct net_device *dev)
1207{
1208 struct sky2_port *sky2 = netdev_priv(dev);
1209 struct sky2_hw *hw = sky2->hw;
1210 int i, nkeys = 4;
1211
1212 /* Supports IPv6 and other modes */
1213 if (hw->flags & SKY2_HW_NEW_LE) {
1214 nkeys = 10;
1215 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1216 }
1217
1218 /* Program RSS initial values */
1219 if (dev->features & NETIF_F_RXHASH) {
1220 u32 key[nkeys];
1221
1222 get_random_bytes(key, nkeys * sizeof(u32));
1223 for (i = 0; i < nkeys; i++)
1224 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1225 key[i]);
1226
1227 /* Need to turn on (undocumented) flag to make hashing work */
1228 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1229 RX_STFW_ENA);
1230
1231 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1232 BMU_ENA_RX_RSS_HASH);
1233 } else
1234 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1235 BMU_DIS_RX_RSS_HASH);
1236}
1237
6b1a3aef 1238/*
1239 * The RX Stop command will not work for Yukon-2 if the BMU does not
1240 * reach the end of packet and since we can't make sure that we have
1241 * incoming data, we must reset the BMU while it is not doing a DMA
1242 * transfer. Since it is possible that the RX path is still active,
1243 * the RX RAM buffer will be stopped first, so any possible incoming
1244 * data will not trigger a DMA. After the RAM buffer is stopped, the
1245 * BMU is polled until any DMA in progress is ended and only then it
1246 * will be reset.
1247 */
1248static void sky2_rx_stop(struct sky2_port *sky2)
1249{
1250 struct sky2_hw *hw = sky2->hw;
1251 unsigned rxq = rxqaddr[sky2->port];
1252 int i;
1253
1254 /* disable the RAM Buffer receive queue */
1255 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1256
1257 for (i = 0; i < 0xffff; i++)
1258 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1259 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1260 goto stopped;
1261
ada1db5c 1262 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef 1263stopped:
1264 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1265
1266 /* reset the Rx prefetch unit */
1267 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1268 mmiowb();
6b1a3aef 1269}
793b883e 1270
d571b694 1271/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1272static void sky2_rx_clean(struct sky2_port *sky2)
1273{
1274 unsigned i;
1275
1276 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1277 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1278 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1279
1280 if (re->skb) {
14d0263f 1281 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1282 kfree_skb(re->skb);
1283 re->skb = NULL;
1284 }
1285 }
1286}
1287
ef743d33 1288/* Basic MII support */
1289static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1290{
1291 struct mii_ioctl_data *data = if_mii(ifr);
1292 struct sky2_port *sky2 = netdev_priv(dev);
1293 struct sky2_hw *hw = sky2->hw;
1294 int err = -EOPNOTSUPP;
1295
1296 if (!netif_running(dev))
1297 return -ENODEV; /* Phy still in reset */
1298
d89e1343 1299 switch (cmd) {
ef743d33 1300 case SIOCGMIIPHY:
1301 data->phy_id = PHY_ADDR_MARV;
1302
1303 /* fallthru */
1304 case SIOCGMIIREG: {
1305 u16 val = 0;
91c86df5 1306
e07b1aa8 1307 spin_lock_bh(&sky2->phy_lock);
ef743d33 1308 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1309 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1310
ef743d33 1311 data->val_out = val;
1312 break;
1313 }
1314
1315 case SIOCSMIIREG:
e07b1aa8 1316 spin_lock_bh(&sky2->phy_lock);
ef743d33 1317 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1318 data->val_in);
e07b1aa8 1319 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1320 break;
1321 }
1322 return err;
1323}
1324
86aa7785 1325#define NETIF_F_ALL_VLAN (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)
d494eacd 1326
86aa7785 1327static void sky2_vlan_mode(struct net_device *dev)
d494eacd
SH		 1328{
1329 struct sky2_port *sky2 = netdev_priv(dev);
1330 struct sky2_hw *hw = sky2->hw;
1331 u16 port = sky2->port;
1332
86aa7785
SH		 1333 if (dev->features & NETIF_F_HW_VLAN_RX)
1334 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1335 RX_VLAN_STRIP_ON);
1336 else
1337 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1338 RX_VLAN_STRIP_OFF);
d494eacd 1339
86aa7785
SH		 1340 dev->vlan_features = dev->features &~ NETIF_F_ALL_VLAN;
1341 if (dev->features & NETIF_F_HW_VLAN_TX)
1342 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1343 TX_VLAN_TAG_ON);
1344 else {
1345 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1346 TX_VLAN_TAG_OFF);
d1f13708 1347
86aa7785
SH		 1348 /* Can't do transmit offload of vlan without hw vlan */
1349 dev->vlan_features &= ~(NETIF_F_TSO | NETIF_F_SG
1350 | NETIF_F_ALL_CSUM);
1351 }
d1f13708 1352}
d1f13708 1353
bd1c6869
SH		 1354/* Amount of required worst case padding in rx buffer */
1355static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1356{
1357 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1358}
1359
82788c7a 1360/*
14d0263f
SH		 1361 * Allocate an skb for receiving. If the MTU is large enough
1362 * make the skb non-linear with a fragment list of pages.
82788c7a 1363 */
14d0263f 1364static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1365{
1366 struct sk_buff *skb;
14d0263f 1367 int i;
82788c7a 1368
724b6942
SH		 1369 skb = netdev_alloc_skb(sky2->netdev,
1370 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1371 if (!skb)
1372 goto nomem;
1373
39dbd958 1374 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1375 unsigned char *start;
1376 /*
1377 * Workaround for a bug in FIFO that cause hang
1378 * if the FIFO if the receive buffer is not 64 byte aligned.
1379 * The buffer returned from netdev_alloc_skb is
1380 * aligned except if slab debugging is enabled.
1381 */
f03b8654
SH		 1382 start = PTR_ALIGN(skb->data, 8);
1383 skb_reserve(skb, start - skb->data);
bd1c6869 1384 } else
f03b8654 1385 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1386
1387 for (i = 0; i < sky2->rx_nfrags; i++) {
1388 struct page *page = alloc_page(GFP_ATOMIC);
1389
1390 if (!page)
1391 goto free_partial;
1392 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1393 }
1394
1395 return skb;
14d0263f
SH		 1396free_partial:
1397 kfree_skb(skb);
1398nomem:
1399 return NULL;
82788c7a
SH		 1400}
1401
55c9dd35
SH		 1402static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1403{
1404 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1405}
1406
200ac492
MM		 1407static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1408{
1409 struct sky2_hw *hw = sky2->hw;
1410 unsigned i;
1411
1412 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1413
1414 /* Fill Rx ring */
1415 for (i = 0; i < sky2->rx_pending; i++) {
1416 struct rx_ring_info *re = sky2->rx_ring + i;
1417
1418 re->skb = sky2_rx_alloc(sky2);
1419 if (!re->skb)
1420 return -ENOMEM;
1421
1422 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1423 dev_kfree_skb(re->skb);
1424 re->skb = NULL;
1425 return -ENOMEM;
1426 }
1427 }
1428 return 0;
1429}
1430
cd28ab6a 1431/*
200ac492 1432 * Setup receiver buffer pool.
14d0263f
SH		 1433 * Normal case this ends up creating one list element for skb
1434 * in the receive ring. Worst case if using large MTU and each
1435 * allocation falls on a different 64 bit region, that results
1436 * in 6 list elements per ring entry.
1437 * One element is used for checksum enable/disable, and one
1438 * extra to avoid wrap.
cd28ab6a 1439 */
200ac492 1440static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1441{
6b1a3aef 1442 struct sky2_hw *hw = sky2->hw;
14d0263f 1443 struct rx_ring_info *re;
6b1a3aef 1444 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1445 unsigned i, thresh;
cd28ab6a 1446
6b1a3aef 1447 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1448 sky2_qset(hw, rxq);
977bdf06 1449
c3905bc4
SH		 1450 /* On PCI express lowering the watermark gives better performance */
1451 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1452 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1453
1454 /* These chips have no ram buffer?
1455 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1456 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1457 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1458 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1459
6b1a3aef 1460 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1461
ea76e635
SH		 1462 if (!(hw->flags & SKY2_HW_NEW_LE))
1463 rx_set_checksum(sky2);
14d0263f 1464
bf73130d
SH		 1465 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1466 rx_set_rss(sky2->netdev);
1467
200ac492 1468 /* submit Rx ring */
793b883e 1469 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1470 re = sky2->rx_ring + i;
14d0263f 1471 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1472 }
1473
a1433ac4
SH		 1474 /*
1475 * The receiver hangs if it receives frames larger than the
1476 * packet buffer. As a workaround, truncate oversize frames, but
1477 * the register is limited to 9 bits, so if you do frames > 2052
1478 * you better get the MTU right!
1479 */
39ef110b 1480 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1481 if (thresh > 0x1ff)
1482 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1483 else {
1484 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1485 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1486 }
1487
6b1a3aef 1488 /* Tell chip about available buffers */
55c9dd35 1489 sky2_rx_update(sky2, rxq);
877c8570
SH		 1490
1491 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1492 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1493 /*
1494 * Disable flushing of non ASF packets;
1495 * must be done after initializing the BMUs;
1496 * drivers without ASF support should do this too, otherwise
1497 * it may happen that they cannot run on ASF devices;
1498 * remember that the MAC FIFO isn't reset during initialization.
1499 */
1500 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1501 }
1502
1503 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1504 /* Enable RX Home Address & Routing Header checksum fix */
1505 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1506 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1507
1508 /* Enable TX Home Address & Routing Header checksum fix */
1509 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1510 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1511 }
cd28ab6a
SH		 1512}
1513
90bbebb4
MM		 1514static int sky2_alloc_buffers(struct sky2_port *sky2)
1515{
1516 struct sky2_hw *hw = sky2->hw;
1517
1518 /* must be power of 2 */
1519 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1520 sky2->tx_ring_size *
1521 sizeof(struct sky2_tx_le),
1522 &sky2->tx_le_map);
1523 if (!sky2->tx_le)
1524 goto nomem;
1525
1526 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1527 GFP_KERNEL);
1528 if (!sky2->tx_ring)
1529 goto nomem;
1530
1531 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1532 &sky2->rx_le_map);
1533 if (!sky2->rx_le)
1534 goto nomem;
1535 memset(sky2->rx_le, 0, RX_LE_BYTES);
1536
1537 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1538 GFP_KERNEL);
1539 if (!sky2->rx_ring)
1540 goto nomem;
1541
200ac492 1542 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1543nomem:
1544 return -ENOMEM;
1545}
1546
1547static void sky2_free_buffers(struct sky2_port *sky2)
1548{
1549 struct sky2_hw *hw = sky2->hw;
1550
200ac492
MM		 1551 sky2_rx_clean(sky2);
1552
90bbebb4
MM		 1553 if (sky2->rx_le) {
1554 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1555 sky2->rx_le, sky2->rx_le_map);
1556 sky2->rx_le = NULL;
1557 }
1558 if (sky2->tx_le) {
1559 pci_free_consistent(hw->pdev,
1560 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1561 sky2->tx_le, sky2->tx_le_map);
1562 sky2->tx_le = NULL;
1563 }
1564 kfree(sky2->tx_ring);
1565 kfree(sky2->rx_ring);
1566
1567 sky2->tx_ring = NULL;
1568 sky2->rx_ring = NULL;
1569}
1570
ea0f71e5 1571static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1572{
cd28ab6a
SH		 1573 struct sky2_hw *hw = sky2->hw;
1574 unsigned port = sky2->port;
ea0f71e5
MM		 1575 u32 ramsize;
1576 int cap;
843a46f4 1577 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1578
ea0f71e5
MM		 1579 tx_init(sky2);
1580
ee7abb04
SH		 1581 /*
1582 * On dual port PCI-X card, there is an problem where status
1583 * can be received out of order due to split transactions
843a46f4 1584 */
ee7abb04
SH		 1585 if (otherdev && netif_running(otherdev) &&
1586 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1587 u16 cmd;
1588
b32f40c4 1589 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1590 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1591 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1592 }
cd28ab6a 1593
cd28ab6a
SH		 1594 sky2_mac_init(hw, port);
1595
e0c28116
SH		 1596 /* Register is number of 4K blocks on internal RAM buffer. */
1597 ramsize = sky2_read8(hw, B2_E_0) * 4;
1598 if (ramsize > 0) {
67712901 1599 u32 rxspace;
cd28ab6a 1600
ada1db5c 1601 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1602 if (ramsize < 16)
1603 rxspace = ramsize / 2;
1604 else
1605 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1606
67712901
SH		 1607 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1608 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1609
1610 /* Make sure SyncQ is disabled */
1611 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1612 RB_RST_SET);
1613 }
793b883e 1614
af4ed7e6 1615 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1616
69161611
SH		 1617 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1618 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1619 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1620
977bdf06 1621 /* Set almost empty threshold */
8e95a202
JP		 1622 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1623 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1624 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1625
6b1a3aef 1626 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1627 sky2->tx_ring_size - 1);
cd28ab6a 1628
86aa7785 1629 sky2_vlan_mode(sky2->netdev);
d494eacd 1630
200ac492 1631 sky2_rx_start(sky2);
ea0f71e5
MM		 1632}
1633
1634/* Bring up network interface. */
1635static int sky2_up(struct net_device *dev)
1636{
1637 struct sky2_port *sky2 = netdev_priv(dev);
1638 struct sky2_hw *hw = sky2->hw;
1639 unsigned port = sky2->port;
1640 u32 imask;
1641 int err;
1642
1643 netif_carrier_off(dev);
1644
1645 err = sky2_alloc_buffers(sky2);
1646 if (err)
1647 goto err_out;
1648
1649 sky2_hw_up(sky2);
cd28ab6a 1650
cd28ab6a 1651 /* Enable interrupts from phy/mac for port */
e07b1aa8 1652 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1653 imask |= portirq_msk[port];
e07b1aa8 1654 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1655 sky2_read32(hw, B0_IMSK);
e07b1aa8 1656
6c35abae 1657 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1658
cd28ab6a
SH		 1659 return 0;
1660
1661err_out:
90bbebb4 1662 sky2_free_buffers(sky2);
cd28ab6a
SH		 1663 return err;
1664}
1665
793b883e 1666/* Modular subtraction in ring */
ee5f68fe 1667static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1668{
ee5f68fe 1669 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1670}
cd28ab6a 1671
793b883e
SH		 1672/* Number of list elements available for next tx */
1673static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1674{
ee5f68fe 1675 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1676}
1677
793b883e 1678/* Estimate of number of transmit list elements required */
28bd181a 1679static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1680{
793b883e
SH		 1681 unsigned count;
1682
07e31637
SH		 1683 count = (skb_shinfo(skb)->nr_frags + 1)
1684 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1685
89114afd 1686 if (skb_is_gso(skb))
793b883e 1687 ++count;
07e31637
SH		 1688 else if (sizeof(dma_addr_t) == sizeof(u32))
1689 ++count; /* possible vlan */
793b883e 1690
84fa7933 1691 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1692 ++count;
1693
1694 return count;
cd28ab6a
SH		 1695}
1696
f6815077 1697static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1698{
1699 if (re->flags & TX_MAP_SINGLE)
7cd26ce5
FT		 1700 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1701 dma_unmap_len(re, maplen),
6b84daca
SH		 1702 PCI_DMA_TODEVICE);
1703 else if (re->flags & TX_MAP_PAGE)
7cd26ce5
FT		 1704 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1705 dma_unmap_len(re, maplen),
6b84daca 1706 PCI_DMA_TODEVICE);
f6815077 1707 re->flags = 0;
6b84daca
SH		 1708}
1709
793b883e
SH		 1710/*
1711 * Put one packet in ring for transmit.
1712 * A single packet can generate multiple list elements, and
1713 * the number of ring elements will probably be less than the number
1714 * of list elements used.
1715 */
61357325
SH		 1716static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1717 struct net_device *dev)
cd28ab6a
SH		 1718{
1719 struct sky2_port *sky2 = netdev_priv(dev);
1720 struct sky2_hw *hw = sky2->hw;
d1f13708 1721 struct sky2_tx_le *le = NULL;
6cdbbdf3 1722 struct tx_ring_info *re;
9b289c33 1723 unsigned i, len;
cd28ab6a 1724 dma_addr_t mapping;
5dce95e5
SH		 1725 u32 upper;
1726 u16 slot;
cd28ab6a
SH		 1727 u16 mss;
1728 u8 ctrl;
1729
2bb8c262
SH		 1730 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1731 return NETDEV_TX_BUSY;
cd28ab6a 1732
cd28ab6a
SH		 1733 len = skb_headlen(skb);
1734 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1735
454e6cb6
SH		 1736 if (pci_dma_mapping_error(hw->pdev, mapping))
1737 goto mapping_error;
1738
9b289c33 1739 slot = sky2->tx_prod;
6c35abae
JP		 1740 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1741 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1742
86c6887e 1743 /* Send high bits if needed */
5dce95e5
SH		 1744 upper = upper_32_bits(mapping);
1745 if (upper != sky2->tx_last_upper) {
9b289c33 1746 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1747 le->addr = cpu_to_le32(upper);
1748 sky2->tx_last_upper = upper;
793b883e 1749 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1750 }
cd28ab6a
SH		 1751
1752 /* Check for TCP Segmentation Offload */
7967168c 1753 mss = skb_shinfo(skb)->gso_size;
793b883e 1754 if (mss != 0) {
ea76e635
SH		 1755
1756 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1757 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1758
1759 if (mss != sky2->tx_last_mss) {
9b289c33 1760 le = get_tx_le(sky2, &slot);
69161611 1761 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1762
1763 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1764 le->opcode = OP_MSS | HW_OWNER;
1765 else
1766 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1767 sky2->tx_last_mss = mss;
1768 }
cd28ab6a
SH		 1769 }
1770
cd28ab6a 1771 ctrl = 0;
86aa7785 1772
d1f13708 1773 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
eab6d18d 1774 if (vlan_tx_tag_present(skb)) {
d1f13708 1775 if (!le) {
9b289c33 1776 le = get_tx_le(sky2, &slot);
f65b138c 1777 le->addr = 0;
d1f13708 1778 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1779 } else
1780 le->opcode |= OP_VLAN;
1781 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1782 ctrl |= INS_VLAN;
1783 }
d1f13708 1784
1785 /* Handle TCP checksum offload */
84fa7933 1786 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1787 /* On Yukon EX (some versions) encoding change. */
ea76e635 1788 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1789 ctrl |= CALSUM; /* auto checksum */
1790 else {
1791 const unsigned offset = skb_transport_offset(skb);
1792 u32 tcpsum;
1793
1794 tcpsum = offset << 16; /* sum start */
1795 tcpsum |= offset + skb->csum_offset; /* sum write */
1796
1797 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1798 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1799 ctrl |= UDPTCP;
1800
1801 if (tcpsum != sky2->tx_tcpsum) {
1802 sky2->tx_tcpsum = tcpsum;
1803
9b289c33 1804 le = get_tx_le(sky2, &slot);
69161611
SH		 1805 le->addr = cpu_to_le32(tcpsum);
1806 le->length = 0; /* initial checksum value */
1807 le->ctrl = 1; /* one packet */
1808 le->opcode = OP_TCPLISW | HW_OWNER;
1809 }
1d179332 1810 }
cd28ab6a
SH		 1811 }
1812
6b84daca
SH		 1813 re = sky2->tx_ring + slot;
1814 re->flags = TX_MAP_SINGLE;
7cd26ce5
FT		 1815 dma_unmap_addr_set(re, mapaddr, mapping);
1816 dma_unmap_len_set(re, maplen, len);
6b84daca 1817
9b289c33 1818 le = get_tx_le(sky2, &slot);
d6e74b6b 1819 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1820 le->length = cpu_to_le16(len);
1821 le->ctrl = ctrl;
793b883e 1822 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1823
cd28ab6a
SH		 1824
1825 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1826 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1827
1828 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1829 frag->size, PCI_DMA_TODEVICE);
86c6887e 1830
454e6cb6
SH		 1831 if (pci_dma_mapping_error(hw->pdev, mapping))
1832 goto mapping_unwind;
1833
5dce95e5
SH		 1834 upper = upper_32_bits(mapping);
1835 if (upper != sky2->tx_last_upper) {
9b289c33 1836 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1837 le->addr = cpu_to_le32(upper);
1838 sky2->tx_last_upper = upper;
793b883e 1839 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1840 }
1841
6b84daca
SH		 1842 re = sky2->tx_ring + slot;
1843 re->flags = TX_MAP_PAGE;
7cd26ce5
FT		 1844 dma_unmap_addr_set(re, mapaddr, mapping);
1845 dma_unmap_len_set(re, maplen, frag->size);
6b84daca 1846
9b289c33 1847 le = get_tx_le(sky2, &slot);
d6e74b6b 1848 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1849 le->length = cpu_to_le16(frag->size);
1850 le->ctrl = ctrl;
793b883e 1851 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1852 }
6cdbbdf3 1853
6b84daca 1854 re->skb = skb;
cd28ab6a
SH		 1855 le->ctrl |= EOP;
1856
9b289c33
MM		 1857 sky2->tx_prod = slot;
1858
97bda706 1859 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1860 netif_stop_queue(dev);
b19666d9 1861
290d4de5 1862 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1863
cd28ab6a 1864 return NETDEV_TX_OK;
454e6cb6
SH		 1865
1866mapping_unwind:
ee5f68fe 1867 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1868 re = sky2->tx_ring + i;
1869
6b84daca 1870 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1871 }
1872
454e6cb6
SH		 1873mapping_error:
1874 if (net_ratelimit())
1875 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1876 dev_kfree_skb(skb);
1877 return NETDEV_TX_OK;
cd28ab6a
SH		 1878}
1879
cd28ab6a 1880/*
793b883e
SH		 1881 * Free ring elements from starting at tx_cons until "done"
1882 *
481cea4a
SH		 1883 * NB:
1884 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1885 * buffers so make sure not to free skb to early.
481cea4a
SH		 1886 * 2. This may run in parallel start_xmit because the it only
1887 * looks at the tail of the queue of FIFO (tx_cons), not
1888 * the head (tx_prod)
cd28ab6a 1889 */
d11c13e7 1890static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1891{
d11c13e7 1892 struct net_device *dev = sky2->netdev;
291ea614 1893 unsigned idx;
cd28ab6a 1894
ee5f68fe 1895 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1896
291ea614 1897 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1898 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1899 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1900 struct sk_buff *skb = re->skb;
291ea614 1901
6b84daca 1902 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1903
6b84daca 1904 if (skb) {
6c35abae
JP		 1905 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1906 "tx done %u\n", idx);
3cf26753 1907
0885a30b 1908 u64_stats_update_begin(&sky2->tx_stats.syncp);
1909 ++sky2->tx_stats.packets;
1910 sky2->tx_stats.bytes += skb->len;
1911 u64_stats_update_end(&sky2->tx_stats.syncp);
bd1c6869 1912
f6815077 1913 re->skb = NULL;
724b6942 1914 dev_kfree_skb_any(skb);
2bf56fe2 1915
ee5f68fe 1916 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1917 }
793b883e 1918 }
793b883e 1919
291ea614 1920 sky2->tx_cons = idx;
50432cb5 1921 smp_mb();
cd28ab6a
SH		 1922}
1923
264bb4fa 1924static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1925{
a510996b
MM		 1926 /* Disable Force Sync bit and Enable Alloc bit */
1927 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1928 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1929
1930 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1931 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1932 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1933
1934 /* Reset the PCI FIFO of the async Tx queue */
1935 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1936 BMU_RST_SET | BMU_FIFO_RST);
1937
1938 /* Reset the Tx prefetch units */
1939 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1940 PREF_UNIT_RST_SET);
1941
1942 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1943 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1944}
1945
f2b31cb3 1946static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 1947{
cd28ab6a
SH		 1948 struct sky2_hw *hw = sky2->hw;
1949 unsigned port = sky2->port;
f2b31cb3 1950 u16 ctrl;
cd28ab6a 1951
d104acaf
SH		 1952 /* Force flow control off */
1953 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1954
cd28ab6a
SH		 1955 /* Stop transmitter */
1956 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1957 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1958
1959 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1960 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1961
1962 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1963 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1964 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1965
1966 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1967
1968 /* Workaround shared GMAC reset */
8e95a202
JP		 1969 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1970 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1971 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1972
cd28ab6a 1973 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1974
6c83504f
SH		 1975 /* Force any delayed status interrrupt and NAPI */
1976 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1977 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1978 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1979 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1980
a947a39d
MM		 1981 sky2_rx_stop(sky2);
1982
0da6d7b3 1983 spin_lock_bh(&sky2->phy_lock);
b96936da 1984 sky2_phy_power_down(hw, port);
0da6d7b3 1985 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1986
264bb4fa
MM		 1987 sky2_tx_reset(hw, port);
1988
481cea4a
SH		 1989 /* Free any pending frames stuck in HW queue */
1990 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 1991}
1992
1993/* Network shutdown */
1994static int sky2_down(struct net_device *dev)
1995{
1996 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 1997 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 1998
1999 /* Never really got started! */
2000 if (!sky2->tx_le)
2001 return 0;
2002
6c35abae 2003 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 2004
8a0c9228
MM		 2005 /* Disable port IRQ */
2006 sky2_write32(hw, B0_IMSK,
2007 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2008 sky2_read32(hw, B0_IMSK);
2009
2010 synchronize_irq(hw->pdev->irq);
2011 napi_synchronize(&hw->napi);
2012
f2b31cb3 2013 sky2_hw_down(sky2);
481cea4a 2014
90bbebb4 2015 sky2_free_buffers(sky2);
1b537565 2016
cd28ab6a
SH		 2017 return 0;
2018}
2019
2020static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2021{
ea76e635 2022 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 2023 return SPEED_1000;
2024
05745c4a
SH		 2025 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2026 if (aux & PHY_M_PS_SPEED_100)
2027 return SPEED_100;
2028 else
2029 return SPEED_10;
2030 }
cd28ab6a
SH		 2031
2032 switch (aux & PHY_M_PS_SPEED_MSK) {
2033 case PHY_M_PS_SPEED_1000:
2034 return SPEED_1000;
2035 case PHY_M_PS_SPEED_100:
2036 return SPEED_100;
2037 default:
2038 return SPEED_10;
2039 }
2040}
2041
2042static void sky2_link_up(struct sky2_port *sky2)
2043{
2044 struct sky2_hw *hw = sky2->hw;
2045 unsigned port = sky2->port;
16ad91e1
SH		 2046 static const char *fc_name[] = {
2047 [FC_NONE] = "none",
2048 [FC_TX] = "tx",
2049 [FC_RX] = "rx",
2050 [FC_BOTH] = "both",
2051 };
cd28ab6a 2052
38000a94 2053 sky2_enable_rx_tx(sky2);
cd28ab6a
SH		 2054
2055 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2056
2057 netif_carrier_on(sky2->netdev);
cd28ab6a 2058
75e80683 2059 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2060
cd28ab6a 2061 /* Turn on link LED */
793b883e 2062 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2063 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2064
6c35abae
JP		 2065 netif_info(sky2, link, sky2->netdev,
2066 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2067 sky2->speed,
2068 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2069 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2070}
2071
2072static void sky2_link_down(struct sky2_port *sky2)
2073{
2074 struct sky2_hw *hw = sky2->hw;
2075 unsigned port = sky2->port;
2076 u16 reg;
2077
2078 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2079
2080 reg = gma_read16(hw, port, GM_GP_CTRL);
2081 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2082 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2083
cd28ab6a 2084 netif_carrier_off(sky2->netdev);
cd28ab6a 2085
809aaaae 2086 /* Turn off link LED */
cd28ab6a
SH		 2087 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2088
6c35abae 2089 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2090
cd28ab6a
SH		 2091 sky2_phy_init(hw, port);
2092}
2093
16ad91e1
SH		 2094static enum flow_control sky2_flow(int rx, int tx)
2095{
2096 if (rx)
2097 return tx ? FC_BOTH : FC_RX;
2098 else
2099 return tx ? FC_TX : FC_NONE;
2100}
2101
793b883e
SH		 2102static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2103{
2104 struct sky2_hw *hw = sky2->hw;
2105 unsigned port = sky2->port;
da4c1ff4 2106 u16 advert, lpa;
793b883e 2107
da4c1ff4 2108 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2109 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2110 if (lpa & PHY_M_AN_RF) {
ada1db5c 2111 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2112 return -1;
2113 }
2114
793b883e 2115 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2116 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2117 return -1;
2118 }
2119
793b883e 2120 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2121 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2122
da4c1ff4
SH		 2123 /* Since the pause result bits seem to in different positions on
2124 * different chips. look at registers.
2125 */
ea76e635 2126 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2127 /* Shift for bits in fiber PHY */
2128 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2129 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2130
2131 if (advert & ADVERTISE_1000XPAUSE)
2132 advert |= ADVERTISE_PAUSE_CAP;
2133 if (advert & ADVERTISE_1000XPSE_ASYM)
2134 advert |= ADVERTISE_PAUSE_ASYM;
2135 if (lpa & LPA_1000XPAUSE)
2136 lpa |= LPA_PAUSE_CAP;
2137 if (lpa & LPA_1000XPAUSE_ASYM)
2138 lpa |= LPA_PAUSE_ASYM;
2139 }
793b883e 2140
da4c1ff4
SH		 2141 sky2->flow_status = FC_NONE;
2142 if (advert & ADVERTISE_PAUSE_CAP) {
2143 if (lpa & LPA_PAUSE_CAP)
2144 sky2->flow_status = FC_BOTH;
2145 else if (advert & ADVERTISE_PAUSE_ASYM)
2146 sky2->flow_status = FC_RX;
2147 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2148 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2149 sky2->flow_status = FC_TX;
2150 }
793b883e 2151
8e95a202
JP		 2152 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2153 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2154 sky2->flow_status = FC_NONE;
2eaba1a2 2155
da4c1ff4 2156 if (sky2->flow_status & FC_TX)
793b883e
SH		 2157 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2158 else
2159 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2160
2161 return 0;
2162}
cd28ab6a 2163
e07b1aa8
SH		 2164/* Interrupt from PHY */
2165static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2166{
e07b1aa8
SH		 2167 struct net_device *dev = hw->dev[port];
2168 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2169 u16 istatus, phystat;
2170
ebc646f6
SH		 2171 if (!netif_running(dev))
2172 return;
2173
e07b1aa8
SH		 2174 spin_lock(&sky2->phy_lock);
2175 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2176 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2177
6c35abae
JP		 2178 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2179 istatus, phystat);
cd28ab6a 2180
0ea065e5 2181 if (istatus & PHY_M_IS_AN_COMPL) {
9badba25 2182 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2183 !netif_carrier_ok(dev))
793b883e
SH		 2184 sky2_link_up(sky2);
2185 goto out;
2186 }
cd28ab6a 2187
793b883e
SH		 2188 if (istatus & PHY_M_IS_LSP_CHANGE)
2189 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2190
793b883e
SH		 2191 if (istatus & PHY_M_IS_DUP_CHANGE)
2192 sky2->duplex =
2193 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2194
793b883e
SH		 2195 if (istatus & PHY_M_IS_LST_CHANGE) {
2196 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2197 sky2_link_up(sky2);
793b883e
SH		 2198 else
2199 sky2_link_down(sky2);
cd28ab6a 2200 }
793b883e 2201out:
e07b1aa8 2202 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2203}
2204
0f5aac70
SH		 2205/* Special quick link interrupt (Yukon-2 Optima only) */
2206static void sky2_qlink_intr(struct sky2_hw *hw)
2207{
2208 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2209 u32 imask;
2210 u16 phy;
2211
2212 /* disable irq */
2213 imask = sky2_read32(hw, B0_IMSK);
2214 imask &= ~Y2_IS_PHY_QLNK;
2215 sky2_write32(hw, B0_IMSK, imask);
2216
2217 /* reset PHY Link Detect */
2218 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2219 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2220 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2221 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2222
2223 sky2_link_up(sky2);
2224}
2225
62335ab0 2226/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2227 * and tx queue is full (stopped).
2228 */
cd28ab6a
SH		 2229static void sky2_tx_timeout(struct net_device *dev)
2230{
2231 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2232 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2233
6c35abae 2234 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2235
ada1db5c
JP		 2236 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2237 sky2->tx_cons, sky2->tx_prod,
2238 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2239 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2240
81906791
SH		 2241 /* can't restart safely under softirq */
2242 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2243}
2244
2245static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2246{
6b1a3aef 2247 struct sky2_port *sky2 = netdev_priv(dev);
2248 struct sky2_hw *hw = sky2->hw;
b628ed98 2249 unsigned port = sky2->port;
6b1a3aef 2250 int err;
2251 u16 ctl, mode;
e07b1aa8 2252 u32 imask;
cd28ab6a 2253
44dde56d 2254 /* MTU size outside the spec */
cd28ab6a
SH		 2255 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2256 return -EINVAL;
2257
44dde56d 2258 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2259 if (new_mtu > ETH_DATA_LEN &&
2260 (hw->chip_id == CHIP_ID_YUKON_FE ||
2261 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2262 return -EINVAL;
2263
44dde56d 2264 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2265 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2266 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2267
6b1a3aef 2268 if (!netif_running(dev)) {
2269 dev->mtu = new_mtu;
2270 return 0;
2271 }
2272
e07b1aa8 2273 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2274 sky2_write32(hw, B0_IMSK, 0);
2275
018d1c66 2276 dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 2277 napi_disable(&hw->napi);
df01093b 2278 netif_tx_disable(dev);
018d1c66 2279
e07b1aa8
SH		 2280 synchronize_irq(hw->pdev->irq);
2281
39dbd958 2282 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2283 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2284
2285 ctl = gma_read16(hw, port, GM_GP_CTRL);
2286 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2287 sky2_rx_stop(sky2);
2288 sky2_rx_clean(sky2);
cd28ab6a
SH		 2289
2290 dev->mtu = new_mtu;
14d0263f 2291
6b1a3aef 2292 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2293 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2294
2295 if (dev->mtu > ETH_DATA_LEN)
2296 mode |= GM_SMOD_JUMBO_ENA;
2297
b628ed98 2298 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2299
b628ed98 2300 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2301
200ac492
MM		 2302 err = sky2_alloc_rx_skbs(sky2);
2303 if (!err)
2304 sky2_rx_start(sky2);
2305 else
2306 sky2_rx_clean(sky2);
e07b1aa8 2307 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2308
d1d08d12 2309 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2310 napi_enable(&hw->napi);
2311
1b537565
SH		 2312 if (err)
2313 dev_close(dev);
2314 else {
b628ed98 2315 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2316
1b537565
SH		 2317 netif_wake_queue(dev);
2318 }
2319
cd28ab6a
SH		 2320 return err;
2321}
2322
14d0263f
SH		 2323/* For small just reuse existing skb for next receive */
2324static struct sk_buff *receive_copy(struct sky2_port *sky2,
2325 const struct rx_ring_info *re,
2326 unsigned length)
2327{
2328 struct sk_buff *skb;
2329
89d71a66 2330 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2331 if (likely(skb)) {
14d0263f
SH		 2332 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2333 length, PCI_DMA_FROMDEVICE);
d626f62b 2334 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2335 skb->ip_summed = re->skb->ip_summed;
2336 skb->csum = re->skb->csum;
2337 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2338 length, PCI_DMA_FROMDEVICE);
2339 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2340 skb_put(skb, length);
14d0263f
SH		 2341 }
2342 return skb;
2343}
2344
2345/* Adjust length of skb with fragments to match received data */
2346static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2347 unsigned int length)
2348{
2349 int i, num_frags;
2350 unsigned int size;
2351
2352 /* put header into skb */
2353 size = min(length, hdr_space);
2354 skb->tail += size;
2355 skb->len += size;
2356 length -= size;
2357
2358 num_frags = skb_shinfo(skb)->nr_frags;
2359 for (i = 0; i < num_frags; i++) {
2360 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2361
2362 if (length == 0) {
2363 /* don't need this page */
2364 __free_page(frag->page);
2365 --skb_shinfo(skb)->nr_frags;
2366 } else {
2367 size = min(length, (unsigned) PAGE_SIZE);
2368
2369 frag->size = size;
2370 skb->data_len += size;
2371 skb->truesize += size;
2372 skb->len += size;
2373 length -= size;
2374 }
2375 }
2376}
2377
2378/* Normal packet - take skb from ring element and put in a new one */
2379static struct sk_buff *receive_new(struct sky2_port *sky2,
2380 struct rx_ring_info *re,
2381 unsigned int length)
2382{
3fbd9187 2383 struct sk_buff *skb;
2384 struct rx_ring_info nre;
14d0263f
SH		 2385 unsigned hdr_space = sky2->rx_data_size;
2386
3fbd9187 2387 nre.skb = sky2_rx_alloc(sky2);
2388 if (unlikely(!nre.skb))
2389 goto nobuf;
2390
2391 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2392 goto nomap;
14d0263f
SH		 2393
2394 skb = re->skb;
2395 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2396 prefetch(skb->data);
3fbd9187 2397 *re = nre;
14d0263f
SH		 2398
2399 if (skb_shinfo(skb)->nr_frags)
2400 skb_put_frags(skb, hdr_space, length);
2401 else
489b10c1 2402 skb_put(skb, length);
14d0263f 2403 return skb;
3fbd9187 2404
2405nomap:
2406 dev_kfree_skb(nre.skb);
2407nobuf:
2408 return NULL;
14d0263f
SH		 2409}
2410
cd28ab6a
SH		 2411/*
2412 * Receive one packet.
d571b694 2413 * For larger packets, get new buffer.
cd28ab6a 2414 */
497d7c86 2415static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2416 u16 length, u32 status)
2417{
497d7c86 2418 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2419 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2420 struct sk_buff *skb = NULL;
d6532232
SH		 2421 u16 count = (status & GMR_FS_LEN) >> 16;
2422
86aa7785
SH		 2423 if (status & GMR_FS_VLAN)
2424 count -= VLAN_HLEN; /* Account for vlan tag */
cd28ab6a 2425
6c35abae
JP		 2426 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2427 "rx slot %u status 0x%x len %d\n",
2428 sky2->rx_next, status, length);
cd28ab6a 2429
793b883e 2430 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2431 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2432
3b12e014
SH		 2433 /* This chip has hardware problems that generates bogus status.
2434 * So do only marginal checking and expect higher level protocols
2435 * to handle crap frames.
2436 */
2437 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2438 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2439 length != count)
2440 goto okay;
2441
42eeea01 2442 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2443 goto error;
2444
42eeea01 2445 if (!(status & GMR_FS_RX_OK))
2446 goto resubmit;
2447
d6532232
SH		 2448 /* if length reported by DMA does not match PHY, packet was truncated */
2449 if (length != count)
0885a30b 2450 goto error;
71749531 2451
3b12e014 2452okay:
14d0263f
SH		 2453 if (length < copybreak)
2454 skb = receive_copy(sky2, re, length);
2455 else
2456 skb = receive_new(sky2, re, length);
90c30335
SH		 2457
2458 dev->stats.rx_dropped += (skb == NULL);
2459
793b883e 2460resubmit:
14d0263f 2461 sky2_rx_submit(sky2, re);
79e57d32 2462
cd28ab6a
SH		 2463 return skb;
2464
2465error:
7138a0f5 2466 ++dev->stats.rx_errors;
6e15b712 2467
6c35abae
JP		 2468 if (net_ratelimit())
2469 netif_info(sky2, rx_err, dev,
2470 "rx error, status 0x%x length %d\n", status, length);
793b883e 2471
793b883e 2472 goto resubmit;
cd28ab6a
SH		 2473}
2474
e07b1aa8
SH		 2475/* Transmit complete */
2476static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2477{
e07b1aa8 2478 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2479
8a0c9228 2480 if (netif_running(dev)) {
e07b1aa8 2481 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2482
2483 /* Wake unless it's detached, and called e.g. from sky2_down() */
2484 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2485 netif_wake_queue(dev);
2486 }
cd28ab6a
SH		 2487}
2488
37e5a243
SH		 2489static inline void sky2_skb_rx(const struct sky2_port *sky2,
2490 u32 status, struct sk_buff *skb)
2491{
86aa7785
SH		 2492 if (status & GMR_FS_VLAN)
2493 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2494
37e5a243
SH		 2495 if (skb->ip_summed == CHECKSUM_NONE)
2496 netif_receive_skb(skb);
2497 else
2498 napi_gro_receive(&sky2->hw->napi, skb);
2499}
2500
bf15fe99
SH		 2501static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2502 unsigned packets, unsigned bytes)
2503{
0885a30b 2504 struct net_device *dev = hw->dev[port];
2505 struct sky2_port *sky2 = netdev_priv(dev);
bf15fe99 2506
0885a30b 2507 if (packets == 0)
2508 return;
2509
2510 u64_stats_update_begin(&sky2->rx_stats.syncp);
2511 sky2->rx_stats.packets += packets;
2512 sky2->rx_stats.bytes += bytes;
2513 u64_stats_update_end(&sky2->rx_stats.syncp);
2514
2515 dev->last_rx = jiffies;
2516 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
bf15fe99
SH		 2517}
2518
375c5688 2519static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2520{
2521 /* If this happens then driver assuming wrong format for chip type */
2522 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2523
2524 /* Both checksum counters are programmed to start at
2525 * the same offset, so unless there is a problem they
2526 * should match. This failure is an early indication that
2527 * hardware receive checksumming won't work.
2528 */
2529 if (likely((u16)(status >> 16) == (u16)status)) {
2530 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2531 skb->ip_summed = CHECKSUM_COMPLETE;
2532 skb->csum = le16_to_cpu(status);
2533 } else {
2534 dev_notice(&sky2->hw->pdev->dev,
2535 "%s: receive checksum problem (status = %#x)\n",
2536 sky2->netdev->name, status);
2537
2538 /* Disable checksum offload */
2539 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2540 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2541 BMU_DIS_RX_CHKSUM);
2542 }
2543}
2544
bf73130d
SH		 2545static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2546{
2547 struct sk_buff *skb;
2548
2549 skb = sky2->rx_ring[sky2->rx_next].skb;
2550 skb->rxhash = le32_to_cpu(status);
2551}
2552
e07b1aa8 2553/* Process status response ring */
26691830 2554static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2555{
e07b1aa8 2556 int work_done = 0;
bf15fe99
SH		 2557 unsigned int total_bytes[2] = { 0 };
2558 unsigned int total_packets[2] = { 0 };
a8fd6266 2559
af2a58ac 2560 rmb();
26691830 2561 do {
55c9dd35 2562 struct sky2_port *sky2;
13210ce5 2563 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2564 unsigned port;
13210ce5 2565 struct net_device *dev;
cd28ab6a 2566 struct sk_buff *skb;
cd28ab6a
SH		 2567 u32 status;
2568 u16 length;
ab5adecb
SH		 2569 u8 opcode = le->opcode;
2570
2571 if (!(opcode & HW_OWNER))
2572 break;
cd28ab6a 2573
efe91932 2574 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
bea86103 2575
ab5adecb 2576 port = le->css & CSS_LINK_BIT;
69161611 2577 dev = hw->dev[port];
13210ce5 2578 sky2 = netdev_priv(dev);
f65b138c
SH		 2579 length = le16_to_cpu(le->length);
2580 status = le32_to_cpu(le->status);
cd28ab6a 2581
ab5adecb
SH		 2582 le->opcode = 0;
2583 switch (opcode & ~HW_OWNER) {
cd28ab6a 2584 case OP_RXSTAT:
bf15fe99
SH		 2585 total_packets[port]++;
2586 total_bytes[port] += length;
90c30335 2587
497d7c86 2588 skb = sky2_receive(dev, length, status);
90c30335 2589 if (!skb)
55c9dd35 2590 break;
13210ce5 2591
69161611 2592 /* This chip reports checksum status differently */
05745c4a 2593 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2594 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2595 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2596 (le->css & CSS_TCPUDPCSOK))
2597 skb->ip_summed = CHECKSUM_UNNECESSARY;
2598 else
2599 skb->ip_summed = CHECKSUM_NONE;
2600 }
2601
13210ce5 2602 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2603
37e5a243 2604 sky2_skb_rx(sky2, status, skb);
13210ce5 2605
22e11703 2606 /* Stop after net poll weight */
13210ce5 2607 if (++work_done >= to_do)
2608 goto exit_loop;
cd28ab6a
SH		 2609 break;
2610
d1f13708 2611 case OP_RXVLAN:
2612 sky2->rx_tag = length;
2613 break;
2614
2615 case OP_RXCHKSVLAN:
2616 sky2->rx_tag = length;
2617 /* fall through */
cd28ab6a 2618 case OP_RXCHKS:
375c5688 2619 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2620 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2621 break;
2622
bf73130d
SH		 2623 case OP_RSS_HASH:
2624 sky2_rx_hash(sky2, status);
2625 break;
2626
cd28ab6a 2627 case OP_TXINDEXLE:
13b97b74 2628 /* TX index reports status for both ports */
f55925d7 2629 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2630 if (hw->dev[1])
2631 sky2_tx_done(hw->dev[1],
2632 ((status >> 24) & 0xff)
2633 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2634 break;
2635
cd28ab6a
SH		 2636 default:
2637 if (net_ratelimit())
ada1db5c 2638 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2639 }
26691830 2640 } while (hw->st_idx != idx);
cd28ab6a 2641
fe2a24df
SH		 2642 /* Fully processed status ring so clear irq */
2643 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2644
13210ce5 2645exit_loop:
bf15fe99
SH		 2646 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2647 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2648
e07b1aa8 2649 return work_done;
cd28ab6a
SH		 2650}
2651
2652static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2653{
2654 struct net_device *dev = hw->dev[port];
2655
3be92a70 2656 if (net_ratelimit())
ada1db5c 2657 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2658
2659 if (status & Y2_IS_PAR_RD1) {
3be92a70 2660 if (net_ratelimit())
ada1db5c 2661 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2662 /* Clear IRQ */
2663 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2664 }
2665
2666 if (status & Y2_IS_PAR_WR1) {
3be92a70 2667 if (net_ratelimit())
ada1db5c 2668 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2669
2670 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2671 }
2672
2673 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2674 if (net_ratelimit())
ada1db5c 2675 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2676 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2677 }
2678
2679 if (status & Y2_IS_PAR_RX1) {
3be92a70 2680 if (net_ratelimit())
ada1db5c 2681 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2682 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2683 }
2684
2685 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2686 if (net_ratelimit())
ada1db5c 2687 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2688 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2689 }
2690}
2691
2692static void sky2_hw_intr(struct sky2_hw *hw)
2693{
555382cb 2694 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2695 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2696 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2697
2698 status &= hwmsk;
cd28ab6a 2699
793b883e 2700 if (status & Y2_IS_TIST_OV)
cd28ab6a 2701 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2702
2703 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2704 u16 pci_err;
2705
a40ccc68 2706 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2707 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2708 if (net_ratelimit())
555382cb 2709 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2710 pci_err);
cd28ab6a 2711
b32f40c4 2712 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2713 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2715 }
2716
2717 if (status & Y2_IS_PCI_EXP) {
d571b694 2718 /* PCI-Express uncorrectable Error occurred */
555382cb 2719 u32 err;
cd28ab6a 2720
a40ccc68 2721 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2722 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2723 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2724 0xfffffffful);
3be92a70 2725 if (net_ratelimit())
555382cb 2726 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2727
7782c8c4 2728 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2729 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2730 }
2731
2732 if (status & Y2_HWE_L1_MASK)
2733 sky2_hw_error(hw, 0, status);
2734 status >>= 8;
2735 if (status & Y2_HWE_L1_MASK)
2736 sky2_hw_error(hw, 1, status);
2737}
2738
2739static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2740{
2741 struct net_device *dev = hw->dev[port];
2742 struct sky2_port *sky2 = netdev_priv(dev);
2743 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2744
6c35abae 2745 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2746
a3caeada
SH		 2747 if (status & GM_IS_RX_CO_OV)
2748 gma_read16(hw, port, GM_RX_IRQ_SRC);
2749
2750 if (status & GM_IS_TX_CO_OV)
2751 gma_read16(hw, port, GM_TX_IRQ_SRC);
2752
cd28ab6a 2753 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2754 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2755 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2756 }
2757
2758 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2759 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2760 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2761 }
cd28ab6a
SH		 2762}
2763
40b01727 2764/* This should never happen it is a bug. */
c119731d 2765static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2766{
2767 struct net_device *dev = hw->dev[port];
c119731d 2768 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2769
ada1db5c 2770 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2771 dev->name, (unsigned) q, (unsigned) idx,
2772 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2773
40b01727 2774 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2775}
cd28ab6a 2776
75e80683
SH		 2777static int sky2_rx_hung(struct net_device *dev)
2778{
2779 struct sky2_port *sky2 = netdev_priv(dev);
2780 struct sky2_hw *hw = sky2->hw;
2781 unsigned port = sky2->port;
2782 unsigned rxq = rxqaddr[port];
2783 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2784 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2785 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2786 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2787
2788 /* If idle and MAC or PCI is stuck */
2789 if (sky2->check.last == dev->last_rx &&
2790 ((mac_rp == sky2->check.mac_rp &&
2791 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2792 /* Check if the PCI RX hang */
2793 (fifo_rp == sky2->check.fifo_rp &&
2794 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2795 netdev_printk(KERN_DEBUG, dev,
2796 "hung mac %d:%d fifo %d (%d:%d)\n",
2797 mac_lev, mac_rp, fifo_lev,
2798 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2799 return 1;
2800 } else {
2801 sky2->check.last = dev->last_rx;
2802 sky2->check.mac_rp = mac_rp;
2803 sky2->check.mac_lev = mac_lev;
2804 sky2->check.fifo_rp = fifo_rp;
2805 sky2->check.fifo_lev = fifo_lev;
2806 return 0;
2807 }
2808}
2809
32c2c300 2810static void sky2_watchdog(unsigned long arg)
d27ed387 2811{
01bd7564 2812 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2813
75e80683 2814 /* Check for lost IRQ once a second */
32c2c300 2815 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2816 napi_schedule(&hw->napi);
75e80683
SH		 2817 } else {
2818 int i, active = 0;
2819
2820 for (i = 0; i < hw->ports; i++) {
bea3348e 2821 struct net_device *dev = hw->dev[i];
75e80683
SH		 2822 if (!netif_running(dev))
2823 continue;
2824 ++active;
2825
2826 /* For chips with Rx FIFO, check if stuck */
39dbd958 2827 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2828 sky2_rx_hung(dev)) {
ada1db5c 2829 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2830 schedule_work(&hw->restart_work);
2831 return;
2832 }
2833 }
2834
2835 if (active == 0)
2836 return;
32c2c300 2837 }
01bd7564 2838
75e80683 2839 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2840}
2841
40b01727
SH		 2842/* Hardware/software error handling */
2843static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2844{
40b01727
SH		 2845 if (net_ratelimit())
2846 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2847
1e5f1283
SH		 2848 if (status & Y2_IS_HW_ERR)
2849 sky2_hw_intr(hw);
d257924e 2850
1e5f1283
SH		 2851 if (status & Y2_IS_IRQ_MAC1)
2852 sky2_mac_intr(hw, 0);
cd28ab6a 2853
1e5f1283
SH		 2854 if (status & Y2_IS_IRQ_MAC2)
2855 sky2_mac_intr(hw, 1);
cd28ab6a 2856
1e5f1283 2857 if (status & Y2_IS_CHK_RX1)
c119731d 2858 sky2_le_error(hw, 0, Q_R1);
d257924e 2859
1e5f1283 2860 if (status & Y2_IS_CHK_RX2)
c119731d 2861 sky2_le_error(hw, 1, Q_R2);
d257924e 2862
1e5f1283 2863 if (status & Y2_IS_CHK_TXA1)
c119731d 2864 sky2_le_error(hw, 0, Q_XA1);
d257924e 2865
1e5f1283 2866 if (status & Y2_IS_CHK_TXA2)
c119731d 2867 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2868}
2869
bea3348e 2870static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2871{
bea3348e 2872 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2873 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2874 int work_done = 0;
26691830 2875 u16 idx;
40b01727
SH		 2876
2877 if (unlikely(status & Y2_IS_ERROR))
2878 sky2_err_intr(hw, status);
2879
2880 if (status & Y2_IS_IRQ_PHY1)
2881 sky2_phy_intr(hw, 0);
2882
2883 if (status & Y2_IS_IRQ_PHY2)
2884 sky2_phy_intr(hw, 1);
cd28ab6a 2885
0f5aac70
SH		 2886 if (status & Y2_IS_PHY_QLNK)
2887 sky2_qlink_intr(hw);
2888
26691830
SH		 2889 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2890 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2891
2892 if (work_done >= work_limit)
26691830
SH		 2893 goto done;
2894 }
6f535763 2895
26691830
SH		 2896 napi_complete(napi);
2897 sky2_read32(hw, B0_Y2_SP_LISR);
2898done:
6f535763 2899
bea3348e 2900 return work_done;
e07b1aa8
SH		 2901}
2902
7d12e780 2903static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2904{
2905 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2906 u32 status;
2907
2908 /* Reading this mask interrupts as side effect */
2909 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2910 if (status == 0 || status == ~0)
2911 return IRQ_NONE;
793b883e 2912
e07b1aa8 2913 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2914
2915 napi_schedule(&hw->napi);
793b883e 2916
cd28ab6a
SH		 2917 return IRQ_HANDLED;
2918}
2919
2920#ifdef CONFIG_NET_POLL_CONTROLLER
2921static void sky2_netpoll(struct net_device *dev)
2922{
2923 struct sky2_port *sky2 = netdev_priv(dev);
2924
bea3348e 2925 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2926}
2927#endif
2928
2929/* Chip internal frequency for clock calculations */
05745c4a 2930static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2931{
793b883e 2932 switch (hw->chip_id) {
cd28ab6a 2933 case CHIP_ID_YUKON_EC:
5a5b1ea0 2934 case CHIP_ID_YUKON_EC_U:
93745494 2935 case CHIP_ID_YUKON_EX:
ed4d4161 2936 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2937 case CHIP_ID_YUKON_UL_2:
0f5aac70 2938 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2939 return 125;
2940
cd28ab6a 2941 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2942 return 100;
2943
2944 case CHIP_ID_YUKON_FE_P:
2945 return 50;
2946
2947 case CHIP_ID_YUKON_XL:
2948 return 156;
2949
2950 default:
2951 BUG();
cd28ab6a
SH		 2952 }
2953}
2954
fb17358f 2955static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2956{
fb17358f 2957 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2958}
2959
fb17358f 2960static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2961{
fb17358f 2962 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2963}
2964
fb17358f 2965
e3173832 2966static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2967{
b89165f2 2968 u8 t8;
cd28ab6a 2969
167f53d0 2970 /* Enable all clocks and check for bad PCI access */
b32f40c4 2971 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2972
cd28ab6a 2973 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2974
cd28ab6a 2975 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2976 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2977
060b946c 2978 switch (hw->chip_id) {
ea76e635 2979 case CHIP_ID_YUKON_XL:
39dbd958 2980 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
bf73130d
SH		 2981 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
2982 hw->flags |= SKY2_HW_RSS_BROKEN;
ea76e635
SH		 2983 break;
2984
2985 case CHIP_ID_YUKON_EC_U:
2986 hw->flags = SKY2_HW_GIGABIT
2987 | SKY2_HW_NEWER_PHY
2988 | SKY2_HW_ADV_POWER_CTL;
2989 break;
2990
2991 case CHIP_ID_YUKON_EX:
2992 hw->flags = SKY2_HW_GIGABIT
2993 | SKY2_HW_NEWER_PHY
2994 | SKY2_HW_NEW_LE
2995 | SKY2_HW_ADV_POWER_CTL;
2996
2997 /* New transmit checksum */
2998 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2999 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3000 break;
3001
3002 case CHIP_ID_YUKON_EC:
3003 /* This rev is really old, and requires untested workarounds */
3004 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3005 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3006 return -EOPNOTSUPP;
3007 }
bf73130d 3008 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3009 break;
3010
3011 case CHIP_ID_YUKON_FE:
bf73130d 3012 hw->flags = SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3013 break;
3014
05745c4a
SH		 3015 case CHIP_ID_YUKON_FE_P:
3016 hw->flags = SKY2_HW_NEWER_PHY
3017 | SKY2_HW_NEW_LE
3018 | SKY2_HW_AUTO_TX_SUM
3019 | SKY2_HW_ADV_POWER_CTL;
86aa7785
SH		 3020
3021 /* The workaround for status conflicts VLAN tag detection. */
3022 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3023 hw->flags |= SKY2_HW_VLAN_BROKEN;
05745c4a 3024 break;
ed4d4161
SH		 3025
3026 case CHIP_ID_YUKON_SUPR:
3027 hw->flags = SKY2_HW_GIGABIT
3028 | SKY2_HW_NEWER_PHY
3029 | SKY2_HW_NEW_LE
3030 | SKY2_HW_AUTO_TX_SUM
3031 | SKY2_HW_ADV_POWER_CTL;
3032 break;
3033
0ce8b98d 3034 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3035 hw->flags = SKY2_HW_GIGABIT
3036 | SKY2_HW_ADV_POWER_CTL;
3037 break;
3038
0f5aac70 3039 case CHIP_ID_YUKON_OPT:
0ce8b98d 3040 hw->flags = SKY2_HW_GIGABIT
b338682d 3041 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3042 | SKY2_HW_ADV_POWER_CTL;
3043 break;
3044
ea76e635 3045 default:
b02a9258
SH		 3046 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3047 hw->chip_id);
cd28ab6a
SH		 3048 return -EOPNOTSUPP;
3049 }
3050
ea76e635
SH		 3051 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3052 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3053 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3054
e3173832
SH		 3055 hw->ports = 1;
3056 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3057 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3058 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3059 ++hw->ports;
3060 }
3061
74a61ebf
MM		 3062 if (sky2_read8(hw, B2_E_0))
3063 hw->flags |= SKY2_HW_RAM_BUFFER;
3064
e3173832
SH		 3065 return 0;
3066}
3067
3068static void sky2_reset(struct sky2_hw *hw)
3069{
555382cb 3070 struct pci_dev *pdev = hw->pdev;
e3173832 3071 u16 status;
555382cb
SH		 3072 int i, cap;
3073 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3074
cd28ab6a 3075 /* disable ASF */
acd12dde 3076 if (hw->chip_id == CHIP_ID_YUKON_EX
3077 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3078 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3079 status = sky2_read16(hw, HCU_CCSR);
3080 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3081 HCU_CCSR_UC_STATE_MSK);
acd12dde 3082 /*
3083 * CPU clock divider shouldn't be used because
3084 * - ASF firmware may malfunction
3085 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3086 */
3087 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3088 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3089 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3090 } else
3091 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3092 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3093
3094 /* do a SW reset */
3095 sky2_write8(hw, B0_CTST, CS_RST_SET);
3096 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3097
ac93a394
SH		 3098 /* allow writes to PCI config */
3099 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3100
cd28ab6a 3101 /* clear PCI errors, if any */
b32f40c4 3102 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3103 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3104 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3105
3106 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3107
555382cb
SH		 3108 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3109 if (cap) {
7782c8c4
SH		 3110 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3111 0xfffffffful);
555382cb
SH		 3112
3113 /* If error bit is stuck on ignore it */
3114 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3115 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3116 else
555382cb
SH		 3117 hwe_mask |= Y2_IS_PCI_EXP;
3118 }
cd28ab6a 3119
ae306cca 3120 sky2_power_on(hw);
a40ccc68 3121 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3122
3123 for (i = 0; i < hw->ports; i++) {
3124 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3125 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3126
ed4d4161
SH		 3127 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3128 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3129 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3130 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3131 | GMC_BYP_RETR_ON);
877c8570
SH		 3132
3133 }
3134
3135 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3136 /* enable MACSec clock gating */
3137 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3138 }
3139
0f5aac70
SH		 3140 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3141 u16 reg;
3142 u32 msk;
3143
3144 if (hw->chip_rev == 0) {
3145 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3146 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3147
3148 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3149 reg = 10;
3150 } else {
3151 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3152 reg = 3;
3153 }
3154
3155 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3156
3157 /* reset PHY Link Detect */
a40ccc68 3158 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3159 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3160 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3161 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3162
3163
3164 /* enable PHY Quick Link */
3165 msk = sky2_read32(hw, B0_IMSK);
3166 msk |= Y2_IS_PHY_QLNK;
3167 sky2_write32(hw, B0_IMSK, msk);
3168
3169 /* check if PSMv2 was running before */
3170 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3171 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3172 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3173 /* restore the PCIe Link Control register */
3174 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3175 }
a40ccc68 3176 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3177
3178 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3179 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3180 }
3181
793b883e
SH		 3182 /* Clear I2C IRQ noise */
3183 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3184
3185 /* turn off hardware timer (unused) */
3186 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3187 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3188
69634ee7
SH		 3189 /* Turn off descriptor polling */
3190 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3191
3192 /* Turn off receive timestamp */
3193 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3194 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3195
3196 /* enable the Tx Arbiters */
3197 for (i = 0; i < hw->ports; i++)
3198 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3199
3200 /* Initialize ram interface */
3201 for (i = 0; i < hw->ports; i++) {
793b883e 3202 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3203
3204 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3205 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3206 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3207 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3208 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3209 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3210 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3211 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3212 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3213 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3214 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3215 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3216 }
3217
555382cb 3218 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3219
cd28ab6a 3220 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3221 sky2_gmac_reset(hw, i);
cd28ab6a 3222
efe91932 3223 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
cd28ab6a
SH		 3224 hw->st_idx = 0;
3225
3226 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3227 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3228
3229 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3230 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3231
3232 /* Set the list last index */
efe91932 3233 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
cd28ab6a 3234
290d4de5
SH		 3235 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3236 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3237
290d4de5
SH		 3238 /* set Status-FIFO ISR watermark */
3239 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3240 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3241 else
3242 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3243
290d4de5 3244 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3245 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3246 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3247
793b883e 3248 /* enable status unit */
cd28ab6a
SH		 3249 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3250
3251 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3252 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3253 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3254}
3255
af18d8b8
SH		 3256/* Take device down (offline).
3257 * Equivalent to doing dev_stop() but this does not
25985edc 3258 * inform upper layers of the transition.
af18d8b8
SH		 3259 */
3260static void sky2_detach(struct net_device *dev)
3261{
3262 if (netif_running(dev)) {
c36531b9 3263 netif_tx_lock(dev);
af18d8b8 3264 netif_device_detach(dev); /* stop txq */
c36531b9 3265 netif_tx_unlock(dev);
af18d8b8
SH		 3266 sky2_down(dev);
3267 }
3268}
3269
3270/* Bring device back after doing sky2_detach */
3271static int sky2_reattach(struct net_device *dev)
3272{
3273 int err = 0;
3274
3275 if (netif_running(dev)) {
3276 err = sky2_up(dev);
3277 if (err) {
ada1db5c 3278 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3279 dev_close(dev);
3280 } else {
3281 netif_device_attach(dev);
3282 sky2_set_multicast(dev);
3283 }
3284 }
3285
3286 return err;
3287}
3288
d72ff8fa 3289static void sky2_all_down(struct sky2_hw *hw)
81906791 3290{
af18d8b8 3291 int i;
81906791 3292
d72ff8fa 3293 sky2_read32(hw, B0_IMSK);
8cfcbe99 3294 sky2_write32(hw, B0_IMSK, 0);
93135a3b
MM		 3295 synchronize_irq(hw->pdev->irq);
3296 napi_disable(&hw->napi);
8a0c9228
MM		 3297
3298 for (i = 0; i < hw->ports; i++) {
3299 struct net_device *dev = hw->dev[i];
3300 struct sky2_port *sky2 = netdev_priv(dev);
3301
3302 if (!netif_running(dev))
3303 continue;
3304
3305 netif_carrier_off(dev);
3306 netif_tx_disable(dev);
3307 sky2_hw_down(sky2);
3308 }
d72ff8fa 3309}
8a0c9228 3310
d72ff8fa
MM		 3311static void sky2_all_up(struct sky2_hw *hw)
3312{
3313 u32 imask = Y2_IS_BASE;
3314 int i;
81906791 3315
8a0c9228
MM		 3316 for (i = 0; i < hw->ports; i++) {
3317 struct net_device *dev = hw->dev[i];
3318 struct sky2_port *sky2 = netdev_priv(dev);
3319
3320 if (!netif_running(dev))
3321 continue;
3322
3323 sky2_hw_up(sky2);
37652522 3324 sky2_set_multicast(dev);
d72ff8fa 3325 imask |= portirq_msk[i];
8a0c9228
MM		 3326 netif_wake_queue(dev);
3327 }
3328
3329 sky2_write32(hw, B0_IMSK, imask);
3330 sky2_read32(hw, B0_IMSK);
3331
3332 sky2_read32(hw, B0_Y2_SP_LISR);
3333 napi_enable(&hw->napi);
d72ff8fa
MM		 3334}
3335
3336static void sky2_restart(struct work_struct *work)
3337{
3338 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3339
3340 rtnl_lock();
3341
3342 sky2_all_down(hw);
3343 sky2_reset(hw);
3344 sky2_all_up(hw);
81906791 3345
81906791
SH		 3346 rtnl_unlock();
3347}
3348
e3173832
SH		 3349static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3350{
3351 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3352}
3353
3354static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3355{
3356 const struct sky2_port *sky2 = netdev_priv(dev);
3357
3358 wol->supported = sky2_wol_supported(sky2->hw);
3359 wol->wolopts = sky2->wol;
3360}
3361
3362static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3363{
3364 struct sky2_port *sky2 = netdev_priv(dev);
3365 struct sky2_hw *hw = sky2->hw;
0f333d10
RW		 3366 bool enable_wakeup = false;
3367 int i;
cd28ab6a 3368
8e95a202
JP		 3369 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3370 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3371 return -EOPNOTSUPP;
3372
3373 sky2->wol = wol->wolopts;
0f333d10
RW		 3374
3375 for (i = 0; i < hw->ports; i++) {
3376 struct net_device *dev = hw->dev[i];
3377 struct sky2_port *sky2 = netdev_priv(dev);
3378
3379 if (sky2->wol)
3380 enable_wakeup = true;
3381 }
3382 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3383
cd28ab6a
SH		 3384 return 0;
3385}
3386
28bd181a 3387static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3388{
b89165f2
SH		 3389 if (sky2_is_copper(hw)) {
3390 u32 modes = SUPPORTED_10baseT_Half
3391 | SUPPORTED_10baseT_Full
3392 | SUPPORTED_100baseT_Half
2aca31e7 3393 | SUPPORTED_100baseT_Full;
cd28ab6a 3394
ea76e635 3395 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3396 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3397 | SUPPORTED_1000baseT_Full;
3398 return modes;
cd28ab6a 3399 } else
2aca31e7
SH		 3400 return SUPPORTED_1000baseT_Half
3401 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 3402}
3403
793b883e 3404static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3405{
3406 struct sky2_port *sky2 = netdev_priv(dev);
3407 struct sky2_hw *hw = sky2->hw;
3408
3409 ecmd->transceiver = XCVR_INTERNAL;
3410 ecmd->supported = sky2_supported_modes(hw);
3411 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3412 if (sky2_is_copper(hw)) {
cd28ab6a 3413 ecmd->port = PORT_TP;
b89165f2 3414 ecmd->speed = sky2->speed;
2aca31e7 3415 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
b89165f2
SH		 3416 } else {
3417 ecmd->speed = SPEED_1000;
cd28ab6a 3418 ecmd->port = PORT_FIBRE;
2aca31e7 3419 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
b89165f2 3420 }
cd28ab6a
SH		 3421
3422 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3423 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3424 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3425 ecmd->duplex = sky2->duplex;
3426 return 0;
3427}
3428
3429static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3430{
3431 struct sky2_port *sky2 = netdev_priv(dev);
3432 const struct sky2_hw *hw = sky2->hw;
3433 u32 supported = sky2_supported_modes(hw);
3434
3435 if (ecmd->autoneg == AUTONEG_ENABLE) {
2aca31e7
SH		 3436 if (ecmd->advertising & ~supported)
3437 return -EINVAL;
3438
3439 if (sky2_is_copper(hw))
3440 sky2->advertising = ecmd->advertising |
3441 ADVERTISED_TP |
3442 ADVERTISED_Autoneg;
3443 else
3444 sky2->advertising = ecmd->advertising |
3445 ADVERTISED_FIBRE |
3446 ADVERTISED_Autoneg;
3447
0ea065e5 3448 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3449 sky2->duplex = -1;
3450 sky2->speed = -1;
3451 } else {
3452 u32 setting;
3453
793b883e 3454 switch (ecmd->speed) {
cd28ab6a
SH		 3455 case SPEED_1000:
3456 if (ecmd->duplex == DUPLEX_FULL)
3457 setting = SUPPORTED_1000baseT_Full;
3458 else if (ecmd->duplex == DUPLEX_HALF)
3459 setting = SUPPORTED_1000baseT_Half;
3460 else
3461 return -EINVAL;
3462 break;
3463 case SPEED_100:
3464 if (ecmd->duplex == DUPLEX_FULL)
3465 setting = SUPPORTED_100baseT_Full;
3466 else if (ecmd->duplex == DUPLEX_HALF)
3467 setting = SUPPORTED_100baseT_Half;
3468 else
3469 return -EINVAL;
3470 break;
3471
3472 case SPEED_10:
3473 if (ecmd->duplex == DUPLEX_FULL)
3474 setting = SUPPORTED_10baseT_Full;
3475 else if (ecmd->duplex == DUPLEX_HALF)
3476 setting = SUPPORTED_10baseT_Half;
3477 else
3478 return -EINVAL;
3479 break;
3480 default:
3481 return -EINVAL;
3482 }
3483
3484 if ((setting & supported) == 0)
3485 return -EINVAL;
3486
3487 sky2->speed = ecmd->speed;
3488 sky2->duplex = ecmd->duplex;
0ea065e5 3489 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3490 }
3491
d1b139c0 3492 if (netif_running(dev)) {
1b537565 3493 sky2_phy_reinit(sky2);
d1b139c0
SH		 3494 sky2_set_multicast(dev);
3495 }
cd28ab6a
SH		 3496
3497 return 0;
3498}
3499
3500static void sky2_get_drvinfo(struct net_device *dev,
3501 struct ethtool_drvinfo *info)
3502{
3503 struct sky2_port *sky2 = netdev_priv(dev);
3504
3505 strcpy(info->driver, DRV_NAME);
3506 strcpy(info->version, DRV_VERSION);
3507 strcpy(info->fw_version, "N/A");
3508 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3509}
3510
3511static const struct sky2_stat {
793b883e
SH		 3512 char name[ETH_GSTRING_LEN];
3513 u16 offset;
cd28ab6a
SH		 3514} sky2_stats[] = {
3515 { "tx_bytes", GM_TXO_OK_HI },
3516 { "rx_bytes", GM_RXO_OK_HI },
3517 { "tx_broadcast", GM_TXF_BC_OK },
3518 { "rx_broadcast", GM_RXF_BC_OK },
3519 { "tx_multicast", GM_TXF_MC_OK },
3520 { "rx_multicast", GM_RXF_MC_OK },
3521 { "tx_unicast", GM_TXF_UC_OK },
3522 { "rx_unicast", GM_RXF_UC_OK },
3523 { "tx_mac_pause", GM_TXF_MPAUSE },
3524 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3525 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3526 { "late_collision",GM_TXF_LAT_COL },
3527 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3528 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3529 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3530
d2604540 3531 { "rx_short", GM_RXF_SHT },
cd28ab6a 3532 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3533 { "rx_64_byte_packets", GM_RXF_64B },
3534 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3535 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3536 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3537 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3538 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3539 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3540 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3541 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3542 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3543 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3544
3545 { "tx_64_byte_packets", GM_TXF_64B },
3546 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3547 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3548 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3549 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3550 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3551 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3552 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3553};
3554
cd28ab6a
SH		 3555static u32 sky2_get_rx_csum(struct net_device *dev)
3556{
3557 struct sky2_port *sky2 = netdev_priv(dev);
3558
0ea065e5 3559 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3560}
3561
3562static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3563{
3564 struct sky2_port *sky2 = netdev_priv(dev);
3565
0ea065e5
SH		 3566 if (data)
3567 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3568 else
3569 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3570
cd28ab6a
SH		 3571 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3572 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3573
3574 return 0;
3575}
3576
3577static u32 sky2_get_msglevel(struct net_device *netdev)
3578{
3579 struct sky2_port *sky2 = netdev_priv(netdev);
3580 return sky2->msg_enable;
3581}
3582
9a7ae0a9
SH		 3583static int sky2_nway_reset(struct net_device *dev)
3584{
3585 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3586
0ea065e5 3587 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3588 return -EINVAL;
3589
1b537565 3590 sky2_phy_reinit(sky2);
d1b139c0 3591 sky2_set_multicast(dev);
9a7ae0a9
SH		 3592
3593 return 0;
3594}
3595
793b883e 3596static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3597{
3598 struct sky2_hw *hw = sky2->hw;
3599 unsigned port = sky2->port;
3600 int i;
3601
0885a30b 3602 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3603 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
cd28ab6a 3604
793b883e 3605 for (i = 2; i < count; i++)
0885a30b 3606 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
cd28ab6a
SH		 3607}
3608
cd28ab6a
SH		 3609static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3610{
3611 struct sky2_port *sky2 = netdev_priv(netdev);
3612 sky2->msg_enable = value;
3613}
3614
b9f2c044 3615static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3616{
b9f2c044
JG		 3617 switch (sset) {
3618 case ETH_SS_STATS:
3619 return ARRAY_SIZE(sky2_stats);
3620 default:
3621 return -EOPNOTSUPP;
3622 }
cd28ab6a
SH		 3623}
3624
3625static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3626 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3627{
3628 struct sky2_port *sky2 = netdev_priv(dev);
3629
793b883e 3630 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3631}
3632
793b883e 3633static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3634{
3635 int i;
3636
3637 switch (stringset) {
3638 case ETH_SS_STATS:
3639 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3640 memcpy(data + i * ETH_GSTRING_LEN,
3641 sky2_stats[i].name, ETH_GSTRING_LEN);
3642 break;
3643 }
3644}
3645
cd28ab6a
SH		 3646static int sky2_set_mac_address(struct net_device *dev, void *p)
3647{
3648 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3649 struct sky2_hw *hw = sky2->hw;
3650 unsigned port = sky2->port;
3651 const struct sockaddr *addr = p;
cd28ab6a
SH		 3652
3653 if (!is_valid_ether_addr(addr->sa_data))
3654 return -EADDRNOTAVAIL;
3655
cd28ab6a 3656 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3657 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3658 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3659 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3660 dev->dev_addr, ETH_ALEN);
1b537565 3661
a8ab1ec0
SH		 3662 /* virtual address for data */
3663 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3664
3665 /* physical address: used for pause frames */
3666 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3667
3668 return 0;
cd28ab6a
SH		 3669}
3670
060b946c 3671static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
a052b52f
SH		 3672{
3673 u32 bit;
3674
3675 bit = ether_crc(ETH_ALEN, addr) & 63;
3676 filter[bit >> 3] |= 1 << (bit & 7);
3677}
3678
cd28ab6a
SH		 3679static void sky2_set_multicast(struct net_device *dev)
3680{
3681 struct sky2_port *sky2 = netdev_priv(dev);
3682 struct sky2_hw *hw = sky2->hw;
3683 unsigned port = sky2->port;
22bedad3 3684 struct netdev_hw_addr *ha;
cd28ab6a
SH		 3685 u16 reg;
3686 u8 filter[8];
a052b52f
SH		 3687 int rx_pause;
3688 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3689
a052b52f 3690 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3691 memset(filter, 0, sizeof(filter));
3692
3693 reg = gma_read16(hw, port, GM_RX_CTRL);
3694 reg |= GM_RXCR_UCF_ENA;
3695
d571b694 3696 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3697 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3698 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3699 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3700 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3701 reg &= ~GM_RXCR_MCF_ENA;
3702 else {
cd28ab6a
SH		 3703 reg |= GM_RXCR_MCF_ENA;
3704
a052b52f
SH		 3705 if (rx_pause)
3706 sky2_add_filter(filter, pause_mc_addr);
3707
22bedad3
JP		 3708 netdev_for_each_mc_addr(ha, dev)
3709 sky2_add_filter(filter, ha->addr);
cd28ab6a
SH		 3710 }
3711
cd28ab6a 3712 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3713 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3714 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3715 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3716 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3717 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3718 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3719 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3720
3721 gma_write16(hw, port, GM_RX_CTRL, reg);
3722}
3723
0885a30b 3724static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3725 struct rtnl_link_stats64 *stats)
3726{
3727 struct sky2_port *sky2 = netdev_priv(dev);
3728 struct sky2_hw *hw = sky2->hw;
3729 unsigned port = sky2->port;
3730 unsigned int start;
3731 u64 _bytes, _packets;
3732
3733 do {
3734 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3735 _bytes = sky2->rx_stats.bytes;
3736 _packets = sky2->rx_stats.packets;
3737 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3738
3739 stats->rx_packets = _packets;
3740 stats->rx_bytes = _bytes;
3741
3742 do {
3743 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3744 _bytes = sky2->tx_stats.bytes;
3745 _packets = sky2->tx_stats.packets;
3746 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3747
3748 stats->tx_packets = _packets;
3749 stats->tx_bytes = _bytes;
3750
3751 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3752 + get_stats32(hw, port, GM_RXF_BC_OK);
3753
3754 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3755
3756 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3757 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3758 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3759 + get_stats32(hw, port, GM_RXE_FRAG);
3760 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3761
3762 stats->rx_dropped = dev->stats.rx_dropped;
3763 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3764 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3765
3766 return stats;
3767}
3768
cd28ab6a
SH		 3769/* Can have one global because blinking is controlled by
3770 * ethtool and that is always under RTNL mutex
3771 */
a84d0a3d 3772static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3773{
a84d0a3d
SH		 3774 struct sky2_hw *hw = sky2->hw;
3775 unsigned port = sky2->port;
793b883e 3776
a84d0a3d
SH		 3777 spin_lock_bh(&sky2->phy_lock);
3778 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3779 hw->chip_id == CHIP_ID_YUKON_EX ||
3780 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3781 u16 pg;
793b883e
SH		 3782 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3783 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3784
a84d0a3d
SH		 3785 switch (mode) {
3786 case MO_LED_OFF:
3787 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3788 PHY_M_LEDC_LOS_CTRL(8) |
3789 PHY_M_LEDC_INIT_CTRL(8) |
3790 PHY_M_LEDC_STA1_CTRL(8) |
3791 PHY_M_LEDC_STA0_CTRL(8));
3792 break;
3793 case MO_LED_ON:
3794 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3795 PHY_M_LEDC_LOS_CTRL(9) |
3796 PHY_M_LEDC_INIT_CTRL(9) |
3797 PHY_M_LEDC_STA1_CTRL(9) |
3798 PHY_M_LEDC_STA0_CTRL(9));
3799 break;
3800 case MO_LED_BLINK:
3801 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3802 PHY_M_LEDC_LOS_CTRL(0xa) |
3803 PHY_M_LEDC_INIT_CTRL(0xa) |
3804 PHY_M_LEDC_STA1_CTRL(0xa) |
3805 PHY_M_LEDC_STA0_CTRL(0xa));
3806 break;
3807 case MO_LED_NORM:
3808 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3809 PHY_M_LEDC_LOS_CTRL(1) |
3810 PHY_M_LEDC_INIT_CTRL(8) |
3811 PHY_M_LEDC_STA1_CTRL(7) |
3812 PHY_M_LEDC_STA0_CTRL(7));
3813 }
793b883e 3814
a84d0a3d
SH		 3815 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3816 } else
7d2e3cb7 3817 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3818 PHY_M_LED_MO_DUP(mode) |
3819 PHY_M_LED_MO_10(mode) |
3820 PHY_M_LED_MO_100(mode) |
3821 PHY_M_LED_MO_1000(mode) |
3822 PHY_M_LED_MO_RX(mode) |
3823 PHY_M_LED_MO_TX(mode));
3824
3825 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3826}
3827
3828/* blink LED's for finding board */
3829static int sky2_phys_id(struct net_device *dev, u32 data)
3830{
3831 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3832 unsigned int i;
cd28ab6a 3833
a84d0a3d
SH		 3834 if (data == 0)
3835 data = UINT_MAX;
cd28ab6a 3836
a84d0a3d
SH		 3837 for (i = 0; i < data; i++) {
3838 sky2_led(sky2, MO_LED_ON);
3839 if (msleep_interruptible(500))
3840 break;
3841 sky2_led(sky2, MO_LED_OFF);
3842 if (msleep_interruptible(500))
3843 break;
793b883e 3844 }
a84d0a3d 3845 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3846
3847 return 0;
3848}
3849
3850static void sky2_get_pauseparam(struct net_device *dev,
3851 struct ethtool_pauseparam *ecmd)
3852{
3853 struct sky2_port *sky2 = netdev_priv(dev);
3854
16ad91e1
SH		 3855 switch (sky2->flow_mode) {
3856 case FC_NONE:
3857 ecmd->tx_pause = ecmd->rx_pause = 0;
3858 break;
3859 case FC_TX:
3860 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3861 break;
3862 case FC_RX:
3863 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3864 break;
3865 case FC_BOTH:
3866 ecmd->tx_pause = ecmd->rx_pause = 1;
3867 }
3868
0ea065e5
SH		 3869 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3870 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3871}
3872
3873static int sky2_set_pauseparam(struct net_device *dev,
3874 struct ethtool_pauseparam *ecmd)
3875{
3876 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3877
0ea065e5
SH		 3878 if (ecmd->autoneg == AUTONEG_ENABLE)
3879 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3880 else
3881 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3882
16ad91e1 3883 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3884
16ad91e1
SH		 3885 if (netif_running(dev))
3886 sky2_phy_reinit(sky2);
cd28ab6a 3887
2eaba1a2 3888 return 0;
cd28ab6a
SH		 3889}
3890
fb17358f
SH		 3891static int sky2_get_coalesce(struct net_device *dev,
3892 struct ethtool_coalesce *ecmd)
3893{
3894 struct sky2_port *sky2 = netdev_priv(dev);
3895 struct sky2_hw *hw = sky2->hw;
3896
3897 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3898 ecmd->tx_coalesce_usecs = 0;
3899 else {
3900 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3901 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3902 }
3903 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3904
3905 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3906 ecmd->rx_coalesce_usecs = 0;
3907 else {
3908 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3909 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3910 }
3911 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3912
3913 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3914 ecmd->rx_coalesce_usecs_irq = 0;
3915 else {
3916 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3917 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3918 }
3919
3920 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3921
3922 return 0;
3923}
3924
3925/* Note: this affect both ports */
3926static int sky2_set_coalesce(struct net_device *dev,
3927 struct ethtool_coalesce *ecmd)
3928{
3929 struct sky2_port *sky2 = netdev_priv(dev);
3930 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3931 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3932
77b3d6a2
SH		 3933 if (ecmd->tx_coalesce_usecs > tmax ||
3934 ecmd->rx_coalesce_usecs > tmax ||
3935 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3936 return -EINVAL;
3937
ee5f68fe 3938 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3939 return -EINVAL;
ff81fbbe 3940 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3941 return -EINVAL;
060b946c 3942 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
fb17358f
SH		 3943 return -EINVAL;
3944
3945 if (ecmd->tx_coalesce_usecs == 0)
3946 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3947 else {
3948 sky2_write32(hw, STAT_TX_TIMER_INI,
3949 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3950 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3951 }
3952 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3953
3954 if (ecmd->rx_coalesce_usecs == 0)
3955 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3956 else {
3957 sky2_write32(hw, STAT_LEV_TIMER_INI,
3958 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3959 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3960 }
3961 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3962
3963 if (ecmd->rx_coalesce_usecs_irq == 0)
3964 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3965 else {
d28d4870 3966 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3967 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3968 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3969 }
3970 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3971 return 0;
3972}
3973
793b883e
SH		 3974static void sky2_get_ringparam(struct net_device *dev,
3975 struct ethtool_ringparam *ering)
3976{
3977 struct sky2_port *sky2 = netdev_priv(dev);
3978
3979 ering->rx_max_pending = RX_MAX_PENDING;
3980 ering->rx_mini_max_pending = 0;
3981 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3982 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3983
3984 ering->rx_pending = sky2->rx_pending;
3985 ering->rx_mini_pending = 0;
3986 ering->rx_jumbo_pending = 0;
3987 ering->tx_pending = sky2->tx_pending;
3988}
3989
3990static int sky2_set_ringparam(struct net_device *dev,
3991 struct ethtool_ringparam *ering)
3992{
3993 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3994
3995 if (ering->rx_pending > RX_MAX_PENDING ||
3996 ering->rx_pending < 8 ||
ee5f68fe
SH		 3997 ering->tx_pending < TX_MIN_PENDING ||
3998 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3999 return -EINVAL;
4000
af18d8b8 4001 sky2_detach(dev);
793b883e
SH		 4002
4003 sky2->rx_pending = ering->rx_pending;
4004 sky2->tx_pending = ering->tx_pending;
ee5f68fe 4005 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 4006
af18d8b8 4007 return sky2_reattach(dev);
793b883e
SH		 4008}
4009
793b883e
SH		 4010static int sky2_get_regs_len(struct net_device *dev)
4011{
6e4cbb34 4012 return 0x4000;
793b883e
SH		 4013}
4014
c32bbff8
MM		 4015static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4016{
4017 /* This complicated switch statement is to make sure and
4018 * only access regions that are unreserved.
4019 * Some blocks are only valid on dual port cards.
4020 */
4021 switch (b) {
4022 /* second port */
4023 case 5: /* Tx Arbiter 2 */
4024 case 9: /* RX2 */
4025 case 14 ... 15: /* TX2 */
4026 case 17: case 19: /* Ram Buffer 2 */
4027 case 22 ... 23: /* Tx Ram Buffer 2 */
4028 case 25: /* Rx MAC Fifo 1 */
4029 case 27: /* Tx MAC Fifo 2 */
4030 case 31: /* GPHY 2 */
4031 case 40 ... 47: /* Pattern Ram 2 */
4032 case 52: case 54: /* TCP Segmentation 2 */
4033 case 112 ... 116: /* GMAC 2 */
4034 return hw->ports > 1;
4035
4036 case 0: /* Control */
4037 case 2: /* Mac address */
4038 case 4: /* Tx Arbiter 1 */
4039 case 7: /* PCI express reg */
4040 case 8: /* RX1 */
4041 case 12 ... 13: /* TX1 */
4042 case 16: case 18:/* Rx Ram Buffer 1 */
4043 case 20 ... 21: /* Tx Ram Buffer 1 */
4044 case 24: /* Rx MAC Fifo 1 */
4045 case 26: /* Tx MAC Fifo 1 */
4046 case 28 ... 29: /* Descriptor and status unit */
4047 case 30: /* GPHY 1*/
4048 case 32 ... 39: /* Pattern Ram 1 */
4049 case 48: case 50: /* TCP Segmentation 1 */
4050 case 56 ... 60: /* PCI space */
4051 case 80 ... 84: /* GMAC 1 */
4052 return 1;
4053
4054 default:
4055 return 0;
4056 }
4057}
4058
793b883e
SH		 4059/*
4060 * Returns copy of control register region
3ead5db7 4061 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 4062 */
4063static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4064 void *p)
4065{
4066 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 4067 const void __iomem *io = sky2->hw->regs;
295b54c4 4068 unsigned int b;
793b883e
SH		 4069
4070 regs->version = 1;
793b883e 4071
295b54c4 4072 for (b = 0; b < 128; b++) {
c32bbff8
MM		 4073 /* skip poisonous diagnostic ram region in block 3 */
4074 if (b == 3)
295b54c4 4075 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 4076 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 4077 memcpy_fromio(p, io, 128);
c32bbff8 4078 else
295b54c4 4079 memset(p, 0, 128);
3ead5db7 4080
295b54c4
SH		 4081 p += 128;
4082 io += 128;
4083 }
793b883e 4084}
cd28ab6a 4085
b628ed98
SH		 4086/* In order to do Jumbo packets on these chips, need to turn off the
4087 * transmit store/forward. Therefore checksum offload won't work.
4088 */
4089static int no_tx_offload(struct net_device *dev)
4090{
4091 const struct sky2_port *sky2 = netdev_priv(dev);
4092 const struct sky2_hw *hw = sky2->hw;
4093
69161611 4094 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 4095}
4096
4097static int sky2_set_tx_csum(struct net_device *dev, u32 data)
4098{
4099 if (data && no_tx_offload(dev))
4100 return -EINVAL;
4101
4102 return ethtool_op_set_tx_csum(dev, data);
4103}
4104
4105
4106static int sky2_set_tso(struct net_device *dev, u32 data)
4107{
4108 if (data && no_tx_offload(dev))
4109 return -EINVAL;
4110
4111 return ethtool_op_set_tso(dev, data);
4112}
4113
f4331a6d
SH		 4114static int sky2_get_eeprom_len(struct net_device *dev)
4115{
4116 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4117 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4118 u16 reg2;
4119
b32f40c4 4120 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4121 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4122}
4123
1413235c 4124static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4125{
1413235c 4126 unsigned long start = jiffies;
f4331a6d 4127
1413235c
SH		 4128 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4129 /* Can take up to 10.6 ms for write */
4130 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4131 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4132 return -ETIMEDOUT;
4133 }
4134 mdelay(1);
4135 }
167f53d0 4136
1413235c
SH		 4137 return 0;
4138}
167f53d0 4139
1413235c
SH		 4140static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4141 u16 offset, size_t length)
4142{
4143 int rc = 0;
4144
4145 while (length > 0) {
4146 u32 val;
4147
4148 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4149 rc = sky2_vpd_wait(hw, cap, 0);
4150 if (rc)
4151 break;
4152
4153 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4154
4155 memcpy(data, &val, min(sizeof(val), length));
4156 offset += sizeof(u32);
4157 data += sizeof(u32);
4158 length -= sizeof(u32);
4159 }
4160
4161 return rc;
f4331a6d
SH		 4162}
4163
1413235c
SH		 4164static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4165 u16 offset, unsigned int length)
f4331a6d 4166{
1413235c
SH		 4167 unsigned int i;
4168 int rc = 0;
4169
4170 for (i = 0; i < length; i += sizeof(u32)) {
4171 u32 val = *(u32 *)(data + i);
4172
4173 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4174 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4175
4176 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4177 if (rc)
4178 break;
4179 }
4180 return rc;
f4331a6d
SH		 4181}
4182
4183static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4184 u8 *data)
4185{
4186 struct sky2_port *sky2 = netdev_priv(dev);
4187 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4188
4189 if (!cap)
4190 return -EINVAL;
4191
4192 eeprom->magic = SKY2_EEPROM_MAGIC;
4193
1413235c 4194 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4195}
4196
4197static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4198 u8 *data)
4199{
4200 struct sky2_port *sky2 = netdev_priv(dev);
4201 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4202
4203 if (!cap)
4204 return -EINVAL;
4205
4206 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4207 return -EINVAL;
4208
1413235c
SH		 4209 /* Partial writes not supported */
4210 if ((eeprom->offset & 3) || (eeprom->len & 3))
4211 return -EINVAL;
f4331a6d 4212
1413235c 4213 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4214}
4215
bf73130d
SH		 4216static int sky2_set_flags(struct net_device *dev, u32 data)
4217{
4218 struct sky2_port *sky2 = netdev_priv(dev);
86aa7785
SH		 4219 unsigned long old_feat = dev->features;
4220 u32 supported = 0;
1437ce39 4221 int rc;
bf73130d 4222
86aa7785
SH		 4223 if (!(sky2->hw->flags & SKY2_HW_RSS_BROKEN))
4224 supported |= ETH_FLAG_RXHASH;
4225
4226 if (!(sky2->hw->flags & SKY2_HW_VLAN_BROKEN))
4227 supported |= ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN;
4228
4229 printk(KERN_DEBUG "sky2 set_flags: supported %x data %x\n",
4230 supported, data);
4231
1437ce39
BH		 4232 rc = ethtool_op_set_flags(dev, data, supported);
4233 if (rc)
4234 return rc;
bf73130d 4235
86aa7785
SH		 4236 if ((old_feat ^ dev->features) & NETIF_F_RXHASH)
4237 rx_set_rss(dev);
4238
4239 if ((old_feat ^ dev->features) & NETIF_F_ALL_VLAN)
4240 sky2_vlan_mode(dev);
bf73130d
SH		 4241
4242 return 0;
4243}
f4331a6d 4244
7282d491 4245static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4246 .get_settings = sky2_get_settings,
4247 .set_settings = sky2_set_settings,
4248 .get_drvinfo = sky2_get_drvinfo,
4249 .get_wol = sky2_get_wol,
4250 .set_wol = sky2_set_wol,
4251 .get_msglevel = sky2_get_msglevel,
4252 .set_msglevel = sky2_set_msglevel,
4253 .nway_reset = sky2_nway_reset,
4254 .get_regs_len = sky2_get_regs_len,
4255 .get_regs = sky2_get_regs,
4256 .get_link = ethtool_op_get_link,
4257 .get_eeprom_len = sky2_get_eeprom_len,
4258 .get_eeprom = sky2_get_eeprom,
4259 .set_eeprom = sky2_set_eeprom,
f4331a6d 4260 .set_sg = ethtool_op_set_sg,
f4331a6d 4261 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4262 .set_tso = sky2_set_tso,
4263 .get_rx_csum = sky2_get_rx_csum,
4264 .set_rx_csum = sky2_set_rx_csum,
4265 .get_strings = sky2_get_strings,
4266 .get_coalesce = sky2_get_coalesce,
4267 .set_coalesce = sky2_set_coalesce,
4268 .get_ringparam = sky2_get_ringparam,
4269 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4270 .get_pauseparam = sky2_get_pauseparam,
4271 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4272 .phys_id = sky2_phys_id,
b9f2c044 4273 .get_sset_count = sky2_get_sset_count,
cd28ab6a 4274 .get_ethtool_stats = sky2_get_ethtool_stats,
bf73130d 4275 .set_flags = sky2_set_flags,
86aa7785 4276 .get_flags = ethtool_op_get_flags,
cd28ab6a
SH		 4277};
4278
3cf26753
SH		 4279#ifdef CONFIG_SKY2_DEBUG
4280
4281static struct dentry *sky2_debug;
4282
e4c2abe2
SH		 4283
4284/*
4285 * Read and parse the first part of Vital Product Data
4286 */
4287#define VPD_SIZE 128
4288#define VPD_MAGIC 0x82
4289
4290static const struct vpd_tag {
4291 char tag[2];
4292 char *label;
4293} vpd_tags[] = {
4294 { "PN", "Part Number" },
4295 { "EC", "Engineering Level" },
4296 { "MN", "Manufacturer" },
4297 { "SN", "Serial Number" },
4298 { "YA", "Asset Tag" },
4299 { "VL", "First Error Log Message" },
4300 { "VF", "Second Error Log Message" },
4301 { "VB", "Boot Agent ROM Configuration" },
4302 { "VE", "EFI UNDI Configuration" },
4303};
4304
4305static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4306{
4307 size_t vpd_size;
4308 loff_t offs;
4309 u8 len;
4310 unsigned char *buf;
4311 u16 reg2;
4312
4313 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4314 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4315
4316 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4317 buf = kmalloc(vpd_size, GFP_KERNEL);
4318 if (!buf) {
4319 seq_puts(seq, "no memory!\n");
4320 return;
4321 }
4322
4323 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4324 seq_puts(seq, "VPD read failed\n");
4325 goto out;
4326 }
4327
4328 if (buf[0] != VPD_MAGIC) {
4329 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4330 goto out;
4331 }
4332 len = buf[1];
4333 if (len == 0 || len > vpd_size - 4) {
4334 seq_printf(seq, "Invalid id length: %d\n", len);
4335 goto out;
4336 }
4337
4338 seq_printf(seq, "%.*s\n", len, buf + 3);
4339 offs = len + 3;
4340
4341 while (offs < vpd_size - 4) {
4342 int i;
4343
4344 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4345 break;
4346 len = buf[offs + 2];
4347 if (offs + len + 3 >= vpd_size)
4348 break;
4349
4350 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4351 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4352 seq_printf(seq, " %s: %.*s\n",
4353 vpd_tags[i].label, len, buf + offs + 3);
4354 break;
4355 }
4356 }
4357 offs += len + 3;
4358 }
4359out:
4360 kfree(buf);
4361}
4362
3cf26753
SH		 4363static int sky2_debug_show(struct seq_file *seq, void *v)
4364{
4365 struct net_device *dev = seq->private;
4366 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4367 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4368 unsigned port = sky2->port;
4369 unsigned idx, last;
4370 int sop;
4371
e4c2abe2 4372 sky2_show_vpd(seq, hw);
3cf26753 4373
e4c2abe2 4374 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4375 sky2_read32(hw, B0_ISRC),
4376 sky2_read32(hw, B0_IMSK),
4377 sky2_read32(hw, B0_Y2_SP_ICR));
4378
e4c2abe2
SH		 4379 if (!netif_running(dev)) {
4380 seq_printf(seq, "network not running\n");
4381 return 0;
4382 }
4383
bea3348e 4384 napi_disable(&hw->napi);
3cf26753
SH		 4385 last = sky2_read16(hw, STAT_PUT_IDX);
4386
efe91932 4387 seq_printf(seq, "Status ring %u\n", hw->st_size);
3cf26753
SH		 4388 if (hw->st_idx == last)
4389 seq_puts(seq, "Status ring (empty)\n");
4390 else {
4391 seq_puts(seq, "Status ring\n");
efe91932 4392 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4393 idx = RING_NEXT(idx, hw->st_size)) {
3cf26753
SH		 4394 const struct sky2_status_le *le = hw->st_le + idx;
4395 seq_printf(seq, "[%d] %#x %d %#x\n",
4396 idx, le->opcode, le->length, le->status);
4397 }
4398 seq_puts(seq, "\n");
4399 }
4400
4401 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4402 sky2->tx_cons, sky2->tx_prod,
4403 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4404 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4405
4406 /* Dump contents of tx ring */
4407 sop = 1;
ee5f68fe
SH		 4408 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4409 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4410 const struct sky2_tx_le *le = sky2->tx_le + idx;
4411 u32 a = le32_to_cpu(le->addr);
4412
4413 if (sop)
4414 seq_printf(seq, "%u:", idx);
4415 sop = 0;
4416
060b946c 4417 switch (le->opcode & ~HW_OWNER) {
3cf26753
SH		 4418 case OP_ADDR64:
4419 seq_printf(seq, " %#x:", a);
4420 break;
4421 case OP_LRGLEN:
4422 seq_printf(seq, " mtu=%d", a);
4423 break;
4424 case OP_VLAN:
4425 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4426 break;
4427 case OP_TCPLISW:
4428 seq_printf(seq, " csum=%#x", a);
4429 break;
4430 case OP_LARGESEND:
4431 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4432 break;
4433 case OP_PACKET:
4434 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4435 break;
4436 case OP_BUFFER:
4437 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4438 break;
4439 default:
4440 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4441 a, le16_to_cpu(le->length));
4442 }
4443
4444 if (le->ctrl & EOP) {
4445 seq_putc(seq, '\n');
4446 sop = 1;
4447 }
4448 }
4449
4450 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4451 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4452 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4453 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4454
d1d08d12 4455 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4456 napi_enable(&hw->napi);
3cf26753
SH		 4457 return 0;
4458}
4459
4460static int sky2_debug_open(struct inode *inode, struct file *file)
4461{
4462 return single_open(file, sky2_debug_show, inode->i_private);
4463}
4464
4465static const struct file_operations sky2_debug_fops = {
4466 .owner = THIS_MODULE,
4467 .open = sky2_debug_open,
4468 .read = seq_read,
4469 .llseek = seq_lseek,
4470 .release = single_release,
4471};
4472
4473/*
4474 * Use network device events to create/remove/rename
4475 * debugfs file entries
4476 */
4477static int sky2_device_event(struct notifier_block *unused,
4478 unsigned long event, void *ptr)
4479{
4480 struct net_device *dev = ptr;
5b296bc9 4481 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4482
1436b301 4483 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4484 return NOTIFY_DONE;
3cf26753 4485
060b946c 4486 switch (event) {
5b296bc9
SH		 4487 case NETDEV_CHANGENAME:
4488 if (sky2->debugfs) {
4489 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4490 sky2_debug, dev->name);
4491 }
4492 break;
3cf26753 4493
5b296bc9
SH		 4494 case NETDEV_GOING_DOWN:
4495 if (sky2->debugfs) {
ada1db5c 4496 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4497 debugfs_remove(sky2->debugfs);
4498 sky2->debugfs = NULL;
3cf26753 4499 }
5b296bc9
SH		 4500 break;
4501
4502 case NETDEV_UP:
4503 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4504 sky2_debug, dev,
4505 &sky2_debug_fops);
4506 if (IS_ERR(sky2->debugfs))
4507 sky2->debugfs = NULL;
3cf26753
SH		 4508 }
4509
4510 return NOTIFY_DONE;
4511}
4512
4513static struct notifier_block sky2_notifier = {
4514 .notifier_call = sky2_device_event,
4515};
4516
4517
4518static __init void sky2_debug_init(void)
4519{
4520 struct dentry *ent;
4521
4522 ent = debugfs_create_dir("sky2", NULL);
4523 if (!ent || IS_ERR(ent))
4524 return;
4525
4526 sky2_debug = ent;
4527 register_netdevice_notifier(&sky2_notifier);
4528}
4529
4530static __exit void sky2_debug_cleanup(void)
4531{
4532 if (sky2_debug) {
4533 unregister_netdevice_notifier(&sky2_notifier);
4534 debugfs_remove(sky2_debug);
4535 sky2_debug = NULL;
4536 }
4537}
4538
4539#else
4540#define sky2_debug_init()
4541#define sky2_debug_cleanup()
4542#endif
4543
1436b301
SH		 4544/* Two copies of network device operations to handle special case of
4545 not allowing netpoll on second port */
4546static const struct net_device_ops sky2_netdev_ops[2] = {
4547 {
4548 .ndo_open = sky2_up,
4549 .ndo_stop = sky2_down,
00829823 4550 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4551 .ndo_do_ioctl = sky2_ioctl,
4552 .ndo_validate_addr = eth_validate_addr,
4553 .ndo_set_mac_address = sky2_set_mac_address,
4554 .ndo_set_multicast_list = sky2_set_multicast,
4555 .ndo_change_mtu = sky2_change_mtu,
4556 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4557 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4558#ifdef CONFIG_NET_POLL_CONTROLLER
4559 .ndo_poll_controller = sky2_netpoll,
4560#endif
4561 },
4562 {
4563 .ndo_open = sky2_up,
4564 .ndo_stop = sky2_down,
00829823 4565 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4566 .ndo_do_ioctl = sky2_ioctl,
4567 .ndo_validate_addr = eth_validate_addr,
4568 .ndo_set_mac_address = sky2_set_mac_address,
4569 .ndo_set_multicast_list = sky2_set_multicast,
4570 .ndo_change_mtu = sky2_change_mtu,
4571 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4572 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4573 },
4574};
3cf26753 4575
cd28ab6a
SH		 4576/* Initialize network device */
4577static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4578 unsigned port,
be63a21c 4579 int highmem, int wol)
cd28ab6a
SH		 4580{
4581 struct sky2_port *sky2;
4582 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4583
4584 if (!dev) {
898eb71c 4585 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4586 return NULL;
4587 }
4588
cd28ab6a 4589 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4590 dev->irq = hw->pdev->irq;
cd28ab6a 4591 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4592 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4593 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4594
4595 sky2 = netdev_priv(dev);
4596 sky2->netdev = dev;
4597 sky2->hw = hw;
4598 sky2->msg_enable = netif_msg_init(debug, default_msg);
4599
cd28ab6a 4600 /* Auto speed and flow control */
0ea065e5
SH		 4601 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4602 if (hw->chip_id != CHIP_ID_YUKON_XL)
4603 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4604
16ad91e1
SH		 4605 sky2->flow_mode = FC_BOTH;
4606
cd28ab6a
SH		 4607 sky2->duplex = -1;
4608 sky2->speed = -1;
4609 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4610 sky2->wol = wol;
75d070c5 4611
e07b1aa8 4612 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4613
793b883e 4614 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4615 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4616 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4617
4618 hw->dev[port] = dev;
4619
4620 sky2->port = port;
4621
1953925e 4622 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG
86aa7785
SH		 4623 | NETIF_F_TSO | NETIF_F_GRO;
4624
cd28ab6a
SH		 4625 if (highmem)
4626 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4627
bf73130d
SH		 4628 /* Enable receive hashing unless hardware is known broken */
4629 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4630 dev->features |= NETIF_F_RXHASH;
4631
86aa7785 4632 if (!(hw->flags & SKY2_HW_VLAN_BROKEN))
d6c9bc1e 4633 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d1f13708 4634
cd28ab6a 4635 /* read the mac address */
793b883e 4636 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4637 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4638
cd28ab6a
SH		 4639 return dev;
4640}
4641
28bd181a 4642static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4643{
4644 const struct sky2_port *sky2 = netdev_priv(dev);
4645
6c35abae 4646 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4647}
4648
fb2690a9 4649/* Handle software interrupt used during MSI test */
7d12e780 4650static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4651{
4652 struct sky2_hw *hw = dev_id;
4653 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4654
4655 if (status == 0)
4656 return IRQ_NONE;
4657
4658 if (status & Y2_IS_IRQ_SW) {
ea76e635 4659 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4660 wake_up(&hw->msi_wait);
4661 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4662 }
4663 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4664
4665 return IRQ_HANDLED;
4666}
4667
4668/* Test interrupt path by forcing a a software IRQ */
4669static int __devinit sky2_test_msi(struct sky2_hw *hw)
4670{
4671 struct pci_dev *pdev = hw->pdev;
4672 int err;
4673
060b946c 4674 init_waitqueue_head(&hw->msi_wait);
bb507fe1 4675
fb2690a9
SH		 4676 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4677
b0a20ded 4678 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4679 if (err) {
b02a9258 4680 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4681 return err;
4682 }
4683
fb2690a9 4684 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4685 sky2_read8(hw, B0_CTST);
fb2690a9 4686
ea76e635 4687 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4688
ea76e635 4689 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4690 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4691 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4692 "switching to INTx mode.\n");
fb2690a9
SH		 4693
4694 err = -EOPNOTSUPP;
4695 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4696 }
4697
4698 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4699 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4700
4701 free_irq(pdev->irq, hw);
4702
4703 return err;
4704}
4705
c7127a34
SH		 4706/* This driver supports yukon2 chipset only */
4707static const char *sky2_name(u8 chipid, char *buf, int sz)
4708{
4709 const char *name[] = {
4710 "XL", /* 0xb3 */
4711 "EC Ultra", /* 0xb4 */
4712 "Extreme", /* 0xb5 */
4713 "EC", /* 0xb6 */
4714 "FE", /* 0xb7 */
4715 "FE+", /* 0xb8 */
4716 "Supreme", /* 0xb9 */
0ce8b98d 4717 "UL 2", /* 0xba */
0f5aac70
SH		 4718 "Unknown", /* 0xbb */
4719 "Optima", /* 0xbc */
c7127a34
SH		 4720 };
4721
dae3a511 4722 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4723 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4724 else
4725 snprintf(buf, sz, "(chip %#x)", chipid);
4726 return buf;
4727}
4728
cd28ab6a
SH		 4729static int __devinit sky2_probe(struct pci_dev *pdev,
4730 const struct pci_device_id *ent)
4731{
7f60c64b 4732 struct net_device *dev;
cd28ab6a 4733 struct sky2_hw *hw;
be63a21c 4734 int err, using_dac = 0, wol_default;
3834507d 4735 u32 reg;
c7127a34 4736 char buf1[16];
cd28ab6a 4737
793b883e
SH		 4738 err = pci_enable_device(pdev);
4739 if (err) {
b02a9258 4740 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4741 goto err_out;
4742 }
4743
6cc90a5a
SH		 4744 /* Get configuration information
4745 * Note: only regular PCI config access once to test for HW issues
4746 * other PCI access through shared memory for speed and to
4747 * avoid MMCONFIG problems.
4748 */
4749 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4750 if (err) {
4751 dev_err(&pdev->dev, "PCI read config failed\n");
4752 goto err_out;
4753 }
4754
4755 if (~reg == 0) {
4756 dev_err(&pdev->dev, "PCI configuration read error\n");
4757 goto err_out;
4758 }
4759
793b883e
SH		 4760 err = pci_request_regions(pdev, DRV_NAME);
4761 if (err) {
b02a9258 4762 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4763 goto err_out_disable;
cd28ab6a
SH		 4764 }
4765
4766 pci_set_master(pdev);
4767
d1f3d4dd 4768 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4769 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4770 using_dac = 1;
6a35528a 4771 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4772 if (err < 0) {
b02a9258
SH		 4773 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4774 "for consistent allocations\n");
d1f3d4dd
SH		 4775 goto err_out_free_regions;
4776 }
d1f3d4dd 4777 } else {
284901a9 4778 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4779 if (err) {
b02a9258 4780 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4781 goto err_out_free_regions;
4782 }
4783 }
d1f3d4dd 4784
3834507d
SH		 4785
4786#ifdef __BIG_ENDIAN
4787 /* The sk98lin vendor driver uses hardware byte swapping but
4788 * this driver uses software swapping.
4789 */
4790 reg &= ~PCI_REV_DESC;
060b946c 4791 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3834507d
SH		 4792 if (err) {
4793 dev_err(&pdev->dev, "PCI write config failed\n");
4794 goto err_out_free_regions;
4795 }
4796#endif
4797
9d731d77 4798 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4799
cd28ab6a 4800 err = -ENOMEM;
66466797
SH		 4801
4802 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4803 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4804 if (!hw) {
b02a9258 4805 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4806 goto err_out_free_regions;
4807 }
4808
cd28ab6a 4809 hw->pdev = pdev;
66466797 4810 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4811
4812 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4813 if (!hw->regs) {
b02a9258 4814 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4815 goto err_out_free_hw;
4816 }
4817
e3173832 4818 err = sky2_init(hw);
cd28ab6a 4819 if (err)
793b883e 4820 goto err_out_iounmap;
cd28ab6a 4821
efe91932 4822 /* ring for status responses */
bf73130d 4823 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
efe91932 4824 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4825 &hw->st_dma);
4826 if (!hw->st_le)
4827 goto err_out_reset;
4828
c844d483
SH		 4829 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4830 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4831
e3173832
SH		 4832 sky2_reset(hw);
4833
be63a21c 4834 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4835 if (!dev) {
4836 err = -ENOMEM;
cd28ab6a 4837 goto err_out_free_pci;
7f60c64b 4838 }
cd28ab6a 4839
9fa1b1f3
SH		 4840 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4841 err = sky2_test_msi(hw);
4842 if (err == -EOPNOTSUPP)
4843 pci_disable_msi(pdev);
4844 else if (err)
4845 goto err_out_free_netdev;
4846 }
4847
793b883e
SH		 4848 err = register_netdev(dev);
4849 if (err) {
b02a9258 4850 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4851 goto err_out_free_netdev;
4852 }
4853
33cb7d33
BP		 4854 netif_carrier_off(dev);
4855
6de16237
SH		 4856 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4857
ea76e635
SH		 4858 err = request_irq(pdev->irq, sky2_intr,
4859 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4860 hw->irq_name, hw);
9fa1b1f3 4861 if (err) {
b02a9258 4862 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4863 goto err_out_unregister;
4864 }
4865 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4866 napi_enable(&hw->napi);
9fa1b1f3 4867
cd28ab6a
SH		 4868 sky2_show_addr(dev);
4869
7f60c64b 4870 if (hw->ports > 1) {
4871 struct net_device *dev1;
4872
ca519274 4873 err = -ENOMEM;
be63a21c 4874 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4875 if (dev1 && (err = register_netdev(dev1)) == 0)
4876 sky2_show_addr(dev1);
4877 else {
b02a9258
SH		 4878 dev_warn(&pdev->dev,
4879 "register of second port failed (%d)\n", err);
cd28ab6a 4880 hw->dev[1] = NULL;
ca519274
SH		 4881 hw->ports = 1;
4882 if (dev1)
4883 free_netdev(dev1);
4884 }
cd28ab6a
SH		 4885 }
4886
32c2c300 4887 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4888 INIT_WORK(&hw->restart_work, sky2_restart);
4889
793b883e 4890 pci_set_drvdata(pdev, hw);
1ae861e6 4891 pdev->d3_delay = 150;
793b883e 4892
cd28ab6a
SH		 4893 return 0;
4894
793b883e 4895err_out_unregister:
ea76e635 4896 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4897 pci_disable_msi(pdev);
793b883e 4898 unregister_netdev(dev);
cd28ab6a
SH		 4899err_out_free_netdev:
4900 free_netdev(dev);
cd28ab6a 4901err_out_free_pci:
efe91932 4902 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4903 hw->st_le, hw->st_dma);
4904err_out_reset:
793b883e 4905 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4906err_out_iounmap:
4907 iounmap(hw->regs);
4908err_out_free_hw:
4909 kfree(hw);
4910err_out_free_regions:
4911 pci_release_regions(pdev);
44a1d2e5 4912err_out_disable:
cd28ab6a 4913 pci_disable_device(pdev);
cd28ab6a 4914err_out:
549a68c3 4915 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4916 return err;
4917}
4918
4919static void __devexit sky2_remove(struct pci_dev *pdev)
4920{
793b883e 4921 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4922 int i;
cd28ab6a 4923
793b883e 4924 if (!hw)
cd28ab6a
SH		 4925 return;
4926
32c2c300 4927 del_timer_sync(&hw->watchdog_timer);
6de16237 4928 cancel_work_sync(&hw->restart_work);
d27ed387 4929
b877fe28 4930 for (i = hw->ports-1; i >= 0; --i)
6de16237 4931 unregister_netdev(hw->dev[i]);
81906791 4932
d27ed387 4933 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4934
ae306cca
SH		 4935 sky2_power_aux(hw);
4936
793b883e 4937 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4938 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4939
4940 free_irq(pdev->irq, hw);
ea76e635 4941 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4942 pci_disable_msi(pdev);
efe91932 4943 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4944 hw->st_le, hw->st_dma);
cd28ab6a
SH		 4945 pci_release_regions(pdev);
4946 pci_disable_device(pdev);
793b883e 4947
b877fe28 4948 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4949 free_netdev(hw->dev[i]);
4950
cd28ab6a
SH		 4951 iounmap(hw->regs);
4952 kfree(hw);
5afa0a9c 4953
cd28ab6a
SH		 4954 pci_set_drvdata(pdev, NULL);
4955}
4956
0f333d10 4957static int sky2_suspend(struct device *dev)
cd28ab6a 4958{
0f333d10 4959 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 4960 struct sky2_hw *hw = pci_get_drvdata(pdev);
0f333d10 4961 int i;
cd28ab6a 4962
549a68c3
SH		 4963 if (!hw)
4964 return 0;
4965
063a0b38
SH		 4966 del_timer_sync(&hw->watchdog_timer);
4967 cancel_work_sync(&hw->restart_work);
4968
19720737 4969 rtnl_lock();
3403aca2
MM		 4970
4971 sky2_all_down(hw);
f05267e7 4972 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4973 struct net_device *dev = hw->dev[i];
e3173832 4974 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4975
e3173832
SH		 4976 if (sky2->wol)
4977 sky2_wol_init(sky2);
cd28ab6a
SH		 4978 }
4979
ae306cca 4980 sky2_power_aux(hw);
19720737 4981 rtnl_unlock();
e3173832 4982
2ccc99b7 4983 return 0;
cd28ab6a
SH		 4984}
4985
94252763 4986#ifdef CONFIG_PM_SLEEP
0f333d10 4987static int sky2_resume(struct device *dev)
cd28ab6a 4988{
0f333d10 4989 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 4990 struct sky2_hw *hw = pci_get_drvdata(pdev);
3403aca2 4991 int err;
cd28ab6a 4992
549a68c3
SH		 4993 if (!hw)
4994 return 0;
4995
1ad5b4a5 4996 /* Re-enable all clocks */
a0db28b8 4997 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4998 if (err) {
4999 dev_err(&pdev->dev, "PCI write config failed\n");
5000 goto out;
5001 }
1ad5b4a5 5002
3403aca2 5003 rtnl_lock();
e3173832 5004 sky2_reset(hw);
3403aca2 5005 sky2_all_up(hw);
af18d8b8 5006 rtnl_unlock();
eb35cf60 5007
ae306cca 5008 return 0;
08c06d8a 5009out:
af18d8b8 5010
b02a9258 5011 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 5012 pci_disable_device(pdev);
08c06d8a 5013 return err;
cd28ab6a 5014}
0f333d10
RW		 5015
5016static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5017#define SKY2_PM_OPS (&sky2_pm_ops)
5018
5019#else
5020
5021#define SKY2_PM_OPS NULL
cd28ab6a
SH		 5022#endif
5023
e3173832
SH		 5024static void sky2_shutdown(struct pci_dev *pdev)
5025{
0f333d10
RW		 5026 sky2_suspend(&pdev->dev);
5027 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5028 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 5029}
5030
cd28ab6a 5031static struct pci_driver sky2_driver = {
793b883e
SH		 5032 .name = DRV_NAME,
5033 .id_table = sky2_id_table,
5034 .probe = sky2_probe,
5035 .remove = __devexit_p(sky2_remove),
e3173832 5036 .shutdown = sky2_shutdown,
0f333d10 5037 .driver.pm = SKY2_PM_OPS,
cd28ab6a
SH		 5038};
5039
5040static int __init sky2_init_module(void)
5041{
ada1db5c 5042 pr_info("driver version " DRV_VERSION "\n");
c844d483 5043
3cf26753 5044 sky2_debug_init();
50241c4c 5045 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 5046}
5047
5048static void __exit sky2_cleanup_module(void)
5049{
5050 pci_unregister_driver(&sky2_driver);
3cf26753 5051 sky2_debug_cleanup();
cd28ab6a
SH		 5052}
5053
5054module_init(sky2_init_module);
5055module_exit(sky2_cleanup_module);
5056
5057MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 5058MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 5059MODULE_LICENSE("GPL");
5f4f9dc1 5060MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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