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Merge remote-tracking branch 'selinux/next'
[deliverable/linux.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
9cb00073 19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
2e55cc72
DB		 20 */
21
607740bc 22#include "asix.h"
933a27d3
DH		 23
24#define PHY_MODE_MARVELL 0x0000
25#define MII_MARVELL_LED_CTRL 0x0018
26#define MII_MARVELL_STATUS 0x001b
27#define MII_MARVELL_CTRL 0x0014
28
29#define MARVELL_LED_MANUAL 0x0019
30
31#define MARVELL_STATUS_HWCFG 0x0004
32
33#define MARVELL_CTRL_TXDELAY 0x0002
34#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 35
3486140e 36#define PHY_MODE_RTL8211CL 0x000C
610d885d 37
4c1442aa
RF		 38#define AX88772A_PHY14H 0x14
39#define AX88772A_PHY14H_DEFAULT 0x442C
40
41#define AX88772A_PHY15H 0x15
42#define AX88772A_PHY15H_DEFAULT 0x03C8
43
44#define AX88772A_PHY16H 0x16
45#define AX88772A_PHY16H_DEFAULT 0x4044
46
2e55cc72 47struct ax88172_int_data {
51bf2976 48 __le16 res1;
2e55cc72 49 u8 link;
51bf2976 50 __le16 res2;
2e55cc72 51 u8 status;
51bf2976 52 __le16 res3;
ba2d3587 53} __packed;
2e55cc72 54
933a27d3
DH		 55static void asix_status(struct usbnet *dev, struct urb *urb)
56{
57 struct ax88172_int_data *event;
58 int link;
59
60 if (urb->actual_length < 8)
61 return;
62
63 event = urb->transfer_buffer;
64 link = event->link & 0x01;
65 if (netif_carrier_ok(dev->net) != link) {
eae65919 66 usbnet_link_change(dev, link, 1);
60b86755 67 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 68 }
69}
70
452b5ecd
JCPV		 71static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
72{
73 if (is_valid_ether_addr(addr)) {
74 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
75 } else {
76 netdev_info(dev->net, "invalid hw address, using random\n");
77 eth_hw_addr_random(dev->net);
78 }
79}
80
933a27d3
DH		 81/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
82static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 83{
933a27d3
DH		 84 int phy_reg;
85 u32 phy_id;
a77929a2 86 int i;
2e55cc72 87
a77929a2
GG		 88 /* Poll for the rare case the FW or phy isn't ready yet. */
89 for (i = 0; i < 100; i++) {
90 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
8a46f665
RF		 91 if (phy_reg < 0)
92 return 0;
a77929a2
GG		 93 if (phy_reg != 0 && phy_reg != 0xFFFF)
94 break;
95 mdelay(1);
96 }
97
98 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 99 return 0;
2e55cc72 100
933a27d3 101 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 102
933a27d3
DH		 103 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
104 if (phy_reg < 0)
105 return 0;
106
107 phy_id |= (phy_reg & 0xffff);
108
109 return phy_id;
2e55cc72
DB		 110}
111
933a27d3
DH		 112static u32 asix_get_link(struct net_device *net)
113{
114 struct usbnet *dev = netdev_priv(net);
115
116 return mii_link_ok(&dev->mii);
117}
118
119static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
120{
121 struct usbnet *dev = netdev_priv(net);
122
123 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
124}
125
126/* We need to override some ethtool_ops so we require our
127 own structure so we don't interfere with other usbnet
128 devices that may be connected at the same time. */
0fc0b732 129static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 130 .get_drvinfo = asix_get_drvinfo,
131 .get_link = asix_get_link,
933a27d3 132 .get_msglevel = usbnet_get_msglevel,
2e55cc72 133 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 134 .get_wol = asix_get_wol,
135 .set_wol = asix_set_wol,
136 .get_eeprom_len = asix_get_eeprom_len,
137 .get_eeprom = asix_get_eeprom,
cb7b24cd 138 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 139 .get_settings = usbnet_get_settings,
140 .set_settings = usbnet_set_settings,
141 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 142};
143
933a27d3 144static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 145{
146 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 147 struct asix_data *data = (struct asix_data *)&dev->data;
148 u8 rx_ctl = 0x8c;
2e55cc72 149
933a27d3
DH		 150 if (net->flags & IFF_PROMISC) {
151 rx_ctl |= 0x01;
8e95a202 152 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 153 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 154 rx_ctl |= 0x02;
4cd24eaf 155 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 156 /* just broadcast and directed */
157 } else {
158 /* We use the 20 byte dev->data
159 * for our 8 byte filter buffer
160 * to avoid allocating memory that
161 * is tricky to free later */
22bedad3 162 struct netdev_hw_addr *ha;
933a27d3 163 u32 crc_bits;
933a27d3
DH		 164
165 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
166
167 /* Build the multicast hash filter. */
22bedad3
JP		 168 netdev_for_each_mc_addr(ha, net) {
169 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH		 170 data->multi_filter[crc_bits >> 3] |=
171 1 << (crc_bits & 7);
933a27d3
DH		 172 }
173
174 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
175 AX_MCAST_FILTER_SIZE, data->multi_filter);
176
177 rx_ctl |= 0x10;
178 }
179
180 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
181}
182
183static int ax88172_link_reset(struct usbnet *dev)
184{
185 u8 mode;
8ae6daca 186 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 187
188 mii_check_media(&dev->mii, 1, 1);
189 mii_ethtool_gset(&dev->mii, &ecmd);
190 mode = AX88172_MEDIUM_DEFAULT;
191
192 if (ecmd.duplex != DUPLEX_FULL)
193 mode |= ~AX88172_MEDIUM_FD;
194
8ae6daca
DD		 195 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
196 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3 197
d9fe64e5 198 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 199
200 return 0;
2e55cc72
DB		 201}
202
1703338c
SH		 203static const struct net_device_ops ax88172_netdev_ops = {
204 .ndo_open = usbnet_open,
205 .ndo_stop = usbnet_stop,
206 .ndo_start_xmit = usbnet_start_xmit,
207 .ndo_tx_timeout = usbnet_tx_timeout,
208 .ndo_change_mtu = usbnet_change_mtu,
209 .ndo_set_mac_address = eth_mac_addr,
210 .ndo_validate_addr = eth_validate_addr,
211 .ndo_do_ioctl = asix_ioctl,
afc4b13d 212 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH		 213};
214
a243c2ef
RF		 215static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
216{
217 unsigned int timeout = 5000;
218
219 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
220
221 /* give phy_id a chance to process reset */
222 udelay(500);
223
224 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
225 while (timeout--) {
226 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
227 & BMCR_RESET)
228 udelay(100);
229 else
230 return;
231 }
232
233 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
234 dev->mii.phy_id);
235}
236
48b1be6a 237static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 238{
239 int ret = 0;
51bf2976 240 u8 buf[ETH_ALEN];
2e55cc72
DB		 241 int i;
242 unsigned long gpio_bits = dev->driver_info->data;
243
244 usbnet_get_endpoints(dev,intf);
245
2e55cc72
DB		 246 /* Toggle the GPIOs in a manufacturer/model specific way */
247 for (i = 2; i >= 0; i--) {
83e1b918 248 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
d9fe64e5 249 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
83e1b918 250 if (ret < 0)
51bf2976 251 goto out;
2e55cc72
DB		 252 msleep(5);
253 }
254
d9fe64e5 255 ret = asix_write_rx_ctl(dev, 0x80, 0);
83e1b918 256 if (ret < 0)
51bf2976 257 goto out;
2e55cc72
DB		 258
259 /* Get the MAC address */
d9fe64e5
RF		 260 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
261 0, 0, ETH_ALEN, buf, 0);
83e1b918 262 if (ret < 0) {
49ae25b0
GKH		 263 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
264 ret);
51bf2976 265 goto out;
2e55cc72 266 }
452b5ecd
JCPV		 267
268 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 269
2e55cc72
DB		 270 /* Initialize MII structure */
271 dev->mii.dev = dev->net;
48b1be6a
DH		 272 dev->mii.mdio_read = asix_mdio_read;
273 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 274 dev->mii.phy_id_mask = 0x3f;
275 dev->mii.reg_num_mask = 0x1f;
933a27d3 276 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 277
1703338c 278 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 279 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED		 280 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
281 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 282
a243c2ef 283 asix_phy_reset(dev, BMCR_RESET);
933a27d3 284 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 285 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
286 mii_nway_restart(&dev->mii);
287
288 return 0;
51bf2976
AV		 289
290out:
2e55cc72
DB		 291 return ret;
292}
293
0fc0b732 294static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 295 .get_drvinfo = asix_get_drvinfo,
933a27d3 296 .get_link = asix_get_link,
2e55cc72
DB		 297 .get_msglevel = usbnet_get_msglevel,
298 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 299 .get_wol = asix_get_wol,
300 .set_wol = asix_set_wol,
301 .get_eeprom_len = asix_get_eeprom_len,
302 .get_eeprom = asix_get_eeprom,
cb7b24cd 303 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 304 .get_settings = usbnet_get_settings,
305 .set_settings = usbnet_set_settings,
306 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 307};
308
933a27d3
DH		 309static int ax88772_link_reset(struct usbnet *dev)
310{
311 u16 mode;
8ae6daca 312 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 313
314 mii_check_media(&dev->mii, 1, 1);
315 mii_ethtool_gset(&dev->mii, &ecmd);
316 mode = AX88772_MEDIUM_DEFAULT;
317
8ae6daca 318 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH		 319 mode &= ~AX_MEDIUM_PS;
320
321 if (ecmd.duplex != DUPLEX_FULL)
322 mode &= ~AX_MEDIUM_FD;
323
8ae6daca
DD		 324 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
325 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3 326
d9fe64e5 327 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 328
329 return 0;
330}
331
4ad1438f 332static int ax88772_reset(struct usbnet *dev)
d9fe64e5
RF		 333{
334 struct asix_data *data = (struct asix_data *)&dev->data;
335 int ret;
336
337 /* Rewrite MAC address */
338 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
339 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
340 ETH_ALEN, data->mac_addr, 0);
341 if (ret < 0)
342 goto out;
343
344 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
345 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
346 if (ret < 0)
347 goto out;
348
349 asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
350 if (ret < 0)
351 goto out;
352
353 return 0;
354
355out:
356 return ret;
357}
358
359static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
2e55cc72 360{
8ef66bdc 361 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 362 int ret, embd_phy;
933a27d3 363 u16 rx_ctl;
2e55cc72 364
d9fe64e5
RF		 365 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
366 AX_GPIO_GPO2EN, 5, in_pm);
83e1b918 367 if (ret < 0)
51bf2976 368 goto out;
2e55cc72 369
d9fe64e5 370 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 371
d9fe64e5
RF		 372 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy,
373 0, 0, NULL, in_pm);
83e1b918 374 if (ret < 0) {
49ae25b0 375 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
51bf2976 376 goto out;
2e55cc72
DB		 377 }
378
d9fe64e5
RF		 379 if (embd_phy) {
380 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
381 if (ret < 0)
382 goto out;
2e55cc72 383
d9fe64e5 384 usleep_range(10000, 11000);
83e1b918 385
d9fe64e5
RF		 386 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
387 if (ret < 0)
388 goto out;
2e55cc72 389
d9fe64e5 390 msleep(60);
4ad1438f 391
d9fe64e5
RF		 392 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
393 in_pm);
83e1b918 394 if (ret < 0)
51bf2976 395 goto out;
83e1b918 396 } else {
d9fe64e5
RF		 397 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
398 in_pm);
83e1b918 399 if (ret < 0)
51bf2976 400 goto out;
d0ffff8f 401 }
2e55cc72
DB		 402
403 msleep(150);
d9fe64e5
RF		 404
405 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
406 MII_PHYSID1))){
407 ret = -EIO;
408 goto out;
409 }
410
411 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
412 if (ret < 0)
413 goto out;
414
415 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
83e1b918 416 if (ret < 0)
51bf2976 417 goto out;
2e55cc72 418
d9fe64e5
RF		 419 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
420 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
421 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
422 if (ret < 0) {
423 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
424 goto out;
425 }
933a27d3 426
d9fe64e5
RF		 427 /* Rewrite MAC address */
428 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
429 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
430 ETH_ALEN, data->mac_addr, in_pm);
83e1b918 431 if (ret < 0)
51bf2976 432 goto out;
2e55cc72 433
d9fe64e5
RF		 434 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
435 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
436 if (ret < 0)
437 goto out;
438
439 rx_ctl = asix_read_rx_ctl(dev, in_pm);
440 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
441 rx_ctl);
442
443 rx_ctl = asix_read_medium_status(dev, in_pm);
444 netdev_dbg(dev->net,
445 "Medium Status is 0x%04x after all initializations\n",
446 rx_ctl);
447
448 return 0;
449
450out:
451 return ret;
452}
453
454static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
455{
456 struct asix_data *data = (struct asix_data *)&dev->data;
457 int ret, embd_phy;
4c1442aa 458 u16 rx_ctl, phy14h, phy15h, phy16h;
d9fe64e5 459 u8 chipcode = 0;
48b1be6a 460
d9fe64e5 461 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
83e1b918 462 if (ret < 0)
51bf2976 463 goto out;
2e55cc72 464
d9fe64e5 465 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
2e55cc72 466
d9fe64e5
RF		 467 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy |
468 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
469 if (ret < 0) {
470 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
471 goto out;
472 }
473 usleep_range(10000, 11000);
2e55cc72 474
d9fe64e5 475 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
83e1b918 476 if (ret < 0)
51bf2976 477 goto out;
2e55cc72 478
d9fe64e5
RF		 479 usleep_range(10000, 11000);
480
481 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
482 if (ret < 0)
483 goto out;
484
485 msleep(160);
486
487 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
488 if (ret < 0)
489 goto out;
490
491 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
492 if (ret < 0)
493 goto out;
494
495 msleep(200);
496
497 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
498 MII_PHYSID1))) {
499 ret = -1;
500 goto out;
501 }
502
503 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0,
504 0, 1, &chipcode, in_pm);
505 if (ret < 0)
506 goto out;
507
508 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) {
509 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
510 0, NULL, in_pm);
511 if (ret < 0) {
512 netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
513 ret);
514 goto out;
515 }
4c1442aa
RF		 516 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) {
517 /* Check if the PHY registers have default settings */
518 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
519 AX88772A_PHY14H);
520 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
521 AX88772A_PHY15H);
522 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
523 AX88772A_PHY16H);
524
525 netdev_dbg(dev->net,
526 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
527 phy14h, phy15h, phy16h);
528
529 /* Restore PHY registers default setting if not */
530 if (phy14h != AX88772A_PHY14H_DEFAULT)
531 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
532 AX88772A_PHY14H,
533 AX88772A_PHY14H_DEFAULT);
534 if (phy15h != AX88772A_PHY15H_DEFAULT)
535 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
536 AX88772A_PHY15H,
537 AX88772A_PHY15H_DEFAULT);
538 if (phy16h != AX88772A_PHY16H_DEFAULT)
539 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
540 AX88772A_PHY16H,
541 AX88772A_PHY16H_DEFAULT);
d9fe64e5
RF		 542 }
543
83e1b918 544 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 545 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
d9fe64e5 546 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
83e1b918 547 if (ret < 0) {
49ae25b0 548 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
51bf2976 549 goto out;
2e55cc72 550 }
2e55cc72 551
8ef66bdc
JK		 552 /* Rewrite MAC address */
553 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
554 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
d9fe64e5
RF		 555 data->mac_addr, in_pm);
556 if (ret < 0)
557 goto out;
558
559 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
560 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
8ef66bdc
JK		 561 if (ret < 0)
562 goto out;
563
d9fe64e5
RF		 564 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
565 if (ret < 0)
566 return ret;
567
2e55cc72 568 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
d9fe64e5 569 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
83e1b918 570 if (ret < 0)
51bf2976 571 goto out;
2e55cc72 572
d9fe64e5 573 rx_ctl = asix_read_rx_ctl(dev, in_pm);
49ae25b0
GKH		 574 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
575 rx_ctl);
933a27d3 576
d9fe64e5 577 rx_ctl = asix_read_medium_status(dev, in_pm);
49ae25b0
GKH		 578 netdev_dbg(dev->net,
579 "Medium Status is 0x%04x after all initializations\n",
580 rx_ctl);
933a27d3 581
4ad1438f
GG		 582 return 0;
583
584out:
585 return ret;
4ad1438f
GG		 586}
587
588static const struct net_device_ops ax88772_netdev_ops = {
589 .ndo_open = usbnet_open,
590 .ndo_stop = usbnet_stop,
591 .ndo_start_xmit = usbnet_start_xmit,
592 .ndo_tx_timeout = usbnet_tx_timeout,
593 .ndo_change_mtu = usbnet_change_mtu,
594 .ndo_set_mac_address = asix_set_mac_address,
595 .ndo_validate_addr = eth_validate_addr,
596 .ndo_do_ioctl = asix_ioctl,
597 .ndo_set_rx_mode = asix_set_multicast,
598};
599
d9fe64e5
RF		 600static void ax88772_suspend(struct usbnet *dev)
601{
602 struct asix_common_private *priv = dev->driver_priv;
4c1442aa
RF		 603 u16 medium;
604
605 /* Stop MAC operation */
606 medium = asix_read_medium_status(dev, 0);
607 medium &= ~AX_MEDIUM_RE;
608 asix_write_medium_mode(dev, medium, 0);
609
610 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
611 asix_read_medium_status(dev, 0));
d9fe64e5
RF		 612
613 /* Preserve BMCR for restoring */
614 priv->presvd_phy_bmcr =
615 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
616
617 /* Preserve ANAR for restoring */
618 priv->presvd_phy_advertise =
619 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
620}
621
622static int asix_suspend(struct usb_interface *intf, pm_message_t message)
623{
624 struct usbnet *dev = usb_get_intfdata(intf);
625 struct asix_common_private *priv = dev->driver_priv;
626
627 if (priv->suspend)
628 priv->suspend(dev);
629
630 return usbnet_suspend(intf, message);
631}
632
633static void ax88772_restore_phy(struct usbnet *dev)
634{
635 struct asix_common_private *priv = dev->driver_priv;
636
637 if (priv->presvd_phy_advertise) {
638 /* Restore Advertisement control reg */
639 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
640 priv->presvd_phy_advertise);
641
642 /* Restore BMCR */
643 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
644 priv->presvd_phy_bmcr);
645
4c1442aa 646 mii_nway_restart(&dev->mii);
d9fe64e5
RF		 647 priv->presvd_phy_advertise = 0;
648 priv->presvd_phy_bmcr = 0;
649 }
650}
651
652static void ax88772_resume(struct usbnet *dev)
653{
654 int i;
655
656 for (i = 0; i < 3; i++)
657 if (!ax88772_hw_reset(dev, 1))
658 break;
659 ax88772_restore_phy(dev);
660}
661
662static void ax88772a_resume(struct usbnet *dev)
663{
664 int i;
665
666 for (i = 0; i < 3; i++) {
667 if (!ax88772a_hw_reset(dev, 1))
668 break;
669 }
670
671 ax88772_restore_phy(dev);
672}
673
674static int asix_resume(struct usb_interface *intf)
675{
676 struct usbnet *dev = usb_get_intfdata(intf);
677 struct asix_common_private *priv = dev->driver_priv;
678
679 if (priv->resume)
680 priv->resume(dev);
681
682 return usbnet_resume(intf);
683}
684
4ad1438f
GG		 685static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
686{
d9fe64e5
RF		 687 int ret, i;
688 u8 buf[ETH_ALEN], chipcode = 0;
4ad1438f 689 u32 phyid;
d9fe64e5 690 struct asix_common_private *priv;
4ad1438f 691
4ad1438f
GG		 692 usbnet_get_endpoints(dev,intf);
693
694 /* Get the MAC address */
5620df65
LS		 695 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
696 for (i = 0; i < (ETH_ALEN >> 1); i++) {
697 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
d9fe64e5 698 0, 2, buf + i * 2, 0);
5620df65
LS		 699 if (ret < 0)
700 break;
701 }
702 } else {
703 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
d9fe64e5 704 0, 0, ETH_ALEN, buf, 0);
5620df65
LS		 705 }
706
83e1b918 707 if (ret < 0) {
49ae25b0 708 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 709 return ret;
4ad1438f 710 }
452b5ecd
JCPV		 711
712 asix_set_netdev_dev_addr(dev, buf);
4ad1438f
GG		 713
714 /* Initialize MII structure */
715 dev->mii.dev = dev->net;
716 dev->mii.mdio_read = asix_mdio_read;
717 dev->mii.mdio_write = asix_mdio_write;
718 dev->mii.phy_id_mask = 0x1f;
719 dev->mii.reg_num_mask = 0x1f;
720 dev->mii.phy_id = asix_get_phy_addr(dev);
721
4ad1438f
GG		 722 dev->net->netdev_ops = &ax88772_netdev_ops;
723 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED		 724 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
725 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 726
d9fe64e5
RF		 727 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0);
728 chipcode &= AX_CHIPCODE_MASK;
d3665188 729
d9fe64e5
RF		 730 (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) :
731 ax88772a_hw_reset(dev, 0);
d3665188
GG		 732
733 /* Read PHYID register *AFTER* the PHY was reset properly */
734 phyid = asix_get_phyid(dev);
49ae25b0 735 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
d3665188 736
2e55cc72
DB		 737 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
738 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
739 /* hard_mtu is still the default - the device does not support
740 jumbo eth frames */
741 dev->rx_urb_size = 2048;
742 }
83e1b918 743
8b5b6f54
LS		 744 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
745 if (!dev->driver_priv)
746 return -ENOMEM;
747
d9fe64e5
RF		 748 priv = dev->driver_priv;
749
750 priv->presvd_phy_bmcr = 0;
751 priv->presvd_phy_advertise = 0;
752 if (chipcode == AX_AX88772_CHIPCODE) {
753 priv->resume = ax88772_resume;
754 priv->suspend = ax88772_suspend;
755 } else {
756 priv->resume = ax88772a_resume;
757 priv->suspend = ax88772_suspend;
758 }
759
2e55cc72 760 return 0;
2e55cc72
DB		 761}
762
ad327910 763static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
8b5b6f54 764{
91ecee68 765 kfree(dev->driver_priv);
8b5b6f54
LS		 766}
767
bc689c97 768static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH		 769 .get_drvinfo = asix_get_drvinfo,
770 .get_link = asix_get_link,
933a27d3
DH		 771 .get_msglevel = usbnet_get_msglevel,
772 .set_msglevel = usbnet_set_msglevel,
773 .get_wol = asix_get_wol,
774 .set_wol = asix_set_wol,
775 .get_eeprom_len = asix_get_eeprom_len,
776 .get_eeprom = asix_get_eeprom,
cb7b24cd 777 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 778 .get_settings = usbnet_get_settings,
779 .set_settings = usbnet_set_settings,
780 .nway_reset = usbnet_nway_reset,
933a27d3
DH		 781};
782
783static int marvell_phy_init(struct usbnet *dev)
2e55cc72 784{
933a27d3
DH		 785 struct asix_data *data = (struct asix_data *)&dev->data;
786 u16 reg;
2e55cc72 787
60b86755 788 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 789
933a27d3 790 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 791 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 792
933a27d3
DH		 793 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
794 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 795
933a27d3
DH		 796 if (data->ledmode) {
797 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
798 MII_MARVELL_LED_CTRL);
60b86755 799 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 800
933a27d3
DH		 801 reg &= 0xf8ff;
802 reg |= (1 + 0x0100);
803 asix_mdio_write(dev->net, dev->mii.phy_id,
804 MII_MARVELL_LED_CTRL, reg);
2e55cc72 805
933a27d3
DH		 806 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
807 MII_MARVELL_LED_CTRL);
60b86755 808 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 809 reg &= 0xfc0f;
810 }
2e55cc72 811
933a27d3
DH		 812 return 0;
813}
814
610d885d
GG		 815static int rtl8211cl_phy_init(struct usbnet *dev)
816{
817 struct asix_data *data = (struct asix_data *)&dev->data;
818
819 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
820
821 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
822 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
823 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
824 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
825 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
826
827 if (data->ledmode == 12) {
828 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
829 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
830 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
831 }
832
833 return 0;
834}
835
933a27d3
DH		 836static int marvell_led_status(struct usbnet *dev, u16 speed)
837{
838 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
839
60b86755 840 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 841
842 /* Clear out the center LED bits - 0x03F0 */
843 reg &= 0xfc0f;
844
845 switch (speed) {
846 case SPEED_1000:
847 reg |= 0x03e0;
848 break;
849 case SPEED_100:
850 reg |= 0x03b0;
851 break;
852 default:
853 reg |= 0x02f0;
2e55cc72
DB		 854 }
855
60b86755 856 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 857 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
858
859 return 0;
860}
861
610d885d
GG		 862static int ax88178_reset(struct usbnet *dev)
863{
864 struct asix_data *data = (struct asix_data *)&dev->data;
865 int ret;
866 __le16 eeprom;
867 u8 status;
868 int gpio0 = 0;
b2d3ad29 869 u32 phyid;
610d885d 870
d9fe64e5 871 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
49ae25b0 872 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
610d885d 873
d9fe64e5
RF		 874 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
875 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
876 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
610d885d 877
49ae25b0 878 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
610d885d
GG		 879
880 if (eeprom == cpu_to_le16(0xffff)) {
881 data->phymode = PHY_MODE_MARVELL;
882 data->ledmode = 0;
883 gpio0 = 1;
884 } else {
b2d3ad29 885 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG		 886 data->ledmode = le16_to_cpu(eeprom) >> 8;
887 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
888 }
49ae25b0 889 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
610d885d 890
b2d3ad29 891 /* Power up external GigaPHY through AX88178 GPIO pin */
d9fe64e5
RF		 892 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
893 AX_GPIO_GPO1EN, 40, 0);
610d885d 894 if ((le16_to_cpu(eeprom) >> 8) != 1) {
d9fe64e5
RF		 895 asix_write_gpio(dev, 0x003c, 30, 0);
896 asix_write_gpio(dev, 0x001c, 300, 0);
897 asix_write_gpio(dev, 0x003c, 30, 0);
610d885d 898 } else {
49ae25b0 899 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
d9fe64e5
RF		 900 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
901 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
610d885d
GG		 902 }
903
b2d3ad29
GG		 904 /* Read PHYID register *AFTER* powering up PHY */
905 phyid = asix_get_phyid(dev);
49ae25b0 906 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
b2d3ad29
GG		 907
908 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
d9fe64e5 909 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
b2d3ad29 910
d9fe64e5 911 asix_sw_reset(dev, 0, 0);
610d885d
GG		 912 msleep(150);
913
d9fe64e5 914 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
610d885d
GG		 915 msleep(150);
916
d9fe64e5 917 asix_write_rx_ctl(dev, 0, 0);
610d885d
GG		 918
919 if (data->phymode == PHY_MODE_MARVELL) {
920 marvell_phy_init(dev);
921 msleep(60);
922 } else if (data->phymode == PHY_MODE_RTL8211CL)
923 rtl8211cl_phy_init(dev);
924
a243c2ef 925 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
610d885d
GG		 926 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
927 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
928 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
929 ADVERTISE_1000FULL);
930
535baf85 931 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
610d885d
GG		 932 mii_nway_restart(&dev->mii);
933
71bc5d94
JK		 934 /* Rewrite MAC address */
935 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
936 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
d9fe64e5 937 data->mac_addr, 0);
71bc5d94
JK		 938 if (ret < 0)
939 return ret;
940
d9fe64e5 941 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
83e1b918
GG		 942 if (ret < 0)
943 return ret;
610d885d
GG		 944
945 return 0;
610d885d
GG		 946}
947
933a27d3
DH		 948static int ax88178_link_reset(struct usbnet *dev)
949{
950 u16 mode;
8ae6daca 951 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 952 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 953 u32 speed;
933a27d3 954
60b86755 955 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 956
957 mii_check_media(&dev->mii, 1, 1);
958 mii_ethtool_gset(&dev->mii, &ecmd);
959 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 960 speed = ethtool_cmd_speed(&ecmd);
933a27d3 961
8ae6daca 962 if (speed == SPEED_1000)
a7f75c0c 963 mode |= AX_MEDIUM_GM;
8ae6daca 964 else if (speed == SPEED_100)
933a27d3
DH		 965 mode |= AX_MEDIUM_PS;
966 else
967 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
968
a7f75c0c
PK		 969 mode |= AX_MEDIUM_ENCK;
970
933a27d3
DH		 971 if (ecmd.duplex == DUPLEX_FULL)
972 mode |= AX_MEDIUM_FD;
973 else
974 mode &= ~AX_MEDIUM_FD;
975
8ae6daca
DD		 976 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
977 speed, ecmd.duplex, mode);
933a27d3 978
d9fe64e5 979 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 980
981 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 982 marvell_led_status(dev, speed);
933a27d3
DH		 983
984 return 0;
985}
986
987static void ax88178_set_mfb(struct usbnet *dev)
988{
989 u16 mfb = AX_RX_CTL_MFB_16384;
990 u16 rxctl;
991 u16 medium;
992 int old_rx_urb_size = dev->rx_urb_size;
993
994 if (dev->hard_mtu < 2048) {
995 dev->rx_urb_size = 2048;
996 mfb = AX_RX_CTL_MFB_2048;
997 } else if (dev->hard_mtu < 4096) {
998 dev->rx_urb_size = 4096;
999 mfb = AX_RX_CTL_MFB_4096;
1000 } else if (dev->hard_mtu < 8192) {
1001 dev->rx_urb_size = 8192;
1002 mfb = AX_RX_CTL_MFB_8192;
1003 } else if (dev->hard_mtu < 16384) {
1004 dev->rx_urb_size = 16384;
1005 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 1006 }
933a27d3 1007
d9fe64e5
RF		 1008 rxctl = asix_read_rx_ctl(dev, 0);
1009 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
933a27d3 1010
d9fe64e5 1011 medium = asix_read_medium_status(dev, 0);
933a27d3
DH		 1012 if (dev->net->mtu > 1500)
1013 medium |= AX_MEDIUM_JFE;
1014 else
1015 medium &= ~AX_MEDIUM_JFE;
d9fe64e5 1016 asix_write_medium_mode(dev, medium, 0);
933a27d3
DH		 1017
1018 if (dev->rx_urb_size > old_rx_urb_size)
1019 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 1020}
1021
933a27d3 1022static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 1023{
933a27d3
DH		 1024 struct usbnet *dev = netdev_priv(net);
1025 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 1026
60b86755 1027 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 1028
933a27d3
DH		 1029 if (new_mtu <= 0 || ll_mtu > 16384)
1030 return -EINVAL;
1031
1032 if ((ll_mtu % dev->maxpacket) == 0)
1033 return -EDOM;
1034
1035 net->mtu = new_mtu;
1036 dev->hard_mtu = net->mtu + net->hard_header_len;
1037 ax88178_set_mfb(dev);
1038
a88c32ae
ML		 1039 /* max qlen depend on hard_mtu and rx_urb_size */
1040 usbnet_update_max_qlen(dev);
1041
933a27d3
DH		 1042 return 0;
1043}
1044
1703338c
SH		 1045static const struct net_device_ops ax88178_netdev_ops = {
1046 .ndo_open = usbnet_open,
1047 .ndo_stop = usbnet_stop,
1048 .ndo_start_xmit = usbnet_start_xmit,
1049 .ndo_tx_timeout = usbnet_tx_timeout,
7f29a3ba 1050 .ndo_set_mac_address = asix_set_mac_address,
1703338c 1051 .ndo_validate_addr = eth_validate_addr,
afc4b13d 1052 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH		 1053 .ndo_do_ioctl = asix_ioctl,
1054 .ndo_change_mtu = ax88178_change_mtu,
1055};
1056
933a27d3
DH		 1057static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1058{
933a27d3 1059 int ret;
51bf2976 1060 u8 buf[ETH_ALEN];
933a27d3
DH		 1061
1062 usbnet_get_endpoints(dev,intf);
1063
933a27d3 1064 /* Get the MAC address */
d9fe64e5 1065 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
83e1b918 1066 if (ret < 0) {
49ae25b0 1067 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 1068 return ret;
2e55cc72 1069 }
452b5ecd
JCPV		 1070
1071 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 1072
933a27d3
DH		 1073 /* Initialize MII structure */
1074 dev->mii.dev = dev->net;
1075 dev->mii.mdio_read = asix_mdio_read;
1076 dev->mii.mdio_write = asix_mdio_write;
1077 dev->mii.phy_id_mask = 0x1f;
1078 dev->mii.reg_num_mask = 0xff;
1079 dev->mii.supports_gmii = 1;
933a27d3 1080 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 1081
1082 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 1083 dev->net->ethtool_ops = &ax88178_ethtool_ops;
2e55cc72 1084
b2d3ad29 1085 /* Blink LEDS so users know driver saw dongle */
d9fe64e5 1086 asix_sw_reset(dev, 0, 0);
b2d3ad29 1087 msleep(150);
2e55cc72 1088
d9fe64e5 1089 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
b2d3ad29 1090 msleep(150);
933a27d3
DH		 1091
1092 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1093 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1094 /* hard_mtu is still the default - the device does not support
1095 jumbo eth frames */
1096 dev->rx_urb_size = 2048;
1097 }
933a27d3 1098
8b5b6f54
LS		 1099 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1100 if (!dev->driver_priv)
1101 return -ENOMEM;
1102
83e1b918 1103 return 0;
2e55cc72
DB		 1104}
1105
1106static const struct driver_info ax8817x_info = {
1107 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 1108 .bind = ax88172_bind,
1109 .status = asix_status,
2e55cc72
DB		 1110 .link_reset = ax88172_link_reset,
1111 .reset = ax88172_link_reset,
37e8273c 1112 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1113 .data = 0x00130103,
1114};
1115
1116static const struct driver_info dlink_dub_e100_info = {
1117 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 1118 .bind = ax88172_bind,
1119 .status = asix_status,
2e55cc72
DB		 1120 .link_reset = ax88172_link_reset,
1121 .reset = ax88172_link_reset,
37e8273c 1122 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1123 .data = 0x009f9d9f,
1124};
1125
1126static const struct driver_info netgear_fa120_info = {
1127 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 1128 .bind = ax88172_bind,
1129 .status = asix_status,
2e55cc72
DB		 1130 .link_reset = ax88172_link_reset,
1131 .reset = ax88172_link_reset,
37e8273c 1132 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1133 .data = 0x00130103,
1134};
1135
1136static const struct driver_info hawking_uf200_info = {
1137 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 1138 .bind = ax88172_bind,
1139 .status = asix_status,
2e55cc72
DB		 1140 .link_reset = ax88172_link_reset,
1141 .reset = ax88172_link_reset,
37e8273c 1142 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1143 .data = 0x001f1d1f,
1144};
1145
1146static const struct driver_info ax88772_info = {
1147 .description = "ASIX AX88772 USB 2.0 Ethernet",
1148 .bind = ax88772_bind,
8b5b6f54 1149 .unbind = ax88772_unbind,
48b1be6a 1150 .status = asix_status,
2e55cc72 1151 .link_reset = ax88772_link_reset,
d9fe64e5 1152 .reset = ax88772_reset,
a9e0aca4 1153 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
8b5b6f54 1154 .rx_fixup = asix_rx_fixup_common,
933a27d3
DH		 1155 .tx_fixup = asix_tx_fixup,
1156};
1157
5620df65
LS		 1158static const struct driver_info ax88772b_info = {
1159 .description = "ASIX AX88772B USB 2.0 Ethernet",
1160 .bind = ax88772_bind,
8b5b6f54 1161 .unbind = ax88772_unbind,
5620df65
LS		 1162 .status = asix_status,
1163 .link_reset = ax88772_link_reset,
1164 .reset = ax88772_reset,
1165 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1166 FLAG_MULTI_PACKET,
8b5b6f54 1167 .rx_fixup = asix_rx_fixup_common,
5620df65
LS		 1168 .tx_fixup = asix_tx_fixup,
1169 .data = FLAG_EEPROM_MAC,
1170};
1171
933a27d3
DH		 1172static const struct driver_info ax88178_info = {
1173 .description = "ASIX AX88178 USB 2.0 Ethernet",
1174 .bind = ax88178_bind,
8b5b6f54 1175 .unbind = ax88772_unbind,
933a27d3
DH		 1176 .status = asix_status,
1177 .link_reset = ax88178_link_reset,
610d885d 1178 .reset = ax88178_reset,
d43ff4cd
EG		 1179 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1180 FLAG_MULTI_PACKET,
8b5b6f54 1181 .rx_fixup = asix_rx_fixup_common,
933a27d3 1182 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 1183};
1184
45af3fb4
GT		 1185/*
1186 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1187 * no-name packaging.
1188 * USB device strings are:
1189 * 1: Manufacturer: USBLINK
1190 * 2: Product: HG20F9 USB2.0
1191 * 3: Serial: 000003
1192 * Appears to be compatible with Asix 88772B.
1193 */
1194static const struct driver_info hg20f9_info = {
1195 .description = "HG20F9 USB 2.0 Ethernet",
1196 .bind = ax88772_bind,
1197 .unbind = ax88772_unbind,
1198 .status = asix_status,
1199 .link_reset = ax88772_link_reset,
1200 .reset = ax88772_reset,
1201 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1202 FLAG_MULTI_PACKET,
1203 .rx_fixup = asix_rx_fixup_common,
1204 .tx_fixup = asix_tx_fixup,
1205 .data = FLAG_EEPROM_MAC,
1206};
1207
2e55cc72
DB		 1208static const struct usb_device_id products [] = {
1209{
1210 // Linksys USB200M
1211 USB_DEVICE (0x077b, 0x2226),
1212 .driver_info = (unsigned long) &ax8817x_info,
1213}, {
1214 // Netgear FA120
1215 USB_DEVICE (0x0846, 0x1040),
1216 .driver_info = (unsigned long) &netgear_fa120_info,
1217}, {
1218 // DLink DUB-E100
1219 USB_DEVICE (0x2001, 0x1a00),
1220 .driver_info = (unsigned long) &dlink_dub_e100_info,
1221}, {
1222 // Intellinet, ST Lab USB Ethernet
1223 USB_DEVICE (0x0b95, 0x1720),
1224 .driver_info = (unsigned long) &ax8817x_info,
1225}, {
1226 // Hawking UF200, TrendNet TU2-ET100
1227 USB_DEVICE (0x07b8, 0x420a),
1228 .driver_info = (unsigned long) &hawking_uf200_info,
1229}, {
39c4b38c
DH		 1230 // Billionton Systems, USB2AR
1231 USB_DEVICE (0x08dd, 0x90ff),
1232 .driver_info = (unsigned long) &ax8817x_info,
80083a3c
CSC		 1233}, {
1234 // Billionton Systems, GUSB2AM-1G-B
1235 USB_DEVICE(0x08dd, 0x0114),
1236 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1237}, {
1238 // ATEN UC210T
1239 USB_DEVICE (0x0557, 0x2009),
1240 .driver_info = (unsigned long) &ax8817x_info,
1241}, {
1242 // Buffalo LUA-U2-KTX
1243 USB_DEVICE (0x0411, 0x003d),
1244 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 1245}, {
1246 // Buffalo LUA-U2-GT 10/100/1000
1247 USB_DEVICE (0x0411, 0x006e),
1248 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1249}, {
1250 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1251 USB_DEVICE (0x6189, 0x182d),
1252 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN		 1253}, {
1254 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1255 USB_DEVICE (0x0df6, 0x0056),
1256 .driver_info = (unsigned long) &ax88178_info,
7488c3e3
LC		 1257}, {
1258 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1259 USB_DEVICE (0x0df6, 0x061c),
1260 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1261}, {
1262 // corega FEther USB2-TX
1263 USB_DEVICE (0x07aa, 0x0017),
1264 .driver_info = (unsigned long) &ax8817x_info,
1265}, {
1266 // Surecom EP-1427X-2
1267 USB_DEVICE (0x1189, 0x0893),
1268 .driver_info = (unsigned long) &ax8817x_info,
1269}, {
1270 // goodway corp usb gwusb2e
1271 USB_DEVICE (0x1631, 0x6200),
1272 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 1273}, {
1274 // JVC MP-PRX1 Port Replicator
1275 USB_DEVICE (0x04f1, 0x3008),
1276 .driver_info = (unsigned long) &ax8817x_info,
66dc81ec
QP		 1277}, {
1278 // Lenovo U2L100P 10/100
1279 USB_DEVICE (0x17ef, 0x7203),
d9fe64e5 1280 .driver_info = (unsigned long)&ax88772b_info,
30885909
MV		 1281}, {
1282 // ASIX AX88772B 10/100
1283 USB_DEVICE (0x0b95, 0x772b),
5620df65 1284 .driver_info = (unsigned long) &ax88772b_info,
2e55cc72
DB		 1285}, {
1286 // ASIX AX88772 10/100
39c4b38c
DH		 1287 USB_DEVICE (0x0b95, 0x7720),
1288 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 1289}, {
1290 // ASIX AX88178 10/100/1000
1291 USB_DEVICE (0x0b95, 0x1780),
933a27d3 1292 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE		 1293}, {
1294 // Logitec LAN-GTJ/U2A
1295 USB_DEVICE (0x0789, 0x0160),
1296 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 1297}, {
1298 // Linksys USB200M Rev 2
1299 USB_DEVICE (0x13b1, 0x0018),
1300 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 1301}, {
1302 // 0Q0 cable ethernet
1303 USB_DEVICE (0x1557, 0x7720),
1304 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1305}, {
1306 // DLink DUB-E100 H/W Ver B1
1307 USB_DEVICE (0x07d1, 0x3c05),
1308 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 1309}, {
1310 // DLink DUB-E100 H/W Ver B1 Alternate
1311 USB_DEVICE (0x2001, 0x3c05),
1312 .driver_info = (unsigned long) &ax88772_info,
ed3770a9
S		 1313}, {
1314 // DLink DUB-E100 H/W Ver C1
1315 USB_DEVICE (0x2001, 0x1a02),
1316 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1317}, {
1318 // Linksys USB1000
1319 USB_DEVICE (0x1737, 0x0039),
1320 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 1321}, {
1322 // IO-DATA ETG-US2
1323 USB_DEVICE (0x04bb, 0x0930),
1324 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 1325}, {
1326 // Belkin F5D5055
1327 USB_DEVICE(0x050d, 0x5055),
1328 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 1329}, {
1330 // Apple USB Ethernet Adapter
1331 USB_DEVICE(0x05ac, 0x1402),
1332 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 1333}, {
1334 // Cables-to-Go USB Ethernet Adapter
1335 USB_DEVICE(0x0b95, 0x772a),
1336 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 1337}, {
1338 // ABOCOM for pci
1339 USB_DEVICE(0x14ea, 0xab11),
1340 .driver_info = (unsigned long) &ax88178_info,
1341}, {
1342 // ASIX 88772a
1343 USB_DEVICE(0x0db0, 0xa877),
1344 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ		 1345}, {
1346 // Asus USB Ethernet Adapter
1347 USB_DEVICE (0x0b95, 0x7e2b),
d9fe64e5 1348 .driver_info = (unsigned long)&ax88772b_info,
16626b0c
CR		 1349}, {
1350 /* ASIX 88172a demo board */
1351 USB_DEVICE(0x0b95, 0x172a),
1352 .driver_info = (unsigned long) &ax88172a_info,
45af3fb4
GT		 1353}, {
1354 /*
1355 * USBLINK HG20F9 "USB 2.0 LAN"
1356 * Appears to have gazumped Linksys's manufacturer ID but
1357 * doesn't (yet) conflict with any known Linksys product.
1358 */
1359 USB_DEVICE(0x066b, 0x20f9),
1360 .driver_info = (unsigned long) &hg20f9_info,
2e55cc72
DB		 1361},
1362 { }, // END
1363};
1364MODULE_DEVICE_TABLE(usb, products);
1365
1366static struct usb_driver asix_driver = {
83e1b918 1367 .name = DRIVER_NAME,
2e55cc72
DB		 1368 .id_table = products,
1369 .probe = usbnet_probe,
d9fe64e5
RF		 1370 .suspend = asix_suspend,
1371 .resume = asix_resume,
2e55cc72 1372 .disconnect = usbnet_disconnect,
a11a6544 1373 .supports_autosuspend = 1,
e1f12eb6 1374 .disable_hub_initiated_lpm = 1,
2e55cc72
DB		 1375};
1376
d632eb1b 1377module_usb_driver(asix_driver);
2e55cc72
DB		 1378
1379MODULE_AUTHOR("David Hollis");
4ad1438f 1380MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB		 1381MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1382MODULE_LICENSE("GPL");
1383
Linux kernel - Deliverables
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