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[deliverable/linux.git] / drivers / net / usb / smsc75xx.c
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d0cad871
SG		 1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2010 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 *****************************************************************************/
20
21#include <linux/module.h>
22#include <linux/kmod.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/mii.h>
28#include <linux/usb.h>
29#include <linux/crc32.h>
30#include <linux/usb/usbnet.h>
5a0e3ad6 31#include <linux/slab.h>
d0cad871
SG		 32#include "smsc75xx.h"
33
34#define SMSC_CHIPNAME "smsc75xx"
35#define SMSC_DRIVER_VERSION "1.0.0"
36#define HS_USB_PKT_SIZE (512)
37#define FS_USB_PKT_SIZE (64)
38#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
39#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
40#define DEFAULT_BULK_IN_DELAY (0x00002000)
41#define MAX_SINGLE_PACKET_SIZE (9000)
42#define LAN75XX_EEPROM_MAGIC (0x7500)
43#define EEPROM_MAC_OFFSET (0x01)
44#define DEFAULT_TX_CSUM_ENABLE (true)
45#define DEFAULT_RX_CSUM_ENABLE (true)
46#define DEFAULT_TSO_ENABLE (true)
47#define SMSC75XX_INTERNAL_PHY_ID (1)
48#define SMSC75XX_TX_OVERHEAD (8)
49#define MAX_RX_FIFO_SIZE (20 * 1024)
50#define MAX_TX_FIFO_SIZE (12 * 1024)
51#define USB_VENDOR_ID_SMSC (0x0424)
52#define USB_PRODUCT_ID_LAN7500 (0x7500)
53#define USB_PRODUCT_ID_LAN7505 (0x7505)
ea1649de 54#define RXW_PADDING 2
d0cad871
SG		 55
56#define check_warn(ret, fmt, args...) \
57 ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); })
58
59#define check_warn_return(ret, fmt, args...) \
60 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } })
61
62#define check_warn_goto_done(ret, fmt, args...) \
63 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } })
64
65struct smsc75xx_priv {
66 struct usbnet *dev;
67 u32 rfe_ctl;
68 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
d0cad871
SG		 69 struct mutex dataport_mutex;
70 spinlock_t rfe_ctl_lock;
71 struct work_struct set_multicast;
72};
73
74struct usb_context {
75 struct usb_ctrlrequest req;
76 struct usbnet *dev;
77};
78
eb939922 79static bool turbo_mode = true;
d0cad871
SG		 80module_param(turbo_mode, bool, 0644);
81MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
82
83static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
84 u32 *data)
85{
86 u32 *buf = kmalloc(4, GFP_KERNEL);
87 int ret;
88
89 BUG_ON(!dev);
90
91 if (!buf)
92 return -ENOMEM;
93
94 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
95 USB_VENDOR_REQUEST_READ_REGISTER,
96 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
97 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
98
99 if (unlikely(ret < 0))
100 netdev_warn(dev->net,
4f49add9 101 "Failed to read reg index 0x%08x: %d", index, ret);
d0cad871
SG		 102
103 le32_to_cpus(buf);
104 *data = *buf;
105 kfree(buf);
106
107 return ret;
108}
109
110static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
111 u32 data)
112{
113 u32 *buf = kmalloc(4, GFP_KERNEL);
114 int ret;
115
116 BUG_ON(!dev);
117
118 if (!buf)
119 return -ENOMEM;
120
121 *buf = data;
122 cpu_to_le32s(buf);
123
124 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
125 USB_VENDOR_REQUEST_WRITE_REGISTER,
126 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
127 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
128
129 if (unlikely(ret < 0))
130 netdev_warn(dev->net,
4f49add9 131 "Failed to write reg index 0x%08x: %d", index, ret);
d0cad871
SG		 132
133 kfree(buf);
134
135 return ret;
136}
137
138/* Loop until the read is completed with timeout
139 * called with phy_mutex held */
140static int smsc75xx_phy_wait_not_busy(struct usbnet *dev)
141{
142 unsigned long start_time = jiffies;
143 u32 val;
144 int ret;
145
146 do {
147 ret = smsc75xx_read_reg(dev, MII_ACCESS, &val);
148 check_warn_return(ret, "Error reading MII_ACCESS");
149
150 if (!(val & MII_ACCESS_BUSY))
151 return 0;
152 } while (!time_after(jiffies, start_time + HZ));
153
154 return -EIO;
155}
156
157static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
158{
159 struct usbnet *dev = netdev_priv(netdev);
160 u32 val, addr;
161 int ret;
162
163 mutex_lock(&dev->phy_mutex);
164
165 /* confirm MII not busy */
166 ret = smsc75xx_phy_wait_not_busy(dev);
167 check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_read");
168
169 /* set the address, index & direction (read from PHY) */
170 phy_id &= dev->mii.phy_id_mask;
171 idx &= dev->mii.reg_num_mask;
172 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
173 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 174 | MII_ACCESS_READ | MII_ACCESS_BUSY;
d0cad871
SG		 175 ret = smsc75xx_write_reg(dev, MII_ACCESS, addr);
176 check_warn_goto_done(ret, "Error writing MII_ACCESS");
177
178 ret = smsc75xx_phy_wait_not_busy(dev);
179 check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx);
180
181 ret = smsc75xx_read_reg(dev, MII_DATA, &val);
182 check_warn_goto_done(ret, "Error reading MII_DATA");
183
184 ret = (u16)(val & 0xFFFF);
185
186done:
187 mutex_unlock(&dev->phy_mutex);
188 return ret;
189}
190
191static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
192 int regval)
193{
194 struct usbnet *dev = netdev_priv(netdev);
195 u32 val, addr;
196 int ret;
197
198 mutex_lock(&dev->phy_mutex);
199
200 /* confirm MII not busy */
201 ret = smsc75xx_phy_wait_not_busy(dev);
202 check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_write");
203
204 val = regval;
205 ret = smsc75xx_write_reg(dev, MII_DATA, val);
206 check_warn_goto_done(ret, "Error writing MII_DATA");
207
208 /* set the address, index & direction (write to PHY) */
209 phy_id &= dev->mii.phy_id_mask;
210 idx &= dev->mii.reg_num_mask;
211 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
212 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 213 | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
d0cad871
SG		 214 ret = smsc75xx_write_reg(dev, MII_ACCESS, addr);
215 check_warn_goto_done(ret, "Error writing MII_ACCESS");
216
217 ret = smsc75xx_phy_wait_not_busy(dev);
218 check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx);
219
220done:
221 mutex_unlock(&dev->phy_mutex);
222}
223
224static int smsc75xx_wait_eeprom(struct usbnet *dev)
225{
226 unsigned long start_time = jiffies;
227 u32 val;
228 int ret;
229
230 do {
231 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
232 check_warn_return(ret, "Error reading E2P_CMD");
233
234 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
235 break;
236 udelay(40);
237 } while (!time_after(jiffies, start_time + HZ));
238
239 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
240 netdev_warn(dev->net, "EEPROM read operation timeout");
241 return -EIO;
242 }
243
244 return 0;
245}
246
247static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
248{
249 unsigned long start_time = jiffies;
250 u32 val;
251 int ret;
252
253 do {
254 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
255 check_warn_return(ret, "Error reading E2P_CMD");
256
257 if (!(val & E2P_CMD_BUSY))
258 return 0;
259
260 udelay(40);
261 } while (!time_after(jiffies, start_time + HZ));
262
263 netdev_warn(dev->net, "EEPROM is busy");
264 return -EIO;
265}
266
267static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
268 u8 *data)
269{
270 u32 val;
271 int i, ret;
272
273 BUG_ON(!dev);
274 BUG_ON(!data);
275
276 ret = smsc75xx_eeprom_confirm_not_busy(dev);
277 if (ret)
278 return ret;
279
280 for (i = 0; i < length; i++) {
281 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
282 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
283 check_warn_return(ret, "Error writing E2P_CMD");
284
285 ret = smsc75xx_wait_eeprom(dev);
286 if (ret < 0)
287 return ret;
288
289 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
290 check_warn_return(ret, "Error reading E2P_DATA");
291
292 data[i] = val & 0xFF;
293 offset++;
294 }
295
296 return 0;
297}
298
299static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
300 u8 *data)
301{
302 u32 val;
303 int i, ret;
304
305 BUG_ON(!dev);
306 BUG_ON(!data);
307
308 ret = smsc75xx_eeprom_confirm_not_busy(dev);
309 if (ret)
310 return ret;
311
312 /* Issue write/erase enable command */
313 val = E2P_CMD_BUSY | E2P_CMD_EWEN;
314 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
315 check_warn_return(ret, "Error writing E2P_CMD");
316
317 ret = smsc75xx_wait_eeprom(dev);
318 if (ret < 0)
319 return ret;
320
321 for (i = 0; i < length; i++) {
322
323 /* Fill data register */
324 val = data[i];
325 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
326 check_warn_return(ret, "Error writing E2P_DATA");
327
328 /* Send "write" command */
329 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
330 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
331 check_warn_return(ret, "Error writing E2P_CMD");
332
333 ret = smsc75xx_wait_eeprom(dev);
334 if (ret < 0)
335 return ret;
336
337 offset++;
338 }
339
340 return 0;
341}
342
343static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
344{
345 int i, ret;
346
347 for (i = 0; i < 100; i++) {
348 u32 dp_sel;
349 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
350 check_warn_return(ret, "Error reading DP_SEL");
351
352 if (dp_sel & DP_SEL_DPRDY)
353 return 0;
354
355 udelay(40);
356 }
357
358 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out");
359
360 return -EIO;
361}
362
363static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
364 u32 length, u32 *buf)
365{
366 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
367 u32 dp_sel;
368 int i, ret;
369
370 mutex_lock(&pdata->dataport_mutex);
371
372 ret = smsc75xx_dataport_wait_not_busy(dev);
373 check_warn_goto_done(ret, "smsc75xx_dataport_write busy on entry");
374
375 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
376 check_warn_goto_done(ret, "Error reading DP_SEL");
377
378 dp_sel &= ~DP_SEL_RSEL;
379 dp_sel |= ram_select;
380 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
381 check_warn_goto_done(ret, "Error writing DP_SEL");
382
383 for (i = 0; i < length; i++) {
384 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
385 check_warn_goto_done(ret, "Error writing DP_ADDR");
386
387 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
388 check_warn_goto_done(ret, "Error writing DP_DATA");
389
390 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
391 check_warn_goto_done(ret, "Error writing DP_CMD");
392
393 ret = smsc75xx_dataport_wait_not_busy(dev);
394 check_warn_goto_done(ret, "smsc75xx_dataport_write timeout");
395 }
396
397done:
398 mutex_unlock(&pdata->dataport_mutex);
399 return ret;
400}
401
402/* returns hash bit number for given MAC address */
403static u32 smsc75xx_hash(char addr[ETH_ALEN])
404{
405 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
406}
407
408static void smsc75xx_deferred_multicast_write(struct work_struct *param)
409{
410 struct smsc75xx_priv *pdata =
411 container_of(param, struct smsc75xx_priv, set_multicast);
412 struct usbnet *dev = pdata->dev;
413 int ret;
414
415 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x",
416 pdata->rfe_ctl);
417
418 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
419 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
420
421 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
422 check_warn(ret, "Error writing RFE_CRL");
423}
424
425static void smsc75xx_set_multicast(struct net_device *netdev)
426{
427 struct usbnet *dev = netdev_priv(netdev);
428 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
429 unsigned long flags;
430 int i;
431
432 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
433
434 pdata->rfe_ctl &=
435 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
436 pdata->rfe_ctl |= RFE_CTL_AB;
437
438 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
439 pdata->multicast_hash_table[i] = 0;
440
441 if (dev->net->flags & IFF_PROMISC) {
442 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled");
443 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
444 } else if (dev->net->flags & IFF_ALLMULTI) {
445 netif_dbg(dev, drv, dev->net, "receive all multicast enabled");
446 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
447 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 448 struct netdev_hw_addr *ha;
d0cad871
SG		 449
450 netif_dbg(dev, drv, dev->net, "receive multicast hash filter");
451
452 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
453
22bedad3
JP		 454 netdev_for_each_mc_addr(ha, netdev) {
455 u32 bitnum = smsc75xx_hash(ha->addr);
d0cad871
SG		 456 pdata->multicast_hash_table[bitnum / 32] |=
457 (1 << (bitnum % 32));
458 }
459 } else {
460 netif_dbg(dev, drv, dev->net, "receive own packets only");
461 pdata->rfe_ctl |= RFE_CTL_DPF;
462 }
463
464 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
465
466 /* defer register writes to a sleepable context */
467 schedule_work(&pdata->set_multicast);
468}
469
470static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
471 u16 lcladv, u16 rmtadv)
472{
473 u32 flow = 0, fct_flow = 0;
474 int ret;
475
476 if (duplex == DUPLEX_FULL) {
477 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
478
479 if (cap & FLOW_CTRL_TX) {
480 flow = (FLOW_TX_FCEN | 0xFFFF);
481 /* set fct_flow thresholds to 20% and 80% */
482 fct_flow = (8 << 8) | 32;
483 }
484
485 if (cap & FLOW_CTRL_RX)
486 flow |= FLOW_RX_FCEN;
487
488 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s",
489 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
490 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
491 } else {
492 netif_dbg(dev, link, dev->net, "half duplex");
493 }
494
495 ret = smsc75xx_write_reg(dev, FLOW, flow);
496 check_warn_return(ret, "Error writing FLOW");
497
498 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
499 check_warn_return(ret, "Error writing FCT_FLOW");
500
501 return 0;
502}
503
504static int smsc75xx_link_reset(struct usbnet *dev)
505{
506 struct mii_if_info *mii = &dev->mii;
8ae6daca 507 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
d0cad871
SG		 508 u16 lcladv, rmtadv;
509 int ret;
510
4f94a929 511 /* write to clear phy interrupt status */
7749622d
SG		 512 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
513 PHY_INT_SRC_CLEAR_ALL);
d0cad871
SG		 514
515 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
516 check_warn_return(ret, "Error writing INT_STS");
517
518 mii_check_media(mii, 1, 1);
519 mii_ethtool_gset(&dev->mii, &ecmd);
520 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
521 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
522
8ae6daca
DD		 523 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x"
524 " rmtadv: %04x", ethtool_cmd_speed(&ecmd),
525 ecmd.duplex, lcladv, rmtadv);
d0cad871
SG		 526
527 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
528}
529
530static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
531{
532 u32 intdata;
533
534 if (urb->actual_length != 4) {
535 netdev_warn(dev->net,
536 "unexpected urb length %d", urb->actual_length);
537 return;
538 }
539
540 memcpy(&intdata, urb->transfer_buffer, 4);
541 le32_to_cpus(&intdata);
542
543 netif_dbg(dev, link, dev->net, "intdata: 0x%08X", intdata);
544
545 if (intdata & INT_ENP_PHY_INT)
546 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
547 else
548 netdev_warn(dev->net,
549 "unexpected interrupt, intdata=0x%08X", intdata);
550}
551
d0cad871
SG		 552static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
553{
554 return MAX_EEPROM_SIZE;
555}
556
557static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
558 struct ethtool_eeprom *ee, u8 *data)
559{
560 struct usbnet *dev = netdev_priv(netdev);
561
562 ee->magic = LAN75XX_EEPROM_MAGIC;
563
564 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
565}
566
567static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
568 struct ethtool_eeprom *ee, u8 *data)
569{
570 struct usbnet *dev = netdev_priv(netdev);
571
572 if (ee->magic != LAN75XX_EEPROM_MAGIC) {
573 netdev_warn(dev->net,
574 "EEPROM: magic value mismatch: 0x%x", ee->magic);
575 return -EINVAL;
576 }
577
578 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
579}
580
d0cad871
SG		 581static const struct ethtool_ops smsc75xx_ethtool_ops = {
582 .get_link = usbnet_get_link,
583 .nway_reset = usbnet_nway_reset,
584 .get_drvinfo = usbnet_get_drvinfo,
585 .get_msglevel = usbnet_get_msglevel,
586 .set_msglevel = usbnet_set_msglevel,
587 .get_settings = usbnet_get_settings,
588 .set_settings = usbnet_set_settings,
589 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
590 .get_eeprom = smsc75xx_ethtool_get_eeprom,
591 .set_eeprom = smsc75xx_ethtool_set_eeprom,
d0cad871
SG		 592};
593
594static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
595{
596 struct usbnet *dev = netdev_priv(netdev);
597
598 if (!netif_running(netdev))
599 return -EINVAL;
600
601 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
602}
603
604static void smsc75xx_init_mac_address(struct usbnet *dev)
605{
606 /* try reading mac address from EEPROM */
607 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
608 dev->net->dev_addr) == 0) {
609 if (is_valid_ether_addr(dev->net->dev_addr)) {
610 /* eeprom values are valid so use them */
611 netif_dbg(dev, ifup, dev->net,
612 "MAC address read from EEPROM");
613 return;
614 }
615 }
616
617 /* no eeprom, or eeprom values are invalid. generate random MAC */
f2cedb63 618 eth_hw_addr_random(dev->net);
d0cad871
SG		 619 netif_dbg(dev, ifup, dev->net, "MAC address set to random_ether_addr");
620}
621
622static int smsc75xx_set_mac_address(struct usbnet *dev)
623{
624 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
625 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
626 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
627
628 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
629 check_warn_return(ret, "Failed to write RX_ADDRH: %d", ret);
630
631 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
632 check_warn_return(ret, "Failed to write RX_ADDRL: %d", ret);
633
634 addr_hi |= ADDR_FILTX_FB_VALID;
635 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
636 check_warn_return(ret, "Failed to write ADDR_FILTX: %d", ret);
637
638 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
639 check_warn_return(ret, "Failed to write ADDR_FILTX+4: %d", ret);
640
641 return 0;
642}
643
644static int smsc75xx_phy_initialize(struct usbnet *dev)
645{
b140504a 646 int bmcr, ret, timeout = 0;
d0cad871
SG		 647
648 /* Initialize MII structure */
649 dev->mii.dev = dev->net;
650 dev->mii.mdio_read = smsc75xx_mdio_read;
651 dev->mii.mdio_write = smsc75xx_mdio_write;
652 dev->mii.phy_id_mask = 0x1f;
653 dev->mii.reg_num_mask = 0x1f;
c0b92e4d 654 dev->mii.supports_gmii = 1;
d0cad871
SG		 655 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
656
657 /* reset phy and wait for reset to complete */
658 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
659
660 do {
661 msleep(10);
662 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
663 check_warn_return(bmcr, "Error reading MII_BMCR");
664 timeout++;
8a1d59d7 665 } while ((bmcr & BMCR_RESET) && (timeout < 100));
d0cad871
SG		 666
667 if (timeout >= 100) {
668 netdev_warn(dev->net, "timeout on PHY Reset");
669 return -EIO;
670 }
671
672 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
673 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
674 ADVERTISE_PAUSE_ASYM);
c0b92e4d
SG		 675 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
676 ADVERTISE_1000FULL);
d0cad871 677
b140504a
SG		 678 /* read and write to clear phy interrupt status */
679 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
680 check_warn_return(ret, "Error reading PHY_INT_SRC");
681 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
d0cad871
SG		 682
683 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
684 PHY_INT_MASK_DEFAULT);
685 mii_nway_restart(&dev->mii);
686
687 netif_dbg(dev, ifup, dev->net, "phy initialised successfully");
688 return 0;
689}
690
691static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
692{
693 int ret = 0;
694 u32 buf;
695 bool rxenabled;
696
697 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
698 check_warn_return(ret, "Failed to read MAC_RX: %d", ret);
699
700 rxenabled = ((buf & MAC_RX_RXEN) != 0);
701
702 if (rxenabled) {
703 buf &= ~MAC_RX_RXEN;
704 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
705 check_warn_return(ret, "Failed to write MAC_RX: %d", ret);
706 }
707
708 /* add 4 to size for FCS */
709 buf &= ~MAC_RX_MAX_SIZE;
710 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
711
712 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
713 check_warn_return(ret, "Failed to write MAC_RX: %d", ret);
714
715 if (rxenabled) {
716 buf |= MAC_RX_RXEN;
717 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
718 check_warn_return(ret, "Failed to write MAC_RX: %d", ret);
719 }
720
721 return 0;
722}
723
724static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
725{
726 struct usbnet *dev = netdev_priv(netdev);
727
728 int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu);
729 check_warn_return(ret, "Failed to set mac rx frame length");
730
731 return usbnet_change_mtu(netdev, new_mtu);
732}
733
78e47fe4 734/* Enable or disable Rx checksum offload engine */
c8f44aff
MM		 735static int smsc75xx_set_features(struct net_device *netdev,
736 netdev_features_t features)
78e47fe4
MM		 737{
738 struct usbnet *dev = netdev_priv(netdev);
739 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
740 unsigned long flags;
741 int ret;
742
743 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
744
745 if (features & NETIF_F_RXCSUM)
746 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
747 else
748 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
749
750 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
751 /* it's racing here! */
752
753 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
754 check_warn_return(ret, "Error writing RFE_CTL");
755
756 return 0;
757}
758
d0cad871
SG		 759static int smsc75xx_reset(struct usbnet *dev)
760{
761 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
762 u32 buf;
763 int ret = 0, timeout;
764
765 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset");
766
767 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
768 check_warn_return(ret, "Failed to read HW_CFG: %d", ret);
769
770 buf |= HW_CFG_LRST;
771
772 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
773 check_warn_return(ret, "Failed to write HW_CFG: %d", ret);
774
775 timeout = 0;
776 do {
777 msleep(10);
778 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
779 check_warn_return(ret, "Failed to read HW_CFG: %d", ret);
780 timeout++;
781 } while ((buf & HW_CFG_LRST) && (timeout < 100));
782
783 if (timeout >= 100) {
784 netdev_warn(dev->net, "timeout on completion of Lite Reset");
785 return -EIO;
786 }
787
788 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY");
789
790 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
791 check_warn_return(ret, "Failed to read PMT_CTL: %d", ret);
792
793 buf |= PMT_CTL_PHY_RST;
794
795 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
796 check_warn_return(ret, "Failed to write PMT_CTL: %d", ret);
797
798 timeout = 0;
799 do {
800 msleep(10);
801 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
802 check_warn_return(ret, "Failed to read PMT_CTL: %d", ret);
803 timeout++;
804 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
805
806 if (timeout >= 100) {
807 netdev_warn(dev->net, "timeout waiting for PHY Reset");
808 return -EIO;
809 }
810
811 netif_dbg(dev, ifup, dev->net, "PHY reset complete");
812
813 smsc75xx_init_mac_address(dev);
814
815 ret = smsc75xx_set_mac_address(dev);
816 check_warn_return(ret, "Failed to set mac address");
817
818 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM", dev->net->dev_addr);
819
820 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
821 check_warn_return(ret, "Failed to read HW_CFG: %d", ret);
822
823 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x", buf);
824
825 buf |= HW_CFG_BIR;
826
827 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
828 check_warn_return(ret, "Failed to write HW_CFG: %d", ret);
829
830 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
831 check_warn_return(ret, "Failed to read HW_CFG: %d", ret);
832
833 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after "
834 "writing HW_CFG_BIR: 0x%08x", buf);
835
836 if (!turbo_mode) {
837 buf = 0;
838 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
839 } else if (dev->udev->speed == USB_SPEED_HIGH) {
840 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
841 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
842 } else {
843 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
844 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
845 }
846
847 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld",
848 (ulong)dev->rx_urb_size);
849
850 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
851 check_warn_return(ret, "Failed to write BURST_CAP: %d", ret);
852
853 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
854 check_warn_return(ret, "Failed to read BURST_CAP: %d", ret);
855
856 netif_dbg(dev, ifup, dev->net,
857 "Read Value from BURST_CAP after writing: 0x%08x", buf);
858
859 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
860 check_warn_return(ret, "Failed to write BULK_IN_DLY: %d", ret);
861
862 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
863 check_warn_return(ret, "Failed to read BULK_IN_DLY: %d", ret);
864
865 netif_dbg(dev, ifup, dev->net,
866 "Read Value from BULK_IN_DLY after writing: 0x%08x", buf);
867
868 if (turbo_mode) {
869 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
870 check_warn_return(ret, "Failed to read HW_CFG: %d", ret);
871
872 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x", buf);
873
874 buf |= (HW_CFG_MEF | HW_CFG_BCE);
875
876 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
877 check_warn_return(ret, "Failed to write HW_CFG: %d", ret);
878
879 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
880 check_warn_return(ret, "Failed to read HW_CFG: %d", ret);
881
882 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x", buf);
883 }
884
885 /* set FIFO sizes */
886 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
887 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
888 check_warn_return(ret, "Failed to write FCT_RX_FIFO_END: %d", ret);
889
890 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x", buf);
891
892 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
893 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
894 check_warn_return(ret, "Failed to write FCT_TX_FIFO_END: %d", ret);
895
896 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x", buf);
897
898 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
899 check_warn_return(ret, "Failed to write INT_STS: %d", ret);
900
901 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
902 check_warn_return(ret, "Failed to read ID_REV: %d", ret);
903
904 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x", buf);
905
97138a1c
SG		 906 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
907 check_warn_return(ret, "Failed to read E2P_CMD: %d", ret);
d0cad871 908
97138a1c
SG		 909 /* only set default GPIO/LED settings if no EEPROM is detected */
910 if (!(buf & E2P_CMD_LOADED)) {
911 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
912 check_warn_return(ret, "Failed to read LED_GPIO_CFG: %d", ret);
d0cad871 913
97138a1c
SG		 914 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
915 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
916
917 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
918 check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d", ret);
919 }
d0cad871
SG		 920
921 ret = smsc75xx_write_reg(dev, FLOW, 0);
922 check_warn_return(ret, "Failed to write FLOW: %d", ret);
923
924 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
925 check_warn_return(ret, "Failed to write FCT_FLOW: %d", ret);
926
927 /* Don't need rfe_ctl_lock during initialisation */
928 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
929 check_warn_return(ret, "Failed to read RFE_CTL: %d", ret);
930
931 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
932
933 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
934 check_warn_return(ret, "Failed to write RFE_CTL: %d", ret);
935
936 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
937 check_warn_return(ret, "Failed to read RFE_CTL: %d", ret);
938
939 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x", pdata->rfe_ctl);
940
941 /* Enable or disable checksum offload engines */
78e47fe4 942 smsc75xx_set_features(dev->net, dev->net->features);
d0cad871
SG		 943
944 smsc75xx_set_multicast(dev->net);
945
946 ret = smsc75xx_phy_initialize(dev);
947 check_warn_return(ret, "Failed to initialize PHY: %d", ret);
948
949 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
950 check_warn_return(ret, "Failed to read INT_EP_CTL: %d", ret);
951
952 /* enable PHY interrupts */
953 buf |= INT_ENP_PHY_INT;
954
955 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
956 check_warn_return(ret, "Failed to write INT_EP_CTL: %d", ret);
957
2f3a081e
SG		 958 /* allow mac to detect speed and duplex from phy */
959 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
960 check_warn_return(ret, "Failed to read MAC_CR: %d", ret);
961
962 buf |= (MAC_CR_ADD | MAC_CR_ASD);
963 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
964 check_warn_return(ret, "Failed to write MAC_CR: %d", ret);
965
d0cad871
SG		 966 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
967 check_warn_return(ret, "Failed to read MAC_TX: %d", ret);
968
969 buf |= MAC_TX_TXEN;
970
971 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
972 check_warn_return(ret, "Failed to write MAC_TX: %d", ret);
973
974 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x", buf);
975
976 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
977 check_warn_return(ret, "Failed to read FCT_TX_CTL: %d", ret);
978
979 buf |= FCT_TX_CTL_EN;
980
981 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
982 check_warn_return(ret, "Failed to write FCT_TX_CTL: %d", ret);
983
984 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x", buf);
985
986 ret = smsc75xx_set_rx_max_frame_length(dev, 1514);
987 check_warn_return(ret, "Failed to set max rx frame length");
988
989 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
990 check_warn_return(ret, "Failed to read MAC_RX: %d", ret);
991
992 buf |= MAC_RX_RXEN;
993
994 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
995 check_warn_return(ret, "Failed to write MAC_RX: %d", ret);
996
997 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x", buf);
998
999 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
1000 check_warn_return(ret, "Failed to read FCT_RX_CTL: %d", ret);
1001
1002 buf |= FCT_RX_CTL_EN;
1003
1004 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
1005 check_warn_return(ret, "Failed to write FCT_RX_CTL: %d", ret);
1006
1007 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x", buf);
1008
1009 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0");
1010 return 0;
1011}
1012
1013static const struct net_device_ops smsc75xx_netdev_ops = {
1014 .ndo_open = usbnet_open,
1015 .ndo_stop = usbnet_stop,
1016 .ndo_start_xmit = usbnet_start_xmit,
1017 .ndo_tx_timeout = usbnet_tx_timeout,
1018 .ndo_change_mtu = smsc75xx_change_mtu,
1019 .ndo_set_mac_address = eth_mac_addr,
1020 .ndo_validate_addr = eth_validate_addr,
1021 .ndo_do_ioctl = smsc75xx_ioctl,
afc4b13d 1022 .ndo_set_rx_mode = smsc75xx_set_multicast,
78e47fe4 1023 .ndo_set_features = smsc75xx_set_features,
d0cad871
SG		 1024};
1025
1026static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
1027{
1028 struct smsc75xx_priv *pdata = NULL;
1029 int ret;
1030
1031 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1032
1033 ret = usbnet_get_endpoints(dev, intf);
1034 check_warn_return(ret, "usbnet_get_endpoints failed: %d", ret);
1035
1036 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
1037 GFP_KERNEL);
1038
1039 pdata = (struct smsc75xx_priv *)(dev->data[0]);
1040 if (!pdata) {
1041 netdev_warn(dev->net, "Unable to allocate smsc75xx_priv");
1042 return -ENOMEM;
1043 }
1044
1045 pdata->dev = dev;
1046
1047 spin_lock_init(&pdata->rfe_ctl_lock);
1048 mutex_init(&pdata->dataport_mutex);
1049
1050 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
1051
78e47fe4
MM		 1052 if (DEFAULT_TX_CSUM_ENABLE) {
1053 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1054 if (DEFAULT_TSO_ENABLE)
1055 dev->net->features |= NETIF_F_SG |
1056 NETIF_F_TSO | NETIF_F_TSO6;
1057 }
1058 if (DEFAULT_RX_CSUM_ENABLE)
1059 dev->net->features |= NETIF_F_RXCSUM;
d0cad871 1060
78e47fe4
MM		 1061 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1062 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_RXCSUM;
d0cad871
SG		 1063
1064 /* Init all registers */
1065 ret = smsc75xx_reset(dev);
1066
1067 dev->net->netdev_ops = &smsc75xx_netdev_ops;
1068 dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
1069 dev->net->flags |= IFF_MULTICAST;
1070 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
a99ff7d0 1071 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
d0cad871
SG		 1072 return 0;
1073}
1074
1075static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1076{
1077 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1078 if (pdata) {
1079 netif_dbg(dev, ifdown, dev->net, "free pdata");
1080 kfree(pdata);
1081 pdata = NULL;
1082 dev->data[0] = 0;
1083 }
1084}
1085
78e47fe4
MM		 1086static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
1087 u32 rx_cmd_a, u32 rx_cmd_b)
d0cad871 1088{
78e47fe4
MM		 1089 if (!(dev->net->features & NETIF_F_RXCSUM) ||
1090 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
d0cad871
SG		 1091 skb->ip_summed = CHECKSUM_NONE;
1092 } else {
1093 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
1094 skb->ip_summed = CHECKSUM_COMPLETE;
1095 }
1096}
1097
1098static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
1099{
d0cad871
SG		 1100 while (skb->len > 0) {
1101 u32 rx_cmd_a, rx_cmd_b, align_count, size;
1102 struct sk_buff *ax_skb;
1103 unsigned char *packet;
1104
1105 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
1106 le32_to_cpus(&rx_cmd_a);
1107 skb_pull(skb, 4);
1108
1109 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
1110 le32_to_cpus(&rx_cmd_b);
ea1649de 1111 skb_pull(skb, 4 + RXW_PADDING);
d0cad871
SG		 1112
1113 packet = skb->data;
1114
1115 /* get the packet length */
ea1649de
NE		 1116 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
1117 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
d0cad871
SG		 1118
1119 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
1120 netif_dbg(dev, rx_err, dev->net,
1121 "Error rx_cmd_a=0x%08x", rx_cmd_a);
1122 dev->net->stats.rx_errors++;
1123 dev->net->stats.rx_dropped++;
1124
1125 if (rx_cmd_a & RX_CMD_A_FCS)
1126 dev->net->stats.rx_crc_errors++;
1127 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
1128 dev->net->stats.rx_frame_errors++;
1129 } else {
1130 /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
1131 if (unlikely(size > (ETH_FRAME_LEN + 12))) {
1132 netif_dbg(dev, rx_err, dev->net,
1133 "size err rx_cmd_a=0x%08x", rx_cmd_a);
1134 return 0;
1135 }
1136
1137 /* last frame in this batch */
1138 if (skb->len == size) {
78e47fe4
MM		 1139 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
1140 rx_cmd_b);
d0cad871
SG		 1141
1142 skb_trim(skb, skb->len - 4); /* remove fcs */
1143 skb->truesize = size + sizeof(struct sk_buff);
1144
1145 return 1;
1146 }
1147
1148 ax_skb = skb_clone(skb, GFP_ATOMIC);
1149 if (unlikely(!ax_skb)) {
1150 netdev_warn(dev->net, "Error allocating skb");
1151 return 0;
1152 }
1153
1154 ax_skb->len = size;
1155 ax_skb->data = packet;
1156 skb_set_tail_pointer(ax_skb, size);
1157
78e47fe4
MM		 1158 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
1159 rx_cmd_b);
d0cad871
SG		 1160
1161 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
1162 ax_skb->truesize = size + sizeof(struct sk_buff);
1163
1164 usbnet_skb_return(dev, ax_skb);
1165 }
1166
1167 skb_pull(skb, size);
1168
1169 /* padding bytes before the next frame starts */
1170 if (skb->len)
1171 skb_pull(skb, align_count);
1172 }
1173
1174 if (unlikely(skb->len < 0)) {
1175 netdev_warn(dev->net, "invalid rx length<0 %d", skb->len);
1176 return 0;
1177 }
1178
1179 return 1;
1180}
1181
1182static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
1183 struct sk_buff *skb, gfp_t flags)
1184{
1185 u32 tx_cmd_a, tx_cmd_b;
1186
1187 skb_linearize(skb);
1188
1189 if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
1190 struct sk_buff *skb2 =
1191 skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
1192 dev_kfree_skb_any(skb);
1193 skb = skb2;
1194 if (!skb)
1195 return NULL;
1196 }
1197
1198 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
1199
1200 if (skb->ip_summed == CHECKSUM_PARTIAL)
1201 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
1202
1203 if (skb_is_gso(skb)) {
1204 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
1205 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
1206
1207 tx_cmd_a |= TX_CMD_A_LSO;
1208 } else {
1209 tx_cmd_b = 0;
1210 }
1211
1212 skb_push(skb, 4);
1213 cpu_to_le32s(&tx_cmd_b);
1214 memcpy(skb->data, &tx_cmd_b, 4);
1215
1216 skb_push(skb, 4);
1217 cpu_to_le32s(&tx_cmd_a);
1218 memcpy(skb->data, &tx_cmd_a, 4);
1219
1220 return skb;
1221}
1222
1223static const struct driver_info smsc75xx_info = {
1224 .description = "smsc75xx USB 2.0 Gigabit Ethernet",
1225 .bind = smsc75xx_bind,
1226 .unbind = smsc75xx_unbind,
1227 .link_reset = smsc75xx_link_reset,
1228 .reset = smsc75xx_reset,
1229 .rx_fixup = smsc75xx_rx_fixup,
1230 .tx_fixup = smsc75xx_tx_fixup,
1231 .status = smsc75xx_status,
7bdd305e 1232 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
d0cad871
SG		 1233};
1234
1235static const struct usb_device_id products[] = {
1236 {
1237 /* SMSC7500 USB Gigabit Ethernet Device */
1238 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
1239 .driver_info = (unsigned long) &smsc75xx_info,
1240 },
1241 {
1242 /* SMSC7500 USB Gigabit Ethernet Device */
1243 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
1244 .driver_info = (unsigned long) &smsc75xx_info,
1245 },
1246 { }, /* END */
1247};
1248MODULE_DEVICE_TABLE(usb, products);
1249
1250static struct usb_driver smsc75xx_driver = {
1251 .name = SMSC_CHIPNAME,
1252 .id_table = products,
1253 .probe = usbnet_probe,
1254 .suspend = usbnet_suspend,
1255 .resume = usbnet_resume,
1256 .disconnect = usbnet_disconnect,
e1f12eb6 1257 .disable_hub_initiated_lpm = 1,
d0cad871
SG		 1258};
1259
d632eb1b 1260module_usb_driver(smsc75xx_driver);
d0cad871
SG		 1261
1262MODULE_AUTHOR("Nancy Lin");
90b24cfb 1263MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
d0cad871
SG		 1264MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
1265MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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