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Fix common misspellings
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
0e472252
BC		 64#define CREATE_TRACE_POINTS
65#include "trace.h"
66
18cb6e32
JL		 67int ath5k_modparam_nohwcrypt;
68module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 69MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 70
42639fcd 71static int modparam_all_channels;
46802a4f 72module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 73MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
fa1c114f
JS		 75/* Module info */
76MODULE_AUTHOR("Jiri Slaby");
77MODULE_AUTHOR("Nick Kossifidis");
78MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 81
132b1c3e 82static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 83static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
84 bool skip_pcu);
cd2c5486
BR		 85int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
86void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f 87
fa1c114f 88/* Known SREVs */
2c91108c 89static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 90#ifdef CONFIG_ATHEROS_AR231X
91 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
92 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
93 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
94 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
95 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
96 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
97 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
98#else
1bef016a
NK		 99 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
100 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
101 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
102 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
103 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
104 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
105 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
106 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
107 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
108 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
109 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
110 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
111 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
112 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
113 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
114 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
115 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
116 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 117#endif
1bef016a 118 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 119 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
120 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 121 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 122 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
123 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
124 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 125 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 128 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
129 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
130 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 131 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 133#ifdef CONFIG_ATHEROS_AR231X
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
136#endif
fa1c114f
JS		 137 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
138};
139
2c91108c 140static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 141 { .bitrate = 10,
142 .hw_value = ATH5K_RATE_CODE_1M, },
143 { .bitrate = 20,
144 .hw_value = ATH5K_RATE_CODE_2M,
145 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
146 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
147 { .bitrate = 55,
148 .hw_value = ATH5K_RATE_CODE_5_5M,
149 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
150 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
151 { .bitrate = 110,
152 .hw_value = ATH5K_RATE_CODE_11M,
153 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
155 { .bitrate = 60,
156 .hw_value = ATH5K_RATE_CODE_6M,
157 .flags = 0 },
158 { .bitrate = 90,
159 .hw_value = ATH5K_RATE_CODE_9M,
160 .flags = 0 },
161 { .bitrate = 120,
162 .hw_value = ATH5K_RATE_CODE_12M,
163 .flags = 0 },
164 { .bitrate = 180,
165 .hw_value = ATH5K_RATE_CODE_18M,
166 .flags = 0 },
167 { .bitrate = 240,
168 .hw_value = ATH5K_RATE_CODE_24M,
169 .flags = 0 },
170 { .bitrate = 360,
171 .hw_value = ATH5K_RATE_CODE_36M,
172 .flags = 0 },
173 { .bitrate = 480,
174 .hw_value = ATH5K_RATE_CODE_48M,
175 .flags = 0 },
176 { .bitrate = 540,
177 .hw_value = ATH5K_RATE_CODE_54M,
178 .flags = 0 },
179 /* XR missing */
180};
181
fa1c114f
JS		 182static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
183{
184 u64 tsf = ath5k_hw_get_tsf64(ah);
185
186 if ((tsf & 0x7fff) < rstamp)
187 tsf -= 0x8000;
188
189 return (tsf & ~0x7fff) | rstamp;
190}
191
e5b046d8 192const char *
fa1c114f
JS		 193ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
194{
195 const char *name = "xxxxx";
196 unsigned int i;
197
198 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
199 if (srev_names[i].sr_type != type)
200 continue;
75d0edb8
NK		 201
202 if ((val & 0xf0) == srev_names[i].sr_val)
203 name = srev_names[i].sr_name;
204
205 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 206 name = srev_names[i].sr_name;
207 break;
208 }
209 }
210
211 return name;
212}
e5aa8474
LR		 213static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
214{
215 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
216 return ath5k_hw_reg_read(ah, reg_offset);
217}
218
219static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
220{
221 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
222 ath5k_hw_reg_write(ah, val, reg_offset);
223}
224
225static const struct ath_ops ath5k_common_ops = {
226 .read = ath5k_ioread32,
227 .write = ath5k_iowrite32,
228};
fa1c114f 229
8a63facc
BC		 230/***********************\
231* Driver Initialization *
232\***********************/
233
234static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 235{
8a63facc
BC		 236 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
237 struct ath5k_softc *sc = hw->priv;
238 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 239
8a63facc
BC		 240 return ath_reg_notifier_apply(wiphy, request, regulatory);
241}
6ccf15a1 242
8a63facc
BC		 243/********************\
244* Channel/mode setup *
245\********************/
fa1c114f 246
8a63facc
BC		 247/*
248 * Returns true for the channel numbers used without all_channels modparam.
249 */
410e6120 250static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 251{
410e6120
BR		 252 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
253 return true;
254
255 return /* UNII 1,2 */
256 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 257 /* midband */
258 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
259 /* UNII-3 */
410e6120
BR		 260 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
261 /* 802.11j 5.030-5.080 GHz (20MHz) */
262 (chan == 8 || chan == 12 || chan == 16) ||
263 /* 802.11j 4.9GHz (20MHz) */
264 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 265}
fa1c114f 266
8a63facc 267static unsigned int
97d9c3a3
BR		 268ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
269 unsigned int mode, unsigned int max)
8a63facc 270{
2b1351a3 271 unsigned int count, size, chfreq, freq, ch;
90c02d72 272 enum ieee80211_band band;
fa1c114f 273
8a63facc
BC		 274 switch (mode) {
275 case AR5K_MODE_11A:
8a63facc 276 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 277 size = 220;
8a63facc 278 chfreq = CHANNEL_5GHZ;
90c02d72 279 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 280 break;
281 case AR5K_MODE_11B:
282 case AR5K_MODE_11G:
8a63facc
BC		 283 size = 26;
284 chfreq = CHANNEL_2GHZ;
90c02d72 285 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 286 break;
287 default:
288 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
289 return 0;
fa1c114f
JS		 290 }
291
2b1351a3
BR		 292 count = 0;
293 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 294 freq = ieee80211_channel_to_frequency(ch, band);
295
296 if (freq == 0) /* mapping failed - not a standard channel */
297 continue;
fa1c114f 298
8a63facc
BC		 299 /* Check if channel is supported by the chipset */
300 if (!ath5k_channel_ok(ah, freq, chfreq))
301 continue;
f59ac048 302
410e6120
BR		 303 if (!modparam_all_channels &&
304 !ath5k_is_standard_channel(ch, band))
8a63facc 305 continue;
f59ac048 306
8a63facc
BC		 307 /* Write channel info and increment counter */
308 channels[count].center_freq = freq;
90c02d72 309 channels[count].band = band;
8a63facc
BC		 310 switch (mode) {
311 case AR5K_MODE_11A:
312 case AR5K_MODE_11G:
313 channels[count].hw_value = chfreq | CHANNEL_OFDM;
314 break;
8a63facc
BC		 315 case AR5K_MODE_11B:
316 channels[count].hw_value = CHANNEL_B;
317 }
fa1c114f 318
8a63facc 319 count++;
8a63facc 320 }
fa1c114f 321
8a63facc
BC		 322 return count;
323}
fa1c114f 324
8a63facc
BC		 325static void
326ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
327{
328 u8 i;
fa1c114f 329
8a63facc
BC		 330 for (i = 0; i < AR5K_MAX_RATES; i++)
331 sc->rate_idx[b->band][i] = -1;
fa1c114f 332
8a63facc
BC		 333 for (i = 0; i < b->n_bitrates; i++) {
334 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
335 if (b->bitrates[i].hw_value_short)
336 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 337 }
8a63facc 338}
fa1c114f 339
8a63facc
BC		 340static int
341ath5k_setup_bands(struct ieee80211_hw *hw)
342{
343 struct ath5k_softc *sc = hw->priv;
344 struct ath5k_hw *ah = sc->ah;
345 struct ieee80211_supported_band *sband;
346 int max_c, count_c = 0;
347 int i;
fa1c114f 348
8a63facc
BC		 349 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
350 max_c = ARRAY_SIZE(sc->channels);
db719718 351
8a63facc
BC		 352 /* 2GHz band */
353 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
354 sband->band = IEEE80211_BAND_2GHZ;
355 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 356
8a63facc
BC		 357 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
358 /* G mode */
359 memcpy(sband->bitrates, &ath5k_rates[0],
360 sizeof(struct ieee80211_rate) * 12);
361 sband->n_bitrates = 12;
2f7fe870 362
8a63facc 363 sband->channels = sc->channels;
08105690 364 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 365 AR5K_MODE_11G, max_c);
fa1c114f 366
8a63facc
BC		 367 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
368 count_c = sband->n_channels;
369 max_c -= count_c;
370 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
371 /* B mode */
372 memcpy(sband->bitrates, &ath5k_rates[0],
373 sizeof(struct ieee80211_rate) * 4);
374 sband->n_bitrates = 4;
fa1c114f 375
8a63facc
BC		 376 /* 5211 only supports B rates and uses 4bit rate codes
377 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
378 * fix them up here:
379 */
380 if (ah->ah_version == AR5K_AR5211) {
381 for (i = 0; i < 4; i++) {
382 sband->bitrates[i].hw_value =
383 sband->bitrates[i].hw_value & 0xF;
384 sband->bitrates[i].hw_value_short =
385 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 386 }
387 }
fa1c114f 388
8a63facc 389 sband->channels = sc->channels;
08105690 390 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 391 AR5K_MODE_11B, max_c);
fa1c114f 392
8a63facc
BC		 393 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
394 count_c = sband->n_channels;
395 max_c -= count_c;
396 }
397 ath5k_setup_rate_idx(sc, sband);
fa1c114f 398
8a63facc
BC		 399 /* 5GHz band, A mode */
400 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
401 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
402 sband->band = IEEE80211_BAND_5GHZ;
403 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 404
8a63facc
BC		 405 memcpy(sband->bitrates, &ath5k_rates[4],
406 sizeof(struct ieee80211_rate) * 8);
407 sband->n_bitrates = 8;
fa1c114f 408
8a63facc 409 sband->channels = &sc->channels[count_c];
08105690 410 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 411 AR5K_MODE_11A, max_c);
fa1c114f 412
8a63facc
BC		 413 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
414 }
415 ath5k_setup_rate_idx(sc, sband);
416
417 ath5k_debug_dump_bands(sc);
fa1c114f 418
fa1c114f
JS		 419 return 0;
420}
421
8a63facc
BC		 422/*
423 * Set/change channels. We always reset the chip.
424 * To accomplish this we must first cleanup any pending DMA,
425 * then restart stuff after a la ath5k_init.
426 *
427 * Called with sc->lock.
428 */
cd2c5486 429int
8a63facc
BC		 430ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
431{
432 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
433 "channel set, resetting (%u -> %u MHz)\n",
434 sc->curchan->center_freq, chan->center_freq);
435
8451d22d 436 /*
8a63facc
BC		 437 * To switch channels clear any pending DMA operations;
438 * wait long enough for the RX fifo to drain, reset the
439 * hardware at the new frequency, and then re-enable
440 * the relevant bits of the h/w.
8451d22d 441 */
8aec7af9 442 return ath5k_reset(sc, chan, true);
fa1c114f 443}
fa1c114f 444
e4b0b32a 445void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
b1ae1edf 446{
e4b0b32a 447 struct ath5k_vif_iter_data *iter_data = data;
b1ae1edf 448 int i;
62c58fb4 449 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 450
451 if (iter_data->hw_macaddr)
452 for (i = 0; i < ETH_ALEN; i++)
453 iter_data->mask[i] &=
454 ~(iter_data->hw_macaddr[i] ^ mac[i]);
455
456 if (!iter_data->found_active) {
457 iter_data->found_active = true;
458 memcpy(iter_data->active_mac, mac, ETH_ALEN);
459 }
460
461 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
462 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
463 iter_data->need_set_hw_addr = false;
464
465 if (!iter_data->any_assoc) {
b1ae1edf
BG		 466 if (avf->assoc)
467 iter_data->any_assoc = true;
468 }
62c58fb4
BG		 469
470 /* Calculate combined mode - when APs are active, operate in AP mode.
471 * Otherwise use the mode of the new interface. This can currently
472 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 473 * interfaces is allowed.
62c58fb4
BG		 474 */
475 if (avf->opmode == NL80211_IFTYPE_AP)
476 iter_data->opmode = NL80211_IFTYPE_AP;
e4b0b32a
BG		 477 else {
478 if (avf->opmode == NL80211_IFTYPE_STATION)
479 iter_data->n_stas++;
62c58fb4
BG		 480 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
481 iter_data->opmode = avf->opmode;
e4b0b32a 482 }
b1ae1edf
BG		 483}
484
cd2c5486
BR		 485void
486ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
487 struct ieee80211_vif *vif)
b1ae1edf
BG		 488{
489 struct ath_common *common = ath5k_hw_common(sc->ah);
e4b0b32a
BG		 490 struct ath5k_vif_iter_data iter_data;
491 u32 rfilt;
b1ae1edf
BG		 492
493 /*
494 * Use the hardware MAC address as reference, the hardware uses it
495 * together with the BSSID mask when matching addresses.
496 */
497 iter_data.hw_macaddr = common->macaddr;
498 memset(&iter_data.mask, 0xff, ETH_ALEN);
499 iter_data.found_active = false;
500 iter_data.need_set_hw_addr = true;
62c58fb4 501 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
e4b0b32a 502 iter_data.n_stas = 0;
b1ae1edf
BG		 503
504 if (vif)
e4b0b32a 505 ath5k_vif_iter(&iter_data, vif->addr, vif);
b1ae1edf
BG		 506
507 /* Get list of all active MAC addresses */
e4b0b32a 508 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
b1ae1edf
BG		 509 &iter_data);
510 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
511
62c58fb4
BG		 512 sc->opmode = iter_data.opmode;
513 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
514 /* Nothing active, default to station mode */
515 sc->opmode = NL80211_IFTYPE_STATION;
516
7afbb2f0
BG		 517 ath5k_hw_set_opmode(sc->ah, sc->opmode);
518 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
519 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 520
b1ae1edf
BG		 521 if (iter_data.need_set_hw_addr && iter_data.found_active)
522 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
523
62c58fb4
BG		 524 if (ath5k_hw_hasbssidmask(sc->ah))
525 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf 526
e4b0b32a
BG		 527 /* Set up RX Filter */
528 if (iter_data.n_stas > 1) {
529 /* If you have multiple STA interfaces connected to
530 * different APs, ARPs are not received (most of the time?)
531 * Enabling PROMISC appears to fix that probem.
532 */
533 sc->filter_flags |= AR5K_RX_FILTER_PROM;
534 }
fa1c114f 535
8a63facc 536 rfilt = sc->filter_flags;
e4b0b32a 537 ath5k_hw_set_rx_filter(sc->ah, rfilt);
8a63facc
BC		 538 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
539}
fa1c114f 540
8a63facc
BC		 541static inline int
542ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
543{
544 int rix;
fa1c114f 545
8a63facc
BC		 546 /* return base rate on errors */
547 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
548 "hw_rix out of bounds: %x\n", hw_rix))
549 return 0;
550
930a7622 551 rix = sc->rate_idx[sc->curchan->band][hw_rix];
8a63facc
BC		 552 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
553 rix = 0;
554
555 return rix;
556}
557
558/***************\
559* Buffers setup *
560\***************/
561
562static
563struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
564{
565 struct ath_common *common = ath5k_hw_common(sc->ah);
566 struct sk_buff *skb;
fa1c114f
JS		 567
568 /*
8a63facc
BC		 569 * Allocate buffer with headroom_needed space for the
570 * fake physical layer header at the start.
fa1c114f 571 */
8a63facc
BC		 572 skb = ath_rxbuf_alloc(common,
573 common->rx_bufsize,
574 GFP_ATOMIC);
fa1c114f 575
8a63facc
BC		 576 if (!skb) {
577 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
578 common->rx_bufsize);
579 return NULL;
fa1c114f
JS		 580 }
581
aeae4ac9 582 *skb_addr = dma_map_single(sc->dev,
8a63facc 583 skb->data, common->rx_bufsize,
aeae4ac9
FF		 584 DMA_FROM_DEVICE);
585
586 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 587 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
588 dev_kfree_skb(skb);
589 return NULL;
0e149cf5 590 }
8a63facc
BC		 591 return skb;
592}
0e149cf5 593
8a63facc
BC		 594static int
595ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
596{
597 struct ath5k_hw *ah = sc->ah;
598 struct sk_buff *skb = bf->skb;
599 struct ath5k_desc *ds;
600 int ret;
fa1c114f 601
8a63facc
BC		 602 if (!skb) {
603 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
604 if (!skb)
605 return -ENOMEM;
606 bf->skb = skb;
f769c36b
BC		 607 }
608
8a63facc
BC		 609 /*
610 * Setup descriptors. For receive we always terminate
611 * the descriptor list with a self-linked entry so we'll
612 * not get overrun under high load (as can happen with a
613 * 5212 when ANI processing enables PHY error frames).
614 *
615 * To ensure the last descriptor is self-linked we create
616 * each descriptor as self-linked and add it to the end. As
617 * each additional descriptor is added the previous self-linked
618 * entry is "fixed" naturally. This should be safe even
619 * if DMA is happening. When processing RX interrupts we
620 * never remove/process the last, self-linked, entry on the
621 * descriptor list. This ensures the hardware always has
622 * someplace to write a new frame.
623 */
624 ds = bf->desc;
625 ds->ds_link = bf->daddr; /* link to self */
626 ds->ds_data = bf->skbaddr;
627 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 628 if (ret) {
8a63facc
BC		 629 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
630 return ret;
fa1c114f
JS		 631 }
632
8a63facc
BC		 633 if (sc->rxlink != NULL)
634 *sc->rxlink = bf->daddr;
635 sc->rxlink = &ds->ds_link;
fa1c114f 636 return 0;
fa1c114f
JS		 637}
638
8a63facc 639static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 640{
8a63facc
BC		 641 struct ieee80211_hdr *hdr;
642 enum ath5k_pkt_type htype;
643 __le16 fc;
fa1c114f 644
8a63facc
BC		 645 hdr = (struct ieee80211_hdr *)skb->data;
646 fc = hdr->frame_control;
fa1c114f 647
8a63facc
BC		 648 if (ieee80211_is_beacon(fc))
649 htype = AR5K_PKT_TYPE_BEACON;
650 else if (ieee80211_is_probe_resp(fc))
651 htype = AR5K_PKT_TYPE_PROBE_RESP;
652 else if (ieee80211_is_atim(fc))
653 htype = AR5K_PKT_TYPE_ATIM;
654 else if (ieee80211_is_pspoll(fc))
655 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 656 else
8a63facc 657 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 658
8a63facc 659 return htype;
42639fcd
BC		 660}
661
8a63facc
BC		 662static int
663ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
664 struct ath5k_txq *txq, int padsize)
fa1c114f 665{
8a63facc
BC		 666 struct ath5k_hw *ah = sc->ah;
667 struct ath5k_desc *ds = bf->desc;
668 struct sk_buff *skb = bf->skb;
669 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
670 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
671 struct ieee80211_rate *rate;
672 unsigned int mrr_rate[3], mrr_tries[3];
673 int i, ret;
674 u16 hw_rate;
675 u16 cts_rate = 0;
676 u16 duration = 0;
677 u8 rc_flags;
fa1c114f 678
8a63facc 679 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 680
8a63facc 681 /* XXX endianness */
aeae4ac9
FF		 682 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
683 DMA_TO_DEVICE);
fa1c114f 684
8a63facc 685 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 686 if (!rate) {
687 ret = -EINVAL;
688 goto err_unmap;
689 }
fa1c114f 690
8a63facc
BC		 691 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
692 flags |= AR5K_TXDESC_NOACK;
fa1c114f 693
8a63facc
BC		 694 rc_flags = info->control.rates[0].flags;
695 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
696 rate->hw_value_short : rate->hw_value;
42639fcd 697
8a63facc
BC		 698 pktlen = skb->len;
699
700 /* FIXME: If we are in g mode and rate is a CCK rate
701 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
702 * from tx power (value is in dB units already) */
703 if (info->control.hw_key) {
704 keyidx = info->control.hw_key->hw_key_idx;
705 pktlen += info->control.hw_key->icv_len;
706 }
707 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
708 flags |= AR5K_TXDESC_RTSENA;
709 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
710 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 711 info->control.vif, pktlen, info));
8a63facc
BC		 712 }
713 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
714 flags |= AR5K_TXDESC_CTSENA;
715 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
716 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 717 info->control.vif, pktlen, info));
8a63facc
BC		 718 }
719 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
720 ieee80211_get_hdrlen_from_skb(skb), padsize,
721 get_hw_packet_type(skb),
722 (sc->power_level * 2),
723 hw_rate,
724 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
725 cts_rate, duration);
726 if (ret)
727 goto err_unmap;
728
729 memset(mrr_rate, 0, sizeof(mrr_rate));
730 memset(mrr_tries, 0, sizeof(mrr_tries));
731 for (i = 0; i < 3; i++) {
732 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
733 if (!rate)
400ec45a 734 break;
fa1c114f 735
8a63facc
BC		 736 mrr_rate[i] = rate->hw_value;
737 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 738 }
739
8a63facc
BC		 740 ath5k_hw_setup_mrr_tx_desc(ah, ds,
741 mrr_rate[0], mrr_tries[0],
742 mrr_rate[1], mrr_tries[1],
743 mrr_rate[2], mrr_tries[2]);
fa1c114f 744
8a63facc
BC		 745 ds->ds_link = 0;
746 ds->ds_data = bf->skbaddr;
63266a65 747
8a63facc
BC		 748 spin_lock_bh(&txq->lock);
749 list_add_tail(&bf->list, &txq->q);
925e0b06 750 txq->txq_len++;
8a63facc
BC		 751 if (txq->link == NULL) /* is this first packet? */
752 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
753 else /* no, so only link it */
754 *txq->link = bf->daddr;
63266a65 755
8a63facc
BC		 756 txq->link = &ds->ds_link;
757 ath5k_hw_start_tx_dma(ah, txq->qnum);
758 mmiowb();
759 spin_unlock_bh(&txq->lock);
760
761 return 0;
762err_unmap:
aeae4ac9 763 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 764 return ret;
63266a65
BR		 765}
766
8a63facc
BC		 767/*******************\
768* Descriptors setup *
769\*******************/
770
d8ee398d 771static int
aeae4ac9 772ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 773{
8a63facc
BC		 774 struct ath5k_desc *ds;
775 struct ath5k_buf *bf;
776 dma_addr_t da;
777 unsigned int i;
778 int ret;
d8ee398d 779
8a63facc
BC		 780 /* allocate descriptors */
781 sc->desc_len = sizeof(struct ath5k_desc) *
782 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 783
784 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
785 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 786 if (sc->desc == NULL) {
787 ATH5K_ERR(sc, "can't allocate descriptors\n");
788 ret = -ENOMEM;
789 goto err;
790 }
791 ds = sc->desc;
792 da = sc->desc_daddr;
793 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
794 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 795
8a63facc
BC		 796 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
797 sizeof(struct ath5k_buf), GFP_KERNEL);
798 if (bf == NULL) {
799 ATH5K_ERR(sc, "can't allocate bufptr\n");
800 ret = -ENOMEM;
801 goto err_free;
802 }
803 sc->bufptr = bf;
fa1c114f 804
8a63facc
BC		 805 INIT_LIST_HEAD(&sc->rxbuf);
806 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
807 bf->desc = ds;
808 bf->daddr = da;
809 list_add_tail(&bf->list, &sc->rxbuf);
810 }
d8ee398d 811
8a63facc
BC		 812 INIT_LIST_HEAD(&sc->txbuf);
813 sc->txbuf_len = ATH_TXBUF;
814 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
815 da += sizeof(*ds)) {
816 bf->desc = ds;
817 bf->daddr = da;
818 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 819 }
820
b1ae1edf
BG		 821 /* beacon buffers */
822 INIT_LIST_HEAD(&sc->bcbuf);
823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
824 bf->desc = ds;
825 bf->daddr = da;
826 list_add_tail(&bf->list, &sc->bcbuf);
827 }
fa1c114f 828
8a63facc
BC		 829 return 0;
830err_free:
aeae4ac9 831 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 832err:
833 sc->desc = NULL;
834 return ret;
835}
fa1c114f 836
cd2c5486
BR		 837void
838ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
839{
840 BUG_ON(!bf);
841 if (!bf->skb)
842 return;
843 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
844 DMA_TO_DEVICE);
845 dev_kfree_skb_any(bf->skb);
846 bf->skb = NULL;
847 bf->skbaddr = 0;
848 bf->desc->ds_data = 0;
849}
850
851void
852ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
853{
854 struct ath5k_hw *ah = sc->ah;
855 struct ath_common *common = ath5k_hw_common(ah);
856
857 BUG_ON(!bf);
858 if (!bf->skb)
859 return;
860 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
861 DMA_FROM_DEVICE);
862 dev_kfree_skb_any(bf->skb);
863 bf->skb = NULL;
864 bf->skbaddr = 0;
865 bf->desc->ds_data = 0;
866}
867
8a63facc 868static void
aeae4ac9 869ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 870{
871 struct ath5k_buf *bf;
d8ee398d 872
8a63facc
BC		 873 list_for_each_entry(bf, &sc->txbuf, list)
874 ath5k_txbuf_free_skb(sc, bf);
875 list_for_each_entry(bf, &sc->rxbuf, list)
876 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 877 list_for_each_entry(bf, &sc->bcbuf, list)
878 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 879
8a63facc 880 /* Free memory associated with all descriptors */
aeae4ac9 881 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 882 sc->desc = NULL;
883 sc->desc_daddr = 0;
d8ee398d 884
8a63facc
BC		 885 kfree(sc->bufptr);
886 sc->bufptr = NULL;
fa1c114f
JS		 887}
888
8a63facc
BC		 889
890/**************\
891* Queues setup *
892\**************/
893
894static struct ath5k_txq *
895ath5k_txq_setup(struct ath5k_softc *sc,
896 int qtype, int subtype)
fa1c114f 897{
8a63facc
BC		 898 struct ath5k_hw *ah = sc->ah;
899 struct ath5k_txq *txq;
900 struct ath5k_txq_info qi = {
901 .tqi_subtype = subtype,
de8af455
BR		 902 /* XXX: default values not correct for B and XR channels,
903 * but who cares? */
904 .tqi_aifs = AR5K_TUNE_AIFS,
905 .tqi_cw_min = AR5K_TUNE_CWMIN,
906 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 907 };
908 int qnum;
d8ee398d 909
e30eb4ab 910 /*
8a63facc
BC		 911 * Enable interrupts only for EOL and DESC conditions.
912 * We mark tx descriptors to receive a DESC interrupt
913 * when a tx queue gets deep; otherwise we wait for the
914 * EOL to reap descriptors. Note that this is done to
915 * reduce interrupt load and this only defers reaping
916 * descriptors, never transmitting frames. Aside from
917 * reducing interrupts this also permits more concurrency.
918 * The only potential downside is if the tx queue backs
919 * up in which case the top half of the kernel may backup
920 * due to a lack of tx descriptors.
e30eb4ab 921 */
8a63facc
BC		 922 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
923 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
924 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
925 if (qnum < 0) {
926 /*
927 * NB: don't print a message, this happens
928 * normally on parts with too few tx queues
929 */
930 return ERR_PTR(qnum);
931 }
932 if (qnum >= ARRAY_SIZE(sc->txqs)) {
933 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
934 qnum, ARRAY_SIZE(sc->txqs));
935 ath5k_hw_release_tx_queue(ah, qnum);
936 return ERR_PTR(-EINVAL);
937 }
938 txq = &sc->txqs[qnum];
939 if (!txq->setup) {
940 txq->qnum = qnum;
941 txq->link = NULL;
942 INIT_LIST_HEAD(&txq->q);
943 spin_lock_init(&txq->lock);
944 txq->setup = true;
925e0b06 945 txq->txq_len = 0;
81266baf 946 txq->txq_max = ATH5K_TXQ_LEN_MAX;
4edd761f 947 txq->txq_poll_mark = false;
923e5b3d 948 txq->txq_stuck = 0;
8a63facc
BC		 949 }
950 return &sc->txqs[qnum];
fa1c114f
JS		 951}
952
8a63facc
BC		 953static int
954ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 955{
8a63facc 956 struct ath5k_txq_info qi = {
de8af455
BR		 957 /* XXX: default values not correct for B and XR channels,
958 * but who cares? */
959 .tqi_aifs = AR5K_TUNE_AIFS,
960 .tqi_cw_min = AR5K_TUNE_CWMIN,
961 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 962 /* NB: for dynamic turbo, don't enable any other interrupts */
963 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
964 };
d8ee398d 965
8a63facc 966 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 967}
968
8a63facc
BC		 969static int
970ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 971{
972 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 973 struct ath5k_txq_info qi;
974 int ret;
fa1c114f 975
8a63facc
BC		 976 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
977 if (ret)
978 goto err;
fa1c114f 979
8a63facc
BC		 980 if (sc->opmode == NL80211_IFTYPE_AP ||
981 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
982 /*
983 * Always burst out beacon and CAB traffic
984 * (aifs = cwmin = cwmax = 0)
985 */
986 qi.tqi_aifs = 0;
987 qi.tqi_cw_min = 0;
988 qi.tqi_cw_max = 0;
989 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
990 /*
991 * Adhoc mode; backoff between 0 and (2 * cw_min).
992 */
993 qi.tqi_aifs = 0;
994 qi.tqi_cw_min = 0;
de8af455 995 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 996 }
fa1c114f 997
8a63facc
BC		 998 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
999 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1000 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1001
8a63facc
BC		 1002 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1003 if (ret) {
1004 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1005 "hardware queue!\n", __func__);
1006 goto err;
1007 }
1008 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1009 if (ret)
1010 goto err;
b7266047 1011
8a63facc
BC		 1012 /* reconfigure cabq with ready time to 80% of beacon_interval */
1013 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1014 if (ret)
1015 goto err;
b7266047 1016
8a63facc
BC		 1017 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1018 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1019 if (ret)
1020 goto err;
b7266047 1021
8a63facc
BC		 1022 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1023err:
1024 return ret;
d8ee398d
LR		 1025}
1026
80dac9ee
NK		 1027/**
1028 * ath5k_drain_tx_buffs - Empty tx buffers
1029 *
1030 * @sc The &struct ath5k_softc
1031 *
1032 * Empty tx buffers from all queues in preparation
1033 * of a reset or during shutdown.
1034 *
1035 * NB: this assumes output has been stopped and
1036 * we do not need to block ath5k_tx_tasklet
1037 */
8a63facc 1038static void
80dac9ee 1039ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1040{
80dac9ee 1041 struct ath5k_txq *txq;
8a63facc 1042 struct ath5k_buf *bf, *bf0;
80dac9ee 1043 int i;
b6ea0356 1044
80dac9ee
NK		 1045 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1046 if (sc->txqs[i].setup) {
1047 txq = &sc->txqs[i];
1048 spin_lock_bh(&txq->lock);
1049 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1050 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1051
80dac9ee 1052 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1053
80dac9ee
NK		 1054 spin_lock_bh(&sc->txbuflock);
1055 list_move_tail(&bf->list, &sc->txbuf);
1056 sc->txbuf_len++;
1057 txq->txq_len--;
1058 spin_unlock_bh(&sc->txbuflock);
8a63facc 1059 }
80dac9ee
NK		 1060 txq->link = NULL;
1061 txq->txq_poll_mark = false;
1062 spin_unlock_bh(&txq->lock);
1063 }
0452d4a5 1064 }
fa1c114f
JS		 1065}
1066
8a63facc
BC		 1067static void
1068ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1069{
8a63facc
BC		 1070 struct ath5k_txq *txq = sc->txqs;
1071 unsigned int i;
2ac2927a 1072
8a63facc
BC		 1073 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1074 if (txq->setup) {
1075 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1076 txq->setup = false;
1077 }
1078}
2ac2927a 1079
2ac2927a 1080
8a63facc
BC		 1081/*************\
1082* RX Handling *
1083\*************/
2ac2927a 1084
8a63facc
BC		 1085/*
1086 * Enable the receive h/w following a reset.
1087 */
fa1c114f 1088static int
8a63facc 1089ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1090{
1091 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1092 struct ath_common *common = ath5k_hw_common(ah);
1093 struct ath5k_buf *bf;
1094 int ret;
fa1c114f 1095
8a63facc 1096 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1097
8a63facc
BC		 1098 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1099 common->cachelsz, common->rx_bufsize);
2f7fe870 1100
8a63facc
BC		 1101 spin_lock_bh(&sc->rxbuflock);
1102 sc->rxlink = NULL;
1103 list_for_each_entry(bf, &sc->rxbuf, list) {
1104 ret = ath5k_rxbuf_setup(sc, bf);
1105 if (ret != 0) {
1106 spin_unlock_bh(&sc->rxbuflock);
1107 goto err;
1108 }
2f7fe870 1109 }
8a63facc
BC		 1110 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1111 ath5k_hw_set_rxdp(ah, bf->daddr);
1112 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1113
8a63facc 1114 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
e4b0b32a 1115 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */
8a63facc 1116 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1117
1118 return 0;
8a63facc 1119err:
fa1c114f
JS		 1120 return ret;
1121}
1122
8a63facc 1123/*
80dac9ee
NK		 1124 * Disable the receive logic on PCU (DRU)
1125 * In preparation for a shutdown.
1126 *
1127 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1128 * does.
8a63facc
BC		 1129 */
1130static void
1131ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1132{
8a63facc 1133 struct ath5k_hw *ah = sc->ah;
fa1c114f 1134
8a63facc 1135 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1136 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1137
8a63facc
BC		 1138 ath5k_debug_printrxbuffs(sc, ah);
1139}
fa1c114f 1140
8a63facc
BC		 1141static unsigned int
1142ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1143 struct ath5k_rx_status *rs)
1144{
1145 struct ath5k_hw *ah = sc->ah;
1146 struct ath_common *common = ath5k_hw_common(ah);
1147 struct ieee80211_hdr *hdr = (void *)skb->data;
1148 unsigned int keyix, hlen;
fa1c114f 1149
8a63facc
BC		 1150 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1151 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1152 return RX_FLAG_DECRYPTED;
fa1c114f 1153
8a63facc
BC		 1154 /* Apparently when a default key is used to decrypt the packet
1155 the hw does not set the index used to decrypt. In such cases
1156 get the index from the packet. */
1157 hlen = ieee80211_hdrlen(hdr->frame_control);
1158 if (ieee80211_has_protected(hdr->frame_control) &&
1159 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1160 skb->len >= hlen + 4) {
1161 keyix = skb->data[hlen + 3] >> 6;
1162
1163 if (test_bit(keyix, common->keymap))
1164 return RX_FLAG_DECRYPTED;
1165 }
fa1c114f
JS		 1166
1167 return 0;
fa1c114f
JS		 1168}
1169
8a63facc 1170
fa1c114f 1171static void
8a63facc
BC		 1172ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1173 struct ieee80211_rx_status *rxs)
fa1c114f 1174{
8a63facc
BC		 1175 struct ath_common *common = ath5k_hw_common(sc->ah);
1176 u64 tsf, bc_tstamp;
1177 u32 hw_tu;
1178 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1179
8a63facc
BC		 1180 if (ieee80211_is_beacon(mgmt->frame_control) &&
1181 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1182 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1183 /*
1184 * Received an IBSS beacon with the same BSSID. Hardware *must*
1185 * have updated the local TSF. We have to work around various
1186 * hardware bugs, though...
1187 */
1188 tsf = ath5k_hw_get_tsf64(sc->ah);
1189 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1190 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1191
8a63facc
BC		 1192 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1193 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1194 (unsigned long long)bc_tstamp,
1195 (unsigned long long)rxs->mactime,
1196 (unsigned long long)(rxs->mactime - bc_tstamp),
1197 (unsigned long long)tsf);
fa1c114f 1198
8a63facc
BC		 1199 /*
1200 * Sometimes the HW will give us a wrong tstamp in the rx
1201 * status, causing the timestamp extension to go wrong.
1202 * (This seems to happen especially with beacon frames bigger
1203 * than 78 byte (incl. FCS))
1204 * But we know that the receive timestamp must be later than the
1205 * timestamp of the beacon since HW must have synced to that.
1206 *
1207 * NOTE: here we assume mactime to be after the frame was
1208 * received, not like mac80211 which defines it at the start.
1209 */
1210 if (bc_tstamp > rxs->mactime) {
1211 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1212 "fixing mactime from %llx to %llx\n",
1213 (unsigned long long)rxs->mactime,
1214 (unsigned long long)tsf);
1215 rxs->mactime = tsf;
1216 }
fa1c114f 1217
8a63facc
BC		 1218 /*
1219 * Local TSF might have moved higher than our beacon timers,
1220 * in that case we have to update them to continue sending
1221 * beacons. This also takes care of synchronizing beacon sending
1222 * times with other stations.
1223 */
1224 if (hw_tu >= sc->nexttbtt)
1225 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1226
1227 /* Check if the beacon timers are still correct, because a TSF
1228 * update might have created a window between them - for a
1229 * longer description see the comment of this function: */
1230 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1231 ath5k_beacon_update_timers(sc, bc_tstamp);
1232 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1233 "fixed beacon timers after beacon receive\n");
1234 }
8a63facc
BC		 1235 }
1236}
fa1c114f 1237
8a63facc
BC		 1238static void
1239ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1240{
1241 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1242 struct ath5k_hw *ah = sc->ah;
1243 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1244
8a63facc
BC		 1245 /* only beacons from our BSSID */
1246 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1247 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1248 return;
fa1c114f 1249
eef39bef 1250 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1251
8a63facc
BC		 1252 /* in IBSS mode we should keep RSSI statistics per neighbour */
1253 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1254}
fa1c114f 1255
8a63facc
BC		 1256/*
1257 * Compute padding position. skb must contain an IEEE 802.11 frame
1258 */
1259static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1260{
8a63facc
BC		 1261 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1262 __le16 frame_control = hdr->frame_control;
1263 int padpos = 24;
fa1c114f 1264
8a63facc
BC		 1265 if (ieee80211_has_a4(frame_control)) {
1266 padpos += ETH_ALEN;
fa1c114f 1267 }
8a63facc
BC		 1268 if (ieee80211_is_data_qos(frame_control)) {
1269 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1270 }
8a63facc
BC		 1271
1272 return padpos;
fa1c114f
JS		 1273}
1274
8a63facc
BC		 1275/*
1276 * This function expects an 802.11 frame and returns the number of
1277 * bytes added, or -1 if we don't have enough header room.
1278 */
1279static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1280{
8a63facc
BC		 1281 int padpos = ath5k_common_padpos(skb);
1282 int padsize = padpos & 3;
fa1c114f 1283
8a63facc 1284 if (padsize && skb->len>padpos) {
fa1c114f 1285
8a63facc
BC		 1286 if (skb_headroom(skb) < padsize)
1287 return -1;
fa1c114f 1288
8a63facc
BC		 1289 skb_push(skb, padsize);
1290 memmove(skb->data, skb->data+padsize, padpos);
1291 return padsize;
1292 }
a951ae21 1293
8a63facc
BC		 1294 return 0;
1295}
fa1c114f 1296
8a63facc
BC		 1297/*
1298 * The MAC header is padded to have 32-bit boundary if the
1299 * packet payload is non-zero. The general calculation for
1300 * padsize would take into account odd header lengths:
1301 * padsize = 4 - (hdrlen & 3); however, since only
1302 * even-length headers are used, padding can only be 0 or 2
1303 * bytes and we can optimize this a bit. We must not try to
1304 * remove padding from short control frames that do not have a
1305 * payload.
1306 *
1307 * This function expects an 802.11 frame and returns the number of
1308 * bytes removed.
1309 */
1310static int ath5k_remove_padding(struct sk_buff *skb)
1311{
1312 int padpos = ath5k_common_padpos(skb);
1313 int padsize = padpos & 3;
6d91e1d8 1314
8a63facc
BC		 1315 if (padsize && skb->len>=padpos+padsize) {
1316 memmove(skb->data + padsize, skb->data, padpos);
1317 skb_pull(skb, padsize);
1318 return padsize;
fa1c114f 1319 }
a951ae21 1320
8a63facc 1321 return 0;
fa1c114f
JS		 1322}
1323
1324static void
8a63facc
BC		 1325ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1326 struct ath5k_rx_status *rs)
fa1c114f 1327{
8a63facc
BC		 1328 struct ieee80211_rx_status *rxs;
1329
1330 ath5k_remove_padding(skb);
1331
1332 rxs = IEEE80211_SKB_RXCB(skb);
1333
1334 rxs->flag = 0;
1335 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1336 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1337
1338 /*
8a63facc
BC		 1339 * always extend the mac timestamp, since this information is
1340 * also needed for proper IBSS merging.
1341 *
1342 * XXX: it might be too late to do it here, since rs_tstamp is
1343 * 15bit only. that means TSF extension has to be done within
1344 * 32768usec (about 32ms). it might be necessary to move this to
1345 * the interrupt handler, like it is done in madwifi.
1346 *
1347 * Unfortunately we don't know when the hardware takes the rx
1348 * timestamp (beginning of phy frame, data frame, end of rx?).
1349 * The only thing we know is that it is hardware specific...
1350 * On AR5213 it seems the rx timestamp is at the end of the
1351 * frame, but i'm not sure.
1352 *
1353 * NOTE: mac80211 defines mactime at the beginning of the first
1354 * data symbol. Since we don't have any time references it's
1355 * impossible to comply to that. This affects IBSS merge only
1356 * right now, so it's not too bad...
fa1c114f 1357 */
8a63facc 1358 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
6ebacbb7 1359 rxs->flag |= RX_FLAG_MACTIME_MPDU;
fa1c114f 1360
8a63facc 1361 rxs->freq = sc->curchan->center_freq;
930a7622 1362 rxs->band = sc->curchan->band;
fa1c114f 1363
8a63facc 1364 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1365
8a63facc 1366 rxs->antenna = rs->rs_antenna;
fa1c114f 1367
8a63facc
BC		 1368 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1369 sc->stats.antenna_rx[rs->rs_antenna]++;
1370 else
1371 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1372
8a63facc
BC		 1373 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1374 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1375
8a63facc 1376 if (rxs->rate_idx >= 0 && rs->rs_rate ==
930a7622 1377 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1378 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1379
0e472252 1380 trace_ath5k_rx(sc, skb);
fa1c114f 1381
8a63facc 1382 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1383
8a63facc
BC		 1384 /* check beacons in IBSS mode */
1385 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1386 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1387
8a63facc
BC		 1388 ieee80211_rx(sc->hw, skb);
1389}
fa1c114f 1390
8a63facc
BC		 1391/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1392 *
1393 * Check if we want to further process this frame or not. Also update
1394 * statistics. Return true if we want this frame, false if not.
fa1c114f 1395 */
8a63facc
BC		 1396static bool
1397ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1398{
8a63facc 1399 sc->stats.rx_all_count++;
b72acddb 1400 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1401
8a63facc
BC		 1402 if (unlikely(rs->rs_status)) {
1403 if (rs->rs_status & AR5K_RXERR_CRC)
1404 sc->stats.rxerr_crc++;
1405 if (rs->rs_status & AR5K_RXERR_FIFO)
1406 sc->stats.rxerr_fifo++;
1407 if (rs->rs_status & AR5K_RXERR_PHY) {
1408 sc->stats.rxerr_phy++;
1409 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1410 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1411 return false;
1412 }
1413 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1414 /*
1415 * Decrypt error. If the error occurred
1416 * because there was no hardware key, then
1417 * let the frame through so the upper layers
1418 * can process it. This is necessary for 5210
1419 * parts which have no way to setup a ``clear''
1420 * key cache entry.
1421 *
1422 * XXX do key cache faulting
1423 */
1424 sc->stats.rxerr_decrypt++;
1425 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1426 !(rs->rs_status & AR5K_RXERR_CRC))
1427 return true;
1428 }
1429 if (rs->rs_status & AR5K_RXERR_MIC) {
1430 sc->stats.rxerr_mic++;
1431 return true;
fa1c114f 1432 }
fa1c114f 1433
8a63facc
BC		 1434 /* reject any frames with non-crypto errors */
1435 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1436 return false;
1437 }
fa1c114f 1438
8a63facc
BC		 1439 if (unlikely(rs->rs_more)) {
1440 sc->stats.rxerr_jumbo++;
1441 return false;
1442 }
1443 return true;
fa1c114f
JS		 1444}
1445
fa1c114f 1446static void
8a63facc 1447ath5k_tasklet_rx(unsigned long data)
fa1c114f 1448{
8a63facc
BC		 1449 struct ath5k_rx_status rs = {};
1450 struct sk_buff *skb, *next_skb;
1451 dma_addr_t next_skb_addr;
1452 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1453 struct ath5k_hw *ah = sc->ah;
1454 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1455 struct ath5k_buf *bf;
1456 struct ath5k_desc *ds;
1457 int ret;
fa1c114f 1458
8a63facc
BC		 1459 spin_lock(&sc->rxbuflock);
1460 if (list_empty(&sc->rxbuf)) {
1461 ATH5K_WARN(sc, "empty rx buf pool\n");
1462 goto unlock;
1463 }
1464 do {
1465 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1466 BUG_ON(bf->skb == NULL);
1467 skb = bf->skb;
1468 ds = bf->desc;
fa1c114f 1469
8a63facc
BC		 1470 /* bail if HW is still using self-linked descriptor */
1471 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1472 break;
fa1c114f 1473
8a63facc
BC		 1474 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1475 if (unlikely(ret == -EINPROGRESS))
1476 break;
1477 else if (unlikely(ret)) {
1478 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1479 sc->stats.rxerr_proc++;
1480 break;
1481 }
fa1c114f 1482
8a63facc
BC		 1483 if (ath5k_receive_frame_ok(sc, &rs)) {
1484 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1485
8a63facc
BC		 1486 /*
1487 * If we can't replace bf->skb with a new skb under
1488 * memory pressure, just skip this packet
1489 */
1490 if (!next_skb)
1491 goto next;
036cd1ec 1492
aeae4ac9 1493 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1494 common->rx_bufsize,
aeae4ac9 1495 DMA_FROM_DEVICE);
036cd1ec 1496
8a63facc 1497 skb_put(skb, rs.rs_datalen);
6ba81c2c 1498
8a63facc 1499 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1500
8a63facc
BC		 1501 bf->skb = next_skb;
1502 bf->skbaddr = next_skb_addr;
036cd1ec 1503 }
8a63facc
BC		 1504next:
1505 list_move_tail(&bf->list, &sc->rxbuf);
1506 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1507unlock:
1508 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1509}
1510
b4ea449d 1511
8a63facc
BC		 1512/*************\
1513* TX Handling *
1514\*************/
b4ea449d 1515
7bb45683 1516void
cd2c5486
BR		 1517ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1518 struct ath5k_txq *txq)
8a63facc
BC		 1519{
1520 struct ath5k_softc *sc = hw->priv;
1521 struct ath5k_buf *bf;
1522 unsigned long flags;
1523 int padsize;
b4ea449d 1524
0e472252 1525 trace_ath5k_tx(sc, skb, txq);
b4ea449d 1526
8a63facc
BC		 1527 /*
1528 * The hardware expects the header padded to 4 byte boundaries.
1529 * If this is not the case, we add the padding after the header.
1530 */
1531 padsize = ath5k_add_padding(skb);
1532 if (padsize < 0) {
1533 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1534 " headroom to pad");
1535 goto drop_packet;
1536 }
8127fbdc 1537
81266baf 1538 if (txq->txq_len >= txq->txq_max)
925e0b06
BR		 1539 ieee80211_stop_queue(hw, txq->qnum);
1540
8a63facc
BC		 1541 spin_lock_irqsave(&sc->txbuflock, flags);
1542 if (list_empty(&sc->txbuf)) {
1543 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1544 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1545 ieee80211_stop_queues(hw);
8a63facc 1546 goto drop_packet;
8127fbdc 1547 }
8a63facc
BC		 1548 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1549 list_del(&bf->list);
1550 sc->txbuf_len--;
1551 if (list_empty(&sc->txbuf))
1552 ieee80211_stop_queues(hw);
1553 spin_unlock_irqrestore(&sc->txbuflock, flags);
1554
1555 bf->skb = skb;
1556
1557 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1558 bf->skb = NULL;
1559 spin_lock_irqsave(&sc->txbuflock, flags);
1560 list_add_tail(&bf->list, &sc->txbuf);
1561 sc->txbuf_len++;
1562 spin_unlock_irqrestore(&sc->txbuflock, flags);
1563 goto drop_packet;
8127fbdc 1564 }
7bb45683 1565 return;
8127fbdc 1566
8a63facc
BC		 1567drop_packet:
1568 dev_kfree_skb_any(skb);
8127fbdc
BP		 1569}
1570
1440401e
BR		 1571static void
1572ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
0e472252 1573 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1440401e
BR		 1574{
1575 struct ieee80211_tx_info *info;
1576 int i;
1577
1578 sc->stats.tx_all_count++;
b72acddb 1579 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1580 info = IEEE80211_SKB_CB(skb);
1581
1582 ieee80211_tx_info_clear_status(info);
1583 for (i = 0; i < 4; i++) {
1584 struct ieee80211_tx_rate *r =
1585 &info->status.rates[i];
1586
1587 if (ts->ts_rate[i]) {
1588 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1589 r->count = ts->ts_retry[i];
1590 } else {
1591 r->idx = -1;
1592 r->count = 0;
1593 }
1594 }
1595
1596 /* count the successful attempt as well */
1597 info->status.rates[ts->ts_final_idx].count++;
1598
1599 if (unlikely(ts->ts_status)) {
1600 sc->stats.ack_fail++;
1601 if (ts->ts_status & AR5K_TXERR_FILT) {
1602 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1603 sc->stats.txerr_filt++;
1604 }
1605 if (ts->ts_status & AR5K_TXERR_XRETRY)
1606 sc->stats.txerr_retry++;
1607 if (ts->ts_status & AR5K_TXERR_FIFO)
1608 sc->stats.txerr_fifo++;
1609 } else {
1610 info->flags |= IEEE80211_TX_STAT_ACK;
1611 info->status.ack_signal = ts->ts_rssi;
1612 }
1613
1614 /*
1615 * Remove MAC header padding before giving the frame
1616 * back to mac80211.
1617 */
1618 ath5k_remove_padding(skb);
1619
1620 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1621 sc->stats.antenna_tx[ts->ts_antenna]++;
1622 else
1623 sc->stats.antenna_tx[0]++; /* invalid */
1624
0e472252 1625 trace_ath5k_tx_complete(sc, skb, txq, ts);
1440401e
BR		 1626 ieee80211_tx_status(sc->hw, skb);
1627}
8a63facc
BC		 1628
1629static void
1630ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1631{
8a63facc
BC		 1632 struct ath5k_tx_status ts = {};
1633 struct ath5k_buf *bf, *bf0;
1634 struct ath5k_desc *ds;
1635 struct sk_buff *skb;
1440401e 1636 int ret;
8127fbdc 1637
8a63facc
BC		 1638 spin_lock(&txq->lock);
1639 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1640
1641 txq->txq_poll_mark = false;
1642
1643 /* skb might already have been processed last time. */
1644 if (bf->skb != NULL) {
1645 ds = bf->desc;
1646
1647 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1648 if (unlikely(ret == -EINPROGRESS))
1649 break;
1650 else if (unlikely(ret)) {
1651 ATH5K_ERR(sc,
1652 "error %d while processing "
1653 "queue %u\n", ret, txq->qnum);
1654 break;
1655 }
1656
1657 skb = bf->skb;
1658 bf->skb = NULL;
aeae4ac9
FF		 1659
1660 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1661 DMA_TO_DEVICE);
0e472252 1662 ath5k_tx_frame_completed(sc, skb, txq, &ts);
23413296 1663 }
8127fbdc 1664
8a63facc
BC		 1665 /*
1666 * It's possible that the hardware can say the buffer is
1667 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1668 * host memory and moved on.
1669 * Always keep the last descriptor to avoid HW races...
8a63facc 1670 */
23413296
BR		 1671 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1672 spin_lock(&sc->txbuflock);
1673 list_move_tail(&bf->list, &sc->txbuf);
1674 sc->txbuf_len++;
1675 txq->txq_len--;
1676 spin_unlock(&sc->txbuflock);
8a63facc 1677 }
fa1c114f 1678 }
fa1c114f 1679 spin_unlock(&txq->lock);
4198a8d0 1680 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1681 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1682}
1683
1684static void
1685ath5k_tasklet_tx(unsigned long data)
1686{
8784d2ee 1687 int i;
fa1c114f
JS		 1688 struct ath5k_softc *sc = (void *)data;
1689
8784d2ee
BC		 1690 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1691 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1692 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1693}
1694
1695
fa1c114f
JS		 1696/*****************\
1697* Beacon handling *
1698\*****************/
1699
1700/*
1701 * Setup the beacon frame for transmit.
1702 */
1703static int
e039fa4a 1704ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1705{
1706 struct sk_buff *skb = bf->skb;
a888d52d 1707 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1708 struct ath5k_hw *ah = sc->ah;
1709 struct ath5k_desc *ds;
2bed03eb
NK		 1710 int ret = 0;
1711 u8 antenna;
fa1c114f 1712 u32 flags;
8127fbdc 1713 const int padsize = 0;
fa1c114f 1714
aeae4ac9
FF		 1715 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1716 DMA_TO_DEVICE);
fa1c114f
JS		 1717 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1718 "skbaddr %llx\n", skb, skb->data, skb->len,
1719 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1720
1721 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1722 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1723 return -EIO;
1724 }
1725
1726 ds = bf->desc;
2bed03eb 1727 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1728
1729 flags = AR5K_TXDESC_NOACK;
05c914fe 1730 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1731 ds->ds_link = bf->daddr; /* self-linked */
1732 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1733 } else
fa1c114f 1734 ds->ds_link = 0;
2bed03eb
NK		 1735
1736 /*
1737 * If we use multiple antennas on AP and use
1738 * the Sectored AP scenario, switch antenna every
1739 * 4 beacons to make sure everybody hears our AP.
1740 * When a client tries to associate, hw will keep
1741 * track of the tx antenna to be used for this client
1742 * automaticaly, based on ACKed packets.
1743 *
1744 * Note: AP still listens and transmits RTS on the
1745 * default antenna which is supposed to be an omni.
1746 *
1747 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1748 * multiple antennas (1 omni -- the default -- and 14
1749 * sectors), so if we choose to actually support this
1750 * mode, we need to allow the user to set how many antennas
1751 * we have and tweak the code below to send beacons
1752 * on all of them.
2bed03eb
NK		 1753 */
1754 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1755 antenna = sc->bsent & 4 ? 2 : 1;
1756
fa1c114f 1757
8f655dde
NK		 1758 /* FIXME: If we are in g mode and rate is a CCK rate
1759 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1760 * from tx power (value is in dB units already) */
fa1c114f 1761 ds->ds_data = bf->skbaddr;
281c56dd 1762 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1763 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1764 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1765 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1766 1, AR5K_TXKEYIX_INVALID,
400ec45a 1767 antenna, flags, 0, 0);
fa1c114f
JS		 1768 if (ret)
1769 goto err_unmap;
1770
1771 return 0;
1772err_unmap:
aeae4ac9 1773 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1774 return ret;
1775}
1776
8a63facc
BC		 1777/*
1778 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1779 * this is called only once at config_bss time, for AP we do it every
1780 * SWBA interrupt so that the TIM will reflect buffered frames.
1781 *
1782 * Called with the beacon lock.
1783 */
cd2c5486 1784int
8a63facc
BC		 1785ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1786{
1787 int ret;
1788 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1789 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1790 struct sk_buff *skb;
1791
1792 if (WARN_ON(!vif)) {
1793 ret = -EINVAL;
1794 goto out;
1795 }
1796
1797 skb = ieee80211_beacon_get(hw, vif);
1798
1799 if (!skb) {
1800 ret = -ENOMEM;
1801 goto out;
1802 }
1803
b1ae1edf
BG		 1804 ath5k_txbuf_free_skb(sc, avf->bbuf);
1805 avf->bbuf->skb = skb;
1806 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1807 if (ret)
b1ae1edf 1808 avf->bbuf->skb = NULL;
8a63facc
BC		 1809out:
1810 return ret;
1811}
1812
fa1c114f
JS		 1813/*
1814 * Transmit a beacon frame at SWBA. Dynamic updates to the
1815 * frame contents are done as needed and the slot time is
1816 * also adjusted based on current state.
1817 *
5faaff74
BC		 1818 * This is called from software irq context (beacontq tasklets)
1819 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1820 */
1821static void
1822ath5k_beacon_send(struct ath5k_softc *sc)
1823{
fa1c114f 1824 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1825 struct ieee80211_vif *vif;
1826 struct ath5k_vif *avf;
1827 struct ath5k_buf *bf;
cec8db23 1828 struct sk_buff *skb;
fa1c114f 1829
be9b7259 1830 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1831
fa1c114f
JS		 1832 /*
1833 * Check if the previous beacon has gone out. If
a180a130 1834 * not, don't don't try to post another: skip this
fa1c114f
JS		 1835 * period and wait for the next. Missed beacons
1836 * indicate a problem and should not occur. If we
1837 * miss too many consecutive beacons reset the device.
1838 */
1839 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1840 sc->bmisscount++;
be9b7259 1841 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1842 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1843 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1844 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1845 "stuck beacon time (%u missed)\n",
1846 sc->bmisscount);
8d67a031
BR		 1847 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1848 "stuck beacon, resetting\n");
5faaff74 1849 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1850 }
1851 return;
1852 }
1853 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1854 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1855 "resume beacon xmit after %u misses\n",
1856 sc->bmisscount);
1857 sc->bmisscount = 0;
1858 }
1859
b93996cf
JC		 1860 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1861 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1862 u64 tsf = ath5k_hw_get_tsf64(ah);
1863 u32 tsftu = TSF_TO_TU(tsf);
1864 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1865 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1866 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1867 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1868 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1869 } else /* only one interface */
1870 vif = sc->bslot[0];
1871
1872 if (!vif)
1873 return;
1874
1875 avf = (void *)vif->drv_priv;
1876 bf = avf->bbuf;
1877 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1878 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1879 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1880 return;
1881 }
1882
fa1c114f
JS		 1883 /*
1884 * Stop any current dma and put the new frame on the queue.
1885 * This should never fail since we check above that no frames
1886 * are still pending on the queue.
1887 */
14fae2d4 1888 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1889 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1890 /* NB: hw still stops DMA, so proceed */
1891 }
fa1c114f 1892
d82b577b
JC		 1893 /* refresh the beacon for AP or MESH mode */
1894 if (sc->opmode == NL80211_IFTYPE_AP ||
1895 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1896 ath5k_beacon_update(sc->hw, vif);
1071db86 1897
0e472252
BC		 1898 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
1899
c6e387a2
NK		 1900 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1901 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1902 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1903 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1904
b1ae1edf 1905 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1906 while (skb) {
1907 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1908 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1909 }
1910
fa1c114f
JS		 1911 sc->bsent++;
1912}
1913
9804b98d
BR		 1914/**
1915 * ath5k_beacon_update_timers - update beacon timers
1916 *
1917 * @sc: struct ath5k_softc pointer we are operating on
1918 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1919 * beacon timer update based on the current HW TSF.
1920 *
1921 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1922 * of a received beacon or the current local hardware TSF and write it to the
1923 * beacon timer registers.
1924 *
1925 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1926 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1927 * when we otherwise know we have to update the timers, but we keep it in this
1928 * function to have it all together in one place.
1929 */
cd2c5486 1930void
9804b98d 1931ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1932{
1933 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1934 u32 nexttbtt, intval, hw_tu, bc_tu;
1935 u64 hw_tsf;
fa1c114f
JS		 1936
1937 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1938 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1939 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1940 if (intval < 15)
1941 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1942 intval);
1943 }
fa1c114f
JS		 1944 if (WARN_ON(!intval))
1945 return;
1946
9804b98d
BR		 1947 /* beacon TSF converted to TU */
1948 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1949
9804b98d
BR		 1950 /* current TSF converted to TU */
1951 hw_tsf = ath5k_hw_get_tsf64(ah);
1952 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1953
11f21df3
BR		 1954#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1955 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
25985edc 1956 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
11f21df3
BR		 1957 * configuration we need to make sure it is bigger than that. */
1958
9804b98d
BR		 1959 if (bc_tsf == -1) {
1960 /*
1961 * no beacons received, called internally.
1962 * just need to refresh timers based on HW TSF.
1963 */
1964 nexttbtt = roundup(hw_tu + FUDGE, intval);
1965 } else if (bc_tsf == 0) {
1966 /*
1967 * no beacon received, probably called by ath5k_reset_tsf().
1968 * reset TSF to start with 0.
1969 */
1970 nexttbtt = intval;
1971 intval |= AR5K_BEACON_RESET_TSF;
1972 } else if (bc_tsf > hw_tsf) {
1973 /*
25985edc 1974 * beacon received, SW merge happened but HW TSF not yet updated.
9804b98d
BR		 1975 * not possible to reconfigure timers yet, but next time we
1976 * receive a beacon with the same BSSID, the hardware will
1977 * automatically update the TSF and then we need to reconfigure
1978 * the timers.
1979 */
1980 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1981 "need to wait for HW TSF sync\n");
1982 return;
1983 } else {
1984 /*
1985 * most important case for beacon synchronization between STA.
1986 *
1987 * beacon received and HW TSF has been already updated by HW.
1988 * update next TBTT based on the TSF of the beacon, but make
1989 * sure it is ahead of our local TSF timer.
1990 */
1991 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
1992 }
1993#undef FUDGE
fa1c114f 1994
036cd1ec
BR		 1995 sc->nexttbtt = nexttbtt;
1996
fa1c114f 1997 intval |= AR5K_BEACON_ENA;
fa1c114f 1998 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 1999
2000 /*
2001 * debugging output last in order to preserve the time critical aspect
2002 * of this function
2003 */
2004 if (bc_tsf == -1)
2005 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2006 "reconfigured timers based on HW TSF\n");
2007 else if (bc_tsf == 0)
2008 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2009 "reset HW TSF and timers\n");
2010 else
2011 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2012 "updated timers based on beacon TSF\n");
2013
2014 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2015 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2016 (unsigned long long) bc_tsf,
2017 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2018 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2019 intval & AR5K_BEACON_PERIOD,
2020 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2021 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2022}
2023
036cd1ec
BR		 2024/**
2025 * ath5k_beacon_config - Configure the beacon queues and interrupts
2026 *
2027 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2028 *
036cd1ec 2029 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2030 * interrupts to detect TSF updates only.
fa1c114f 2031 */
cd2c5486 2032void
fa1c114f
JS		 2033ath5k_beacon_config(struct ath5k_softc *sc)
2034{
2035 struct ath5k_hw *ah = sc->ah;
b5f03956 2036 unsigned long flags;
fa1c114f 2037
21800491 2038 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2039 sc->bmisscount = 0;
dc1968e7 2040 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2041
21800491 2042 if (sc->enable_beacon) {
fa1c114f 2043 /*
036cd1ec
BR		 2044 * In IBSS mode we use a self-linked tx descriptor and let the
2045 * hardware send the beacons automatically. We have to load it
fa1c114f 2046 * only once here.
036cd1ec 2047 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2048 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2049 */
2050 ath5k_beaconq_config(sc);
fa1c114f 2051
036cd1ec
BR		 2052 sc->imask |= AR5K_INT_SWBA;
2053
da966bca 2054 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2055 if (ath5k_hw_hasveol(ah))
da966bca 2056 ath5k_beacon_send(sc);
da966bca
JS		 2057 } else
2058 ath5k_beacon_update_timers(sc, -1);
21800491 2059 } else {
14fae2d4 2060 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2061 }
fa1c114f 2062
c6e387a2 2063 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2064 mmiowb();
2065 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2066}
2067
428cbd4f
NK		 2068static void ath5k_tasklet_beacon(unsigned long data)
2069{
2070 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2071
2072 /*
2073 * Software beacon alert--time to send a beacon.
2074 *
2075 * In IBSS mode we use this interrupt just to
2076 * keep track of the next TBTT (target beacon
2077 * transmission time) in order to detect wether
2078 * automatic TSF updates happened.
2079 */
2080 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2081 /* XXX: only if VEOL suppported */
2082 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2083 sc->nexttbtt += sc->bintval;
2084 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2085 "SWBA nexttbtt: %x hw_tu: %x "
2086 "TSF: %llx\n",
2087 sc->nexttbtt,
2088 TSF_TO_TU(tsf),
2089 (unsigned long long) tsf);
2090 } else {
2091 spin_lock(&sc->block);
2092 ath5k_beacon_send(sc);
2093 spin_unlock(&sc->block);
2094 }
2095}
2096
fa1c114f
JS		 2097
2098/********************\
2099* Interrupt handling *
2100\********************/
2101
6a8a3f6b
BR		 2102static void
2103ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2104{
2111ac0d
BR		 2105 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2106 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2107 /* run ANI only when full calibration is not active */
2108 ah->ah_cal_next_ani = jiffies +
2109 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2110 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2111
2112 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2113 ah->ah_cal_next_full = jiffies +
2114 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2115 tasklet_schedule(&ah->ah_sc->calib);
2116 }
2117 /* we could use SWI to generate enough interrupts to meet our
2118 * calibration interval requirements, if necessary:
2119 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2120}
2121
132b1c3e 2122irqreturn_t
fa1c114f
JS		 2123ath5k_intr(int irq, void *dev_id)
2124{
2125 struct ath5k_softc *sc = dev_id;
2126 struct ath5k_hw *ah = sc->ah;
2127 enum ath5k_int status;
2128 unsigned int counter = 1000;
2129
2130 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2131 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2132 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2133 return IRQ_NONE;
2134
2135 do {
fa1c114f
JS		 2136 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2137 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2138 status, sc->imask);
fa1c114f
JS		 2139 if (unlikely(status & AR5K_INT_FATAL)) {
2140 /*
2141 * Fatal errors are unrecoverable.
2142 * Typically these are caused by DMA errors.
2143 */
8d67a031
BR		 2144 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2145 "fatal int, resetting\n");
5faaff74 2146 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2147 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2148 /*
2149 * Receive buffers are full. Either the bus is busy or
2150 * the CPU is not fast enough to process all received
2151 * frames.
2152 * Older chipsets need a reset to come out of this
2153 * condition, but we treat it as RX for newer chips.
2154 * We don't know exactly which versions need a reset -
2155 * this guess is copied from the HAL.
2156 */
2157 sc->stats.rxorn_intr++;
8d67a031
BR		 2158 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2159 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2160 "rx overrun, resetting\n");
5faaff74 2161 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2162 }
87d77c4e
BR		 2163 else
2164 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2165 } else {
2166 if (status & AR5K_INT_SWBA) {
56d2ac76 2167 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2168 }
2169 if (status & AR5K_INT_RXEOL) {
2170 /*
2171 * NB: the hardware should re-read the link when
2172 * RXE bit is written, but it doesn't work at
2173 * least on older hardware revs.
2174 */
b3f194e5 2175 sc->stats.rxeol_intr++;
fa1c114f
JS		 2176 }
2177 if (status & AR5K_INT_TXURN) {
2178 /* bump tx trigger level */
2179 ath5k_hw_update_tx_triglevel(ah, true);
2180 }
4c674c60 2181 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2182 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2183 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2184 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2185 tasklet_schedule(&sc->txtq);
2186 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2187 /* TODO */
fa1c114f
JS		 2188 }
2189 if (status & AR5K_INT_MIB) {
2111ac0d 2190 sc->stats.mib_intr++;
495391d7 2191 ath5k_hw_update_mib_counters(ah);
2111ac0d 2192 ath5k_ani_mib_intr(ah);
fa1c114f 2193 }
e6a3b616 2194 if (status & AR5K_INT_GPIO)
e6a3b616 2195 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2196
fa1c114f 2197 }
4cebb34c
FF		 2198
2199 if (ath5k_get_bus_type(ah) == ATH_AHB)
2200 break;
2201
2516baa6 2202 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2203
2204 if (unlikely(!counter))
2205 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2206
6a8a3f6b 2207 ath5k_intr_calibration_poll(ah);
6e220662 2208
fa1c114f
JS		 2209 return IRQ_HANDLED;
2210}
2211
fa1c114f
JS		 2212/*
2213 * Periodically recalibrate the PHY to account
2214 * for temperature/environment changes.
2215 */
2216static void
6e220662 2217ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2218{
2219 struct ath5k_softc *sc = (void *)data;
2220 struct ath5k_hw *ah = sc->ah;
2221
6e220662 2222 /* Only full calibration for now */
e65e1d77 2223 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2224
fa1c114f 2225 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2226 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2227 sc->curchan->hw_value);
fa1c114f 2228
6f3b414a 2229 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2230 /*
2231 * Rfgain is out of bounds, reset the chip
2232 * to load new gain values.
2233 */
2234 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2235 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2236 }
2237 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2238 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2239 ieee80211_frequency_to_channel(
2240 sc->curchan->center_freq));
fa1c114f 2241
0e8e02dd 2242 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2243 * doesn't.
2244 * TODO: We should stop TX here, so that it doesn't interfere.
2245 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2246 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2247 ah->ah_cal_next_nf = jiffies +
2248 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2249 ath5k_hw_update_noise_floor(ah);
afe86286 2250 }
6e220662 2251
e65e1d77 2252 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2253}
2254
2255
2111ac0d
BR		 2256static void
2257ath5k_tasklet_ani(unsigned long data)
2258{
2259 struct ath5k_softc *sc = (void *)data;
2260 struct ath5k_hw *ah = sc->ah;
2261
2262 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2263 ath5k_ani_calibration(ah);
2264 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2265}
2266
2267
4edd761f
BR		 2268static void
2269ath5k_tx_complete_poll_work(struct work_struct *work)
2270{
2271 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2272 tx_complete_work.work);
2273 struct ath5k_txq *txq;
2274 int i;
2275 bool needreset = false;
2276
599b13ad
BC		 2277 mutex_lock(&sc->lock);
2278
4edd761f
BR		 2279 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2280 if (sc->txqs[i].setup) {
2281 txq = &sc->txqs[i];
2282 spin_lock_bh(&txq->lock);
23413296 2283 if (txq->txq_len > 1) {
4edd761f
BR		 2284 if (txq->txq_poll_mark) {
2285 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2286 "TX queue stuck %d\n",
2287 txq->qnum);
2288 needreset = true;
923e5b3d 2289 txq->txq_stuck++;
4edd761f
BR		 2290 spin_unlock_bh(&txq->lock);
2291 break;
2292 } else {
2293 txq->txq_poll_mark = true;
2294 }
2295 }
2296 spin_unlock_bh(&txq->lock);
2297 }
2298 }
2299
2300 if (needreset) {
2301 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2302 "TX queues stuck, resetting\n");
8aec7af9 2303 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2304 }
2305
599b13ad
BC		 2306 mutex_unlock(&sc->lock);
2307
4edd761f
BR		 2308 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2309 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2310}
2311
2312
8a63facc
BC		 2313/*************************\
2314* Initialization routines *
2315\*************************/
fa1c114f 2316
132b1c3e
FF		 2317int
2318ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2319{
2320 struct ieee80211_hw *hw = sc->hw;
2321 struct ath_common *common;
2322 int ret;
2323 int csz;
2324
2325 /* Initialize driver private data */
2326 SET_IEEE80211_DEV(hw, sc->dev);
2327 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2328 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2329 IEEE80211_HW_SIGNAL_DBM |
2330 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2331
2332 hw->wiphy->interface_modes =
2333 BIT(NL80211_IFTYPE_AP) |
2334 BIT(NL80211_IFTYPE_STATION) |
2335 BIT(NL80211_IFTYPE_ADHOC) |
2336 BIT(NL80211_IFTYPE_MESH_POINT);
2337
3de135db
BR		 2338 /* both antennas can be configured as RX or TX */
2339 hw->wiphy->available_antennas_tx = 0x3;
2340 hw->wiphy->available_antennas_rx = 0x3;
2341
132b1c3e
FF		 2342 hw->extra_tx_headroom = 2;
2343 hw->channel_change_time = 5000;
2344
2345 /*
2346 * Mark the device as detached to avoid processing
2347 * interrupts until setup is complete.
2348 */
2349 __set_bit(ATH_STAT_INVALID, sc->status);
2350
2351 sc->opmode = NL80211_IFTYPE_STATION;
2352 sc->bintval = 1000;
2353 mutex_init(&sc->lock);
2354 spin_lock_init(&sc->rxbuflock);
2355 spin_lock_init(&sc->txbuflock);
2356 spin_lock_init(&sc->block);
2357
2358
2359 /* Setup interrupt handler */
2360 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2361 if (ret) {
2362 ATH5K_ERR(sc, "request_irq failed\n");
2363 goto err;
2364 }
2365
2366 /* If we passed the test, malloc an ath5k_hw struct */
2367 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2368 if (!sc->ah) {
2369 ret = -ENOMEM;
2370 ATH5K_ERR(sc, "out of memory\n");
2371 goto err_irq;
2372 }
2373
2374 sc->ah->ah_sc = sc;
2375 sc->ah->ah_iobase = sc->iobase;
2376 common = ath5k_hw_common(sc->ah);
2377 common->ops = &ath5k_common_ops;
2378 common->bus_ops = bus_ops;
2379 common->ah = sc->ah;
2380 common->hw = hw;
2381 common->priv = sc;
2382
2383 /*
2384 * Cache line size is used to size and align various
2385 * structures used to communicate with the hardware.
2386 */
2387 ath5k_read_cachesize(common, &csz);
2388 common->cachelsz = csz << 2; /* convert to bytes */
2389
2390 spin_lock_init(&common->cc_lock);
2391
2392 /* Initialize device */
2393 ret = ath5k_hw_init(sc);
2394 if (ret)
2395 goto err_free_ah;
2396
2397 /* set up multi-rate retry capabilities */
2398 if (sc->ah->ah_version == AR5K_AR5212) {
2399 hw->max_rates = 4;
76a9f6fd
BR		 2400 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2401 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2402 }
2403
2404 hw->vif_data_size = sizeof(struct ath5k_vif);
2405
2406 /* Finish private driver data initialization */
2407 ret = ath5k_init(hw);
2408 if (ret)
2409 goto err_ah;
2410
2411 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2412 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2413 sc->ah->ah_mac_srev,
2414 sc->ah->ah_phy_revision);
2415
2416 if (!sc->ah->ah_single_chip) {
2417 /* Single chip radio (!RF5111) */
2418 if (sc->ah->ah_radio_5ghz_revision &&
2419 !sc->ah->ah_radio_2ghz_revision) {
2420 /* No 5GHz support -> report 2GHz radio */
2421 if (!test_bit(AR5K_MODE_11A,
2422 sc->ah->ah_capabilities.cap_mode)) {
2423 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2424 ath5k_chip_name(AR5K_VERSION_RAD,
2425 sc->ah->ah_radio_5ghz_revision),
2426 sc->ah->ah_radio_5ghz_revision);
2427 /* No 2GHz support (5110 and some
2428 * 5Ghz only cards) -> report 5Ghz radio */
2429 } else if (!test_bit(AR5K_MODE_11B,
2430 sc->ah->ah_capabilities.cap_mode)) {
2431 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2432 ath5k_chip_name(AR5K_VERSION_RAD,
2433 sc->ah->ah_radio_5ghz_revision),
2434 sc->ah->ah_radio_5ghz_revision);
2435 /* Multiband radio */
2436 } else {
2437 ATH5K_INFO(sc, "RF%s multiband radio found"
2438 " (0x%x)\n",
2439 ath5k_chip_name(AR5K_VERSION_RAD,
2440 sc->ah->ah_radio_5ghz_revision),
2441 sc->ah->ah_radio_5ghz_revision);
2442 }
2443 }
2444 /* Multi chip radio (RF5111 - RF2111) ->
2445 * report both 2GHz/5GHz radios */
2446 else if (sc->ah->ah_radio_5ghz_revision &&
2447 sc->ah->ah_radio_2ghz_revision){
2448 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2449 ath5k_chip_name(AR5K_VERSION_RAD,
2450 sc->ah->ah_radio_5ghz_revision),
2451 sc->ah->ah_radio_5ghz_revision);
2452 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2453 ath5k_chip_name(AR5K_VERSION_RAD,
2454 sc->ah->ah_radio_2ghz_revision),
2455 sc->ah->ah_radio_2ghz_revision);
2456 }
2457 }
2458
2459 ath5k_debug_init_device(sc);
2460
2461 /* ready to process interrupts */
2462 __clear_bit(ATH_STAT_INVALID, sc->status);
2463
2464 return 0;
2465err_ah:
2466 ath5k_hw_deinit(sc->ah);
2467err_free_ah:
2468 kfree(sc->ah);
2469err_irq:
2470 free_irq(sc->irq, sc);
2471err:
2472 return ret;
2473}
2474
fa1c114f 2475static int
8a63facc 2476ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2477{
8a63facc 2478 struct ath5k_hw *ah = sc->ah;
cec8db23 2479
8a63facc
BC		 2480 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2481 test_bit(ATH_STAT_INVALID, sc->status));
2482
2483 /*
2484 * Shutdown the hardware and driver:
2485 * stop output from above
2486 * disable interrupts
2487 * turn off timers
2488 * turn off the radio
2489 * clear transmit machinery
2490 * clear receive machinery
2491 * drain and release tx queues
2492 * reclaim beacon resources
2493 * power down hardware
2494 *
2495 * Note that some of this work is not possible if the
2496 * hardware is gone (invalid).
2497 */
2498 ieee80211_stop_queues(sc->hw);
2499
2500 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2501 ath5k_led_off(sc);
2502 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2503 synchronize_irq(sc->irq);
8a63facc 2504 ath5k_rx_stop(sc);
80dac9ee
NK		 2505 ath5k_hw_dma_stop(ah);
2506 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2507 ath5k_hw_phy_disable(ah);
2508 }
2509
2510 return 0;
cec8db23
BC		 2511}
2512
cd2c5486 2513int
132b1c3e 2514ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2515{
8a63facc
BC		 2516 struct ath5k_hw *ah = sc->ah;
2517 struct ath_common *common = ath5k_hw_common(ah);
2518 int ret, i;
fa1c114f 2519
8a63facc
BC		 2520 mutex_lock(&sc->lock);
2521
2522 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2523
fa1c114f 2524 /*
8a63facc
BC		 2525 * Stop anything previously setup. This is safe
2526 * no matter this is the first time through or not.
fa1c114f 2527 */
8a63facc 2528 ath5k_stop_locked(sc);
fa1c114f 2529
8a63facc
BC		 2530 /*
2531 * The basic interface to setting the hardware in a good
2532 * state is ``reset''. On return the hardware is known to
2533 * be powered up and with interrupts disabled. This must
2534 * be followed by initialization of the appropriate bits
2535 * and then setup of the interrupt mask.
2536 */
2537 sc->curchan = sc->hw->conf.channel;
8a63facc
BC		 2538 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2539 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2540 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2541
8aec7af9 2542 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2543 if (ret)
2544 goto done;
fa1c114f 2545
8a63facc
BC		 2546 ath5k_rfkill_hw_start(ah);
2547
2548 /*
2549 * Reset the key cache since some parts do not reset the
2550 * contents on initial power up or resume from suspend.
2551 */
2552 for (i = 0; i < common->keymax; i++)
2553 ath_hw_keyreset(common, (u16) i);
2554
61cde037
NK		 2555 /* Use higher rates for acks instead of base
2556 * rate */
2557 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2558
2559 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2560 sc->bslot[i] = NULL;
2561
8a63facc
BC		 2562 ret = 0;
2563done:
2564 mmiowb();
2565 mutex_unlock(&sc->lock);
4edd761f
BR		 2566
2567 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2568 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2569
8a63facc
BC		 2570 return ret;
2571}
2572
2573static void stop_tasklets(struct ath5k_softc *sc)
2574{
2575 tasklet_kill(&sc->rxtq);
2576 tasklet_kill(&sc->txtq);
2577 tasklet_kill(&sc->calib);
2578 tasklet_kill(&sc->beacontq);
2579 tasklet_kill(&sc->ani_tasklet);
2580}
2581
2582/*
2583 * Stop the device, grabbing the top-level lock to protect
2584 * against concurrent entry through ath5k_init (which can happen
2585 * if another thread does a system call and the thread doing the
2586 * stop is preempted).
2587 */
cd2c5486 2588int
8a63facc
BC		 2589ath5k_stop_hw(struct ath5k_softc *sc)
2590{
2591 int ret;
2592
2593 mutex_lock(&sc->lock);
2594 ret = ath5k_stop_locked(sc);
2595 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2596 /*
2597 * Don't set the card in full sleep mode!
2598 *
2599 * a) When the device is in this state it must be carefully
2600 * woken up or references to registers in the PCI clock
2601 * domain may freeze the bus (and system). This varies
2602 * by chip and is mostly an issue with newer parts
2603 * (madwifi sources mentioned srev >= 0x78) that go to
2604 * sleep more quickly.
2605 *
2606 * b) On older chips full sleep results a weird behaviour
2607 * during wakeup. I tested various cards with srev < 0x78
2608 * and they don't wake up after module reload, a second
2609 * module reload is needed to bring the card up again.
2610 *
2611 * Until we figure out what's going on don't enable
2612 * full chip reset on any chip (this is what Legacy HAL
2613 * and Sam's HAL do anyway). Instead Perform a full reset
2614 * on the device (same as initial state after attach) and
2615 * leave it idle (keep MAC/BB on warm reset) */
2616 ret = ath5k_hw_on_hold(sc->ah);
2617
2618 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2619 "putting device to sleep\n");
fa1c114f
JS		 2620 }
2621
8a63facc
BC		 2622 mmiowb();
2623 mutex_unlock(&sc->lock);
2624
2625 stop_tasklets(sc);
2626
4edd761f
BR		 2627 cancel_delayed_work_sync(&sc->tx_complete_work);
2628
8a63facc
BC		 2629 ath5k_rfkill_hw_stop(sc->ah);
2630
2631 return ret;
fa1c114f
JS		 2632}
2633
209d889b
BC		 2634/*
2635 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2636 * and change to the given channel.
5faaff74
BC		 2637 *
2638 * This should be called with sc->lock.
209d889b 2639 */
fa1c114f 2640static int
8aec7af9
NK		 2641ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2642 bool skip_pcu)
fa1c114f 2643{
fa1c114f 2644 struct ath5k_hw *ah = sc->ah;
f15a4bb2 2645 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2646 int ret, ani_mode;
fa1c114f
JS		 2647
2648 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2649
450464de 2650 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2651 synchronize_irq(sc->irq);
450464de
BC		 2652 stop_tasklets(sc);
2653
25985edc 2654 /* Save ani mode and disable ANI during
344b54b9
NK		 2655 * reset. If we don't we might get false
2656 * PHY error interrupts. */
2657 ani_mode = ah->ah_sc->ani_state.ani_mode;
2658 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2659
19252ecb
NK		 2660 /* We are going to empty hw queues
2661 * so we should also free any remaining
2662 * tx buffers */
2663 ath5k_drain_tx_buffs(sc);
930a7622 2664 if (chan)
209d889b 2665 sc->curchan = chan;
8aec7af9
NK		 2666 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2667 skip_pcu);
d7dc1003 2668 if (ret) {
fa1c114f
JS		 2669 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2670 goto err;
2671 }
d7dc1003 2672
fa1c114f 2673 ret = ath5k_rx_start(sc);
d7dc1003 2674 if (ret) {
fa1c114f
JS		 2675 ATH5K_ERR(sc, "can't start recv logic\n");
2676 goto err;
2677 }
d7dc1003 2678
344b54b9 2679 ath5k_ani_init(ah, ani_mode);
2111ac0d 2680
ac559526
BR		 2681 ah->ah_cal_next_full = jiffies;
2682 ah->ah_cal_next_ani = jiffies;
afe86286 2683 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2684 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2685
f15a4bb2
BR		 2686 /* clear survey data and cycle counters */
2687 memset(&sc->survey, 0, sizeof(sc->survey));
bb007554 2688 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2689 ath_hw_cycle_counters_update(common);
2690 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2691 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2692 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2693
fa1c114f 2694 /*
d7dc1003
JS		 2695 * Change channels and update the h/w rate map if we're switching;
2696 * e.g. 11a to 11b/g.
2697 *
2698 * We may be doing a reset in response to an ioctl that changes the
2699 * channel so update any state that might change as a result.
fa1c114f
JS		 2700 *
2701 * XXX needed?
2702 */
2703/* ath5k_chan_change(sc, c); */
fa1c114f 2704
d7dc1003
JS		 2705 ath5k_beacon_config(sc);
2706 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2707
397f385b
BR		 2708 ieee80211_wake_queues(sc->hw);
2709
fa1c114f
JS		 2710 return 0;
2711err:
2712 return ret;
2713}
2714
5faaff74
BC		 2715static void ath5k_reset_work(struct work_struct *work)
2716{
2717 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2718 reset_work);
2719
2720 mutex_lock(&sc->lock);
8aec7af9 2721 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2722 mutex_unlock(&sc->lock);
2723}
2724
8a63facc 2725static int
132b1c3e 2726ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2727{
132b1c3e 2728
fa1c114f 2729 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2730 struct ath5k_hw *ah = sc->ah;
2731 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2732 struct ath5k_txq *txq;
8a63facc 2733 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2734 int ret;
2735
fa1c114f 2736
8a63facc
BC		 2737 /*
2738 * Check if the MAC has multi-rate retry support.
2739 * We do this by trying to setup a fake extended
2740 * descriptor. MACs that don't have support will
2741 * return false w/o doing anything. MACs that do
2742 * support it will return true w/o doing anything.
2743 */
2744 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2745
8a63facc
BC		 2746 if (ret < 0)
2747 goto err;
2748 if (ret > 0)
2749 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2750
8a63facc
BC		 2751 /*
2752 * Collect the channel list. The 802.11 layer
2753 * is resposible for filtering this list based
2754 * on settings like the phy mode and regulatory
2755 * domain restrictions.
2756 */
2757 ret = ath5k_setup_bands(hw);
2758 if (ret) {
2759 ATH5K_ERR(sc, "can't get channels\n");
2760 goto err;
2761 }
67d2e2df 2762
8a63facc
BC		 2763 /*
2764 * Allocate tx+rx descriptors and populate the lists.
2765 */
aeae4ac9 2766 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2767 if (ret) {
2768 ATH5K_ERR(sc, "can't allocate descriptors\n");
2769 goto err;
2770 }
fa1c114f 2771
8a63facc
BC		 2772 /*
2773 * Allocate hardware transmit queues: one queue for
2774 * beacon frames and one data queue for each QoS
2775 * priority. Note that hw functions handle resetting
2776 * these queues at the needed time.
2777 */
2778 ret = ath5k_beaconq_setup(ah);
2779 if (ret < 0) {
2780 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2781 goto err_desc;
2782 }
2783 sc->bhalq = ret;
2784 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2785 if (IS_ERR(sc->cabq)) {
2786 ATH5K_ERR(sc, "can't setup cab queue\n");
2787 ret = PTR_ERR(sc->cabq);
2788 goto err_bhal;
2789 }
fa1c114f 2790
22d8d9f8
BR		 2791 /* 5211 and 5212 usually support 10 queues but we better rely on the
2792 * capability information */
2793 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2794 /* This order matches mac80211's queue priority, so we can
2795 * directly use the mac80211 queue number without any mapping */
2796 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2797 if (IS_ERR(txq)) {
2798 ATH5K_ERR(sc, "can't setup xmit queue\n");
2799 ret = PTR_ERR(txq);
2800 goto err_queues;
2801 }
2802 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2803 if (IS_ERR(txq)) {
2804 ATH5K_ERR(sc, "can't setup xmit queue\n");
2805 ret = PTR_ERR(txq);
2806 goto err_queues;
2807 }
2808 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2809 if (IS_ERR(txq)) {
2810 ATH5K_ERR(sc, "can't setup xmit queue\n");
2811 ret = PTR_ERR(txq);
2812 goto err_queues;
2813 }
2814 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2815 if (IS_ERR(txq)) {
2816 ATH5K_ERR(sc, "can't setup xmit queue\n");
2817 ret = PTR_ERR(txq);
2818 goto err_queues;
2819 }
2820 hw->queues = 4;
2821 } else {
2822 /* older hardware (5210) can only support one data queue */
2823 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2824 if (IS_ERR(txq)) {
2825 ATH5K_ERR(sc, "can't setup xmit queue\n");
2826 ret = PTR_ERR(txq);
2827 goto err_queues;
2828 }
2829 hw->queues = 1;
2830 }
fa1c114f 2831
8a63facc
BC		 2832 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2833 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2834 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2835 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2836 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2837
8a63facc 2838 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2839 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2840
8a63facc
BC		 2841 ret = ath5k_eeprom_read_mac(ah, mac);
2842 if (ret) {
aeae4ac9 2843 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2844 goto err_queues;
e30eb4ab 2845 }
2bed03eb 2846
8a63facc 2847 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2848 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2849 /* All MAC address bits matter for ACKs */
62c58fb4 2850 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2851
2852 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2853 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2854 if (ret) {
2855 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2856 goto err_queues;
2857 }
2858
2859 ret = ieee80211_register_hw(hw);
2860 if (ret) {
2861 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2862 goto err_queues;
2863 }
2864
2865 if (!ath_is_world_regd(regulatory))
2866 regulatory_hint(hw->wiphy, regulatory->alpha2);
2867
2868 ath5k_init_leds(sc);
2869
2870 ath5k_sysfs_register(sc);
2871
2872 return 0;
2873err_queues:
2874 ath5k_txq_release(sc);
2875err_bhal:
2876 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2877err_desc:
aeae4ac9 2878 ath5k_desc_free(sc);
8a63facc
BC		 2879err:
2880 return ret;
2881}
2882
132b1c3e
FF		 2883void
2884ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2885{
132b1c3e 2886 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2887
2888 /*
2889 * NB: the order of these is important:
2890 * o call the 802.11 layer before detaching ath5k_hw to
2891 * ensure callbacks into the driver to delete global
2892 * key cache entries can be handled
2893 * o reclaim the tx queue data structures after calling
2894 * the 802.11 layer as we'll get called back to reclaim
2895 * node state and potentially want to use them
2896 * o to cleanup the tx queues the hal is called, so detach
2897 * it last
2898 * XXX: ??? detach ath5k_hw ???
2899 * Other than that, it's straightforward...
2900 */
132b1c3e 2901 ath5k_debug_finish_device(sc);
8a63facc 2902 ieee80211_unregister_hw(hw);
aeae4ac9 2903 ath5k_desc_free(sc);
8a63facc
BC		 2904 ath5k_txq_release(sc);
2905 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2906 ath5k_unregister_leds(sc);
2907
2908 ath5k_sysfs_unregister(sc);
2909 /*
2910 * NB: can't reclaim these until after ieee80211_ifdetach
2911 * returns because we'll get called back to reclaim node
2912 * state and potentially want to use them.
2913 */
132b1c3e
FF		 2914 ath5k_hw_deinit(sc->ah);
2915 free_irq(sc->irq, sc);
8a63facc
BC		 2916}
2917
cd2c5486
BR		 2918bool
2919ath_any_vif_assoc(struct ath5k_softc *sc)
b1ae1edf 2920{
e4b0b32a 2921 struct ath5k_vif_iter_data iter_data;
b1ae1edf
BG		 2922 iter_data.hw_macaddr = NULL;
2923 iter_data.any_assoc = false;
2924 iter_data.need_set_hw_addr = false;
2925 iter_data.found_active = true;
2926
e4b0b32a 2927 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
b1ae1edf
BG		 2928 &iter_data);
2929 return iter_data.any_assoc;
2930}
2931
cd2c5486 2932void
8a63facc
BC		 2933set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2934{
2935 struct ath5k_softc *sc = hw->priv;
2936 struct ath5k_hw *ah = sc->ah;
2937 u32 rfilt;
2938 rfilt = ath5k_hw_get_rx_filter(ah);
2939 if (enable)
2940 rfilt |= AR5K_RX_FILTER_BEACON;
2941 else
2942 rfilt &= ~AR5K_RX_FILTER_BEACON;
2943 ath5k_hw_set_rx_filter(ah, rfilt);
2944 sc->filter_flags = rfilt;
2945}
Linux kernel - Deliverables
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