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Merge branches 'pm-opp-fixes', 'pm-cpufreq-fixes' and 'pm-cpuidle-fixes'
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar5008_phy.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
cfe8cba9 17#include "hw.h"
8fe65368
LR		 18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
a043dfb9 21#include "ar5008_initvals.h"
e16393bb 22
e36b27af
LR		 23/* All code below is for AR5008, AR9001, AR9002 */
24
c08267dc
LB		 25#define AR5008_OFDM_RATES 8
26#define AR5008_HT_SS_RATES 8
27#define AR5008_HT_DS_RATES 8
28
29#define AR5008_HT20_SHIFT 16
30#define AR5008_HT40_SHIFT 24
31
32#define AR5008_11NA_OFDM_SHIFT 0
33#define AR5008_11NA_HT_SS_SHIFT 8
34#define AR5008_11NA_HT_DS_SHIFT 16
35
36#define AR5008_11NG_OFDM_SHIFT 4
37#define AR5008_11NG_HT_SS_SHIFT 12
38#define AR5008_11NG_HT_DS_SHIFT 20
39
e36b27af
LR		 40static const int firstep_table[] =
41/* level: 0 1 2 3 4 5 6 7 8 */
42 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
43
e36b27af
LR		 44/*
45 * register values to turn OFDM weak signal detection OFF
46 */
47static const int m1ThreshLow_off = 127;
48static const int m2ThreshLow_off = 127;
49static const int m1Thresh_off = 127;
50static const int m2Thresh_off = 127;
51static const int m2CountThr_off = 31;
52static const int m2CountThrLow_off = 63;
53static const int m1ThreshLowExt_off = 127;
54static const int m2ThreshLowExt_off = 127;
55static const int m1ThreshExt_off = 127;
56static const int m2ThreshExt_off = 127;
57
a043dfb9
FF		 58static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0);
59static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1);
60static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2);
61static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3);
62static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7);
e16393bb 63
a043dfb9 64static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt)
a9b6b256 65{
a043dfb9
FF		 66 struct ar5416IniArray *array = &ah->iniBank6;
67 u32 *data = ah->analogBank6Data;
a9b6b256
FF		 68 int r;
69
70 ENABLE_REGWRITE_BUFFER(ah);
71
72 for (r = 0; r < array->ia_rows; r++) {
73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
74 DO_DELAY(*writecnt);
75 }
76
77 REGWRITE_BUFFER_FLUSH(ah);
78}
79
ddcd4c08 80/**
8fe65368 81 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
ddcd4c08
LR		 82 * @rfbuf:
83 * @reg32:
84 * @numBits:
85 * @firstBit:
86 * @column:
87 *
88 * Performs analog "swizzling" of parameters into their location.
89 * Used on external AR2133/AR5133 radios.
90 */
8fe65368
LR		 91static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
92 u32 numBits, u32 firstBit,
93 u32 column)
ddcd4c08
LR		 94{
95 u32 tmp32, mask, arrayEntry, lastBit;
96 int32_t bitPosition, bitsLeft;
97
98 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
99 arrayEntry = (firstBit - 1) / 8;
100 bitPosition = (firstBit - 1) % 8;
101 bitsLeft = numBits;
102 while (bitsLeft > 0) {
103 lastBit = (bitPosition + bitsLeft > 8) ?
104 8 : bitPosition + bitsLeft;
105 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
106 (column * 8);
107 rfBuf[arrayEntry] &= ~mask;
108 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
109 (column * 8)) & mask;
110 bitsLeft -= 8 - bitPosition;
111 tmp32 = tmp32 >> (8 - bitPosition);
112 bitPosition = 0;
113 arrayEntry++;
114 }
115}
116
a7765828
LR		 117/*
118 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
119 * rf_pwd_icsyndiv.
120 *
121 * Theoretical Rules:
122 * if 2 GHz band
123 * if forceBiasAuto
124 * if synth_freq < 2412
125 * bias = 0
126 * else if 2412 <= synth_freq <= 2422
127 * bias = 1
128 * else // synth_freq > 2422
129 * bias = 2
130 * else if forceBias > 0
131 * bias = forceBias & 7
132 * else
133 * no change, use value from ini file
134 * else
135 * no change, invalid band
136 *
137 * 1st Mod:
138 * 2422 also uses value of 2
139 * <approved>
140 *
141 * 2nd Mod:
142 * Less than 2412 uses value of 0, 2412 and above uses value of 2
143 */
8fe65368 144static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
a7765828
LR		 145{
146 struct ath_common *common = ath9k_hw_common(ah);
147 u32 tmp_reg;
148 int reg_writes = 0;
149 u32 new_bias = 0;
150
8fe65368 151 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
a7765828 152 return;
a7765828 153
7a37081e 154 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
a7765828
LR		 155
156 if (synth_freq < 2412)
157 new_bias = 0;
158 else if (synth_freq < 2422)
159 new_bias = 1;
160 else
161 new_bias = 2;
162
163 /* pre-reverse this field */
164 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
165
d2182b69 166 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
226afe68 167 new_bias, synth_freq);
a7765828
LR		 168
169 /* swizzle rf_pwd_icsyndiv */
8fe65368 170 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
a7765828
LR		 171
172 /* write Bank 6 with new params */
a043dfb9 173 ar5008_write_bank6(ah, &reg_writes);
a7765828
LR		 174}
175
e16393bb 176/**
8fe65368 177 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
25985edc 178 * @ah: atheros hardware structure
e16393bb
LR		 179 * @chan:
180 *
181 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
182 * the channel value. Assumes writes enabled to analog bus and bank6 register
183 * cache in ah->analogBank6Data.
184 */
8fe65368 185static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
e16393bb
LR		 186{
187 struct ath_common *common = ath9k_hw_common(ah);
188 u32 channelSel = 0;
189 u32 bModeSynth = 0;
190 u32 aModeRefSel = 0;
191 u32 reg32 = 0;
192 u16 freq;
193 struct chan_centers centers;
194
195 ath9k_hw_get_channel_centers(ah, chan, &centers);
196 freq = centers.synth_center;
197
198 if (freq < 4800) {
199 u32 txctl;
200
201 if (((freq - 2192) % 5) == 0) {
202 channelSel = ((freq - 672) * 2 - 3040) / 10;
203 bModeSynth = 0;
204 } else if (((freq - 2224) % 5) == 0) {
205 channelSel = ((freq - 704) * 2 - 3040) / 10;
206 bModeSynth = 1;
207 } else {
3800276a 208 ath_err(common, "Invalid channel %u MHz\n", freq);
e16393bb
LR		 209 return -EINVAL;
210 }
211
212 channelSel = (channelSel << 2) & 0xff;
213 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
214
215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
216 if (freq == 2484) {
217
218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
219 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
220 } else {
221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
222 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
223 }
224
225 } else if ((freq % 20) == 0 && freq >= 5120) {
226 channelSel =
227 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
228 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
229 } else if ((freq % 10) == 0) {
230 channelSel =
231 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
232 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
233 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
234 else
235 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
236 } else if ((freq % 5) == 0) {
237 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
238 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
239 } else {
3800276a 240 ath_err(common, "Invalid channel %u MHz\n", freq);
e16393bb
LR		 241 return -EINVAL;
242 }
243
8fe65368 244 ar5008_hw_force_bias(ah, freq);
a7765828 245
e16393bb
LR		 246 reg32 =
247 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
248 (1 << 5) | 0x1;
249
250 REG_WRITE(ah, AR_PHY(0x37), reg32);
251
252 ah->curchan = chan;
e16393bb
LR		 253
254 return 0;
255}
256
f911085f
OR		 257void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
258 struct ath9k_channel *chan, int bin)
e16393bb 259{
f911085f 260 int cur_bin;
e16393bb 261 int upper, lower, cur_vit_mask;
e16393bb 262 int i;
f911085f
OR		 263 int8_t mask_m[123];
264 int8_t mask_p[123];
265 int8_t mask_amt;
266 int tmp_mask;
267 static const int pilot_mask_reg[4] = {
07b2fa5a
JP		 268 AR_PHY_TIMING7, AR_PHY_TIMING8,
269 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
e16393bb 270 };
f911085f 271 static const int chan_mask_reg[4] = {
07b2fa5a
JP		 272 AR_PHY_TIMING9, AR_PHY_TIMING10,
273 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
e16393bb 274 };
f911085f 275 static const int inc[4] = { 0, 100, 0, 0 };
e16393bb
LR		 276
277 cur_bin = -6000;
278 upper = bin + 100;
279 lower = bin - 100;
280
281 for (i = 0; i < 4; i++) {
282 int pilot_mask = 0;
283 int chan_mask = 0;
284 int bp = 0;
f911085f 285
e16393bb
LR		 286 for (bp = 0; bp < 30; bp++) {
287 if ((cur_bin > lower) && (cur_bin < upper)) {
288 pilot_mask = pilot_mask | 0x1 << bp;
289 chan_mask = chan_mask | 0x1 << bp;
290 }
291 cur_bin += 100;
292 }
293 cur_bin += inc[i];
294 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
295 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
296 }
297
298 cur_vit_mask = 6100;
299 upper = bin + 120;
300 lower = bin - 120;
301
302 for (i = 0; i < 123; i++) {
303 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
e16393bb
LR		 304 /* workaround for gcc bug #37014 */
305 volatile int tmp_v = abs(cur_vit_mask - bin);
306
307 if (tmp_v < 75)
308 mask_amt = 1;
309 else
310 mask_amt = 0;
311 if (cur_vit_mask < 0)
312 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
313 else
314 mask_p[cur_vit_mask / 100] = mask_amt;
315 }
316 cur_vit_mask -= 100;
317 }
318
319 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
320 | (mask_m[48] << 26) | (mask_m[49] << 24)
321 | (mask_m[50] << 22) | (mask_m[51] << 20)
322 | (mask_m[52] << 18) | (mask_m[53] << 16)
323 | (mask_m[54] << 14) | (mask_m[55] << 12)
324 | (mask_m[56] << 10) | (mask_m[57] << 8)
325 | (mask_m[58] << 6) | (mask_m[59] << 4)
326 | (mask_m[60] << 2) | (mask_m[61] << 0);
327 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
328 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
329
330 tmp_mask = (mask_m[31] << 28)
331 | (mask_m[32] << 26) | (mask_m[33] << 24)
332 | (mask_m[34] << 22) | (mask_m[35] << 20)
333 | (mask_m[36] << 18) | (mask_m[37] << 16)
334 | (mask_m[48] << 14) | (mask_m[39] << 12)
335 | (mask_m[40] << 10) | (mask_m[41] << 8)
336 | (mask_m[42] << 6) | (mask_m[43] << 4)
337 | (mask_m[44] << 2) | (mask_m[45] << 0);
338 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
339 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
340
341 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
342 | (mask_m[18] << 26) | (mask_m[18] << 24)
343 | (mask_m[20] << 22) | (mask_m[20] << 20)
344 | (mask_m[22] << 18) | (mask_m[22] << 16)
345 | (mask_m[24] << 14) | (mask_m[24] << 12)
346 | (mask_m[25] << 10) | (mask_m[26] << 8)
347 | (mask_m[27] << 6) | (mask_m[28] << 4)
348 | (mask_m[29] << 2) | (mask_m[30] << 0);
349 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
350 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
351
352 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
353 | (mask_m[2] << 26) | (mask_m[3] << 24)
354 | (mask_m[4] << 22) | (mask_m[5] << 20)
355 | (mask_m[6] << 18) | (mask_m[7] << 16)
356 | (mask_m[8] << 14) | (mask_m[9] << 12)
357 | (mask_m[10] << 10) | (mask_m[11] << 8)
358 | (mask_m[12] << 6) | (mask_m[13] << 4)
359 | (mask_m[14] << 2) | (mask_m[15] << 0);
360 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
361 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
362
363 tmp_mask = (mask_p[15] << 28)
364 | (mask_p[14] << 26) | (mask_p[13] << 24)
365 | (mask_p[12] << 22) | (mask_p[11] << 20)
366 | (mask_p[10] << 18) | (mask_p[9] << 16)
367 | (mask_p[8] << 14) | (mask_p[7] << 12)
368 | (mask_p[6] << 10) | (mask_p[5] << 8)
369 | (mask_p[4] << 6) | (mask_p[3] << 4)
370 | (mask_p[2] << 2) | (mask_p[1] << 0);
371 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
372 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
373
374 tmp_mask = (mask_p[30] << 28)
375 | (mask_p[29] << 26) | (mask_p[28] << 24)
376 | (mask_p[27] << 22) | (mask_p[26] << 20)
377 | (mask_p[25] << 18) | (mask_p[24] << 16)
378 | (mask_p[23] << 14) | (mask_p[22] << 12)
379 | (mask_p[21] << 10) | (mask_p[20] << 8)
380 | (mask_p[19] << 6) | (mask_p[18] << 4)
381 | (mask_p[17] << 2) | (mask_p[16] << 0);
382 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
383 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
384
385 tmp_mask = (mask_p[45] << 28)
386 | (mask_p[44] << 26) | (mask_p[43] << 24)
387 | (mask_p[42] << 22) | (mask_p[41] << 20)
388 | (mask_p[40] << 18) | (mask_p[39] << 16)
389 | (mask_p[38] << 14) | (mask_p[37] << 12)
390 | (mask_p[36] << 10) | (mask_p[35] << 8)
391 | (mask_p[34] << 6) | (mask_p[33] << 4)
392 | (mask_p[32] << 2) | (mask_p[31] << 0);
393 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
394 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
395
396 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
397 | (mask_p[59] << 26) | (mask_p[58] << 24)
398 | (mask_p[57] << 22) | (mask_p[56] << 20)
399 | (mask_p[55] << 18) | (mask_p[54] << 16)
400 | (mask_p[53] << 14) | (mask_p[52] << 12)
401 | (mask_p[51] << 10) | (mask_p[50] << 8)
402 | (mask_p[49] << 6) | (mask_p[48] << 4)
403 | (mask_p[47] << 2) | (mask_p[46] << 0);
404 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
405 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
406}
407
f911085f
OR		 408/**
409 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
410 * @ah: atheros hardware structure
411 * @chan:
412 *
413 * For non single-chip solutions. Converts to baseband spur frequency given the
414 * input channel frequency and compute register settings below.
415 */
416static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
417 struct ath9k_channel *chan)
418{
419 int bb_spur = AR_NO_SPUR;
420 int bin;
421 int spur_freq_sd;
422 int spur_delta_phase;
423 int denominator;
424 int tmp, new;
425 int i;
426
427 int8_t mask_m[123];
428 int8_t mask_p[123];
429 int cur_bb_spur;
430 bool is2GHz = IS_CHAN_2GHZ(chan);
431
432 memset(&mask_m, 0, sizeof(int8_t) * 123);
433 memset(&mask_p, 0, sizeof(int8_t) * 123);
434
435 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
436 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
437 if (AR_NO_SPUR == cur_bb_spur)
438 break;
439 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
440 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
441 bb_spur = cur_bb_spur;
442 break;
443 }
444 }
445
446 if (AR_NO_SPUR == bb_spur)
447 return;
448
449 bin = bb_spur * 32;
450
451 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
452 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
453 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
454 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
455 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
456
457 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
458
459 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
460 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
461 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
462 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
463 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
464 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
465
466 spur_delta_phase = ((bb_spur * 524288) / 100) &
467 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
468
469 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
470 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
471
472 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
473 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
474 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
475 REG_WRITE(ah, AR_PHY_TIMING11, new);
476
477 ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
478}
479
e16393bb 480/**
8fe65368 481 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
e16393bb
LR		 482 * @ah: atheros hardware structure
483 *
484 * Only required for older devices with external AR2133/AR5133 radios.
485 */
8fe65368 486static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
e16393bb 487{
a043dfb9 488 int size = ah->iniBank6.ia_rows * sizeof(u32);
e16393bb 489
c1b976d2
FF		 490 if (AR_SREV_9280_20_OR_LATER(ah))
491 return 0;
e16393bb 492
a043dfb9
FF		 493 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
494 if (!ah->analogBank6Data)
495 return -ENOMEM;
e16393bb
LR		 496
497 return 0;
e16393bb
LR		 498}
499
500
131d1d03 501/* *
8fe65368 502 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
131d1d03
LR		 503 * @ah: atheros hardware structure
504 * @chan:
505 * @modesIndex:
506 *
507 * Used for the external AR2133/AR5133 radios.
508 *
509 * Reads the EEPROM header info from the device structure and programs
510 * all rf registers. This routine requires access to the analog
511 * rf device. This is not required for single-chip devices.
512 */
8fe65368
LR		 513static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
514 struct ath9k_channel *chan,
515 u16 modesIndex)
f078f209 516{
f078f209
LR		 517 u32 eepMinorRev;
518 u32 ob5GHz = 0, db5GHz = 0;
519 u32 ob2GHz = 0, db2GHz = 0;
520 int regWrites = 0;
37c62fec 521 int i;
f078f209 522
131d1d03
LR		 523 /*
524 * Software does not need to program bank data
525 * for single chip devices, that is AR9280 or anything
526 * after that.
527 */
7a37081e 528 if (AR_SREV_9280_20_OR_LATER(ah))
f078f209
LR		 529 return true;
530
131d1d03 531 /* Setup rf parameters */
f74df6fb 532 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
f078f209 533
37c62fec
FF		 534 for (i = 0; i < ah->iniBank6.ia_rows; i++)
535 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
f078f209 536
131d1d03 537 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
f078f209
LR		 538 if (eepMinorRev >= 2) {
539 if (IS_CHAN_2GHZ(chan)) {
f74df6fb
S		 540 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
541 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
8fe65368
LR		 542 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
543 ob2GHz, 3, 197, 0);
544 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
545 db2GHz, 3, 194, 0);
f078f209 546 } else {
f74df6fb
S		 547 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
548 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
8fe65368
LR		 549 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
550 ob5GHz, 3, 203, 0);
551 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
552 db5GHz, 3, 200, 0);
f078f209
LR		 553 }
554 }
555
131d1d03 556 /* Write Analog registers */
a043dfb9
FF		 557 REG_WRITE_ARRAY(&bank0, 1, regWrites);
558 REG_WRITE_ARRAY(&bank1, 1, regWrites);
559 REG_WRITE_ARRAY(&bank2, 1, regWrites);
560 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites);
561 ar5008_write_bank6(ah, &regWrites);
562 REG_WRITE_ARRAY(&bank7, 1, regWrites);
f078f209
LR		 563
564 return true;
565}
8fe65368
LR		 566
567static void ar5008_hw_init_bb(struct ath_hw *ah,
568 struct ath9k_channel *chan)
569{
570 u32 synthDelay;
571
572 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
7d865c70 573
8fe65368
LR		 574 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
575
7c5adc8d 576 ath9k_hw_synth_delay(ah, chan, synthDelay);
8fe65368
LR		 577}
578
579static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
580{
581 int rx_chainmask, tx_chainmask;
582
583 rx_chainmask = ah->rxchainmask;
584 tx_chainmask = ah->txchainmask;
585
7d0d0df0 586
8fe65368
LR		 587 switch (rx_chainmask) {
588 case 0x5:
589 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
590 AR_PHY_SWAP_ALT_CHAIN);
591 case 0x3:
592 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
593 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
594 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
595 break;
596 }
597 case 0x1:
598 case 0x2:
599 case 0x7:
435c1610 600 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 601 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
602 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
603 break;
604 default:
435c1610 605 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 606 break;
607 }
608
609 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
7d0d0df0
S		 610
611 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 612
8fe65368
LR		 613 if (tx_chainmask == 0x5) {
614 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
615 AR_PHY_SWAP_ALT_CHAIN);
616 }
617 if (AR_SREV_9100(ah))
618 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
619 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
620}
621
622static void ar5008_hw_override_ini(struct ath_hw *ah,
623 struct ath9k_channel *chan)
624{
625 u32 val;
626
627 /*
628 * Set the RX_ABORT and RX_DIS and clear if off only after
629 * RXE is set for MAC. This prevents frames with corrupted
630 * descriptor status.
631 */
632 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
633
7a37081e 634 if (AR_SREV_9280_20_OR_LATER(ah)) {
64b6f46f
SM		 635 /*
636 * For AR9280 and above, there is a new feature that allows
637 * Multicast search based on both MAC Address and Key ID.
638 * By default, this feature is enabled. But since the driver
639 * is not using this feature, we switch it off; otherwise
640 * multicast search based on MAC addr only will fail.
641 */
642 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
643 (~AR_ADHOC_MCAST_KEYID_ENABLE);
8fe65368
LR		 644
645 if (!AR_SREV_9271(ah))
646 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
647
a42acef0 648 if (AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 649 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
650
9ef48932
SM		 651 val |= AR_PCU_MISC_MODE2_CFP_IGNORE;
652
8fe65368
LR		 653 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
654 }
655
1b8714f7 656 if (AR_SREV_9280_20_OR_LATER(ah))
8fe65368
LR		 657 return;
658 /*
659 * Disable BB clock gating
660 * Necessary to avoid issues on AR5416 2.0
661 */
662 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
663
664 /*
665 * Disable RIFS search on some chips to avoid baseband
666 * hang issues.
667 */
668 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
669 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
670 val &= ~AR_PHY_RIFS_INIT_DELAY;
671 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
672 }
673}
674
675static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
676 struct ath9k_channel *chan)
677{
678 u32 phymode;
679 u32 enableDacFifo = 0;
680
e17f83ea 681 if (AR_SREV_9285_12_OR_LATER(ah))
8fe65368
LR		 682 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
683 AR_PHY_FC_ENABLE_DAC_FIFO);
684
685 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
686 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
687
688 if (IS_CHAN_HT40(chan)) {
689 phymode |= AR_PHY_FC_DYN2040_EN;
690
8896934c 691 if (IS_CHAN_HT40PLUS(chan))
8fe65368
LR		 692 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
693
694 }
3df5dd90 695 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 696 REG_WRITE(ah, AR_PHY_TURBO, phymode);
697
3df5dd90
OR		 698 /* This function do only REG_WRITE, so
699 * we can include it to REGWRITE_BUFFER. */
e4744ec7 700 ath9k_hw_set11nmac2040(ah, chan);
8fe65368
LR		 701
702 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
703 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
7d0d0df0
S		 704
705 REGWRITE_BUFFER_FLUSH(ah);
8fe65368
LR		 706}
707
708
709static int ar5008_hw_process_ini(struct ath_hw *ah,
710 struct ath9k_channel *chan)
711{
e7fc6338 712 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 713 int i, regWrites = 0;
8fe65368
LR		 714 u32 modesIndex, freqIndex;
715
8896934c 716 if (IS_CHAN_5GHZ(chan)) {
8fe65368 717 freqIndex = 1;
8896934c
FF		 718 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
719 } else {
8fe65368 720 freqIndex = 2;
8896934c 721 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
8fe65368
LR		 722 }
723
8fe65368
LR		 724 /*
725 * Set correct baseband to analog shift setting to
726 * access analog chips.
727 */
728 REG_WRITE(ah, AR_PHY(0), 0x00000007);
729
730 /* Write ADDAC shifts */
731 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
d7084da0
FF		 732 if (ah->eep_ops->set_addac)
733 ah->eep_ops->set_addac(ah, chan);
8fe65368 734
9bbb8168 735 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
8fe65368
LR		 736 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
737
7d0d0df0
S		 738 ENABLE_REGWRITE_BUFFER(ah);
739
8fe65368
LR		 740 for (i = 0; i < ah->iniModes.ia_rows; i++) {
741 u32 reg = INI_RA(&ah->iniModes, i, 0);
742 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
743
744 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
745 val &= ~AR_AN_TOP2_PWDCLKIND;
746
747 REG_WRITE(ah, reg, val);
748
749 if (reg >= 0x7800 && reg < 0x78a0
e7fc6338
RM		 750 && ah->config.analog_shiftreg
751 && (common->bus_ops->ath_bus_type != ATH_USB)) {
8fe65368
LR		 752 udelay(100);
753 }
754
755 DO_DELAY(regWrites);
756 }
757
7d0d0df0 758 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 759
a42acef0 760 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 761 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
762
763 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
a42acef0 764 AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 765 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
766
c7effd35
FF		 767 if (AR_SREV_9271_10(ah)) {
768 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA);
769 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa);
770 }
8fe65368 771
7d0d0df0
S		 772 ENABLE_REGWRITE_BUFFER(ah);
773
8fe65368
LR		 774 /* Write common array parameters */
775 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
776 u32 reg = INI_RA(&ah->iniCommon, i, 0);
777 u32 val = INI_RA(&ah->iniCommon, i, 1);
778
779 REG_WRITE(ah, reg, val);
780
781 if (reg >= 0x7800 && reg < 0x78a0
e7fc6338
RM		 782 && ah->config.analog_shiftreg
783 && (common->bus_ops->ath_bus_type != ATH_USB)) {
8fe65368
LR		 784 udelay(100);
785 }
786
787 DO_DELAY(regWrites);
788 }
789
7d0d0df0 790 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 791
8fe65368
LR		 792 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
793
c7d36f9f
FF		 794 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
795 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,
8fe65368 796 regWrites);
8fe65368
LR		 797
798 ar5008_hw_override_ini(ah, chan);
799 ar5008_hw_set_channel_regs(ah, chan);
800 ar5008_hw_init_chain_masks(ah);
801 ath9k_olc_init(ah);
64ea57d0 802 ath9k_hw_apply_txpower(ah, chan, false);
8fe65368
LR		 803
804 /* Write analog registers */
805 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
3800276a 806 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
8fe65368
LR		 807 return -EIO;
808 }
809
810 return 0;
811}
812
813static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
814{
815 u32 rfMode = 0;
816
817 if (chan == NULL)
818 return;
819
1a5e6326
FF		 820 if (IS_CHAN_2GHZ(chan))
821 rfMode |= AR_PHY_MODE_DYNAMIC;
822 else
823 rfMode |= AR_PHY_MODE_OFDM;
8fe65368 824
7a37081e 825 if (!AR_SREV_9280_20_OR_LATER(ah))
8fe65368
LR		 826 rfMode |= (IS_CHAN_5GHZ(chan)) ?
827 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
828
6b42e8d0 829 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
8fe65368
LR		 830 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
831
832 REG_WRITE(ah, AR_PHY_MODE, rfMode);
833}
834
835static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
836{
837 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
838}
839
840static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
841 struct ath9k_channel *chan)
842{
843 u32 coef_scaled, ds_coef_exp, ds_coef_man;
844 u32 clockMhzScaled = 0x64000000;
845 struct chan_centers centers;
846
847 if (IS_CHAN_HALF_RATE(chan))
848 clockMhzScaled = clockMhzScaled >> 1;
849 else if (IS_CHAN_QUARTER_RATE(chan))
850 clockMhzScaled = clockMhzScaled >> 2;
851
852 ath9k_hw_get_channel_centers(ah, chan, &centers);
853 coef_scaled = clockMhzScaled / centers.synth_center;
854
855 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
856 &ds_coef_exp);
857
858 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
859 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
860 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
861 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
862
863 coef_scaled = (9 * coef_scaled) / 10;
864
865 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
866 &ds_coef_exp);
867
868 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
869 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
870 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
871 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
872}
873
874static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
875{
876 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
877 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
878 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
879}
880
881static void ar5008_hw_rfbus_done(struct ath_hw *ah)
882{
883 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
8fe65368 884
7c5adc8d 885 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
8fe65368
LR		 886
887 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
888}
889
8fe65368
LR		 890static void ar5008_restore_chainmask(struct ath_hw *ah)
891{
892 int rx_chainmask = ah->rxchainmask;
893
894 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
895 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
896 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
897 }
898}
899
64773964
LR		 900static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
901 struct ath9k_channel *chan)
902{
903 u32 pll;
904
905 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
906
907 if (chan && IS_CHAN_HALF_RATE(chan))
908 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
909 else if (chan && IS_CHAN_QUARTER_RATE(chan))
910 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
911
912 if (chan && IS_CHAN_5GHZ(chan))
913 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
914 else
915 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
916
917 return pll;
918}
919
920static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
921 struct ath9k_channel *chan)
922{
923 u32 pll;
924
925 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
926
927 if (chan && IS_CHAN_HALF_RATE(chan))
928 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
929 else if (chan && IS_CHAN_QUARTER_RATE(chan))
930 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
931
932 if (chan && IS_CHAN_5GHZ(chan))
933 pll |= SM(0xa, AR_RTC_PLL_DIV);
934 else
935 pll |= SM(0xb, AR_RTC_PLL_DIV);
936
937 return pll;
938}
939
e36b27af
LR		 940static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
941 enum ath9k_ani_cmd cmd,
942 int param)
943{
e36b27af
LR		 944 struct ath_common *common = ath9k_hw_common(ah);
945 struct ath9k_channel *chan = ah->curchan;
c24bd362 946 struct ar5416AniState *aniState = &ah->ani;
9301ca90 947 s32 value;
e36b27af
LR		 948
949 switch (cmd & ah->ani_function) {
950 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
951 /*
952 * on == 1 means ofdm weak signal detection is ON
953 * on == 1 is the default, for less noise immunity
954 *
955 * on == 0 means ofdm weak signal detection is OFF
956 * on == 0 means more noise imm
957 */
958 u32 on = param ? 1 : 0;
959 /*
960 * make register setting for default
961 * (weak sig detect ON) come from INI file
962 */
963 int m1ThreshLow = on ?
964 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
965 int m2ThreshLow = on ?
966 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
967 int m1Thresh = on ?
968 aniState->iniDef.m1Thresh : m1Thresh_off;
969 int m2Thresh = on ?
970 aniState->iniDef.m2Thresh : m2Thresh_off;
971 int m2CountThr = on ?
972 aniState->iniDef.m2CountThr : m2CountThr_off;
973 int m2CountThrLow = on ?
974 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
975 int m1ThreshLowExt = on ?
976 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
977 int m2ThreshLowExt = on ?
978 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
979 int m1ThreshExt = on ?
980 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
981 int m2ThreshExt = on ?
982 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
983
984 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
985 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
986 m1ThreshLow);
987 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
988 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
989 m2ThreshLow);
990 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
991 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
992 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
993 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
994 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
995 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
996 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
997 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
998 m2CountThrLow);
999
1000 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1001 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1002 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1003 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1004 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1005 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1006 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1007 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1008
1009 if (on)
1010 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1011 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1012 else
1013 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1014 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1015
7067e701 1016 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 1017 ath_dbg(common, ANI,
226afe68
JP		 1018 "** ch %d: ofdm weak signal: %s=>%s\n",
1019 chan->channel,
7067e701 1020 aniState->ofdmWeakSigDetect ?
226afe68
JP		 1021 "on" : "off",
1022 on ? "on" : "off");
e36b27af
LR		 1023 if (on)
1024 ah->stats.ast_ani_ofdmon++;
1025 else
1026 ah->stats.ast_ani_ofdmoff++;
7067e701 1027 aniState->ofdmWeakSigDetect = on;
e36b27af
LR		 1028 }
1029 break;
1030 }
1031 case ATH9K_ANI_FIRSTEP_LEVEL:{
1032 u32 level = param;
1033
171cdab8 1034 value = level * 2;
e36b27af 1035 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
9301ca90 1036 AR_PHY_FIND_SIG_FIRSTEP, value);
171cdab8
FF		 1037 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1038 AR_PHY_FIND_SIG_FIRSTEP_LOW, value);
e36b27af
LR		 1039
1040 if (level != aniState->firstepLevel) {
d2182b69 1041 ath_dbg(common, ANI,
226afe68
JP		 1042 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1043 chan->channel,
1044 aniState->firstepLevel,
1045 level,
465dce62 1046 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1047 value,
1048 aniState->iniDef.firstep);
d2182b69 1049 ath_dbg(common, ANI,
226afe68
JP		 1050 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1051 chan->channel,
1052 aniState->firstepLevel,
1053 level,
465dce62 1054 ATH9K_ANI_FIRSTEP_LVL,
9301ca90 1055 value,
226afe68 1056 aniState->iniDef.firstepLow);
e36b27af
LR		 1057 if (level > aniState->firstepLevel)
1058 ah->stats.ast_ani_stepup++;
1059 else if (level < aniState->firstepLevel)
1060 ah->stats.ast_ani_stepdown++;
1061 aniState->firstepLevel = level;
1062 }
1063 break;
1064 }
1065 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1066 u32 level = param;
1067
28327fd0 1068 value = (level + 1) * 2;
e36b27af 1069 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
28327fd0 1070 AR_PHY_TIMING5_CYCPWR_THR1, value);
e36b27af 1071
b874ec8d
FF		 1072 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1073 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1);
e36b27af
LR		 1074
1075 if (level != aniState->spurImmunityLevel) {
d2182b69 1076 ath_dbg(common, ANI,
226afe68
JP		 1077 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1078 chan->channel,
1079 aniState->spurImmunityLevel,
1080 level,
465dce62 1081 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1082 value,
1083 aniState->iniDef.cycpwrThr1);
d2182b69 1084 ath_dbg(common, ANI,
226afe68
JP		 1085 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1086 chan->channel,
1087 aniState->spurImmunityLevel,
1088 level,
465dce62 1089 ATH9K_ANI_SPUR_IMMUNE_LVL,
28327fd0 1090 value,
226afe68 1091 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1092 if (level > aniState->spurImmunityLevel)
1093 ah->stats.ast_ani_spurup++;
1094 else if (level < aniState->spurImmunityLevel)
1095 ah->stats.ast_ani_spurdown++;
1096 aniState->spurImmunityLevel = level;
1097 }
1098 break;
1099 }
1100 case ATH9K_ANI_MRC_CCK:
1101 /*
1102 * You should not see this as AR5008, AR9001, AR9002
1103 * does not have hardware support for MRC CCK.
1104 */
1105 WARN_ON(1);
1106 break;
e36b27af 1107 default:
d2182b69 1108 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
e36b27af
LR		 1109 return false;
1110 }
1111
d2182b69 1112 ath_dbg(common, ANI,
226afe68
JP		 1113 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1114 aniState->spurImmunityLevel,
7067e701 1115 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1116 aniState->firstepLevel,
81b67fd6 1117 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1118 aniState->listenTime,
1119 aniState->ofdmPhyErrCount,
1120 aniState->cckPhyErrCount);
e36b27af
LR		 1121 return true;
1122}
1123
641d9921
FF		 1124static void ar5008_hw_do_getnf(struct ath_hw *ah,
1125 int16_t nfarray[NUM_NF_READINGS])
1126{
641d9921
FF		 1127 int16_t nf;
1128
1129 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
7919a57b 1130 nfarray[0] = sign_extend32(nf, 8);
641d9921
FF		 1131
1132 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
7919a57b 1133 nfarray[1] = sign_extend32(nf, 8);
641d9921
FF		 1134
1135 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
7919a57b 1136 nfarray[2] = sign_extend32(nf, 8);
641d9921 1137
866b7780
FF		 1138 if (!IS_CHAN_HT40(ah->curchan))
1139 return;
1140
641d9921 1141 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
7919a57b 1142 nfarray[3] = sign_extend32(nf, 8);
641d9921
FF		 1143
1144 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
7919a57b 1145 nfarray[4] = sign_extend32(nf, 8);
641d9921
FF		 1146
1147 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
7919a57b 1148 nfarray[5] = sign_extend32(nf, 8);
641d9921
FF		 1149}
1150
e36b27af
LR		 1151/*
1152 * Initialize the ANI register values with default (ini) values.
1153 * This routine is called during a (full) hardware reset after
1154 * all the registers are initialised from the INI.
1155 */
1156static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1157{
e36b27af
LR		 1158 struct ath_common *common = ath9k_hw_common(ah);
1159 struct ath9k_channel *chan = ah->curchan;
c24bd362 1160 struct ar5416AniState *aniState = &ah->ani;
e36b27af 1161 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1162 u32 val;
1163
e36b27af
LR		 1164 iniDef = &aniState->iniDef;
1165
8896934c 1166 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
226afe68
JP		 1167 ah->hw_version.macVersion,
1168 ah->hw_version.macRev,
1169 ah->opmode,
8896934c 1170 chan->channel);
e36b27af
LR		 1171
1172 val = REG_READ(ah, AR_PHY_SFCORR);
1173 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1174 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1175 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1176
1177 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1178 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1179 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1180 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1181
1182 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1183 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1184 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1185 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1186 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1187 iniDef->firstep = REG_READ_FIELD(ah,
1188 AR_PHY_FIND_SIG,
1189 AR_PHY_FIND_SIG_FIRSTEP);
1190 iniDef->firstepLow = REG_READ_FIELD(ah,
1191 AR_PHY_FIND_SIG_LOW,
1192 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1193 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1194 AR_PHY_TIMING5,
1195 AR_PHY_TIMING5_CYCPWR_THR1);
1196 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1197 AR_PHY_EXT_CCA,
1198 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1199
1200 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1201 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1202 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
4f4395c6 1203 aniState->ofdmWeakSigDetect = true;
81b67fd6 1204 aniState->mrcCCK = false; /* not available on pre AR9003 */
e36b27af
LR		 1205}
1206
f2552e28
FF		 1207static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1208{
1209 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1210 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1211 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1212 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1213 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1214 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1215}
e36b27af 1216
4e8c14e9
FF		 1217static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1218 struct ath_hw_radar_conf *conf)
1219{
992a36a6 1220 u32 radar_0 = 0, radar_1;
4e8c14e9
FF		 1221
1222 if (!conf) {
1223 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1224 return;
1225 }
1226
1227 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1228 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1229 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1230 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1231 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1232 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1233
992a36a6
LB		 1234 radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1235 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1236 AR_PHY_RADAR_1_RELPWR_THRESH);
4e8c14e9
FF		 1237 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1238 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1239 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1240 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1241 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1242
1243 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1244 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1245 if (conf->ext_channel)
1246 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1247 else
1248 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1249}
1250
c5d0855a
FF		 1251static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1252{
1253 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1254
1255 conf->fir_power = -33;
1256 conf->radar_rssi = 20;
1257 conf->pulse_height = 10;
edad1873 1258 conf->pulse_rssi = 15;
c5d0855a
FF		 1259 conf->pulse_inband = 15;
1260 conf->pulse_maxlen = 255;
1261 conf->pulse_inband_step = 12;
1262 conf->radar_inband = 8;
1263}
1264
c08267dc
LB		 1265static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array)
1266{
1267#define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x))
1268 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]);
1269 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l],
1270 rate_array[rate2s]));
1271 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l],
1272 rate_array[rate5_5s]));
1273 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l],
1274 rate_array[rate11s]));
1275#undef CCK_DELTA
1276}
1277
1278static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array,
1279 int offset)
1280{
1281 int i, idx = 0;
1282
1283 for (i = offset; i < offset + AR5008_OFDM_RATES; i++) {
1284 ah->tx_power[i] = rate_array[idx];
1285 idx++;
1286 }
1287}
1288
1289static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array,
1290 int ss_offset, int ds_offset,
1291 bool is_40, int ht40_delta)
1292{
1293 int i, mcs_idx = (is_40) ? AR5008_HT40_SHIFT : AR5008_HT20_SHIFT;
1294
1295 for (i = ss_offset; i < ss_offset + AR5008_HT_SS_RATES; i++) {
1296 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta;
1297 mcs_idx++;
1298 }
1299 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset],
1300 AR5008_HT_SS_RATES);
1301}
1302
1303void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1304 struct ath9k_channel *chan, int ht40_delta)
1305{
1306 if (IS_CHAN_5GHZ(chan)) {
1307 ar5008_hw_init_txpower_ofdm(ah, rate_array,
1308 AR5008_11NA_OFDM_SHIFT);
1309 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1310 ar5008_hw_init_txpower_ht(ah, rate_array,
1311 AR5008_11NA_HT_SS_SHIFT,
1312 AR5008_11NA_HT_DS_SHIFT,
1313 IS_CHAN_HT40(chan),
1314 ht40_delta);
1315 }
1316 } else {
1317 ar5008_hw_init_txpower_cck(ah, rate_array);
1318 ar5008_hw_init_txpower_ofdm(ah, rate_array,
1319 AR5008_11NG_OFDM_SHIFT);
1320 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1321 ar5008_hw_init_txpower_ht(ah, rate_array,
1322 AR5008_11NG_HT_SS_SHIFT,
1323 AR5008_11NG_HT_DS_SHIFT,
1324 IS_CHAN_HT40(chan),
1325 ht40_delta);
1326 }
1327 }
1328}
1329
c1b976d2 1330int ar5008_hw_attach_phy_ops(struct ath_hw *ah)
8fe65368
LR		 1331{
1332 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
07b2fa5a 1333 static const u32 ar5416_cca_regs[6] = {
bbacee13
FF		 1334 AR_PHY_CCA,
1335 AR_PHY_CH1_CCA,
1336 AR_PHY_CH2_CCA,
1337 AR_PHY_EXT_CCA,
1338 AR_PHY_CH1_EXT_CCA,
1339 AR_PHY_CH2_EXT_CCA
1340 };
c1b976d2
FF		 1341 int ret;
1342
1343 ret = ar5008_hw_rf_alloc_ext_banks(ah);
1344 if (ret)
1345 return ret;
8fe65368
LR		 1346
1347 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1348 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1349
8fe65368
LR		 1350 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1351 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1352 priv_ops->init_bb = ar5008_hw_init_bb;
1353 priv_ops->process_ini = ar5008_hw_process_ini;
1354 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1355 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1356 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1357 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1358 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
8fe65368 1359 priv_ops->restore_chainmask = ar5008_restore_chainmask;
641d9921 1360 priv_ops->do_getnf = ar5008_hw_do_getnf;
4e8c14e9 1361 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
64773964 1362
6790ae7a
FF		 1363 priv_ops->ani_control = ar5008_hw_ani_control_new;
1364 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
e36b27af 1365
491b209d 1366 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
64773964
LR		 1367 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1368 else
1369 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
f2552e28
FF		 1370
1371 ar5008_hw_set_nf_limits(ah);
c5d0855a 1372 ar5008_hw_set_radar_conf(ah);
bbacee13 1373 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
c1b976d2 1374 return 0;
8fe65368 1375}
Linux kernel - Deliverables
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