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Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
5ca06ebe 22#include <linux/etherdevice.h>
61b559de 23#include <linux/gpio.h>
f078f209
LR		 24#include <asm/unaligned.h>
25
af03abec 26#include "hw.h"
d70357d5 27#include "hw-ops.h"
b622a720 28#include "ar9003_mac.h"
f4701b5a 29#include "ar9003_mci.h"
362cd03f 30#include "ar9003_phy.h"
462e58f2 31#include "ath9k.h"
f078f209 32
cbe61d8a 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 34
7322fd19
LR		 35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
dfdac8ac 40static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 41{
dfdac8ac 42 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 43 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 44 unsigned int clockrate;
cbe61d8a 45
087b6ff6
FF		 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
e4744ec7 49 else if (!chan) /* should really check for CCK instead */
dfdac8ac 50 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 51 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 55 else
dfdac8ac
FF		 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
beae416b
MN		 58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
e4744ec7 61 if (IS_CHAN_HALF_RATE(chan))
906c7205 62 clockrate /= 2;
e4744ec7 63 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 64 clockrate /= 4;
65 }
66
dfdac8ac 67 common->clockrate = clockrate;
f1dc5600
S		 68}
69
cbe61d8a 70static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 71{
dfdac8ac 72 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 73
dfdac8ac 74 return usecs * common->clockrate;
f1dc5600 75}
f078f209 76
0caa7b14 77bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 78{
79 int i;
80
0caa7b14
S		 81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
04bd4638 89
d2182b69 90 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 93
f1dc5600 94 return false;
f078f209 95}
7322fd19 96EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 97
7c5adc8d
FF		 98void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100{
1a5e6326 101 hw_delay /= 10;
7c5adc8d
FF		 102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109}
110
0166b4be 111void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 112 int column, unsigned int *writecnt)
113{
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123}
124
a57cb45a
OR		 125void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
126{
127 u32 *tmp_reg_list, *tmp_data;
128 int i;
129
130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
131 if (!tmp_reg_list) {
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
133 return;
134 }
135
136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
137 if (!tmp_data) {
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
139 goto error_tmp_data;
140 }
141
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
144
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
146
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
149
150 kfree(tmp_data);
151error_tmp_data:
152 kfree(tmp_reg_list);
153}
154
f078f209
LR		 155u32 ath9k_hw_reverse_bits(u32 val, u32 n)
156{
157 u32 retval;
158 int i;
159
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
162 val >>= 1;
163 }
164 return retval;
165}
166
cbe61d8a 167u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 168 u8 phy, int kbps,
f1dc5600
S		 169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
f078f209 171{
f1dc5600 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 173
f1dc5600
S		 174 if (kbps == 0)
175 return 0;
f078f209 176
545750d3 177 switch (phy) {
46d14a58 178 case WLAN_RC_PHY_CCK:
f1dc5600 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 180 if (shortPreamble)
f1dc5600
S		 181 phyTime >>= 1;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
184 break;
46d14a58 185 case WLAN_RC_PHY_OFDM:
2660b81a 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_QUARTER
191 + OFDM_PREAMBLE_TIME_QUARTER
192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
196 numBits = OFDM_PLCP_BITS + (frameLen << 3);
197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
198 txTime = OFDM_SIFS_TIME_HALF +
199 OFDM_PREAMBLE_TIME_HALF
200 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
201 } else {
202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
203 numBits = OFDM_PLCP_BITS + (frameLen << 3);
204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
206 + (numSymbols * OFDM_SYMBOL_TIME);
207 }
208 break;
209 default:
3800276a
JP		 210 ath_err(ath9k_hw_common(ah),
211 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 212 txTime = 0;
213 break;
214 }
f078f209 215
f1dc5600
S		 216 return txTime;
217}
7322fd19 218EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 219
cbe61d8a 220void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 221 struct ath9k_channel *chan,
222 struct chan_centers *centers)
f078f209 223{
f1dc5600 224 int8_t extoff;
f078f209 225
f1dc5600
S		 226 if (!IS_CHAN_HT40(chan)) {
227 centers->ctl_center = centers->ext_center =
228 centers->synth_center = chan->channel;
229 return;
f078f209 230 }
f078f209 231
8896934c 232 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 233 centers->synth_center =
234 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
235 extoff = 1;
236 } else {
237 centers->synth_center =
238 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
239 extoff = -1;
240 }
f078f209 241
f1dc5600
S		 242 centers->ctl_center =
243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 244 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 245 centers->ext_center =
6420014c 246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 247}
248
f1dc5600
S		 249/******************/
250/* Chip Revisions */
251/******************/
252
cbe61d8a 253static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 254{
f1dc5600 255 u32 val;
f078f209 256
09c74f7b
FF		 257 if (ah->get_mac_revision)
258 ah->hw_version.macRev = ah->get_mac_revision();
259
ecb1d385
VT		 260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
3762561a
GJ		 264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
09c74f7b 266 if (!ah->get_mac_revision) {
3762561a
GJ		 267 val = REG_READ(ah, AR_SREV);
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 }
270 return;
ecb1d385
VT		 271 case AR9300_DEVID_AR9340:
272 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
ecb1d385 273 return;
813831dc
GJ		 274 case AR9300_DEVID_QCA955X:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
276 return;
e6b1e46e
SM		 277 case AR9300_DEVID_AR953X:
278 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
279 return;
2131fabb
MP		 280 case AR9300_DEVID_QCA956X:
281 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
7865598e 282 return;
ecb1d385
VT		 283 }
284
f1dc5600 285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 286
f1dc5600
S		 287 if (val == 0xFF) {
288 val = REG_READ(ah, AR_SREV);
d535a42a
S		 289 ah->hw_version.macVersion =
290 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 292
77fac465 293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 294 ah->is_pciexpress = true;
295 else
296 ah->is_pciexpress = (val &
297 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 298 } else {
299 if (!AR_SREV_9100(ah))
d535a42a 300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 301
d535a42a 302 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 303
d535a42a 304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 305 ah->is_pciexpress = true;
f1dc5600 306 }
f078f209
LR		 307}
308
f1dc5600
S		 309/************************************/
310/* HW Attach, Detach, Init Routines */
311/************************************/
312
cbe61d8a 313static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 314{
040b74f7 315 if (!AR_SREV_5416(ah))
f1dc5600 316 return;
f078f209 317
f1dc5600
S		 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 327
f1dc5600 328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 329}
330
1f3f0618 331/* This should work for all families including legacy */
cbe61d8a 332static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 333{
c46917bb 334 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 335 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 336 u32 regHold[2];
07b2fa5a
JP		 337 static const u32 patternData[4] = {
338 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
339 };
1f3f0618 340 int i, j, loop_max;
f078f209 341
1f3f0618
SB		 342 if (!AR_SREV_9300_20_OR_LATER(ah)) {
343 loop_max = 2;
344 regAddr[1] = AR_PHY_BASE + (8 << 2);
345 } else
346 loop_max = 1;
347
348 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 349 u32 addr = regAddr[i];
350 u32 wrData, rdData;
f078f209 351
f1dc5600
S		 352 regHold[i] = REG_READ(ah, addr);
353 for (j = 0; j < 0x100; j++) {
354 wrData = (j << 16) | j;
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (rdData != wrData) {
3800276a
JP		 358 ath_err(common,
359 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
360 addr, wrData, rdData);
f1dc5600
S		 361 return false;
362 }
363 }
364 for (j = 0; j < 4; j++) {
365 wrData = patternData[j];
366 REG_WRITE(ah, addr, wrData);
367 rdData = REG_READ(ah, addr);
368 if (wrData != rdData) {
3800276a
JP		 369 ath_err(common,
370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 addr, wrData, rdData);
f1dc5600
S		 372 return false;
373 }
f078f209 374 }
f1dc5600 375 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 376 }
f1dc5600 377 udelay(100);
cbe61d8a 378
f078f209
LR		 379 return true;
380}
381
b8b0f377 382static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 383{
f57cf939
SM		 384 struct ath_common *common = ath9k_hw_common(ah);
385
689e756f
FF		 386 ah->config.dma_beacon_response_time = 1;
387 ah->config.sw_beacon_response_time = 6;
621a5f7a 388 ah->config.cwm_ignore_extcca = false;
2660b81a 389 ah->config.analog_shiftreg = 1;
f078f209 390
0ce024cb 391 ah->config.rx_intr_mitigation = true;
6158425b 392
a64e1a45
SM		 393 if (AR_SREV_9300_20_OR_LATER(ah)) {
394 ah->config.rimt_last = 500;
395 ah->config.rimt_first = 2000;
396 } else {
397 ah->config.rimt_last = 250;
398 ah->config.rimt_first = 700;
399 }
400
656cd75c
SM		 401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
402 ah->config.pll_pwrsave = 7;
403
6158425b
LR		 404 /*
405 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
406 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
407 * This means we use it for all AR5416 devices, and the few
408 * minor PCI AR9280 devices out there.
409 *
410 * Serialization is required because these devices do not handle
411 * well the case of two concurrent reads/writes due to the latency
412 * involved. During one read/write another read/write can be issued
413 * on another CPU while the previous read/write may still be working
414 * on our hardware, if we hit this case the hardware poops in a loop.
415 * We prevent this by serializing reads and writes.
416 *
417 * This issue is not present on PCI-Express devices or pre-AR5416
418 * devices (legacy, 802.11abg).
419 */
420 if (num_possible_cpus() > 1)
2d6a5e95 421 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 422
423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
426 !ah->is_pciexpress)) {
427 ah->config.serialize_regmode = SER_REG_MODE_ON;
428 } else {
429 ah->config.serialize_regmode = SER_REG_MODE_OFF;
430 }
431 }
432
433 ath_dbg(common, RESET, "serialize_regmode is %d\n",
434 ah->config.serialize_regmode);
435
436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
438 else
439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 440}
441
50aca25b 442static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 443{
608b88cb
LR		 444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
445
446 regulatory->country_code = CTRY_DEFAULT;
447 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 448
d535a42a 449 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 450 ah->hw_version.subvendorid = 0;
f078f209 451
f57cf939
SM		 452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
453 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 454 if (AR_SREV_9100(ah))
455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 456
11b0ac2e 457 ah->slottime = 9;
2660b81a 458 ah->globaltxtimeout = (u32) -1;
cbdec975 459 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 460 ah->htc_reset_init = true;
f57cf939 461
c09396eb 462 ah->tpc_enabled = false;
a9abe302 463
f57cf939
SM		 464 ah->ani_function = ATH9K_ANI_ALL;
465 if (!AR_SREV_9300_20_OR_LATER(ah))
466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
467
468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
470 else
471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 472}
473
d323cb71 474static void ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 475{
1510718d 476 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 477 int i;
478 u16 eeval;
07b2fa5a 479 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209 480
0cefa974
MB		 481 /* MAC address may already be loaded via ath9k_platform_data */
482 if (is_valid_ether_addr(common->macaddr))
d323cb71 483 return;
0cefa974 484
f078f209 485 for (i = 0; i < 3; i++) {
49101676 486 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
1510718d
LR		 487 common->macaddr[2 * i] = eeval >> 8;
488 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 489 }
0cefa974
MB		 490
491 if (is_valid_ether_addr(common->macaddr))
d323cb71 492 return;
0cefa974
MB		 493
494 ath_err(common, "eeprom contains invalid mac address: %pM\n",
495 common->macaddr);
496
497 random_ether_addr(common->macaddr);
498 ath_err(common, "random mac address will be used: %pM\n",
499 common->macaddr);
f078f209 500
d323cb71 501 return;
f078f209
LR		 502}
503
f637cfd6 504static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 505{
6cae913d 506 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 507 int ecode;
f078f209 508
6cae913d 509 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 510 if (!ath9k_hw_chip_test(ah))
511 return -ENODEV;
512 }
f078f209 513
ebd5a14a
LR		 514 if (!AR_SREV_9300_20_OR_LATER(ah)) {
515 ecode = ar9002_hw_rf_claim(ah);
516 if (ecode != 0)
517 return ecode;
518 }
f078f209 519
f637cfd6 520 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 521 if (ecode != 0)
522 return ecode;
7d01b221 523
d2182b69 524 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 525 ah->eep_ops->get_eeprom_ver(ah),
526 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 527
e323300d 528 ath9k_hw_ani_init(ah);
f078f209 529
d3b371cb
SM		 530 /*
531 * EEPROM needs to be initialized before we do this.
532 * This is required for regulatory compliance.
533 */
0c7c2bb4 534 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 535 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
536 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 537 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
538 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 539 }
540 }
541
f078f209
LR		 542 return 0;
543}
544
c1b976d2 545static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 546{
c1b976d2
FF		 547 if (!AR_SREV_9300_20_OR_LATER(ah))
548 return ar9002_hw_attach_ops(ah);
549
550 ar9003_hw_attach_ops(ah);
551 return 0;
aa4058ae
LR		 552}
553
d70357d5
LR		 554/* Called for all hardware families */
555static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 556{
c46917bb 557 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 558 int r = 0;
aa4058ae 559
ac45c12d
SB		 560 ath9k_hw_read_revisions(ah);
561
de82582b
SM		 562 switch (ah->hw_version.macVersion) {
563 case AR_SREV_VERSION_5416_PCI:
564 case AR_SREV_VERSION_5416_PCIE:
565 case AR_SREV_VERSION_9160:
566 case AR_SREV_VERSION_9100:
567 case AR_SREV_VERSION_9280:
568 case AR_SREV_VERSION_9285:
569 case AR_SREV_VERSION_9287:
570 case AR_SREV_VERSION_9271:
571 case AR_SREV_VERSION_9300:
572 case AR_SREV_VERSION_9330:
573 case AR_SREV_VERSION_9485:
574 case AR_SREV_VERSION_9340:
575 case AR_SREV_VERSION_9462:
576 case AR_SREV_VERSION_9550:
577 case AR_SREV_VERSION_9565:
e6b1e46e 578 case AR_SREV_VERSION_9531:
2131fabb 579 case AR_SREV_VERSION_9561:
de82582b
SM		 580 break;
581 default:
582 ath_err(common,
583 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
584 ah->hw_version.macVersion, ah->hw_version.macRev);
585 return -EOPNOTSUPP;
586 }
587
0a8d7cb0
SB		 588 /*
589 * Read back AR_WA into a permanent copy and set bits 14 and 17.
590 * We need to do this to avoid RMW of this register. We cannot
591 * read the reg when chip is asleep.
592 */
27251e00
SM		 593 if (AR_SREV_9300_20_OR_LATER(ah)) {
594 ah->WARegVal = REG_READ(ah, AR_WA);
595 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
596 AR_WA_ASPM_TIMER_BASED_DISABLE);
597 }
0a8d7cb0 598
aa4058ae 599 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 600 ath_err(common, "Couldn't reset chip\n");
95fafca2 601 return -EIO;
aa4058ae
LR		 602 }
603
a4a2954f
SM		 604 if (AR_SREV_9565(ah)) {
605 ah->WARegVal |= AR_WA_BIT22;
606 REG_WRITE(ah, AR_WA, ah->WARegVal);
607 }
608
bab1f62e
LR		 609 ath9k_hw_init_defaults(ah);
610 ath9k_hw_init_config(ah);
611
c1b976d2
FF		 612 r = ath9k_hw_attach_ops(ah);
613 if (r)
614 return r;
d70357d5 615
9ecdef4b 616 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 617 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 618 return -EIO;
aa4058ae
LR		 619 }
620
2c8e5937 621 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 622 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 623 ah->is_pciexpress = false;
624
aa4058ae 625 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 626 ath9k_hw_init_cal_settings(ah);
627
69ce674b 628 if (!ah->is_pciexpress)
aa4058ae
LR		 629 ath9k_hw_disablepcie(ah);
630
f637cfd6 631 r = ath9k_hw_post_init(ah);
aa4058ae 632 if (r)
95fafca2 633 return r;
aa4058ae
LR		 634
635 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 636 r = ath9k_hw_fill_cap_info(ah);
637 if (r)
638 return r;
639
d323cb71 640 ath9k_hw_init_macaddr(ah);
4598702d 641 ath9k_hw_init_hang_checks(ah);
f078f209 642
211f5859
LR		 643 common->state = ATH_HW_INITIALIZED;
644
4f3acf81 645 return 0;
f078f209
LR		 646}
647
d70357d5 648int ath9k_hw_init(struct ath_hw *ah)
f078f209 649{
d70357d5
LR		 650 int ret;
651 struct ath_common *common = ath9k_hw_common(ah);
f078f209 652
77fac465 653 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 654 switch (ah->hw_version.devid) {
655 case AR5416_DEVID_PCI:
656 case AR5416_DEVID_PCIE:
657 case AR5416_AR9100_DEVID:
658 case AR9160_DEVID_PCI:
659 case AR9280_DEVID_PCI:
660 case AR9280_DEVID_PCIE:
661 case AR9285_DEVID_PCIE:
db3cc53a
SB		 662 case AR9287_DEVID_PCI:
663 case AR9287_DEVID_PCIE:
d70357d5 664 case AR2427_DEVID_PCIE:
db3cc53a 665 case AR9300_DEVID_PCIE:
3050c914 666 case AR9300_DEVID_AR9485_PCIE:
999a7a88 667 case AR9300_DEVID_AR9330:
bca04689 668 case AR9300_DEVID_AR9340:
2b943a33 669 case AR9300_DEVID_QCA955X:
5a63ef0f 670 case AR9300_DEVID_AR9580:
423e38e8 671 case AR9300_DEVID_AR9462:
d4e5979c 672 case AR9485_DEVID_AR1111:
77fac465 673 case AR9300_DEVID_AR9565:
e6b1e46e 674 case AR9300_DEVID_AR953X:
2131fabb 675 case AR9300_DEVID_QCA956X:
d70357d5
LR		 676 break;
677 default:
678 if (common->bus_ops->ath_bus_type == ATH_USB)
679 break;
3800276a
JP		 680 ath_err(common, "Hardware device ID 0x%04x not supported\n",
681 ah->hw_version.devid);
d70357d5
LR		 682 return -EOPNOTSUPP;
683 }
f078f209 684
d70357d5
LR		 685 ret = __ath9k_hw_init(ah);
686 if (ret) {
3800276a
JP		 687 ath_err(common,
688 "Unable to initialize hardware; initialization status: %d\n",
689 ret);
d70357d5
LR		 690 return ret;
691 }
f078f209 692
c774d57f
LB		 693 ath_dynack_init(ah);
694
d70357d5 695 return 0;
f078f209 696}
d70357d5 697EXPORT_SYMBOL(ath9k_hw_init);
f078f209 698
cbe61d8a 699static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 700{
7d0d0df0
S		 701 ENABLE_REGWRITE_BUFFER(ah);
702
f1dc5600
S		 703 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
704 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 705
f1dc5600
S		 706 REG_WRITE(ah, AR_QOS_NO_ACK,
707 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
708 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
709 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
710
711 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
712 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
713 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
714 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
715 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 716
717 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 718}
719
b84628eb 720u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 721{
f18e3c6b
MSS		 722 struct ath_common *common = ath9k_hw_common(ah);
723 int i = 0;
724
ca7a4deb
FF		 725 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
726 udelay(100);
727 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 728
f18e3c6b
MSS		 729 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
730
ca7a4deb 731 udelay(100);
b1415819 732
f18e3c6b
MSS		 733 if (WARN_ON_ONCE(i >= 100)) {
734 ath_err(common, "PLL4 meaurement not done\n");
735 break;
736 }
737
738 i++;
739 }
740
ca7a4deb 741 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 742}
743EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
744
cbe61d8a 745static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 746 struct ath9k_channel *chan)
f078f209 747{
d09b17f7
VT		 748 u32 pll;
749
5fb9b1b9
FF		 750 pll = ath9k_hw_compute_pll_control(ah, chan);
751
a4a2954f 752 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 753 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
755 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
757 AR_CH0_DPLL2_KD, 0x40);
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_DPLL2_KI, 0x4);
22983c30 760
3dfd7f60
VT		 761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
762 AR_CH0_BB_DPLL1_REFDIV, 0x5);
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
764 AR_CH0_BB_DPLL1_NINI, 0x58);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
766 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 767
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 769 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
771 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 773 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 774
3dfd7f60 775 /* program BB PLL phase_shift to 0x6 */
22983c30 776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 777 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
778
779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
780 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 781 udelay(1000);
a5415d62
GJ		 782 } else if (AR_SREV_9330(ah)) {
783 u32 ddr_dpll2, pll_control2, kd;
784
785 if (ah->is_clk_25mhz) {
786 ddr_dpll2 = 0x18e82f01;
787 pll_control2 = 0xe04a3d;
788 kd = 0x1d;
789 } else {
790 ddr_dpll2 = 0x19e82f01;
791 pll_control2 = 0x886666;
792 kd = 0x3d;
793 }
794
795 /* program DDR PLL ki and kd value */
796 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
797
798 /* program DDR PLL phase_shift */
799 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
800 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
801
5fb9b1b9
FF		 802 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
803 pll | AR_RTC_9300_PLL_BYPASS);
a5415d62
GJ		 804 udelay(1000);
805
806 /* program refdiv, nint, frac to RTC register */
807 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
808
809 /* program BB PLL kd and ki value */
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
812
813 /* program BB PLL phase_shift */
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
815 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
ede6a5e7
MP		 816 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
817 AR_SREV_9561(ah)) {
0b488ac6
VT		 818 u32 regval, pll2_divint, pll2_divfrac, refdiv;
819
5fb9b1b9
FF		 820 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
821 pll | AR_RTC_9300_SOC_PLL_BYPASS);
0b488ac6
VT		 822 udelay(1000);
823
824 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
825 udelay(100);
826
827 if (ah->is_clk_25mhz) {
ede6a5e7 828 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 829 pll2_divint = 0x1c;
830 pll2_divfrac = 0xa3d2;
831 refdiv = 1;
832 } else {
833 pll2_divint = 0x54;
834 pll2_divfrac = 0x1eb85;
835 refdiv = 3;
836 }
0b488ac6 837 } else {
fc05a317
GJ		 838 if (AR_SREV_9340(ah)) {
839 pll2_divint = 88;
840 pll2_divfrac = 0;
841 refdiv = 5;
842 } else {
843 pll2_divint = 0x11;
ede6a5e7
MP		 844 pll2_divfrac = (AR_SREV_9531(ah) ||
845 AR_SREV_9561(ah)) ?
846 0x26665 : 0x26666;
fc05a317
GJ		 847 refdiv = 1;
848 }
0b488ac6
VT		 849 }
850
851 regval = REG_READ(ah, AR_PHY_PLL_MODE);
ede6a5e7 852 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 853 regval |= (0x1 << 22);
854 else
855 regval |= (0x1 << 16);
0b488ac6
VT		 856 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
857 udelay(100);
858
859 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
860 (pll2_divint << 18) | pll2_divfrac);
861 udelay(100);
862
863 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 864 if (AR_SREV_9340(ah))
2c323058
SM		 865 regval = (regval & 0x80071fff) |
866 (0x1 << 30) |
867 (0x1 << 13) |
868 (0x4 << 26) |
869 (0x18 << 19);
ede6a5e7 870 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 871 regval = (regval & 0x01c00fff) |
872 (0x1 << 31) |
873 (0x2 << 29) |
874 (0xa << 25) |
ede6a5e7
MP		 875 (0x1 << 19);
876
877 if (AR_SREV_9531(ah))
878 regval |= (0x6 << 12);
879 } else
2c323058
SM		 880 regval = (regval & 0x80071fff) |
881 (0x3 << 30) |
882 (0x1 << 13) |
883 (0x4 << 26) |
884 (0x60 << 19);
0b488ac6 885 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058 886
ede6a5e7 887 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 888 REG_WRITE(ah, AR_PHY_PLL_MODE,
889 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
890 else
891 REG_WRITE(ah, AR_PHY_PLL_MODE,
892 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
893
0b488ac6 894 udelay(1000);
22983c30 895 }
d09b17f7 896
8565f8bf
SM		 897 if (AR_SREV_9565(ah))
898 pll |= 0x40000;
d03a66c1 899 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 900
fc05a317
GJ		 901 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
902 AR_SREV_9550(ah))
3dfd7f60
VT		 903 udelay(1000);
904
c75724d1
LR		 905 /* Switch the core clock for ar9271 to 117Mhz */
906 if (AR_SREV_9271(ah)) {
25e2ab17
S		 907 udelay(500);
908 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 909 }
910
f1dc5600
S		 911 udelay(RTC_PLL_SETTLE_DELAY);
912
913 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 914}
915
cbe61d8a 916static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 917 enum nl80211_iftype opmode)
f078f209 918{
79d1d2b8 919 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 920 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 921 AR_IMR_TXURN |
922 AR_IMR_RXERR |
923 AR_IMR_RXORN |
924 AR_IMR_BCNMISC;
f078f209 925
ede6a5e7
MP		 926 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
927 AR_SREV_9561(ah))
79d1d2b8
VT		 928 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
929
66860240
VT		 930 if (AR_SREV_9300_20_OR_LATER(ah)) {
931 imr_reg |= AR_IMR_RXOK_HP;
932 if (ah->config.rx_intr_mitigation)
933 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
934 else
935 imr_reg |= AR_IMR_RXOK_LP;
f078f209 936
66860240
VT		 937 } else {
938 if (ah->config.rx_intr_mitigation)
939 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
940 else
941 imr_reg |= AR_IMR_RXOK;
942 }
f078f209 943
66860240
VT		 944 if (ah->config.tx_intr_mitigation)
945 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
946 else
947 imr_reg |= AR_IMR_TXOK;
f078f209 948
7d0d0df0
S		 949 ENABLE_REGWRITE_BUFFER(ah);
950
152d530d 951 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 952 ah->imrs2_reg |= AR_IMR_S2_GTT;
953 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 954
f1dc5600
S		 955 if (!AR_SREV_9100(ah)) {
956 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 957 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 958 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
959 }
66860240 960
7d0d0df0 961 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 962
66860240
VT		 963 if (AR_SREV_9300_20_OR_LATER(ah)) {
964 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
965 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
966 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
967 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
968 }
f078f209
LR		 969}
970
b6ba41bb
FF		 971static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
972{
973 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
974 val = min(val, (u32) 0xFFFF);
975 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
976}
977
8e15e094 978void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 979{
0005baf4
FF		 980 u32 val = ath9k_hw_mac_to_clks(ah, us);
981 val = min(val, (u32) 0xFFFF);
982 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 983}
984
8e15e094 985void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 986{
0005baf4
FF		 987 u32 val = ath9k_hw_mac_to_clks(ah, us);
988 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
989 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
990}
991
8e15e094 992void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
0005baf4
FF		 993{
994 u32 val = ath9k_hw_mac_to_clks(ah, us);
995 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
996 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 997}
f1dc5600 998
cbe61d8a 999static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1000{
f078f209 1001 if (tu > 0xFFFF) {
d2182b69
JP		 1002 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1003 tu);
2660b81a 1004 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1005 return false;
1006 } else {
1007 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1008 ah->globaltxtimeout = tu;
f078f209
LR		 1009 return true;
1010 }
1011}
1012
0005baf4 1013void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1014{
b6ba41bb 1015 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 1016 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1017 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1018 int slottime;
0005baf4 1019 int sifstime;
b6ba41bb
FF		 1020 int rx_lat = 0, tx_lat = 0, eifs = 0;
1021 u32 reg;
0005baf4 1022
d2182b69 1023 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1024 ah->misc_mode);
f078f209 1025
b6ba41bb
FF		 1026 if (!chan)
1027 return;
1028
2660b81a 1029 if (ah->misc_mode != 0)
ca7a4deb 1030 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1031
81a91d57
RM		 1032 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1033 rx_lat = 41;
1034 else
1035 rx_lat = 37;
b6ba41bb
FF		 1036 tx_lat = 54;
1037
e88e4861
FF		 1038 if (IS_CHAN_5GHZ(chan))
1039 sifstime = 16;
1040 else
1041 sifstime = 10;
1042
b6ba41bb
FF		 1043 if (IS_CHAN_HALF_RATE(chan)) {
1044 eifs = 175;
1045 rx_lat *= 2;
1046 tx_lat *= 2;
1047 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1048 tx_lat += 11;
1049
92367fe7 1050 sifstime = 32;
e115b7ec 1051 ack_offset = 16;
b6ba41bb 1052 slottime = 13;
b6ba41bb
FF		 1053 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1054 eifs = 340;
81a91d57 1055 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1056 tx_lat *= 4;
1057 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1058 tx_lat += 22;
1059
92367fe7 1060 sifstime = 64;
e115b7ec 1061 ack_offset = 32;
b6ba41bb 1062 slottime = 21;
b6ba41bb 1063 } else {
a7be039d
RM		 1064 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1065 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1066 reg = AR_USEC_ASYNC_FIFO;
1067 } else {
1068 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1069 common->clockrate;
1070 reg = REG_READ(ah, AR_USEC);
1071 }
b6ba41bb
FF		 1072 rx_lat = MS(reg, AR_USEC_RX_LAT);
1073 tx_lat = MS(reg, AR_USEC_TX_LAT);
1074
1075 slottime = ah->slottime;
b6ba41bb 1076 }
0005baf4 1077
e239d859 1078 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1079 slottime += 3 * ah->coverage_class;
1080 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1081 ctstimeout = acktimeout;
42c4568a
FF		 1082
1083 /*
1084 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1085 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1086 * This was initially only meant to work around an issue with delayed
1087 * BA frames in some implementations, but it has been found to fix ACK
1088 * timeout issues in other cases as well.
1089 */
e4744ec7 1090 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1091 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1092 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1093 ctstimeout += 48 - sifstime - ah->slottime;
1094 }
1095
7aefa8aa
LB		 1096 if (ah->dynack.enabled) {
1097 acktimeout = ah->dynack.ackto;
1098 ctstimeout = acktimeout;
1099 slottime = (acktimeout - 3) / 2;
1100 } else {
1101 ah->dynack.ackto = acktimeout;
1102 }
1103
b6ba41bb
FF		 1104 ath9k_hw_set_sifs_time(ah, sifstime);
1105 ath9k_hw_setslottime(ah, slottime);
0005baf4 1106 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1107 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1108 if (ah->globaltxtimeout != (u32) -1)
1109 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1110
1111 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1112 REG_RMW(ah, AR_USEC,
1113 (common->clockrate - 1) |
1114 SM(rx_lat, AR_USEC_RX_LAT) |
1115 SM(tx_lat, AR_USEC_TX_LAT),
1116 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1117
f1dc5600 1118}
0005baf4 1119EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1120
285f2dda 1121void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1122{
211f5859
LR		 1123 struct ath_common *common = ath9k_hw_common(ah);
1124
736b3a27 1125 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1126 return;
211f5859 1127
9ecdef4b 1128 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1129}
285f2dda 1130EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1131
f1dc5600
S		 1132/*******/
1133/* INI */
1134/*******/
1135
8fe65368 1136u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1137{
1138 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1139
6b21fd20 1140 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1141 ctl |= CTL_11G;
1142 else
1143 ctl |= CTL_11A;
1144
1145 return ctl;
1146}
1147
f1dc5600
S		 1148/****************************************/
1149/* Reset and Channel Switching Routines */
1150/****************************************/
f1dc5600 1151
cbe61d8a 1152static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1153{
57b32227 1154 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1155 int txbuf_size;
f1dc5600 1156
7d0d0df0
S		 1157 ENABLE_REGWRITE_BUFFER(ah);
1158
d7e7d229
LR		 1159 /*
1160 * set AHB_MODE not to do cacheline prefetches
1161 */
ca7a4deb
FF		 1162 if (!AR_SREV_9300_20_OR_LATER(ah))
1163 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1164
d7e7d229
LR		 1165 /*
1166 * let mac dma reads be in 128 byte chunks
1167 */
ca7a4deb 1168 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1169
7d0d0df0 1170 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1171
d7e7d229
LR		 1172 /*
1173 * Restore TX Trigger Level to its pre-reset value.
1174 * The initial value depends on whether aggregation is enabled, and is
1175 * adjusted whenever underruns are detected.
1176 */
57b32227
FF		 1177 if (!AR_SREV_9300_20_OR_LATER(ah))
1178 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1179
7d0d0df0 1180 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1181
d7e7d229
LR		 1182 /*
1183 * let mac dma writes be in 128 byte chunks
1184 */
ca7a4deb 1185 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1186
d7e7d229
LR		 1187 /*
1188 * Setup receive FIFO threshold to hold off TX activities
1189 */
f1dc5600
S		 1190 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1191
57b32227
FF		 1192 if (AR_SREV_9300_20_OR_LATER(ah)) {
1193 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1194 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1195
1196 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1197 ah->caps.rx_status_len);
1198 }
1199
d7e7d229
LR		 1200 /*
1201 * reduce the number of usable entries in PCU TXBUF to avoid
1202 * wrap around issues.
1203 */
f1dc5600 1204 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1205 /* For AR9285 the number of Fifos are reduced to half.
1206 * So set the usable tx buf size also to half to
1207 * avoid data/delimiter underruns
1208 */
86c157b3
FF		 1209 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1210 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1211 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1212 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1213 } else {
1214 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1215 }
744d4025 1216
86c157b3
FF		 1217 if (!AR_SREV_9271(ah))
1218 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1219
7d0d0df0 1220 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1221
744d4025
VT		 1222 if (AR_SREV_9300_20_OR_LATER(ah))
1223 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1224}
1225
cbe61d8a 1226static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1227{
ca7a4deb
FF		 1228 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1229 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1230
7b37e0d4 1231 ENABLE_REG_RMW_BUFFER(ah);
f1dc5600 1232 switch (opmode) {
d97809db 1233 case NL80211_IFTYPE_ADHOC:
83322eb8
FF		 1234 if (!AR_SREV_9340_13(ah)) {
1235 set |= AR_STA_ID1_ADHOC;
1236 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1237 break;
1238 }
1239 /* fall through */
862a336c 1240 case NL80211_IFTYPE_OCB:
2664d666 1241 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1242 case NL80211_IFTYPE_AP:
1243 set |= AR_STA_ID1_STA_AP;
1244 /* fall through */
d97809db 1245 case NL80211_IFTYPE_STATION:
ca7a4deb 1246 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1247 break;
5f841b41 1248 default:
ca7a4deb
FF		 1249 if (!ah->is_monitoring)
1250 set = 0;
5f841b41 1251 break;
f1dc5600 1252 }
ca7a4deb 1253 REG_RMW(ah, AR_STA_ID1, set, mask);
7b37e0d4 1254 REG_RMW_BUFFER_FLUSH(ah);
f1dc5600
S		 1255}
1256
8fe65368
LR		 1257void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1258 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1259{
1260 u32 coef_exp, coef_man;
1261
1262 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1263 if ((coef_scaled >> coef_exp) & 0x1)
1264 break;
1265
1266 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1267
1268 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1269
1270 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1271 *coef_exponent = coef_exp - 16;
1272}
1273
d7df7a55
SM		 1274/* AR9330 WAR:
1275 * call external reset function to reset WMAC if:
1276 * - doing a cold reset
1277 * - we have pending frames in the TX queues.
1278 */
1279static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1280{
1281 int i, npend = 0;
1282
1283 for (i = 0; i < AR_NUM_QCU; i++) {
1284 npend = ath9k_hw_numtxpending(ah, i);
1285 if (npend)
1286 break;
1287 }
1288
1289 if (ah->external_reset &&
1290 (npend || type == ATH9K_RESET_COLD)) {
1291 int reset_err = 0;
1292
1293 ath_dbg(ath9k_hw_common(ah), RESET,
1294 "reset MAC via external reset\n");
1295
1296 reset_err = ah->external_reset();
1297 if (reset_err) {
1298 ath_err(ath9k_hw_common(ah),
1299 "External reset failed, err=%d\n",
1300 reset_err);
1301 return false;
1302 }
1303
1304 REG_WRITE(ah, AR_RTC_RESET, 1);
1305 }
1306
1307 return true;
1308}
1309
cbe61d8a 1310static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1311{
1312 u32 rst_flags;
1313 u32 tmpReg;
1314
70768496 1315 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1316 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1317 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1318 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1319 }
1320
7d0d0df0
S		 1321 ENABLE_REGWRITE_BUFFER(ah);
1322
9a658d2b
LR		 1323 if (AR_SREV_9300_20_OR_LATER(ah)) {
1324 REG_WRITE(ah, AR_WA, ah->WARegVal);
1325 udelay(10);
1326 }
1327
f1dc5600
S		 1328 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1329 AR_RTC_FORCE_WAKE_ON_INT);
1330
1331 if (AR_SREV_9100(ah)) {
1332 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1333 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1334 } else {
1335 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1336 if (AR_SREV_9340(ah))
1337 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1338 else
1339 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1340 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1341
1342 if (tmpReg) {
42d5bc3f 1343 u32 val;
f1dc5600 1344 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1345
1346 val = AR_RC_HOSTIF;
1347 if (!AR_SREV_9300_20_OR_LATER(ah))
1348 val |= AR_RC_AHB;
1349 REG_WRITE(ah, AR_RC, val);
1350
1351 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1352 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1353
1354 rst_flags = AR_RTC_RC_MAC_WARM;
1355 if (type == ATH9K_RESET_COLD)
1356 rst_flags |= AR_RTC_RC_MAC_COLD;
1357 }
1358
7d95847c 1359 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1360 if (!ath9k_hw_ar9330_reset_war(ah, type))
1361 return false;
7d95847c
GJ		 1362 }
1363
3863495b 1364 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1365 ar9003_mci_check_gpm_offset(ah);
3863495b 1366
466b0f02
MP		 1367 /* DMA HALT added to resolve ar9300 and ar9580 bus error during
1368 * RTC_RC reg read
1369 */
1370 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1371 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1372 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1373 20 * AH_WAIT_TIMEOUT);
1374 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1375 }
1376
d03a66c1 1377 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1378
1379 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1380
4dc78c43
SM		 1381 if (AR_SREV_9300_20_OR_LATER(ah))
1382 udelay(50);
1383 else if (AR_SREV_9100(ah))
3683a07b 1384 mdelay(10);
4dc78c43
SM		 1385 else
1386 udelay(100);
f1dc5600 1387
d03a66c1 1388 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1389 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1390 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1391 return false;
1392 }
1393
1394 if (!AR_SREV_9100(ah))
1395 REG_WRITE(ah, AR_RC, 0);
1396
f1dc5600
S		 1397 if (AR_SREV_9100(ah))
1398 udelay(50);
1399
1400 return true;
1401}
1402
cbe61d8a 1403static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1404{
7d0d0df0
S		 1405 ENABLE_REGWRITE_BUFFER(ah);
1406
9a658d2b
LR		 1407 if (AR_SREV_9300_20_OR_LATER(ah)) {
1408 REG_WRITE(ah, AR_WA, ah->WARegVal);
1409 udelay(10);
1410 }
1411
f1dc5600
S		 1412 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1413 AR_RTC_FORCE_WAKE_ON_INT);
1414
42d5bc3f 1415 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1416 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1417
d03a66c1 1418 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1419
7d0d0df0 1420 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1421
afe36533 1422 udelay(2);
84e2169b
SB		 1423
1424 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1425 REG_WRITE(ah, AR_RC, 0);
1426
d03a66c1 1427 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1428
1429 if (!ath9k_hw_wait(ah,
1430 AR_RTC_STATUS,
1431 AR_RTC_STATUS_M,
0caa7b14
S		 1432 AR_RTC_STATUS_ON,
1433 AH_WAIT_TIMEOUT)) {
d2182b69 1434 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1435 return false;
f078f209
LR		 1436 }
1437
f1dc5600
S		 1438 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1439}
1440
cbe61d8a 1441static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1442{
7a9233ff 1443 bool ret = false;
2577c6e8 1444
9a658d2b
LR		 1445 if (AR_SREV_9300_20_OR_LATER(ah)) {
1446 REG_WRITE(ah, AR_WA, ah->WARegVal);
1447 udelay(10);
1448 }
1449
f1dc5600
S		 1450 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1451 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1452
ceb26a60
FF		 1453 if (!ah->reset_power_on)
1454 type = ATH9K_RESET_POWER_ON;
1455
f1dc5600
S		 1456 switch (type) {
1457 case ATH9K_RESET_POWER_ON:
7a9233ff 1458 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1459 if (ret)
ceb26a60 1460 ah->reset_power_on = true;
7a9233ff 1461 break;
f1dc5600
S		 1462 case ATH9K_RESET_WARM:
1463 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1464 ret = ath9k_hw_set_reset(ah, type);
1465 break;
f1dc5600 1466 default:
7a9233ff 1467 break;
f1dc5600 1468 }
7a9233ff 1469
7a9233ff 1470 return ret;
f078f209
LR		 1471}
1472
cbe61d8a 1473static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1474 struct ath9k_channel *chan)
f078f209 1475{
9c083af8
FF		 1476 int reset_type = ATH9K_RESET_WARM;
1477
1478 if (AR_SREV_9280(ah)) {
1479 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1480 reset_type = ATH9K_RESET_POWER_ON;
1481 else
1482 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1483 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1484 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1485 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1486
1487 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1488 return false;
f078f209 1489
9ecdef4b 1490 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1491 return false;
f078f209 1492
2660b81a 1493 ah->chip_fullsleep = false;
bfc441a4
FF		 1494
1495 if (AR_SREV_9330(ah))
1496 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1497 ath9k_hw_init_pll(ah, chan);
f078f209 1498
f1dc5600 1499 return true;
f078f209
LR		 1500}
1501
cbe61d8a 1502static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1503 struct ath9k_channel *chan)
f078f209 1504{
c46917bb 1505 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1506 struct ath9k_hw_capabilities *pCap = &ah->caps;
1507 bool band_switch = false, mode_diff = false;
70e89a71 1508 u8 ini_reloaded = 0;
8fe65368 1509 u32 qnum;
0a3b7bac 1510 int r;
5f0c04ea 1511
b840cffe 1512 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1513 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1514 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1515 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1516 }
f078f209
LR		 1517
1518 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1519 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1520 ath_dbg(common, QUEUE,
226afe68 1521 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1522 return false;
1523 }
1524 }
1525
8fe65368 1526 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1527 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1528 return false;
1529 }
1530
b840cffe 1531 if (band_switch || mode_diff) {
5f0c04ea
RM		 1532 ath9k_hw_mark_phy_inactive(ah);
1533 udelay(5);
1534
5f35c0fa
SM		 1535 if (band_switch)
1536 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1537
1538 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1539 ath_err(common, "Failed to do fast channel change\n");
1540 return false;
1541 }
1542 }
1543
8fe65368 1544 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1545
8fe65368 1546 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1547 if (r) {
3800276a 1548 ath_err(common, "Failed to set channel\n");
0a3b7bac 1549 return false;
f078f209 1550 }
dfdac8ac 1551 ath9k_hw_set_clockrate(ah);
64ea57d0 1552 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1553
81c507a8 1554 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1555 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1556
70e89a71
SM		 1557 if (band_switch || ini_reloaded)
1558 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1559
70e89a71
SM		 1560 ath9k_hw_init_bb(ah, chan);
1561 ath9k_hw_rfbus_done(ah);
5f0c04ea 1562
70e89a71
SM		 1563 if (band_switch || ini_reloaded) {
1564 ah->ah_flags |= AH_FASTCC;
1565 ath9k_hw_init_cal(ah, chan);
a126ff51 1566 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1567 }
1568
f1dc5600
S		 1569 return true;
1570}
1571
691680b8
FF		 1572static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1573{
1574 u32 gpio_mask = ah->gpio_mask;
1575 int i;
1576
1577 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1578 if (!(gpio_mask & 1))
1579 continue;
1580
b2d70d49
MP		 1581 ath9k_hw_gpio_request_out(ah, i, NULL,
1582 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
691680b8 1583 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
db222190 1584 ath9k_hw_gpio_free(ah, i);
691680b8
FF		 1585 }
1586}
1587
1e516ca7
SM		 1588void ath9k_hw_check_nav(struct ath_hw *ah)
1589{
1590 struct ath_common *common = ath9k_hw_common(ah);
1591 u32 val;
1592
1593 val = REG_READ(ah, AR_NAV);
1594 if (val != 0xdeadbeef && val > 0x7fff) {
1595 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1596 REG_WRITE(ah, AR_NAV, 0);
1597 }
1598}
1599EXPORT_SYMBOL(ath9k_hw_check_nav);
1600
c9c99e5e 1601bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1602{
c9c99e5e 1603 int count = 50;
d31a36a6 1604 u32 reg, last_val;
c9c99e5e 1605
01e18918
RM		 1606 if (AR_SREV_9300(ah))
1607 return !ath9k_hw_detect_mac_hang(ah);
1608
e17f83ea 1609 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1610 return true;
1611
d31a36a6 1612 last_val = REG_READ(ah, AR_OBS_BUS_1);
c9c99e5e
FF		 1613 do {
1614 reg = REG_READ(ah, AR_OBS_BUS_1);
d31a36a6
FF		 1615 if (reg != last_val)
1616 return true;
3b319aae 1617
105ff411 1618 udelay(1);
d31a36a6 1619 last_val = reg;
c9c99e5e
FF		 1620 if ((reg & 0x7E7FFFEF) == 0x00702400)
1621 continue;
1622
1623 switch (reg & 0x7E000B00) {
1624 case 0x1E000000:
1625 case 0x52000B00:
1626 case 0x18000B00:
1627 continue;
1628 default:
1629 return true;
1630 }
1631 } while (count-- > 0);
3b319aae 1632
c9c99e5e 1633 return false;
3b319aae 1634}
c9c99e5e 1635EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1636
15d2b585
SM		 1637static void ath9k_hw_init_mfp(struct ath_hw *ah)
1638{
1639 /* Setup MFP options for CCMP */
1640 if (AR_SREV_9280_20_OR_LATER(ah)) {
1641 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1642 * frames when constructing CCMP AAD. */
1643 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1644 0xc7ff);
60fc4962
CYY		 1645 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1646 ah->sw_mgmt_crypto_tx = true;
1647 else
1648 ah->sw_mgmt_crypto_tx = false;
e6510b11 1649 ah->sw_mgmt_crypto_rx = false;
15d2b585
SM		 1650 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1651 /* Disable hardware crypto for management frames */
1652 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1653 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1654 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1655 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
e6510b11
CYY		 1656 ah->sw_mgmt_crypto_tx = true;
1657 ah->sw_mgmt_crypto_rx = true;
15d2b585 1658 } else {
e6510b11
CYY		 1659 ah->sw_mgmt_crypto_tx = true;
1660 ah->sw_mgmt_crypto_rx = true;
15d2b585
SM		 1661 }
1662}
1663
1664static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1665 u32 macStaId1, u32 saveDefAntenna)
1666{
1667 struct ath_common *common = ath9k_hw_common(ah);
1668
1669 ENABLE_REGWRITE_BUFFER(ah);
1670
ecbbed32 1671 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1672 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1673 | ah->sta_id1_defaults,
1674 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1675 ath_hw_setbssidmask(common);
1676 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1677 ath9k_hw_write_associd(ah);
1678 REG_WRITE(ah, AR_ISR, ~0);
1679 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1680
1681 REGWRITE_BUFFER_FLUSH(ah);
1682
1683 ath9k_hw_set_operating_mode(ah, ah->opmode);
1684}
1685
1686static void ath9k_hw_init_queues(struct ath_hw *ah)
1687{
1688 int i;
1689
1690 ENABLE_REGWRITE_BUFFER(ah);
1691
1692 for (i = 0; i < AR_NUM_DCU; i++)
1693 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1694
1695 REGWRITE_BUFFER_FLUSH(ah);
1696
1697 ah->intr_txqs = 0;
1698 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1699 ath9k_hw_resettxqueue(ah, i);
1700}
1701
1702/*
1703 * For big endian systems turn on swapping for descriptors
1704 */
1705static void ath9k_hw_init_desc(struct ath_hw *ah)
1706{
1707 struct ath_common *common = ath9k_hw_common(ah);
1708
1709 if (AR_SREV_9100(ah)) {
1710 u32 mask;
1711 mask = REG_READ(ah, AR_CFG);
1712 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1713 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1714 mask);
1715 } else {
1716 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1717 REG_WRITE(ah, AR_CFG, mask);
1718 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1719 REG_READ(ah, AR_CFG));
1720 }
1721 } else {
1722 if (common->bus_ops->ath_bus_type == ATH_USB) {
1723 /* Configure AR9271 target WLAN */
1724 if (AR_SREV_9271(ah))
1725 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1726 else
1727 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1728 }
1729#ifdef __BIG_ENDIAN
1730 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
ede6a5e7
MP		 1731 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1732 AR_SREV_9561(ah))
15d2b585
SM		 1733 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1734 else
1735 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1736#endif
1737 }
1738}
1739
caed6579
SM		 1740/*
1741 * Fast channel change:
1742 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1743 */
1744static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1745{
1746 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1747 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1748 int ret;
1749
1750 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1751 goto fail;
1752
1753 if (ah->chip_fullsleep)
1754 goto fail;
1755
1756 if (!ah->curchan)
1757 goto fail;
1758
1759 if (chan->channel == ah->curchan->channel)
1760 goto fail;
1761
feb7bc99
FF		 1762 if ((ah->curchan->channelFlags | chan->channelFlags) &
1763 (CHANNEL_HALF | CHANNEL_QUARTER))
1764 goto fail;
1765
b840cffe 1766 /*
6b21fd20 1767 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1768 */
6b21fd20 1769 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1770 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1771 goto fail;
caed6579
SM		 1772
1773 if (!ath9k_hw_check_alive(ah))
1774 goto fail;
1775
1776 /*
1777 * For AR9462, make sure that calibration data for
1778 * re-using are present.
1779 */
8a90555f 1780 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1781 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1782 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1783 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1784 goto fail;
1785
1786 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1787 ah->curchan->channel, chan->channel);
1788
1789 ret = ath9k_hw_channel_change(ah, chan);
1790 if (!ret)
1791 goto fail;
1792
5955b2b0 1793 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1794 ar9003_mci_2g5g_switch(ah, false);
caed6579 1795
88033318
RM		 1796 ath9k_hw_loadnf(ah, ah->curchan);
1797 ath9k_hw_start_nfcal(ah, true);
1798
caed6579
SM		 1799 if (AR_SREV_9271(ah))
1800 ar9002_hw_load_ani_reg(ah, chan);
1801
1802 return 0;
1803fail:
1804 return -EINVAL;
1805}
1806
8d7e09dd
FF		 1807u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1808{
1809 struct timespec ts;
1810 s64 usec;
1811
1812 if (!cur) {
1813 getrawmonotonic(&ts);
1814 cur = &ts;
1815 }
1816
1817 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1818 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1819
1820 return (u32) usec;
1821}
1822EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1823
cbe61d8a 1824int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1825 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1826{
1510718d 1827 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1828 u32 saveLedState;
f078f209
LR		 1829 u32 saveDefAntenna;
1830 u32 macStaId1;
bec9a94b
BB		 1831 struct timespec tsf_ts;
1832 u32 tsf_offset;
46fe782c 1833 u64 tsf = 0;
15d2b585 1834 int r;
caed6579 1835 bool start_mci_reset = false;
63d32967
MSS		 1836 bool save_fullsleep = ah->chip_fullsleep;
1837
5955b2b0 1838 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1839 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1840 if (start_mci_reset)
1841 return 0;
63d32967
MSS		 1842 }
1843
9ecdef4b 1844 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1845 return -EIO;
f078f209 1846
caed6579
SM		 1847 if (ah->curchan && !ah->chip_fullsleep)
1848 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1849
20bd2a09 1850 ah->caldata = caldata;
fcb9a3de 1851 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1852 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1853 /* Operating channel changed, reset channel calibration data */
1854 memset(caldata, 0, sizeof(*caldata));
1855 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1856 } else if (caldata) {
4b9b42bf 1857 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1858 }
5bc225ac 1859 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1860
caed6579
SM		 1861 if (fastcc) {
1862 r = ath9k_hw_do_fastcc(ah, chan);
1863 if (!r)
1864 return r;
f078f209
LR		 1865 }
1866
5955b2b0 1867 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1868 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1869
f078f209
LR		 1870 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1871 if (saveDefAntenna == 0)
1872 saveDefAntenna = 1;
1873
1874 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1875
09d8e315 1876 /* Save TSF before chip reset, a cold reset clears it */
bec9a94b 1877 getrawmonotonic(&tsf_ts);
09d8e315 1878 tsf = ath9k_hw_gettsf64(ah);
46fe782c 1879
f078f209
LR		 1880 saveLedState = REG_READ(ah, AR_CFG_LED) &
1881 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1882 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1883
1884 ath9k_hw_mark_phy_inactive(ah);
1885
45ef6a0b
VT		 1886 ah->paprd_table_write_done = false;
1887
05020d23 1888 /* Only required on the first reset */
d7e7d229
LR		 1889 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1890 REG_WRITE(ah,
1891 AR9271_RESET_POWER_DOWN_CONTROL,
1892 AR9271_RADIO_RF_RST);
1893 udelay(50);
1894 }
1895
f078f209 1896 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1897 ath_err(common, "Chip reset failed\n");
ae8d2858 1898 return -EINVAL;
f078f209
LR		 1899 }
1900
05020d23 1901 /* Only required on the first reset */
d7e7d229
LR		 1902 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1903 ah->htc_reset_init = false;
1904 REG_WRITE(ah,
1905 AR9271_RESET_POWER_DOWN_CONTROL,
1906 AR9271_GATE_MAC_CTL);
1907 udelay(50);
1908 }
1909
46fe782c 1910 /* Restore TSF */
bec9a94b
BB		 1911 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1912 ath9k_hw_settsf64(ah, tsf + tsf_offset);
46fe782c 1913
7a37081e 1914 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1915 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1916
e9141f71
S		 1917 if (!AR_SREV_9300_20_OR_LATER(ah))
1918 ar9002_hw_enable_async_fifo(ah);
1919
25c56eec 1920 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1921 if (r)
1922 return r;
f078f209 1923
935d00cc
LB		 1924 ath9k_hw_set_rfmode(ah, chan);
1925
5955b2b0 1926 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1927 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1928
f860d526
FF		 1929 /*
1930 * Some AR91xx SoC devices frequently fail to accept TSF writes
1931 * right after the chip reset. When that happens, write a new
bec9a94b 1932 * value after the initvals have been applied.
f860d526
FF		 1933 */
1934 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
bec9a94b
BB		 1935 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1936 ath9k_hw_settsf64(ah, tsf + tsf_offset);
f860d526
FF		 1937 }
1938
15d2b585 1939 ath9k_hw_init_mfp(ah);
0ced0e17 1940
81c507a8 1941 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1942 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1943 ah->eep_ops->set_board_values(ah, chan);
a7765828 1944
15d2b585 1945 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1946
8fe65368 1947 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1948 if (r)
1949 return r;
f078f209 1950
dfdac8ac
FF		 1951 ath9k_hw_set_clockrate(ah);
1952
15d2b585 1953 ath9k_hw_init_queues(ah);
2660b81a 1954 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1955 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1956 ath9k_hw_init_qos(ah);
1957
2660b81a 1958 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
b2d70d49 1959 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
3b319aae 1960
0005baf4 1961 ath9k_hw_init_global_settings(ah);
f078f209 1962
fe2b6afb
FF		 1963 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1964 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1965 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1966 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1967 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1968 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1969 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1970 }
1971
ca7a4deb 1972 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1973
1974 ath9k_hw_set_dma(ah);
1975
ed6ebd8b
RM		 1976 if (!ath9k_hw_mci_is_enabled(ah))
1977 REG_WRITE(ah, AR_OBS, 8);
f078f209 1978
7b37e0d4 1979 ENABLE_REG_RMW_BUFFER(ah);
0ce024cb 1980 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 1981 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1982 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 1983 }
1984
7f62a136
VT		 1985 if (ah->config.tx_intr_mitigation) {
1986 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1987 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1988 }
7b37e0d4 1989 REG_RMW_BUFFER_FLUSH(ah);
7f62a136 1990
f078f209
LR		 1991 ath9k_hw_init_bb(ah, chan);
1992
77a5a664 1993 if (caldata) {
4b9b42bf
SM		 1994 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1995 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1996 }
ae8d2858 1997 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1998 return -EIO;
f078f209 1999
5955b2b0 2000 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 2001 return -EIO;
63d32967 2002
7d0d0df0 2003 ENABLE_REGWRITE_BUFFER(ah);
f078f209 2004
8fe65368 2005 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 2006 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2007
7d0d0df0 2008 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2009
f4c34af4
SM		 2010 ath9k_hw_gen_timer_start_tsf2(ah);
2011
15d2b585 2012 ath9k_hw_init_desc(ah);
f078f209 2013
dbccdd1d 2014 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2015 ath9k_hw_btcoex_enable(ah);
2016
5955b2b0 2017 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2018 ar9003_mci_check_bt(ah);
63d32967 2019
7b89fccf
FF		 2020 if (AR_SREV_9300_20_OR_LATER(ah)) {
2021 ath9k_hw_loadnf(ah, chan);
2022 ath9k_hw_start_nfcal(ah, true);
2023 }
1fe860ed 2024
a7abaf7d 2025 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 2026 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 2027
2028 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 2029 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 2030
691680b8
FF		 2031 ath9k_hw_apply_gpio_override(ah);
2032
7bdea96a 2033 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 2034 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2035
4307b0fe
LB		 2036 if (ah->hw->conf.radar_enabled) {
2037 /* set HW specific DFS configuration */
7a0a260a 2038 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
4307b0fe
LB		 2039 ath9k_hw_set_radar_params(ah);
2040 }
2041
ae8d2858 2042 return 0;
f078f209 2043}
7322fd19 2044EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2045
f1dc5600
S		 2046/******************************/
2047/* Power Management (Chipset) */
2048/******************************/
2049
42d5bc3f
LR		 2050/*
2051 * Notify Power Mgt is disabled in self-generated frames.
2052 * If requested, force chip to sleep.
2053 */
31604cf0 2054static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2055{
f1dc5600 2056 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2057
a4a2954f 2058 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2059 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2060 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2061 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2062 /* xxx Required for WLAN only case ? */
2063 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2064 udelay(100);
2065 }
2577c6e8 2066
31604cf0
SM		 2067 /*
2068 * Clear the RTC force wake bit to allow the
2069 * mac to go to sleep.
2070 */
2071 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2072
153dccd4 2073 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2074 udelay(100);
2577c6e8 2075
31604cf0
SM		 2076 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2077 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2078
31604cf0
SM		 2079 /* Shutdown chip. Active low */
2080 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2081 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2082 udelay(2);
f1dc5600 2083 }
9a658d2b
LR		 2084
2085 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2086 if (AR_SREV_9300_20_OR_LATER(ah))
2087 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2088}
2089
bbd79af5
LR		 2090/*
2091 * Notify Power Management is enabled in self-generating
2092 * frames. If request, set power mode of chip to
2093 * auto/normal. Duration in units of 128us (1/8 TU).
2094 */
31604cf0 2095static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2096{
31604cf0 2097 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2098
f1dc5600 2099 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2100
31604cf0
SM		 2101 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2102 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2103 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2104 AR_RTC_FORCE_WAKE_ON_INT);
2105 } else {
2577c6e8 2106
31604cf0
SM		 2107 /* When chip goes into network sleep, it could be waken
2108 * up by MCI_INT interrupt caused by BT's HW messages
2109 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2110 * rate (~100us). This will cause chip to leave and
2111 * re-enter network sleep mode frequently, which in
2112 * consequence will have WLAN MCI HW to generate lots of
2113 * SYS_WAKING and SYS_SLEEPING messages which will make
2114 * BT CPU to busy to process.
2115 */
153dccd4
RM		 2116 if (ath9k_hw_mci_is_enabled(ah))
2117 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2118 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2119 /*
2120 * Clear the RTC force wake bit to allow the
2121 * mac to go to sleep.
2122 */
153dccd4 2123 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2124
153dccd4 2125 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2126 udelay(30);
f078f209 2127 }
9a658d2b
LR		 2128
2129 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2130 if (AR_SREV_9300_20_OR_LATER(ah))
2131 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2132}
2133
31604cf0 2134static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2135{
f1dc5600
S		 2136 u32 val;
2137 int i;
f078f209 2138
9a658d2b
LR		 2139 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2140 if (AR_SREV_9300_20_OR_LATER(ah)) {
2141 REG_WRITE(ah, AR_WA, ah->WARegVal);
2142 udelay(10);
2143 }
2144
31604cf0
SM		 2145 if ((REG_READ(ah, AR_RTC_STATUS) &
2146 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2147 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2148 return false;
f1dc5600 2149 }
31604cf0
SM		 2150 if (!AR_SREV_9300_20_OR_LATER(ah))
2151 ath9k_hw_init_pll(ah, NULL);
2152 }
2153 if (AR_SREV_9100(ah))
2154 REG_SET_BIT(ah, AR_RTC_RESET,
2155 AR_RTC_RESET_EN);
2156
2157 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2158 AR_RTC_FORCE_WAKE_EN);
04575f21 2159 if (AR_SREV_9100(ah))
3683a07b 2160 mdelay(10);
04575f21
SM		 2161 else
2162 udelay(50);
f078f209 2163
31604cf0
SM		 2164 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2165 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2166 if (val == AR_RTC_STATUS_ON)
2167 break;
2168 udelay(50);
f1dc5600
S		 2169 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2170 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2171 }
2172 if (i == 0) {
2173 ath_err(ath9k_hw_common(ah),
2174 "Failed to wakeup in %uus\n",
2175 POWER_UP_TIME / 20);
2176 return false;
f078f209
LR		 2177 }
2178
cdbe408d
RM		 2179 if (ath9k_hw_mci_is_enabled(ah))
2180 ar9003_mci_set_power_awake(ah);
2181
f1dc5600 2182 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2183
f1dc5600 2184 return true;
f078f209
LR		 2185}
2186
9ecdef4b 2187bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2188{
c46917bb 2189 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2190 int status = true;
f1dc5600
S		 2191 static const char *modes[] = {
2192 "AWAKE",
2193 "FULL-SLEEP",
2194 "NETWORK SLEEP",
2195 "UNDEFINED"
2196 };
f1dc5600 2197
cbdec975
GJ		 2198 if (ah->power_mode == mode)
2199 return status;
2200
d2182b69 2201 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2202 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2203
2204 switch (mode) {
2205 case ATH9K_PM_AWAKE:
31604cf0 2206 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2207 break;
2208 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2209 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2210 ar9003_mci_set_full_sleep(ah);
1010911e 2211
31604cf0 2212 ath9k_set_power_sleep(ah);
2660b81a 2213 ah->chip_fullsleep = true;
f1dc5600
S		 2214 break;
2215 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2216 ath9k_set_power_network_sleep(ah);
f1dc5600 2217 break;
f078f209 2218 default:
3800276a 2219 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2220 return false;
2221 }
2660b81a 2222 ah->power_mode = mode;
f1dc5600 2223
69f4aab1
LR		 2224 /*
2225 * XXX: If this warning never comes up after a while then
2226 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2227 * ath9k_hw_setpower() return type void.
2228 */
97dcec57
SM		 2229
2230 if (!(ah->ah_flags & AH_UNPLUGGED))
2231 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2232
f1dc5600 2233 return status;
f078f209 2234}
7322fd19 2235EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2236
f1dc5600
S		 2237/*******************/
2238/* Beacon Handling */
2239/*******************/
2240
cbe61d8a 2241void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2242{
f078f209
LR		 2243 int flags = 0;
2244
7d0d0df0
S		 2245 ENABLE_REGWRITE_BUFFER(ah);
2246
2660b81a 2247 switch (ah->opmode) {
d97809db 2248 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2249 REG_SET_BIT(ah, AR_TXCFG,
2250 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2251 case NL80211_IFTYPE_MESH_POINT:
d97809db 2252 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2253 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2254 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2255 TU_TO_USEC(ah->config.dma_beacon_response_time));
2256 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2257 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2258 flags |=
2259 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2260 break;
d97809db 2261 default:
d2182b69
JP		 2262 ath_dbg(ath9k_hw_common(ah), BEACON,
2263 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2264 return;
2265 break;
f078f209
LR		 2266 }
2267
dd347f2f
FF		 2268 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2269 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2270 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2271
7d0d0df0 2272 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2273
f078f209
LR		 2274 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2275}
7322fd19 2276EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2277
cbe61d8a 2278void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2279 const struct ath9k_beacon_state *bs)
f078f209
LR		 2280{
2281 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2282 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2283 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2284
7d0d0df0
S		 2285 ENABLE_REGWRITE_BUFFER(ah);
2286
4ed15762
FF		 2287 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2288 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2289 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2290
7d0d0df0 2291 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2292
f078f209
LR		 2293 REG_RMW_FIELD(ah, AR_RSSI_THR,
2294 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2295
f29f5c08 2296 beaconintval = bs->bs_intval;
f078f209
LR		 2297
2298 if (bs->bs_sleepduration > beaconintval)
2299 beaconintval = bs->bs_sleepduration;
2300
2301 dtimperiod = bs->bs_dtimperiod;
2302 if (bs->bs_sleepduration > dtimperiod)
2303 dtimperiod = bs->bs_sleepduration;
2304
2305 if (beaconintval == dtimperiod)
2306 nextTbtt = bs->bs_nextdtim;
2307 else
2308 nextTbtt = bs->bs_nexttbtt;
2309
58bb9ca8
JD		 2310 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);
2311 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);
2312 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);
2313 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);
f078f209 2314
7d0d0df0
S		 2315 ENABLE_REGWRITE_BUFFER(ah);
2316
4ed15762
FF		 2317 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2318 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2319
f1dc5600
S		 2320 REG_WRITE(ah, AR_SLEEP1,
2321 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2322 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2323
f1dc5600
S		 2324 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2325 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2326 else
2327 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2328
f1dc5600
S		 2329 REG_WRITE(ah, AR_SLEEP2,
2330 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2331
4ed15762
FF		 2332 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2333 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2334
7d0d0df0 2335 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2336
f1dc5600
S		 2337 REG_SET_BIT(ah, AR_TIMER_MODE,
2338 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2339 AR_DTIM_TIMER_EN);
f078f209 2340
4af9cf4f
S		 2341 /* TSF Out of Range Threshold */
2342 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2343}
7322fd19 2344EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2345
f1dc5600
S		 2346/*******************/
2347/* HW Capabilities */
2348/*******************/
2349
6054069a
FF		 2350static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2351{
2352 eeprom_chainmask &= chip_chainmask;
2353 if (eeprom_chainmask)
2354 return eeprom_chainmask;
2355 else
2356 return chip_chainmask;
2357}
2358
9a66af33
ZK		 2359/**
2360 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2361 * @ah: the atheros hardware data structure
2362 *
2363 * We enable DFS support upstream on chipsets which have passed a series
2364 * of tests. The testing requirements are going to be documented. Desired
2365 * test requirements are documented at:
2366 *
2367 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2368 *
2369 * Once a new chipset gets properly tested an individual commit can be used
2370 * to document the testing for DFS for that chipset.
2371 */
2372static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2373{
2374
2375 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2376 /* for temporary testing DFS with 9280 */
2377 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2378 /* AR9580 will likely be our first target to get testing on */
2379 case AR_SREV_VERSION_9580:
73e4937d 2380 return true;
9a66af33
ZK		 2381 default:
2382 return false;
2383 }
2384}
2385
a01ab81b
MP		 2386static void ath9k_gpio_cap_init(struct ath_hw *ah)
2387{
2388 struct ath9k_hw_capabilities *pCap = &ah->caps;
2389
2390 if (AR_SREV_9271(ah)) {
2391 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2392 pCap->gpio_mask = AR9271_GPIO_MASK;
2393 } else if (AR_DEVID_7010(ah)) {
2394 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2395 pCap->gpio_mask = AR7010_GPIO_MASK;
2396 } else if (AR_SREV_9287(ah)) {
2397 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2398 pCap->gpio_mask = AR9287_GPIO_MASK;
2399 } else if (AR_SREV_9285(ah)) {
2400 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2401 pCap->gpio_mask = AR9285_GPIO_MASK;
2402 } else if (AR_SREV_9280(ah)) {
2403 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2404 pCap->gpio_mask = AR9280_GPIO_MASK;
2405 } else if (AR_SREV_9300(ah)) {
2406 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2407 pCap->gpio_mask = AR9300_GPIO_MASK;
2408 } else if (AR_SREV_9330(ah)) {
2409 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2410 pCap->gpio_mask = AR9330_GPIO_MASK;
2411 } else if (AR_SREV_9340(ah)) {
2412 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2413 pCap->gpio_mask = AR9340_GPIO_MASK;
2414 } else if (AR_SREV_9462(ah)) {
2415 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2416 pCap->gpio_mask = AR9462_GPIO_MASK;
2417 } else if (AR_SREV_9485(ah)) {
2418 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2419 pCap->gpio_mask = AR9485_GPIO_MASK;
2420 } else if (AR_SREV_9531(ah)) {
2421 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2422 pCap->gpio_mask = AR9531_GPIO_MASK;
2423 } else if (AR_SREV_9550(ah)) {
2424 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2425 pCap->gpio_mask = AR9550_GPIO_MASK;
2426 } else if (AR_SREV_9561(ah)) {
2427 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2428 pCap->gpio_mask = AR9561_GPIO_MASK;
2429 } else if (AR_SREV_9565(ah)) {
2430 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2431 pCap->gpio_mask = AR9565_GPIO_MASK;
2432 } else if (AR_SREV_9580(ah)) {
2433 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2434 pCap->gpio_mask = AR9580_GPIO_MASK;
2435 } else {
2436 pCap->num_gpio_pins = AR_NUM_GPIO;
2437 pCap->gpio_mask = AR_GPIO_MASK;
2438 }
2439}
2440
a9a29ce6 2441int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2442{
2660b81a 2443 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2445 struct ath_common *common = ath9k_hw_common(ah);
608b88cb 2446
0ff2b5c0 2447 u16 eeval;
47c80de6 2448 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2449
f74df6fb 2450 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2451 regulatory->current_rd = eeval;
f078f209 2452
2660b81a 2453 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2454 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2455 if (regulatory->current_rd == 0x64 ||
2456 regulatory->current_rd == 0x65)
2457 regulatory->current_rd += 5;
2458 else if (regulatory->current_rd == 0x41)
2459 regulatory->current_rd = 0x43;
d2182b69
JP		 2460 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2461 regulatory->current_rd);
f1dc5600 2462 }
f078f209 2463
f74df6fb 2464 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3468968e
FF		 2465
2466 if (eeval & AR5416_OPFLAGS_11A) {
2467 if (ah->disable_5ghz)
2468 ath_warn(common, "disabling 5GHz band\n");
2469 else
2470 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
a9a29ce6
GJ		 2471 }
2472
3468968e
FF		 2473 if (eeval & AR5416_OPFLAGS_11G) {
2474 if (ah->disable_2ghz)
2475 ath_warn(common, "disabling 2GHz band\n");
2476 else
2477 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2478 }
f078f209 2479
3468968e
FF		 2480 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2481 ath_err(common, "both bands are disabled\n");
2482 return -EINVAL;
2483 }
f1dc5600 2484
db7b542e
MP		 2485 ath9k_gpio_cap_init(ah);
2486
e41db61d
SM		 2487 if (AR_SREV_9485(ah) ||
2488 AR_SREV_9285(ah) ||
2489 AR_SREV_9330(ah) ||
2490 AR_SREV_9565(ah))
ee79ccd9 2491 pCap->chip_chainmask = 1;
6054069a 2492 else if (!AR_SREV_9280_20_OR_LATER(ah))
ee79ccd9
SM		 2493 pCap->chip_chainmask = 7;
2494 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2495 AR_SREV_9340(ah) ||
2496 AR_SREV_9462(ah) ||
2497 AR_SREV_9531(ah))
2498 pCap->chip_chainmask = 3;
6054069a 2499 else
ee79ccd9 2500 pCap->chip_chainmask = 7;
6054069a 2501
f74df6fb 2502 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2503 /*
2504 * For AR9271 we will temporarilly uses the rx chainmax as read from
2505 * the EEPROM.
2506 */
8147f5de 2507 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2508 !(eeval & AR5416_OPFLAGS_11A) &&
2509 !(AR_SREV_9271(ah)))
2510 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2511 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2512 else if (AR_SREV_9100(ah))
2513 pCap->rx_chainmask = 0x7;
8147f5de 2514 else
d7e7d229 2515 /* Use rx_chainmask from EEPROM. */
8147f5de 2516 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2517
ee79ccd9
SM		 2518 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2519 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2520 ah->txchainmask = pCap->tx_chainmask;
2521 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2522
7a37081e 2523 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2524
02d2ebb2
FF		 2525 /* enable key search for every frame in an aggregate */
2526 if (AR_SREV_9300_20_OR_LATER(ah))
2527 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2528
ce2220d1
BR		 2529 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2530
0db156e9 2531 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2532 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2533 else
2534 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2535
1b2538b2 2536 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2537 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2538 else
f1dc5600 2539 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2540
74e13060 2541#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2542 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2543 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2544 ah->rfkill_gpio =
2545 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2546 ah->rfkill_polarity =
2547 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2548
2549 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2550 }
f1dc5600 2551#endif
d5d1154f 2552 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2553 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2554 else
2555 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2556
e7594072 2557 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2558 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2559 else
2560 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2561
ceb26445 2562 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2563 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
ede6a5e7
MP		 2564 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2565 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2566 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2567
ceb26445
VT		 2568 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2569 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2570 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2571 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2572 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2573 } else {
2574 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2575 if (AR_SREV_9280_20(ah))
6b42e8d0 2576 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2577 }
1adf02ff 2578
6c84ce08
VT		 2579 if (AR_SREV_9300_20_OR_LATER(ah))
2580 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2581
ede6a5e7
MP		 2582 if (AR_SREV_9561(ah))
2583 ah->ent_mode = 0x3BDA000;
2584 else if (AR_SREV_9300_20_OR_LATER(ah))
6ee63f55
SB		 2585 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2586
a42acef0 2587 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2588 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2589
f85c3371 2590 if (AR_SREV_9285(ah)) {
754dc536
VT		 2591 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2592 ant_div_ctl1 =
2593 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2594 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2595 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2596 ath_info(common, "Enable LNA combining\n");
2597 }
754dc536 2598 }
f85c3371
SM		 2599 }
2600
ea066d5a
MSS		 2601 if (AR_SREV_9300_20_OR_LATER(ah)) {
2602 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2603 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2604 }
2605
06236e53 2606 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2607 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2608 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2609 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2610 ath_info(common, "Enable LNA combining\n");
2611 }
21d2c63a 2612 }
754dc536 2613
9a66af33
ZK		 2614 if (ath9k_hw_dfs_tested(ah))
2615 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2616
47c80de6
VT		 2617 tx_chainmask = pCap->tx_chainmask;
2618 rx_chainmask = pCap->rx_chainmask;
2619 while (tx_chainmask || rx_chainmask) {
2620 if (tx_chainmask & BIT(0))
2621 pCap->max_txchains++;
2622 if (rx_chainmask & BIT(0))
2623 pCap->max_rxchains++;
2624
2625 tx_chainmask >>= 1;
2626 rx_chainmask >>= 1;
2627 }
2628
a4a2954f 2629 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2630 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2631 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2632
2b5e54e2 2633 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2634 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2635 }
2636
0f21ee8d
SM		 2637 if (AR_SREV_9300_20_OR_LATER(ah) &&
2638 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2639 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2640
12a44422
SM		 2641#ifdef CONFIG_ATH9K_WOW
2642 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2643 ah->wow.max_patterns = MAX_NUM_PATTERN;
2644 else
2645 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2646#endif
2647
a9a29ce6 2648 return 0;
f078f209
LR		 2649}
2650
f1dc5600
S		 2651/****************************/
2652/* GPIO / RFKILL / Antennae */
2653/****************************/
f078f209 2654
b2d70d49 2655static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
f1dc5600
S		 2656{
2657 int addr;
2658 u32 gpio_shift, tmp;
f078f209 2659
f1dc5600
S		 2660 if (gpio > 11)
2661 addr = AR_GPIO_OUTPUT_MUX3;
2662 else if (gpio > 5)
2663 addr = AR_GPIO_OUTPUT_MUX2;
2664 else
2665 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2666
f1dc5600 2667 gpio_shift = (gpio % 6) * 5;
f078f209 2668
b2d70d49
MP		 2669 if (AR_SREV_9280_20_OR_LATER(ah) ||
2670 (addr != AR_GPIO_OUTPUT_MUX1)) {
f1dc5600
S		 2671 REG_RMW(ah, addr, (type << gpio_shift),
2672 (0x1f << gpio_shift));
f078f209 2673 } else {
f1dc5600
S		 2674 tmp = REG_READ(ah, addr);
2675 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2676 tmp &= ~(0x1f << gpio_shift);
2677 tmp |= (type << gpio_shift);
2678 REG_WRITE(ah, addr, tmp);
f078f209 2679 }
f078f209
LR		 2680}
2681
b2d70d49
MP		 2682/* BSP should set the corresponding MUX register correctly.
2683 */
2684static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2685 const char *label)
f078f209 2686{
b2d70d49
MP		 2687 if (ah->caps.gpio_requested & BIT(gpio))
2688 return;
f078f209 2689
b2d70d49
MP		 2690 /* may be requested by BSP, free anyway */
2691 gpio_free(gpio);
f078f209 2692
b2d70d49 2693 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label))
88c1f4f6 2694 return;
f078f209 2695
b2d70d49 2696 ah->caps.gpio_requested |= BIT(gpio);
f078f209
LR		 2697}
2698
b2d70d49
MP		 2699static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2700 u32 ah_signal_type)
f078f209 2701{
b2d70d49 2702 u32 gpio_set, gpio_shift = gpio;
f078f209 2703
88c1f4f6 2704 if (AR_DEVID_7010(ah)) {
b2d70d49
MP		 2705 gpio_set = out ?
2706 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;
2707 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2708 AR7010_GPIO_OE_MASK << gpio_shift);
2709 } else if (AR_SREV_SOC(ah)) {
2710 gpio_set = out ? 1 : 0;
2711 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2712 gpio_set << gpio_shift);
2713 } else {
2714 gpio_shift = gpio << 1;
2715 gpio_set = out ?
2716 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;
2717 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2718 AR_GPIO_OE_OUT_DRV << gpio_shift);
2719
2720 if (out)
2721 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2722 }
f078f209
LR		 2723}
2724
b2d70d49
MP		 2725static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2726 const char *label, u32 ah_signal_type)
f078f209 2727{
b2d70d49 2728 WARN_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2729
b2d70d49
MP		 2730 if (BIT(gpio) & ah->caps.gpio_mask)
2731 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2732 else if (AR_SREV_SOC(ah))
2733 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2734 else
2735 WARN_ON(1);
2736}
f078f209 2737
b2d70d49
MP		 2738void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2739{
2740 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
f078f209 2741}
b2d70d49 2742EXPORT_SYMBOL(ath9k_hw_gpio_request_in);
f078f209 2743
b2d70d49
MP		 2744void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2745 u32 ah_signal_type)
f078f209 2746{
b2d70d49
MP		 2747 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2748}
2749EXPORT_SYMBOL(ath9k_hw_gpio_request_out);
2750
2751void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2752{
2753 if (!AR_SREV_SOC(ah))
88c1f4f6 2754 return;
b2d70d49
MP		 2755
2756 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2757
2758 if (ah->caps.gpio_requested & BIT(gpio)) {
2759 gpio_free(gpio);
2760 ah->caps.gpio_requested &= ~BIT(gpio);
88c1f4f6 2761 }
b2d70d49
MP		 2762}
2763EXPORT_SYMBOL(ath9k_hw_gpio_free);
88c1f4f6 2764
b2d70d49
MP		 2765u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2766{
2767 u32 val = 0xffffffff;
5b5fa355 2768
b2d70d49
MP		 2769#define MS_REG_READ(x, y) \
2770 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y))
2771
2772 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2773
2774 if (BIT(gpio) & ah->caps.gpio_mask) {
2775 if (AR_SREV_9271(ah))
2776 val = MS_REG_READ(AR9271, gpio);
2777 else if (AR_SREV_9287(ah))
2778 val = MS_REG_READ(AR9287, gpio);
2779 else if (AR_SREV_9285(ah))
2780 val = MS_REG_READ(AR9285, gpio);
2781 else if (AR_SREV_9280(ah))
2782 val = MS_REG_READ(AR928X, gpio);
2783 else if (AR_DEVID_7010(ah))
2784 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2785 else if (AR_SREV_9300_20_OR_LATER(ah))
2786 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio);
2787 else
2788 val = MS_REG_READ(AR, gpio);
2789 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2790 val = gpio_get_value(gpio) & BIT(gpio);
2791 } else {
2792 WARN_ON(1);
2793 }
2794
2795 return val;
f078f209 2796}
b2d70d49 2797EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2798
b2d70d49 2799void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
61b559de 2800{
b2d70d49 2801 WARN_ON(gpio >= ah->caps.num_gpio_pins);
61b559de 2802
b2d70d49
MP		 2803 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2804 val = !val;
2805 else
2806 val = !!val;
2807
2808 if (BIT(gpio) & ah->caps.gpio_mask) {
2809 u32 out_addr = AR_DEVID_7010(ah) ?
2810 AR7010_GPIO_OUT : AR_GPIO_IN_OUT;
2811
2812 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2813 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2814 gpio_set_value(gpio, val);
2815 } else {
2816 WARN_ON(1);
2817 }
61b559de 2818}
b2d70d49 2819EXPORT_SYMBOL(ath9k_hw_set_gpio);
61b559de 2820
cbe61d8a 2821void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2822{
f1dc5600 2823 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2824}
7322fd19 2825EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2826
f1dc5600
S		 2827/*********************/
2828/* General Operation */
2829/*********************/
2830
cbe61d8a 2831u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2832{
f1dc5600
S		 2833 u32 bits = REG_READ(ah, AR_RX_FILTER);
2834 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2835
f1dc5600
S		 2836 if (phybits & AR_PHY_ERR_RADAR)
2837 bits |= ATH9K_RX_FILTER_PHYRADAR;
2838 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2839 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2840
f1dc5600 2841 return bits;
f078f209 2842}
7322fd19 2843EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2844
cbe61d8a 2845void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2846{
f1dc5600 2847 u32 phybits;
f078f209 2848
7d0d0df0
S		 2849 ENABLE_REGWRITE_BUFFER(ah);
2850
7ea310be
S		 2851 REG_WRITE(ah, AR_RX_FILTER, bits);
2852
f1dc5600
S		 2853 phybits = 0;
2854 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2855 phybits |= AR_PHY_ERR_RADAR;
2856 if (bits & ATH9K_RX_FILTER_PHYERR)
2857 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2858 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2859
f1dc5600 2860 if (phybits)
ca7a4deb 2861 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2862 else
ca7a4deb 2863 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2864
2865 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2866}
7322fd19 2867EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2868
cbe61d8a 2869bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2870{
99922a45
RM		 2871 if (ath9k_hw_mci_is_enabled(ah))
2872 ar9003_mci_bt_gain_ctrl(ah);
2873
63a75b91
SB		 2874 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2875 return false;
2876
2877 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2878 ah->htc_reset_init = true;
63a75b91 2879 return true;
f1dc5600 2880}
7322fd19 2881EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2882
cbe61d8a 2883bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2884{
9ecdef4b 2885 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2886 return false;
f078f209 2887
63a75b91
SB		 2888 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2889 return false;
2890
2891 ath9k_hw_init_pll(ah, NULL);
2892 return true;
f078f209 2893}
7322fd19 2894EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2895
ca2c68cc
FF		 2896static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2897{
2898 enum eeprom_param gain_param;
2899
2900 if (IS_CHAN_2GHZ(chan))
2901 gain_param = EEP_ANTENNA_GAIN_2G;
2902 else
2903 gain_param = EEP_ANTENNA_GAIN_5G;
2904
2905 return ah->eep_ops->get_eeprom(ah, gain_param);
2906}
2907
64ea57d0
GJ		 2908void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2909 bool test)
ca2c68cc
FF		 2910{
2911 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2912 struct ieee80211_channel *channel;
71f5137b 2913 int chan_pwr, new_pwr;
ca2c68cc
FF		 2914
2915 if (!chan)
2916 return;
2917
2918 channel = chan->chan;
2919 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2920 new_pwr = min_t(int, chan_pwr, reg->power_limit);
ca2c68cc
FF		 2921
2922 ah->eep_ops->set_txpower(ah, chan,
2923 ath9k_regd_get_ctl(reg, chan),
71f5137b 2924 get_antenna_gain(ah, chan), new_pwr, test);
ca2c68cc
FF		 2925}
2926
de40f316 2927void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2928{
ca2c68cc 2929 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2930 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2931 struct ieee80211_channel *channel = chan->chan;
9c204b46 2932
48ef5c42 2933 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2934 if (test)
ca2c68cc 2935 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2936
64ea57d0 2937 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2938
ca2c68cc
FF		 2939 if (test)
2940 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2941}
7322fd19 2942EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2943
cbe61d8a 2944void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2945{
2660b81a 2946 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2947}
7322fd19 2948EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2949
cbe61d8a 2950void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2951{
f1dc5600
S		 2952 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2953 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2954}
7322fd19 2955EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2956
f2b2143e 2957void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2958{
1510718d
LR		 2959 struct ath_common *common = ath9k_hw_common(ah);
2960
2961 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2962 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2963 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2964}
7322fd19 2965EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2966
1c0fc65e
BP		 2967#define ATH9K_MAX_TSF_READ 10
2968
cbe61d8a 2969u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2970{
1c0fc65e
BP		 2971 u32 tsf_lower, tsf_upper1, tsf_upper2;
2972 int i;
2973
2974 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2975 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2976 tsf_lower = REG_READ(ah, AR_TSF_L32);
2977 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2978 if (tsf_upper2 == tsf_upper1)
2979 break;
2980 tsf_upper1 = tsf_upper2;
2981 }
f078f209 2982
1c0fc65e 2983 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2984
1c0fc65e 2985 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2986}
7322fd19 2987EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2988
cbe61d8a 2989void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2990{
27abe060 2991 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2992 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2993}
7322fd19 2994EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2995
cbe61d8a 2996void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2997{
f9b604f6
GJ		 2998 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2999 AH_TSF_WRITE_TIMEOUT))
d2182b69 3000 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 3001 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 3002
f1dc5600
S		 3003 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3004}
7322fd19 3005EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 3006
60ca9f87 3007void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 3008{
60ca9f87 3009 if (set)
2660b81a 3010 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3011 else
2660b81a 3012 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 3013}
7322fd19 3014EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 3015
e4744ec7 3016void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 3017{
3018 u32 macmode;
3019
e4744ec7 3020 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3021 macmode = AR_2040_JOINED_RX_CLEAR;
3022 else
3023 macmode = 0;
f078f209 3024
f1dc5600 3025 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3026}
ff155a45
VT		 3027
3028/* HW Generic timers configuration */
3029
3030static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3031{
3032 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3033 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3034 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3035 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3036 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3037 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3038 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3039 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3040 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3041 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3042 AR_NDP2_TIMER_MODE, 0x0002},
3043 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3044 AR_NDP2_TIMER_MODE, 0x0004},
3045 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3046 AR_NDP2_TIMER_MODE, 0x0008},
3047 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3048 AR_NDP2_TIMER_MODE, 0x0010},
3049 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3050 AR_NDP2_TIMER_MODE, 0x0020},
3051 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3052 AR_NDP2_TIMER_MODE, 0x0040},
3053 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3054 AR_NDP2_TIMER_MODE, 0x0080}
3055};
3056
3057/* HW generic timer primitives */
3058
dd347f2f 3059u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 3060{
3061 return REG_READ(ah, AR_TSF_L32);
3062}
dd347f2f 3063EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45 3064
f4c34af4
SM		 3065void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3066{
3067 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3068
3069 if (timer_table->tsf2_enabled) {
3070 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3071 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3072 }
3073}
3074
ff155a45
VT		 3075struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3076 void (*trigger)(void *),
3077 void (*overflow)(void *),
3078 void *arg,
3079 u8 timer_index)
3080{
3081 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3082 struct ath_gen_timer *timer;
3083
c67ce339 3084 if ((timer_index < AR_FIRST_NDP_TIMER) ||
f4c34af4
SM		 3085 (timer_index >= ATH_MAX_GEN_TIMER))
3086 return NULL;
3087
3088 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3089 !AR_SREV_9300_20_OR_LATER(ah))
c67ce339
FF		 3090 return NULL;
3091
ff155a45 3092 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 3093 if (timer == NULL)
ff155a45 3094 return NULL;
ff155a45
VT		 3095
3096 /* allocate a hardware generic timer slot */
3097 timer_table->timers[timer_index] = timer;
3098 timer->index = timer_index;
3099 timer->trigger = trigger;
3100 timer->overflow = overflow;
3101 timer->arg = arg;
3102
f4c34af4
SM		 3103 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3104 timer_table->tsf2_enabled = true;
3105 ath9k_hw_gen_timer_start_tsf2(ah);
3106 }
3107
ff155a45
VT		 3108 return timer;
3109}
7322fd19 3110EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3111
cd9bf689
LR		 3112void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3113 struct ath_gen_timer *timer,
c67ce339 3114 u32 timer_next,
cd9bf689 3115 u32 timer_period)
ff155a45
VT		 3116{
3117 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 3118 u32 mask = 0;
788f6875 3119
c67ce339 3120 timer_table->timer_mask |= BIT(timer->index);
ff155a45 3121
ff155a45
VT		 3122 /*
3123 * Program generic timer registers
3124 */
3125 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3126 timer_next);
3127 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3128 timer_period);
3129 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3130 gen_tmr_configuration[timer->index].mode_mask);
3131
a4a2954f 3132 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3133 /*
423e38e8 3134 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3135 * to use. But we still follow the old rule, 0 - 7 use tsf and
3136 * 8 - 15 use tsf2.
3137 */
3138 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3139 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3140 (1 << timer->index));
3141 else
3142 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3143 (1 << timer->index));
3144 }
3145
c67ce339
FF		 3146 if (timer->trigger)
3147 mask |= SM(AR_GENTMR_BIT(timer->index),
3148 AR_IMR_S5_GENTIMER_TRIG);
3149 if (timer->overflow)
3150 mask |= SM(AR_GENTMR_BIT(timer->index),
3151 AR_IMR_S5_GENTIMER_THRESH);
3152
3153 REG_SET_BIT(ah, AR_IMR_S5, mask);
3154
3155 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3156 ah->imask |= ATH9K_INT_GENTIMER;
3157 ath9k_hw_set_interrupts(ah);
3158 }
ff155a45 3159}
7322fd19 3160EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3161
cd9bf689 3162void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3163{
3164 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3165
ff155a45
VT		 3166 /* Clear generic timer enable bits. */
3167 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3168 gen_tmr_configuration[timer->index].mode_mask);
3169
b7f59766
SM		 3170 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3171 /*
3172 * Need to switch back to TSF if it was using TSF2.
3173 */
3174 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3175 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3176 (1 << timer->index));
3177 }
3178 }
3179
ff155a45
VT		 3180 /* Disable both trigger and thresh interrupt masks */
3181 REG_CLR_BIT(ah, AR_IMR_S5,
3182 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3183 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3184
c67ce339
FF		 3185 timer_table->timer_mask &= ~BIT(timer->index);
3186
3187 if (timer_table->timer_mask == 0) {
3188 ah->imask &= ~ATH9K_INT_GENTIMER;
3189 ath9k_hw_set_interrupts(ah);
3190 }
ff155a45 3191}
7322fd19 3192EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3193
3194void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3195{
3196 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3197
3198 /* free the hardware generic timer slot */
3199 timer_table->timers[timer->index] = NULL;
3200 kfree(timer);
3201}
7322fd19 3202EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3203
3204/*
3205 * Generic Timer Interrupts handling
3206 */
3207void ath_gen_timer_isr(struct ath_hw *ah)
3208{
3209 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3210 struct ath_gen_timer *timer;
c67ce339
FF		 3211 unsigned long trigger_mask, thresh_mask;
3212 unsigned int index;
ff155a45
VT		 3213
3214 /* get hardware generic timer interrupt status */
3215 trigger_mask = ah->intr_gen_timer_trigger;
3216 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3217 trigger_mask &= timer_table->timer_mask;
3218 thresh_mask &= timer_table->timer_mask;
ff155a45 3219
c67ce339 3220 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3221 timer = timer_table->timers[index];
c67ce339
FF		 3222 if (!timer)
3223 continue;
3224 if (!timer->overflow)
3225 continue;
a6a172b2
FF		 3226
3227 trigger_mask &= ~BIT(index);
ff155a45
VT		 3228 timer->overflow(timer->arg);
3229 }
3230
c67ce339 3231 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3232 timer = timer_table->timers[index];
c67ce339
FF		 3233 if (!timer)
3234 continue;
3235 if (!timer->trigger)
3236 continue;
ff155a45
VT		 3237 timer->trigger(timer->arg);
3238 }
3239}
7322fd19 3240EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3241
05020d23
S		 3242/********/
3243/* HTC */
3244/********/
3245
2da4f01a
LR		 3246static struct {
3247 u32 version;
3248 const char * name;
3249} ath_mac_bb_names[] = {
3250 /* Devices with external radios */
3251 { AR_SREV_VERSION_5416_PCI, "5416" },
3252 { AR_SREV_VERSION_5416_PCIE, "5418" },
3253 { AR_SREV_VERSION_9100, "9100" },
3254 { AR_SREV_VERSION_9160, "9160" },
3255 /* Single-chip solutions */
3256 { AR_SREV_VERSION_9280, "9280" },
3257 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3258 { AR_SREV_VERSION_9287, "9287" },
3259 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3260 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3261 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3262 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3263 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3264 { AR_SREV_VERSION_9462, "9462" },
485124cb 3265 { AR_SREV_VERSION_9550, "9550" },
77fac465 3266 { AR_SREV_VERSION_9565, "9565" },
c08148bb 3267 { AR_SREV_VERSION_9531, "9531" },
1165dd90 3268 { AR_SREV_VERSION_9561, "9561" },
2da4f01a
LR		 3269};
3270
3271/* For devices with external radios */
3272static struct {
3273 u16 version;
3274 const char * name;
3275} ath_rf_names[] = {
3276 { 0, "5133" },
3277 { AR_RAD5133_SREV_MAJOR, "5133" },
3278 { AR_RAD5122_SREV_MAJOR, "5122" },
3279 { AR_RAD2133_SREV_MAJOR, "2133" },
3280 { AR_RAD2122_SREV_MAJOR, "2122" }
3281};
3282
3283/*
3284 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3285 */
f934c4d9 3286static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3287{
3288 int i;
3289
3290 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3291 if (ath_mac_bb_names[i].version == mac_bb_version) {
3292 return ath_mac_bb_names[i].name;
3293 }
3294 }
3295
3296 return "????";
3297}
2da4f01a
LR		 3298
3299/*
3300 * Return the RF name. "????" is returned if the RF is unknown.
3301 * Used for devices with external radios.
3302 */
f934c4d9 3303static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3304{
3305 int i;
3306
3307 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3308 if (ath_rf_names[i].version == rf_version) {
3309 return ath_rf_names[i].name;
3310 }
3311 }
3312
3313 return "????";
3314}
f934c4d9
LR		 3315
3316void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3317{
3318 int used;
3319
3320 /* chipsets >= AR9280 are single-chip */
7a37081e 3321 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3322 used = scnprintf(hw_name, len,
3323 "Atheros AR%s Rev:%x",
3324 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3325 ah->hw_version.macRev);
f934c4d9
LR		 3326 }
3327 else {
5e88ba62
ZK		 3328 used = scnprintf(hw_name, len,
3329 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3330 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3331 ah->hw_version.macRev,
3332 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3333 & AR_RADIO_SREV_MAJOR)),
3334 ah->hw_version.phyRev);
f934c4d9
LR		 3335 }
3336
3337 hw_name[used] = '\0';
3338}
3339EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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