Merge remote-tracking branch 'xen-tip/linux-next'
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
313eb87f 22u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
e2d389b5
SM
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 bool sw_pending)
69081624
VT
59{
60 bool pending = false;
61
62 spin_lock_bh(&txq->axq_lock);
63
b7367285 64 if (txq->axq_depth) {
69081624 65 pending = true;
b7367285
SM
66 goto out;
67 }
69081624 68
e2d389b5
SM
69 if (!sw_pending)
70 goto out;
71
0453531e
FF
72 if (txq->mac80211_qnum >= 0) {
73 struct list_head *list;
74
75 list = &sc->cur_chan->acq[txq->mac80211_qnum];
76 if (!list_empty(list))
77 pending = true;
78 }
b7367285 79out:
69081624
VT
80 spin_unlock_bh(&txq->axq_lock);
81 return pending;
82}
83
6d79cb4c 84static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
85{
86 unsigned long flags;
87 bool ret;
88
9ecdef4b
LR
89 spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
92
93 return ret;
94}
95
bf3dac5a
FF
96void ath_ps_full_sleep(unsigned long data)
97{
98 struct ath_softc *sc = (struct ath_softc *) data;
99 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 bool reset;
101
102 spin_lock(&common->cc_lock);
103 ath_hw_cycle_counters_update(common);
104 spin_unlock(&common->cc_lock);
105
106 ath9k_hw_setrxabort(sc->sc_ah, 1);
107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
108
109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
110}
111
a91d75ae
LR
112void ath9k_ps_wakeup(struct ath_softc *sc)
113{
898c914a 114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 115 unsigned long flags;
fbb078fc 116 enum ath9k_power_mode power_mode;
a91d75ae
LR
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (++sc->ps_usecount != 1)
120 goto unlock;
121
bf3dac5a 122 del_timer_sync(&sc->sleep_timer);
fbb078fc 123 power_mode = sc->sc_ah->power_mode;
9ecdef4b 124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 125
898c914a
FF
126 /*
127 * While the hardware is asleep, the cycle counters contain no
128 * useful data. Better clear them now so that they don't mess up
129 * survey data results.
130 */
fbb078fc
FF
131 if (power_mode != ATH9K_PM_AWAKE) {
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 135 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF
136 spin_unlock(&common->cc_lock);
137 }
898c914a 138
a91d75ae
LR
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141}
142
143void ath9k_ps_restore(struct ath_softc *sc)
144{
898c914a 145 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 146 enum ath9k_power_mode mode;
a91d75ae
LR
147 unsigned long flags;
148
149 spin_lock_irqsave(&sc->sc_pm_lock, flags);
150 if (--sc->ps_usecount != 0)
151 goto unlock;
152
ad128860 153 if (sc->ps_idle) {
bf3dac5a
FF
154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
155 goto unlock;
156 }
157
158 if (sc->ps_enabled &&
ad128860
SM
159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
160 PS_WAIT_FOR_CAB |
161 PS_WAIT_FOR_PSPOLL_DATA |
424749c7
RM
162 PS_WAIT_FOR_TX_ACK |
163 PS_WAIT_FOR_ANI))) {
c6c539f0 164 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM
165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
166 ath9k_btcoex_stop_gen_timer(sc);
ad128860 167 } else {
c6c539f0 168 goto unlock;
ad128860 169 }
c6c539f0
FF
170
171 spin_lock(&common->cc_lock);
172 ath_hw_cycle_counters_update(common);
173 spin_unlock(&common->cc_lock);
174
1a8f0d39 175 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
176
177 unlock:
178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
179}
180
9adcf440 181static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 182{
5ee08656 183 cancel_work_sync(&sc->paprd_work);
5ee08656 184 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 185 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 186
bf52592f 187#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM
188 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
189 cancel_work_sync(&sc->mci_work);
bf52592f 190#endif
9adcf440 191}
5ee08656 192
e60001e7 193void ath_cancel_work(struct ath_softc *sc)
9adcf440
FF
194{
195 __ath_cancel_work(sc);
196 cancel_work_sync(&sc->hw_reset_work);
197}
3cbb5dd7 198
e60001e7 199void ath_restart_work(struct ath_softc *sc)
af68abad 200{
af68abad
SM
201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
202
19c36160 203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
af68abad
SM
204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
206
da0d45f7 207 ath_start_ani(sc);
af68abad
SM
208}
209
9ebea382 210static bool ath_prepare_reset(struct ath_softc *sc)
9adcf440
FF
211{
212 struct ath_hw *ah = sc->sc_ah;
ceea2a51 213 bool ret = true;
6a6733f2 214
9adcf440 215 ieee80211_stop_queues(sc->hw);
da0d45f7 216 ath_stop_ani(sc);
9adcf440 217 ath9k_hw_disable_interrupts(ah);
8b3f4616 218
300f77c0
FF
219 if (AR_SREV_9300_20_OR_LATER(ah)) {
220 ret &= ath_stoprecv(sc);
221 ret &= ath_drain_all_txq(sc);
222 } else {
223 ret &= ath_drain_all_txq(sc);
224 ret &= ath_stoprecv(sc);
225 }
ceea2a51 226
9adcf440
FF
227 return ret;
228}
ff37e337 229
9adcf440
FF
230static bool ath_complete_reset(struct ath_softc *sc, bool start)
231{
232 struct ath_hw *ah = sc->sc_ah;
233 struct ath_common *common = ath9k_hw_common(ah);
196fb860 234 unsigned long flags;
c0d7c7af 235
9019f646 236 ath9k_calculate_summary_state(sc, sc->cur_chan);
19ec477f 237 ath_startrecv(sc);
d385c5c2
FF
238 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
239 sc->cur_chan->txpower,
240 &sc->cur_chan->cur_txpower);
eefa01dd 241 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
3989279c 242
fbbcd146 243 if (!sc->cur_chan->offchannel && start) {
8d7e09dd
FF
244 /* restore per chanctx TSF timer */
245 if (sc->cur_chan->tsf_val) {
246 u32 offset;
247
248 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
249 NULL);
250 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
251 }
252
253
eefa01dd 254 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
196fb860
SM
255 goto work;
256
196fb860 257 if (ah->opmode == NL80211_IFTYPE_STATION &&
eefa01dd 258 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
196fb860
SM
259 spin_lock_irqsave(&sc->sc_pm_lock, flags);
260 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
261 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
a6768280
SM
262 } else {
263 ath9k_set_beacon(sc);
196fb860
SM
264 }
265 work:
af68abad 266 ath_restart_work(sc);
0453531e 267 ath_txq_schedule_all(sc);
5ee08656
FF
268 }
269
071aa9a8 270 sc->gtt_cnt = 0;
9a9c4fbc
RM
271
272 ath9k_hw_set_interrupts(ah);
273 ath9k_hw_enable_interrupts(ah);
5ba8d9d2 274 ieee80211_wake_queues(sc->hw);
d463af4a
FF
275 ath9k_p2p_ps_timer(sc);
276
9adcf440
FF
277 return true;
278}
279
5555c955 280static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
9adcf440
FF
281{
282 struct ath_hw *ah = sc->sc_ah;
283 struct ath_common *common = ath9k_hw_common(ah);
284 struct ath9k_hw_cal_data *caldata = NULL;
285 bool fastcc = true;
9adcf440
FF
286 int r;
287
288 __ath_cancel_work(sc);
289
e3f31175 290 disable_irq(sc->irq);
4668cce5 291 tasklet_disable(&sc->intr_tq);
eaf04a69 292 tasklet_disable(&sc->bcon_tasklet);
9adcf440 293 spin_lock_bh(&sc->sc_pcu_lock);
92460412 294
fbbcd146 295 if (!sc->cur_chan->offchannel) {
9adcf440 296 fastcc = false;
b01459e8 297 caldata = &sc->cur_chan->caldata;
9adcf440
FF
298 }
299
300 if (!hchan) {
301 fastcc = false;
9adcf440
FF
302 hchan = ah->curchan;
303 }
304
9ebea382 305 if (!ath_prepare_reset(sc))
9adcf440
FF
306 fastcc = false;
307
9ea3598b
SM
308 if (ath9k_is_chanctx_enabled())
309 fastcc = false;
310
d6067f0e
RM
311 spin_lock_bh(&sc->chan_lock);
312 sc->cur_chandef = sc->cur_chan->chandef;
313 spin_unlock_bh(&sc->chan_lock);
bff11766 314
d2182b69 315 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 316 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF
317
318 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
319 if (r) {
320 ath_err(common,
321 "Unable to reset channel, reset status %d\n", r);
f50b1cd3
RS
322
323 ath9k_hw_enable_interrupts(ah);
324 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
325
9adcf440
FF
326 goto out;
327 }
328
e82cb03f 329 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
fbbcd146 330 sc->cur_chan->offchannel)
e82cb03f
RM
331 ath9k_mci_set_txpower(sc, true, false);
332
9adcf440
FF
333 if (!ath_complete_reset(sc, true))
334 r = -EIO;
335
336out:
e3f31175 337 enable_irq(sc->irq);
6a6733f2 338 spin_unlock_bh(&sc->sc_pcu_lock);
eaf04a69 339 tasklet_enable(&sc->bcon_tasklet);
4668cce5
FF
340 tasklet_enable(&sc->intr_tq);
341
9adcf440
FF
342 return r;
343}
344
7e1e3864
BG
345static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
346 struct ieee80211_vif *vif)
ff37e337
S
347{
348 struct ath_node *an;
ff37e337
S
349 an = (struct ath_node *)sta->drv_priv;
350
a145daf7 351 an->sc = sc;
7f010c93 352 an->sta = sta;
7e1e3864 353 an->vif = vif;
4bbf4414 354 memset(&an->key_idx, 0, sizeof(an->key_idx));
3d4e20f2 355
dd5ee59b 356 ath_tx_node_init(sc, an);
44b47a7d
LB
357
358 ath_dynack_node_init(sc->sc_ah, an);
ff37e337
S
359}
360
361static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
362{
363 struct ath_node *an = (struct ath_node *)sta->drv_priv;
dd5ee59b 364 ath_tx_node_cleanup(sc, an);
44b47a7d
LB
365
366 ath_dynack_node_deinit(sc->sc_ah, an);
ff37e337
S
367}
368
55624204 369void ath9k_tasklet(unsigned long data)
ff37e337
S
370{
371 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 372 struct ath_hw *ah = sc->sc_ah;
c46917bb 373 struct ath_common *common = ath9k_hw_common(ah);
124b979b 374 enum ath_reset_type type;
07c15a3f 375 unsigned long flags;
17d7904d 376 u32 status = sc->intrstatus;
b5c80475 377 u32 rxmask;
ff37e337 378
e3927007
FF
379 ath9k_ps_wakeup(sc);
380 spin_lock(&sc->sc_pcu_lock);
381
6549a860
SM
382 if (status & ATH9K_INT_FATAL) {
383 type = RESET_TYPE_FATAL_INT;
124b979b 384 ath9k_queue_reset(sc, type);
c6cc47b1
SM
385
386 /*
387 * Increment the ref. counter here so that
388 * interrupts are enabled in the reset routine.
389 */
390 atomic_inc(&ah->intr_ref_cnt);
affad456 391 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
e3927007 392 goto out;
063d8be3 393 }
ff37e337 394
6549a860
SM
395 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
396 (status & ATH9K_INT_BB_WATCHDOG)) {
0c759977
SM
397 spin_lock(&common->cc_lock);
398 ath_hw_cycle_counters_update(common);
399 ar9003_hw_bb_watchdog_dbg_info(ah);
400 spin_unlock(&common->cc_lock);
401
6549a860
SM
402 if (ar9003_hw_bb_watchdog_check(ah)) {
403 type = RESET_TYPE_BB_WATCHDOG;
404 ath9k_queue_reset(sc, type);
405
406 /*
407 * Increment the ref. counter here so that
408 * interrupts are enabled in the reset routine.
409 */
410 atomic_inc(&ah->intr_ref_cnt);
affad456 411 ath_dbg(common, RESET,
6549a860
SM
412 "BB_WATCHDOG: Skipping interrupts\n");
413 goto out;
414 }
415 }
416
071aa9a8
SM
417 if (status & ATH9K_INT_GTT) {
418 sc->gtt_cnt++;
419
420 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
421 type = RESET_TYPE_TX_GTT;
422 ath9k_queue_reset(sc, type);
423 atomic_inc(&ah->intr_ref_cnt);
affad456 424 ath_dbg(common, RESET,
071aa9a8
SM
425 "GTT: Skipping interrupts\n");
426 goto out;
427 }
428 }
429
07c15a3f 430 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM
431 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
432 /*
433 * TSF sync does not look correct; remain awake to sync with
434 * the next Beacon.
435 */
d2182b69 436 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 437 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 438 }
07c15a3f 439 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 440
b5c80475
FF
441 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
442 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
443 ATH9K_INT_RXORN);
444 else
445 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
446
447 if (status & rxmask) {
b5c80475
FF
448 /* Check for high priority Rx first */
449 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
450 (status & ATH9K_INT_RXHP))
451 ath_rx_tasklet(sc, 0, true);
452
453 ath_rx_tasklet(sc, 0, false);
ff37e337
S
454 }
455
e5003249 456 if (status & ATH9K_INT_TX) {
071aa9a8
SM
457 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
458 /*
459 * For EDMA chips, TX completion is enabled for the
460 * beacon queue, so if a beacon has been transmitted
461 * successfully after a GTT interrupt, the GTT counter
462 * gets reset to zero here.
463 */
3b745c7b 464 sc->gtt_cnt = 0;
071aa9a8 465
e5003249 466 ath_tx_edma_tasklet(sc);
071aa9a8 467 } else {
e5003249 468 ath_tx_tasklet(sc);
071aa9a8 469 }
10e23181
FF
470
471 wake_up(&sc->tx_wait);
e5003249 472 }
063d8be3 473
c67ce339
FF
474 if (status & ATH9K_INT_GENTIMER)
475 ath_gen_timer_isr(sc->sc_ah);
476
56ca0dba 477 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 478
ff37e337 479 /* re-enable hardware interrupt */
4df3071e 480 ath9k_hw_enable_interrupts(ah);
c6cc47b1 481out:
52671e43 482 spin_unlock(&sc->sc_pcu_lock);
153e080d 483 ath9k_ps_restore(sc);
ff37e337
S
484}
485
6baff7f9 486irqreturn_t ath_isr(int irq, void *dev)
ff37e337 487{
063d8be3
S
488#define SCHED_INTR ( \
489 ATH9K_INT_FATAL | \
a4d86d95 490 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
491 ATH9K_INT_RXORN | \
492 ATH9K_INT_RXEOL | \
493 ATH9K_INT_RX | \
b5c80475
FF
494 ATH9K_INT_RXLP | \
495 ATH9K_INT_RXHP | \
063d8be3
S
496 ATH9K_INT_TX | \
497 ATH9K_INT_BMISS | \
498 ATH9K_INT_CST | \
071aa9a8 499 ATH9K_INT_GTT | \
ebb8e1d7 500 ATH9K_INT_TSFOOR | \
40dc5392
MSS
501 ATH9K_INT_GENTIMER | \
502 ATH9K_INT_MCI)
063d8be3 503
ff37e337 504 struct ath_softc *sc = dev;
cbe61d8a 505 struct ath_hw *ah = sc->sc_ah;
eefa01dd 506 struct ath_common *common = ath9k_hw_common(ah);
ff37e337 507 enum ath9k_int status;
78c8a950 508 u32 sync_cause = 0;
ff37e337
S
509 bool sched = false;
510
063d8be3
S
511 /*
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
515 */
2ba7d144 516 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
063d8be3 517 return IRQ_NONE;
ff37e337 518
872b5d81 519 /* shared irq, not for us */
153e080d 520 if (!ath9k_hw_intrpend(ah))
063d8be3 521 return IRQ_NONE;
063d8be3
S
522
523 /*
524 * Figure out the reason(s) for the interrupt. Note
525 * that the hal returns a pseudo-ISR that may include
526 * bits we haven't explicitly enabled so we mask the
527 * value to insure we only process bits we requested.
528 */
6a4d05dc
FF
529 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
530 ath9k_debug_sync_cause(sc, sync_cause);
3069168c 531 status &= ah->imask; /* discard unasked-for bits */
ff37e337 532
e3f31175 533 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
872b5d81
FF
534 return IRQ_HANDLED;
535
063d8be3
S
536 /*
537 * If there are no status bits set, then this interrupt was not
538 * for me (should have been caught above).
539 */
153e080d 540 if (!status)
063d8be3 541 return IRQ_NONE;
ff37e337 542
063d8be3
S
543 /* Cache the status */
544 sc->intrstatus = status;
545
546 if (status & SCHED_INTR)
547 sched = true;
548
549 /*
3b580144
FF
550 * If a FATAL interrupt is received, we have to reset the chip
551 * immediately.
063d8be3 552 */
3b580144 553 if (status & ATH9K_INT_FATAL)
063d8be3
S
554 goto chip_reset;
555
a6bb860b 556 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
0c759977 557 (status & ATH9K_INT_BB_WATCHDOG))
08578b8f 558 goto chip_reset;
e60001e7 559
063d8be3
S
560 if (status & ATH9K_INT_SWBA)
561 tasklet_schedule(&sc->bcon_tasklet);
562
563 if (status & ATH9K_INT_TXURN)
564 ath9k_hw_updatetxtriglevel(ah, true);
565
0682c9b5
RM
566 if (status & ATH9K_INT_RXEOL) {
567 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 568 ath9k_hw_set_interrupts(ah);
b5c80475
FF
569 }
570
153e080d
VT
571 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
572 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
573 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
574 goto chip_reset;
063d8be3
S
575 /* Clear RxAbort bit so that we can
576 * receive frames */
9ecdef4b 577 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 578 spin_lock(&sc->sc_pm_lock);
153e080d 579 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 580 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 581 spin_unlock(&sc->sc_pm_lock);
ff37e337 582 }
063d8be3
S
583
584chip_reset:
ff37e337 585
817e11de
S
586 ath_debug_stat_interrupt(sc, status);
587
ff37e337 588 if (sched) {
4df3071e
FF
589 /* turn off every interrupt */
590 ath9k_hw_disable_interrupts(ah);
ff37e337
S
591 tasklet_schedule(&sc->intr_tq);
592 }
593
594 return IRQ_HANDLED;
063d8be3
S
595
596#undef SCHED_INTR
ff37e337
S
597}
598
ae2ff239
SM
599/*
600 * This function is called when a HW reset cannot be deferred
601 * and has to be immediate.
602 */
5555c955 603int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
ff37e337 604{
ae2ff239 605 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ec30326e 606 int r;
ff37e337 607
872b5d81 608 ath9k_hw_kill_interrupts(sc->sc_ah);
ae2ff239
SM
609 set_bit(ATH_OP_HW_RESET, &common->op_flags);
610
783cd01e 611 ath9k_ps_wakeup(sc);
5555c955 612 r = ath_reset_internal(sc, hchan);
783cd01e 613 ath9k_ps_restore(sc);
2ab81d4a 614
ae8d2858 615 return r;
ff37e337
S
616}
617
ae2ff239
SM
618/*
619 * When a HW reset can be deferred, it is added to the
620 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
621 * queueing.
622 */
124b979b
RM
623void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
624{
eefa01dd 625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
124b979b
RM
626#ifdef CONFIG_ATH9K_DEBUGFS
627 RESET_STAT_INC(sc, type);
628#endif
872b5d81 629 ath9k_hw_kill_interrupts(sc->sc_ah);
eefa01dd 630 set_bit(ATH_OP_HW_RESET, &common->op_flags);
124b979b
RM
631 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
632}
633
236de514
FF
634void ath_reset_work(struct work_struct *work)
635{
636 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
637
5555c955
SM
638 ath9k_ps_wakeup(sc);
639 ath_reset_internal(sc, NULL);
640 ath9k_ps_restore(sc);
236de514
FF
641}
642
ff37e337
S
643/**********************/
644/* mac80211 callbacks */
645/**********************/
646
8feceb67 647static int ath9k_start(struct ieee80211_hw *hw)
f078f209 648{
9ac58615 649 struct ath_softc *sc = hw->priv;
af03abec 650 struct ath_hw *ah = sc->sc_ah;
c46917bb 651 struct ath_common *common = ath9k_hw_common(ah);
39305635 652 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
fbbcd146 653 struct ath_chanctx *ctx = sc->cur_chan;
ff37e337 654 struct ath9k_channel *init_channel;
82880a7c 655 int r;
f078f209 656
d2182b69 657 ath_dbg(common, CONFIG,
226afe68
JP
658 "Starting driver with initial channel: %d MHz\n",
659 curchan->center_freq);
f078f209 660
f62d816f 661 ath9k_ps_wakeup(sc);
141b38b6
S
662 mutex_lock(&sc->mutex);
663
fbbcd146 664 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
bff11766 665 sc->cur_chandef = hw->conf.chandef;
ff37e337
S
666
667 /* Reset SERDES registers */
84c87dc8 668 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
669
670 /*
671 * The basic interface to setting the hardware in a good
672 * state is ``reset''. On return the hardware is known to
673 * be powered up and with interrupts disabled. This must
674 * be followed by initialization of the appropriate bits
675 * and then setup of the interrupt mask.
676 */
4bdd1e97 677 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF
678
679 atomic_set(&ah->intr_ref_cnt, -1);
680
20bd2a09 681 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 682 if (r) {
3800276a
JP
683 ath_err(common,
684 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
685 r, curchan->center_freq);
ceb26a60 686 ah->reset_power_on = false;
ff37e337 687 }
ff37e337 688
ff37e337 689 /* Setup our intr mask. */
b5c80475
FF
690 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
691 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
692 ATH9K_INT_GLOBAL;
693
694 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f 695 ah->imask |= ATH9K_INT_RXHP |
a6bb860b 696 ATH9K_INT_RXLP;
b5c80475
FF
697 else
698 ah->imask |= ATH9K_INT_RX;
ff37e337 699
a6bb860b
SM
700 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
701 ah->imask |= ATH9K_INT_BB_WATCHDOG;
702
071aa9a8
SM
703 /*
704 * Enable GTT interrupts only for AR9003/AR9004 chips
705 * for now.
706 */
707 if (AR_SREV_9300_20_OR_LATER(ah))
708 ah->imask |= ATH9K_INT_GTT;
ff37e337 709
af03abec 710 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 711 ah->imask |= ATH9K_INT_CST;
ff37e337 712
e270e776 713 ath_mci_enable(sc);
40dc5392 714
eefa01dd 715 clear_bit(ATH_OP_INVALID, &common->op_flags);
5f841b41 716 sc->sc_ah->is_monitoring = false;
ff37e337 717
ceb26a60
FF
718 if (!ath_complete_reset(sc, false))
719 ah->reset_power_on = false;
ff37e337 720
e34f2ff4 721 if (ah->led_pin >= 0) {
aeeb2065
SM
722 ath9k_hw_set_gpio(ah, ah->led_pin,
723 (ah->config.led_active_high) ? 1 : 0);
e34f2ff4
GS
724 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
725 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
726 }
c0c11741
FF
727
728 /*
729 * Reset key cache to sane defaults (all entries cleared) instead of
730 * semi-random values after suspend/resume.
731 */
732 ath9k_cmn_init_crypto(sc->sc_ah);
733
a35051ce
FF
734 ath9k_hw_reset_tsf(ah);
735
9adcf440 736 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 737
141b38b6
S
738 mutex_unlock(&sc->mutex);
739
f62d816f
FF
740 ath9k_ps_restore(sc);
741
ed14dc0a
MP
742 ath9k_rng_start(sc);
743
ceb26a60 744 return 0;
f078f209
LR
745}
746
36323f81
TH
747static void ath9k_tx(struct ieee80211_hw *hw,
748 struct ieee80211_tx_control *control,
749 struct sk_buff *skb)
f078f209 750{
9ac58615 751 struct ath_softc *sc = hw->priv;
c46917bb 752 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 753 struct ath_tx_control txctl;
1bc14880 754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 755 unsigned long flags;
528f0c6b 756
96148326 757 if (sc->ps_enabled) {
dc8c4585
JM
758 /*
759 * mac80211 does not set PM field for normal data frames, so we
760 * need to update that based on the current PS mode.
761 */
762 if (ieee80211_is_data(hdr->frame_control) &&
763 !ieee80211_is_nullfunc(hdr->frame_control) &&
764 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 765 ath_dbg(common, PS,
226afe68 766 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
767 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
768 }
769 }
770
ad128860 771 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM
772 /*
773 * We are using PS-Poll and mac80211 can request TX while in
774 * power save mode. Need to wake up hardware for the TX to be
775 * completed and if needed, also for RX of buffered frames.
776 */
9a23f9ca 777 ath9k_ps_wakeup(sc);
07c15a3f 778 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT
779 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
780 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 781 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 782 ath_dbg(common, PS,
226afe68 783 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 784 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 785 } else {
d2182b69 786 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 787 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
788 }
789 /*
790 * The actual restore operation will happen only after
ad128860 791 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM
792 * the ps_usecount here.
793 */
07c15a3f 794 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM
795 ath9k_ps_restore(sc);
796 }
797
ad128860
SM
798 /*
799 * Cannot tx while the hardware is in full sleep, it first needs a full
800 * chip reset to recover from that
801 */
802 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
803 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
804 goto exit;
805 }
806
528f0c6b 807 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 808 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
36323f81 809 txctl.sta = control->sta;
528f0c6b 810
d2182b69 811 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 812
c52f33d0 813 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 814 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 815 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 816 goto exit;
8feceb67
VT
817 }
818
7bb45683 819 return;
528f0c6b 820exit:
249ee722 821 ieee80211_free_txskb(hw, skb);
f078f209
LR
822}
823
8feceb67 824static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 825{
9ac58615 826 struct ath_softc *sc = hw->priv;
af03abec 827 struct ath_hw *ah = sc->sc_ah;
c46917bb 828 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 829 bool prev_idle;
f078f209 830
ea22df29
SM
831 ath9k_deinit_channel_context(sc);
832
ed14dc0a
MP
833 ath9k_rng_stop(sc);
834
4c483817
S
835 mutex_lock(&sc->mutex);
836
9adcf440 837 ath_cancel_work(sc);
c94dbff7 838
eefa01dd 839 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 840 ath_dbg(common, ANY, "Device not present\n");
4c483817 841 mutex_unlock(&sc->mutex);
9c84b797
S
842 return;
843 }
8feceb67 844
3867cf6a
S
845 /* Ensure HW is awake when we try to shut it down. */
846 ath9k_ps_wakeup(sc);
847
6a6733f2
LR
848 spin_lock_bh(&sc->sc_pcu_lock);
849
203043f5
SG
850 /* prevent tasklets to enable interrupts once we disable them */
851 ah->imask &= ~ATH9K_INT_GLOBAL;
852
ff37e337
S
853 /* make sure h/w will not generate any interrupt
854 * before setting the invalid flag. */
4df3071e 855 ath9k_hw_disable_interrupts(ah);
ff37e337 856
c0c11741
FF
857 spin_unlock_bh(&sc->sc_pcu_lock);
858
859 /* we can now sync irq and kill any running tasklets, since we already
860 * disabled interrupts and not holding a spin lock */
861 synchronize_irq(sc->irq);
862 tasklet_kill(&sc->intr_tq);
863 tasklet_kill(&sc->bcon_tasklet);
864
865 prev_idle = sc->ps_idle;
866 sc->ps_idle = true;
867
868 spin_lock_bh(&sc->sc_pcu_lock);
869
e34f2ff4 870 if (ah->led_pin >= 0) {
aeeb2065
SM
871 ath9k_hw_set_gpio(ah, ah->led_pin,
872 (ah->config.led_active_high) ? 0 : 1);
e34f2ff4
GS
873 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
874 }
c0c11741 875
9ebea382 876 ath_prepare_reset(sc);
ff37e337 877
0d95521e
FF
878 if (sc->rx.frag) {
879 dev_kfree_skb_any(sc->rx.frag);
880 sc->rx.frag = NULL;
881 }
882
c0c11741 883 if (!ah->curchan)
fbbcd146
FF
884 ah->curchan = ath9k_cmn_get_channel(hw, ah,
885 &sc->cur_chan->chandef);
6a6733f2 886
c0c11741 887 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ef739ab6
FF
888
889 set_bit(ATH_OP_INVALID, &common->op_flags);
890
c0c11741 891 ath9k_hw_phy_disable(ah);
6a6733f2 892
c0c11741 893 ath9k_hw_configpcipowersave(ah, true);
203043f5 894
c0c11741 895 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 896
c0c11741 897 ath9k_ps_restore(sc);
ff37e337 898
c0c11741 899 sc->ps_idle = prev_idle;
500c064d 900
141b38b6
S
901 mutex_unlock(&sc->mutex);
902
d2182b69 903 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR
904}
905
c648ecb0 906static bool ath9k_uses_beacons(int type)
4801416c
BG
907{
908 switch (type) {
909 case NL80211_IFTYPE_AP:
910 case NL80211_IFTYPE_ADHOC:
911 case NL80211_IFTYPE_MESH_POINT:
912 return true;
913 default:
914 return false;
915 }
916}
917
cfda2d8e
BB
918static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
919 struct ieee80211_vif *vif)
920{
921 /* Use the first (configured) interface, but prefering AP interfaces. */
922 if (!iter_data->primary_beacon_vif) {
923 iter_data->primary_beacon_vif = vif;
924 } else {
925 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
926 vif->type == NL80211_IFTYPE_AP)
927 iter_data->primary_beacon_vif = vif;
928 }
929
930 iter_data->beacons = true;
931 iter_data->nbcnvifs += 1;
932}
933
4b93fd29
SM
934static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
935 u8 *mac, struct ieee80211_vif *vif)
4801416c 936{
cb35582a 937 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
4801416c
BG
938 int i;
939
ab11bb28 940 if (iter_data->has_hw_macaddr) {
4801416c
BG
941 for (i = 0; i < ETH_ALEN; i++)
942 iter_data->mask[i] &=
943 ~(iter_data->hw_macaddr[i] ^ mac[i]);
ab11bb28
FF
944 } else {
945 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
946 iter_data->has_hw_macaddr = true;
947 }
141b38b6 948
9a9c4fbc 949 if (!vif->bss_conf.use_short_slot)
11b0ac2e 950 iter_data->slottime = 20;
9a9c4fbc 951
1ed32e4f 952 switch (vif->type) {
4801416c
BG
953 case NL80211_IFTYPE_AP:
954 iter_data->naps++;
cfda2d8e
BB
955 if (vif->bss_conf.enable_beacon)
956 ath9k_vif_iter_set_beacon(iter_data, vif);
f078f209 957 break;
4801416c
BG
958 case NL80211_IFTYPE_STATION:
959 iter_data->nstations++;
cb35582a 960 if (avp->assoc && !iter_data->primary_sta)
9a9c4fbc 961 iter_data->primary_sta = vif;
e51f3eff 962 break;
862a336c
JK
963 case NL80211_IFTYPE_OCB:
964 iter_data->nocbs++;
965 break;
05c914fe 966 case NL80211_IFTYPE_ADHOC:
4801416c 967 iter_data->nadhocs++;
9a9c4fbc 968 if (vif->bss_conf.enable_beacon)
cfda2d8e 969 ath9k_vif_iter_set_beacon(iter_data, vif);
4801416c 970 break;
9cb5412b 971 case NL80211_IFTYPE_MESH_POINT:
4801416c 972 iter_data->nmeshes++;
9a9c4fbc 973 if (vif->bss_conf.enable_beacon)
cfda2d8e 974 ath9k_vif_iter_set_beacon(iter_data, vif);
4801416c
BG
975 break;
976 case NL80211_IFTYPE_WDS:
977 iter_data->nwds++;
f078f209
LR
978 break;
979 default:
4801416c 980 break;
f078f209 981 }
4801416c 982}
f078f209 983
2ce73c02
SM
984static void ath9k_update_bssid_mask(struct ath_softc *sc,
985 struct ath_chanctx *ctx,
986 struct ath9k_vif_iter_data *iter_data)
987{
988 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
989 struct ath_vif *avp;
990 int i;
991
992 if (!ath9k_is_chanctx_enabled())
993 return;
994
995 list_for_each_entry(avp, &ctx->vifs, list) {
996 if (ctx->nvifs_assigned != 1)
997 continue;
998
b9a9693f 999 if (!iter_data->has_hw_macaddr)
2ce73c02
SM
1000 continue;
1001
1002 ether_addr_copy(common->curbssid, avp->bssid);
1003
1004 /* perm_addr will be used as the p2p device address. */
1005 for (i = 0; i < ETH_ALEN; i++)
1006 iter_data->mask[i] &=
1007 ~(iter_data->hw_macaddr[i] ^
1008 sc->hw->wiphy->perm_addr[i]);
1009 }
1010}
1011
4801416c 1012/* Called with sc->mutex held. */
9a9c4fbc
RM
1013void ath9k_calculate_iter_data(struct ath_softc *sc,
1014 struct ath_chanctx *ctx,
4801416c
BG
1015 struct ath9k_vif_iter_data *iter_data)
1016{
9a9c4fbc 1017 struct ath_vif *avp;
8feceb67 1018
4801416c 1019 /*
daad1660
BG
1020 * The hardware will use primary station addr together with the
1021 * BSSID mask when matching addresses.
4801416c
BG
1022 */
1023 memset(iter_data, 0, sizeof(*iter_data));
93803b33 1024 eth_broadcast_addr(iter_data->mask);
11b0ac2e 1025 iter_data->slottime = 9;
9a9c4fbc
RM
1026
1027 list_for_each_entry(avp, &ctx->vifs, list)
1028 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
2ce73c02
SM
1029
1030 ath9k_update_bssid_mask(sc, ctx, iter_data);
9a9c4fbc
RM
1031}
1032
1033static void ath9k_set_assoc_state(struct ath_softc *sc,
1034 struct ieee80211_vif *vif, bool changed)
1035{
1036 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cb35582a 1037 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
9a9c4fbc
RM
1038 unsigned long flags;
1039
1040 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
9a9c4fbc 1041
cb35582a
SM
1042 ether_addr_copy(common->curbssid, avp->bssid);
1043 common->curaid = avp->aid;
9a9c4fbc
RM
1044 ath9k_hw_write_associd(sc->sc_ah);
1045
1046 if (changed) {
1047 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1048 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
5640b08e 1049
9a9c4fbc
RM
1050 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1051 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1052 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1053 }
4801416c 1054
9a9c4fbc
RM
1055 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1056 ath9k_mci_update_wlan_channels(sc, false);
ab11bb28 1057
9a9c4fbc
RM
1058 ath_dbg(common, CONFIG,
1059 "Primary Station interface: %pM, BSSID: %pM\n",
1060 vif->addr, common->curbssid);
4801416c 1061}
8ca21f01 1062
4ee26de1
SM
1063#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1064static void ath9k_set_offchannel_state(struct ath_softc *sc)
1065{
1066 struct ath_hw *ah = sc->sc_ah;
1067 struct ath_common *common = ath9k_hw_common(ah);
1068 struct ieee80211_vif *vif = NULL;
1069
1070 ath9k_ps_wakeup(sc);
1071
1072 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1073 vif = sc->offchannel.scan_vif;
1074 else
1075 vif = sc->offchannel.roc_vif;
1076
1077 if (WARN_ON(!vif))
1078 goto exit;
1079
1080 eth_zero_addr(common->curbssid);
1081 eth_broadcast_addr(common->bssidmask);
62ae1aef 1082 memcpy(common->macaddr, vif->addr, ETH_ALEN);
4ee26de1
SM
1083 common->curaid = 0;
1084 ah->opmode = vif->type;
1085 ah->imask &= ~ATH9K_INT_SWBA;
1086 ah->imask &= ~ATH9K_INT_TSFOOR;
11b0ac2e 1087 ah->slottime = 9;
4ee26de1
SM
1088
1089 ath_hw_setbssidmask(common);
1090 ath9k_hw_setopmode(ah);
1091 ath9k_hw_write_associd(sc->sc_ah);
1092 ath9k_hw_set_interrupts(ah);
1093 ath9k_hw_init_global_settings(ah);
1094
1095exit:
1096 ath9k_ps_restore(sc);
1097}
1098#endif
1099
4801416c 1100/* Called with sc->mutex held. */
9a9c4fbc
RM
1101void ath9k_calculate_summary_state(struct ath_softc *sc,
1102 struct ath_chanctx *ctx)
4801416c 1103{
4801416c
BG
1104 struct ath_hw *ah = sc->sc_ah;
1105 struct ath_common *common = ath9k_hw_common(ah);
1106 struct ath9k_vif_iter_data iter_data;
8ca21f01 1107
9a9c4fbc
RM
1108 ath_chanctx_check_active(sc, ctx);
1109
1110 if (ctx != sc->cur_chan)
1111 return;
1112
4ee26de1
SM
1113#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1114 if (ctx == &sc->offchannel.chan)
1115 return ath9k_set_offchannel_state(sc);
1116#endif
1117
9a9c4fbc
RM
1118 ath9k_ps_wakeup(sc);
1119 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1120
1121 if (iter_data.has_hw_macaddr)
62ae1aef 1122 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
2c3db3d5 1123
4801416c
BG
1124 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1125 ath_hw_setbssidmask(common);
1126
4801416c 1127 if (iter_data.naps > 0) {
60ca9f87 1128 ath9k_hw_set_tsfadjust(ah, true);
4801416c
BG
1129 ah->opmode = NL80211_IFTYPE_AP;
1130 } else {
60ca9f87 1131 ath9k_hw_set_tsfadjust(ah, false);
cfda2d8e
BB
1132 if (iter_data.beacons)
1133 ath9k_beacon_ensure_primary_slot(sc);
5640b08e 1134
fd5999cf
JC
1135 if (iter_data.nmeshes)
1136 ah->opmode = NL80211_IFTYPE_MESH_POINT;
862a336c
JK
1137 else if (iter_data.nocbs)
1138 ah->opmode = NL80211_IFTYPE_OCB;
fd5999cf 1139 else if (iter_data.nwds)
4801416c
BG
1140 ah->opmode = NL80211_IFTYPE_AP;
1141 else if (iter_data.nadhocs)
1142 ah->opmode = NL80211_IFTYPE_ADHOC;
1143 else
1144 ah->opmode = NL80211_IFTYPE_STATION;
1145 }
5640b08e 1146
df35d29e
SM
1147 ath9k_hw_setopmode(ah);
1148
748299f2 1149 ctx->switch_after_beacon = false;
198823fd 1150 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 1151 ah->imask |= ATH9K_INT_TSFOOR;
748299f2 1152 else {
4801416c 1153 ah->imask &= ~ATH9K_INT_TSFOOR;
748299f2
FF
1154 if (iter_data.naps == 1 && iter_data.beacons)
1155 ctx->switch_after_beacon = true;
1156 }
4af9cf4f 1157
9a9c4fbc
RM
1158 if (ah->opmode == NL80211_IFTYPE_STATION) {
1159 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1160
9a9c4fbc 1161 if (iter_data.primary_sta) {
05860bed 1162 iter_data.primary_beacon_vif = iter_data.primary_sta;
602607b6 1163 iter_data.beacons = true;
9a9c4fbc
RM
1164 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1165 changed);
1030f9fe 1166 ctx->primary_sta = iter_data.primary_sta;
9a9c4fbc
RM
1167 } else {
1168 ctx->primary_sta = NULL;
93803b33 1169 eth_zero_addr(common->curbssid);
9a9c4fbc
RM
1170 common->curaid = 0;
1171 ath9k_hw_write_associd(sc->sc_ah);
1172 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1173 ath9k_mci_update_wlan_channels(sc, true);
1174 }
9a9c4fbc 1175 }
cfda2d8e
BB
1176 sc->nbcnvifs = iter_data.nbcnvifs;
1177 ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1178 iter_data.beacons);
72d874c6 1179 ath9k_hw_set_interrupts(ah);
6dcc3444 1180
9a9c4fbc
RM
1181 if (ah->slottime != iter_data.slottime) {
1182 ah->slottime = iter_data.slottime;
1183 ath9k_hw_init_global_settings(ah);
6dcc3444 1184 }
9a9c4fbc
RM
1185
1186 if (iter_data.primary_sta)
1187 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1188 else
1189 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1190
2ce73c02
SM
1191 ath_dbg(common, CONFIG,
1192 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1193 common->macaddr, common->curbssid, common->bssidmask);
1194
9a9c4fbc 1195 ath9k_ps_restore(sc);
4801416c 1196}
6f255425 1197
283dd119
LB
1198static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1199{
1200 int *power = (int *)data;
1201
1202 if (*power < vif->bss_conf.txpower)
1203 *power = vif->bss_conf.txpower;
1204}
1205
1206/* Called with sc->mutex held. */
1207void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1208{
1209 int power;
1210 struct ath_hw *ah = sc->sc_ah;
1211 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1212
1213 ath9k_ps_wakeup(sc);
1214 if (ah->tpc_enabled) {
1215 power = (vif) ? vif->bss_conf.txpower : -1;
1216 ieee80211_iterate_active_interfaces_atomic(
1217 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1218 ath9k_tpc_vif_iter, &power);
1219 if (power == -1)
1220 power = sc->hw->conf.power_level;
1221 } else {
1222 power = sc->hw->conf.power_level;
1223 }
1224 sc->cur_chan->txpower = 2 * power;
1225 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1226 sc->cur_chan->cur_txpower = reg->max_power_level;
1227 ath9k_ps_restore(sc);
1228}
1229
a4027644
SM
1230static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1231 struct ieee80211_vif *vif)
1232{
1233 int i;
1234
868caae3
SM
1235 if (!ath9k_is_chanctx_enabled())
1236 return;
1237
a4027644
SM
1238 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1239 vif->hw_queue[i] = i;
1240
4b870c26
CYY
1241 if (vif->type == NL80211_IFTYPE_AP ||
1242 vif->type == NL80211_IFTYPE_MESH_POINT)
a4027644
SM
1243 vif->cab_queue = hw->queues - 2;
1244 else
1245 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1246}
1247
4801416c
BG
1248static int ath9k_add_interface(struct ieee80211_hw *hw,
1249 struct ieee80211_vif *vif)
6b3b991d 1250{
9ac58615 1251 struct ath_softc *sc = hw->priv;
4801416c
BG
1252 struct ath_hw *ah = sc->sc_ah;
1253 struct ath_common *common = ath9k_hw_common(ah);
f89d1bc4
FF
1254 struct ath_vif *avp = (void *)vif->drv_priv;
1255 struct ath_node *an = &avp->mcast_node;
6b3b991d 1256
4801416c 1257 mutex_lock(&sc->mutex);
6b3b991d 1258
97f2645f 1259 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
ca529c93 1260 if (sc->cur_chan->nvifs >= 1) {
89f927af
LR
1261 mutex_unlock(&sc->mutex);
1262 return -EOPNOTSUPP;
1263 }
1264 sc->tx99_vif = vif;
1265 }
1266
d2182b69 1267 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
ca529c93 1268 sc->cur_chan->nvifs++;
4801416c 1269
b9a9693f
KV
1270 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1271 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1272
130ef6e9
SM
1273 if (ath9k_uses_beacons(vif->type))
1274 ath9k_beacon_assign_slot(sc, vif);
1275
d463af4a 1276 avp->vif = vif;
499afacc 1277 if (!ath9k_is_chanctx_enabled()) {
39305635 1278 avp->chanctx = sc->cur_chan;
9a9c4fbc
RM
1279 list_add_tail(&avp->list, &avp->chanctx->vifs);
1280 }
a4027644 1281
daad1660
BG
1282 ath9k_calculate_summary_state(sc, avp->chanctx);
1283
a4027644 1284 ath9k_assign_hw_queues(hw, vif);
0453531e 1285
283dd119
LB
1286 ath9k_set_txpower(sc, vif);
1287
f89d1bc4
FF
1288 an->sc = sc;
1289 an->sta = NULL;
1290 an->vif = vif;
1291 an->no_ps_filter = true;
1292 ath_tx_node_init(sc, an);
1293
4801416c 1294 mutex_unlock(&sc->mutex);
327967cb 1295 return 0;
6b3b991d
RM
1296}
1297
1298static int ath9k_change_interface(struct ieee80211_hw *hw,
1299 struct ieee80211_vif *vif,
1300 enum nl80211_iftype new_type,
1301 bool p2p)
1302{
9ac58615 1303 struct ath_softc *sc = hw->priv;
6b3b991d 1304 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c083ce99 1305 struct ath_vif *avp = (void *)vif->drv_priv;
6b3b991d 1306
6b3b991d 1307 mutex_lock(&sc->mutex);
4801416c 1308
97f2645f 1309 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
89f927af
LR
1310 mutex_unlock(&sc->mutex);
1311 return -EOPNOTSUPP;
1312 }
1313
1314 ath_dbg(common, CONFIG, "Change Interface\n");
1315
4801416c 1316 if (ath9k_uses_beacons(vif->type))
130ef6e9 1317 ath9k_beacon_remove_slot(sc, vif);
4801416c 1318
6b3b991d
RM
1319 vif->type = new_type;
1320 vif->p2p = p2p;
1321
130ef6e9
SM
1322 if (ath9k_uses_beacons(vif->type))
1323 ath9k_beacon_assign_slot(sc, vif);
9a9c4fbc 1324
a4027644 1325 ath9k_assign_hw_queues(hw, vif);
9a9c4fbc 1326 ath9k_calculate_summary_state(sc, avp->chanctx);
130ef6e9 1327
283dd119
LB
1328 ath9k_set_txpower(sc, vif);
1329
6b3b991d 1330 mutex_unlock(&sc->mutex);
327967cb 1331 return 0;
6b3b991d
RM
1332}
1333
8feceb67 1334static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1335 struct ieee80211_vif *vif)
f078f209 1336{
9ac58615 1337 struct ath_softc *sc = hw->priv;
c46917bb 1338 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f89d1bc4 1339 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 1340
d2182b69 1341 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1342
141b38b6
S
1343 mutex_lock(&sc->mutex);
1344
c7dd40c9 1345 ath9k_p2p_remove_vif(sc, vif);
d463af4a 1346
ca529c93 1347 sc->cur_chan->nvifs--;
89f927af 1348 sc->tx99_vif = NULL;
499afacc 1349 if (!ath9k_is_chanctx_enabled())
9a9c4fbc 1350 list_del(&avp->list);
580f0b8a 1351
4801416c 1352 if (ath9k_uses_beacons(vif->type))
130ef6e9 1353 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1354
f89d1bc4
FF
1355 ath_tx_node_cleanup(sc, &avp->mcast_node);
1356
daad1660
BG
1357 ath9k_calculate_summary_state(sc, avp->chanctx);
1358
283dd119
LB
1359 ath9k_set_txpower(sc, NULL);
1360
141b38b6 1361 mutex_unlock(&sc->mutex);
f078f209
LR
1362}
1363
fbab7390 1364static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1365{
3069168c 1366 struct ath_hw *ah = sc->sc_ah;
ad128860 1367 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1368
97f2645f 1369 if (IS_ENABLED(CONFIG_ATH9K_TX99))
89f927af
LR
1370 return;
1371
3f7c5c10 1372 sc->ps_enabled = true;
3069168c
PR
1373 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1374 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1375 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1376 ath9k_hw_set_interrupts(ah);
3f7c5c10 1377 }
fdf76622 1378 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1379 }
ad128860 1380 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB
1381}
1382
845d708e
SB
1383static void ath9k_disable_ps(struct ath_softc *sc)
1384{
1385 struct ath_hw *ah = sc->sc_ah;
ad128860 1386 struct ath_common *common = ath9k_hw_common(ah);
845d708e 1387
97f2645f 1388 if (IS_ENABLED(CONFIG_ATH9K_TX99))
89f927af
LR
1389 return;
1390
845d708e
SB
1391 sc->ps_enabled = false;
1392 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1393 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1394 ath9k_hw_setrxabort(ah, 0);
1395 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1396 PS_WAIT_FOR_CAB |
1397 PS_WAIT_FOR_PSPOLL_DATA |
1398 PS_WAIT_FOR_TX_ACK);
1399 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1400 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1401 ath9k_hw_set_interrupts(ah);
845d708e
SB
1402 }
1403 }
ad128860 1404 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB
1405}
1406
e8975581 1407static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1408{
9ac58615 1409 struct ath_softc *sc = hw->priv;
3430098a
FF
1410 struct ath_hw *ah = sc->sc_ah;
1411 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1412 struct ieee80211_conf *conf = &hw->conf;
fbbcd146 1413 struct ath_chanctx *ctx = sc->cur_chan;
f078f209 1414
c0c11741 1415 ath9k_ps_wakeup(sc);
aa33de09 1416 mutex_lock(&sc->mutex);
141b38b6 1417
daa1b6ee 1418 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1419 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1420 if (sc->ps_idle) {
daa1b6ee 1421 ath_cancel_work(sc);
b73f3e78
RM
1422 ath9k_stop_btcoex(sc);
1423 } else {
1424 ath9k_start_btcoex(sc);
75600abf
FF
1425 /*
1426 * The chip needs a reset to properly wake up from
1427 * full sleep
1428 */
39305635 1429 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
b73f3e78 1430 }
daa1b6ee 1431 }
64839170 1432
e7824a50
LR
1433 /*
1434 * We just prepare to enable PS. We have to wait until our AP has
1435 * ACK'd our null data frame to disable RX otherwise we'll ignore
1436 * those ACKs and end up retransmitting the same null data frames.
1437 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1438 */
3cbb5dd7 1439 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1440 unsigned long flags;
1441 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1442 if (conf->flags & IEEE80211_CONF_PS)
1443 ath9k_enable_ps(sc);
845d708e
SB
1444 else
1445 ath9k_disable_ps(sc);
8ab2cd09 1446 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1447 }
1448
199afd9d
S
1449 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1450 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1451 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM
1452 sc->sc_ah->is_monitoring = true;
1453 } else {
d2182b69 1454 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1455 sc->sc_ah->is_monitoring = false;
199afd9d
S
1456 }
1457 }
1458
499afacc 1459 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
fbbcd146 1460 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
bff11766 1461 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
094d05dc 1462 }
f078f209 1463
aa33de09 1464 mutex_unlock(&sc->mutex);
c0c11741 1465 ath9k_ps_restore(sc);
141b38b6 1466
f078f209
LR
1467 return 0;
1468}
1469
8feceb67 1470#define SUPPORTED_FILTERS \
df140465 1471 (FIF_ALLMULTI | \
8feceb67 1472 FIF_CONTROL | \
af6a3fc7 1473 FIF_PSPOLL | \
8feceb67
VT
1474 FIF_OTHER_BSS | \
1475 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1476 FIF_PROBE_REQ | \
8feceb67 1477 FIF_FCSFAIL)
c83be688 1478
8feceb67
VT
1479/* FIXME: sc->sc_full_reset ? */
1480static void ath9k_configure_filter(struct ieee80211_hw *hw,
1481 unsigned int changed_flags,
1482 unsigned int *total_flags,
3ac64bee 1483 u64 multicast)
8feceb67 1484{
9ac58615 1485 struct ath_softc *sc = hw->priv;
f3771c08 1486 struct ath_chanctx *ctx;
8feceb67 1487 u32 rfilt;
f078f209 1488
8feceb67
VT
1489 changed_flags &= SUPPORTED_FILTERS;
1490 *total_flags &= SUPPORTED_FILTERS;
f078f209 1491
fce34430 1492 spin_lock_bh(&sc->chan_lock);
f3771c08
JD
1493 ath_for_each_chanctx(sc, ctx)
1494 ctx->rxfilter = *total_flags;
1738203e
JD
1495#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1496 sc->offchannel.chan.rxfilter = *total_flags;
1497#endif
fce34430
SM
1498 spin_unlock_bh(&sc->chan_lock);
1499
aa68aeaa 1500 ath9k_ps_wakeup(sc);
8feceb67
VT
1501 rfilt = ath_calcrxfilter(sc);
1502 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1503 ath9k_ps_restore(sc);
f078f209 1504
d2182b69
JP
1505 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1506 rfilt);
8feceb67 1507}
f078f209 1508
4ca77860
JB
1509static int ath9k_sta_add(struct ieee80211_hw *hw,
1510 struct ieee80211_vif *vif,
1511 struct ieee80211_sta *sta)
8feceb67 1512{
9ac58615 1513 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1514 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1515 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1516 struct ieee80211_key_conf ps_key = { };
4ef69d03 1517 int key;
f078f209 1518
7e1e3864 1519 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1520
1521 if (vif->type != NL80211_IFTYPE_AP &&
1522 vif->type != NL80211_IFTYPE_AP_VLAN)
1523 return 0;
1524
4ef69d03 1525 key = ath_key_config(common, vif, sta, &ps_key);
4bbf4414 1526 if (key > 0) {
4ef69d03 1527 an->ps_key = key;
4bbf4414
RM
1528 an->key_idx[0] = key;
1529 }
4ca77860
JB
1530
1531 return 0;
1532}
1533
93ae2dd2
FF
1534static void ath9k_del_ps_key(struct ath_softc *sc,
1535 struct ieee80211_vif *vif,
1536 struct ieee80211_sta *sta)
1537{
1538 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1539 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1540 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1541
1542 if (!an->ps_key)
1543 return;
1544
1545 ath_key_delete(common, &ps_key);
4ef69d03 1546 an->ps_key = 0;
4bbf4414 1547 an->key_idx[0] = 0;
93ae2dd2
FF
1548}
1549
4ca77860
JB
1550static int ath9k_sta_remove(struct ieee80211_hw *hw,
1551 struct ieee80211_vif *vif,
1552 struct ieee80211_sta *sta)
1553{
9ac58615 1554 struct ath_softc *sc = hw->priv;
4ca77860 1555
93ae2dd2 1556 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1557 ath_node_detach(sc, sta);
1558
1559 return 0;
f078f209
LR
1560}
1561
df3c6eb3
SM
1562static int ath9k_sta_state(struct ieee80211_hw *hw,
1563 struct ieee80211_vif *vif,
1564 struct ieee80211_sta *sta,
1565 enum ieee80211_sta_state old_state,
1566 enum ieee80211_sta_state new_state)
1567{
1568 struct ath_softc *sc = hw->priv;
1569 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1570 int ret = 0;
1571
7711aaf0
FF
1572 if (old_state == IEEE80211_STA_NOTEXIST &&
1573 new_state == IEEE80211_STA_NONE) {
df3c6eb3
SM
1574 ret = ath9k_sta_add(hw, vif, sta);
1575 ath_dbg(common, CONFIG,
1576 "Add station: %pM\n", sta->addr);
7711aaf0
FF
1577 } else if (old_state == IEEE80211_STA_NONE &&
1578 new_state == IEEE80211_STA_NOTEXIST) {
df3c6eb3
SM
1579 ret = ath9k_sta_remove(hw, vif, sta);
1580 ath_dbg(common, CONFIG,
1581 "Remove station: %pM\n", sta->addr);
1582 }
1583
b8f9279b 1584 if (ath9k_is_chanctx_enabled()) {
91e6ceb3
SM
1585 if (vif->type == NL80211_IFTYPE_STATION) {
1586 if (old_state == IEEE80211_STA_ASSOC &&
1587 new_state == IEEE80211_STA_AUTHORIZED)
1588 ath_chanctx_event(sc, vif,
1589 ATH_CHANCTX_EVENT_AUTHORIZED);
1590 }
b8f9279b
SM
1591 }
1592
df3c6eb3
SM
1593 return ret;
1594}
1595
4bbf4414
RM
1596static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1597 struct ath_node *an,
1598 bool set)
1599{
1600 int i;
1601
1602 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1603 if (!an->key_idx[i])
1604 continue;
1605 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1606 }
1607}
1608
5519541d
FF
1609static void ath9k_sta_notify(struct ieee80211_hw *hw,
1610 struct ieee80211_vif *vif,
1611 enum sta_notify_cmd cmd,
1612 struct ieee80211_sta *sta)
1613{
1614 struct ath_softc *sc = hw->priv;
1615 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1616
1617 switch (cmd) {
1618 case STA_NOTIFY_SLEEP:
1619 an->sleeping = true;
042ec453 1620 ath_tx_aggr_sleep(sta, sc, an);
4bbf4414 1621 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
5519541d
FF
1622 break;
1623 case STA_NOTIFY_AWAKE:
4bbf4414 1624 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
5519541d
FF
1625 an->sleeping = false;
1626 ath_tx_aggr_wakeup(sc, an);
1627 break;
1628 }
1629}
1630
8a3a3c85
EP
1631static int ath9k_conf_tx(struct ieee80211_hw *hw,
1632 struct ieee80211_vif *vif, u16 queue,
8feceb67 1633 const struct ieee80211_tx_queue_params *params)
f078f209 1634{
9ac58615 1635 struct ath_softc *sc = hw->priv;
c46917bb 1636 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1637 struct ath_txq *txq;
8feceb67 1638 struct ath9k_tx_queue_info qi;
066dae93 1639 int ret = 0;
f078f209 1640
bea843c7 1641 if (queue >= IEEE80211_NUM_ACS)
8feceb67 1642 return 0;
f078f209 1643
066dae93
FF
1644 txq = sc->tx.txq_map[queue];
1645
96f372c9 1646 ath9k_ps_wakeup(sc);
141b38b6
S
1647 mutex_lock(&sc->mutex);
1648
1ffb0610
S
1649 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1650
8feceb67
VT
1651 qi.tqi_aifs = params->aifs;
1652 qi.tqi_cwmin = params->cw_min;
1653 qi.tqi_cwmax = params->cw_max;
531bd079 1654 qi.tqi_burstTime = params->txop * 32;
f078f209 1655
d2182b69 1656 ath_dbg(common, CONFIG,
226afe68
JP
1657 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1658 queue, txq->axq_qnum, params->aifs, params->cw_min,
1659 params->cw_max, params->txop);
f078f209 1660
aa5955c3 1661 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1662 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1663 if (ret)
3800276a 1664 ath_err(common, "TXQ Update failed\n");
f078f209 1665
141b38b6 1666 mutex_unlock(&sc->mutex);
96f372c9 1667 ath9k_ps_restore(sc);
141b38b6 1668
8feceb67
VT
1669 return ret;
1670}
f078f209 1671
8feceb67
VT
1672static int ath9k_set_key(struct ieee80211_hw *hw,
1673 enum set_key_cmd cmd,
dc822b5d
JB
1674 struct ieee80211_vif *vif,
1675 struct ieee80211_sta *sta,
8feceb67
VT
1676 struct ieee80211_key_conf *key)
1677{
9ac58615 1678 struct ath_softc *sc = hw->priv;
c46917bb 1679 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4bbf4414
RM
1680 struct ath_node *an = NULL;
1681 int ret = 0, i;
f078f209 1682
3e6109c5 1683 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1684 return -ENOSPC;
1685
5bd5e9a6
CYY
1686 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1687 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM
1688 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1689 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1690 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1691 /*
1692 * For now, disable hw crypto for the RSN IBSS group keys. This
1693 * could be optimized in the future to use a modified key cache
1694 * design to support per-STA RX GTK, but until that gets
1695 * implemented, use of software crypto for group addressed
1696 * frames is a acceptable to allow RSN IBSS to be used.
1697 */
1698 return -EOPNOTSUPP;
1699 }
1700
141b38b6 1701 mutex_lock(&sc->mutex);
3cbb5dd7 1702 ath9k_ps_wakeup(sc);
4bbf4414
RM
1703 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1704 if (sta)
1705 an = (struct ath_node *)sta->drv_priv;
f078f209 1706
8feceb67
VT
1707 switch (cmd) {
1708 case SET_KEY:
93ae2dd2
FF
1709 if (sta)
1710 ath9k_del_ps_key(sc, vif, sta);
1711
4bbf4414 1712 key->hw_key_idx = 0;
040e539e 1713 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1714 if (ret >= 0) {
1715 key->hw_key_idx = ret;
8feceb67
VT
1716 /* push IV and Michael MIC generation to stack */
1717 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1718 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1719 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e6510b11 1720 if (sc->sc_ah->sw_mgmt_crypto_tx &&
97359d12 1721 key->cipher == WLAN_CIPHER_SUITE_CCMP)
e548c49e 1722 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6ace2891 1723 ret = 0;
8feceb67 1724 }
4bbf4414
RM
1725 if (an && key->hw_key_idx) {
1726 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1727 if (an->key_idx[i])
1728 continue;
1729 an->key_idx[i] = key->hw_key_idx;
1730 break;
1731 }
1732 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1733 }
8feceb67
VT
1734 break;
1735 case DISABLE_KEY:
040e539e 1736 ath_key_delete(common, key);
4bbf4414
RM
1737 if (an) {
1738 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1739 if (an->key_idx[i] != key->hw_key_idx)
1740 continue;
1741 an->key_idx[i] = 0;
1742 break;
1743 }
1744 }
1745 key->hw_key_idx = 0;
8feceb67
VT
1746 break;
1747 default:
1748 ret = -EINVAL;
1749 }
f078f209 1750
3cbb5dd7 1751 ath9k_ps_restore(sc);
141b38b6
S
1752 mutex_unlock(&sc->mutex);
1753
8feceb67
VT
1754 return ret;
1755}
6c43c090 1756
8feceb67
VT
1757static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1758 struct ieee80211_vif *vif,
1759 struct ieee80211_bss_conf *bss_conf,
1760 u32 changed)
1761{
da0d45f7
SM
1762#define CHECK_ANI \
1763 (BSS_CHANGED_ASSOC | \
1764 BSS_CHANGED_IBSS | \
1765 BSS_CHANGED_BEACON_ENABLED)
1766
9ac58615 1767 struct ath_softc *sc = hw->priv;
2d0ddec5 1768 struct ath_hw *ah = sc->sc_ah;
1510718d 1769 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1770 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1771 int slottime;
f078f209 1772
96f372c9 1773 ath9k_ps_wakeup(sc);
141b38b6
S
1774 mutex_lock(&sc->mutex);
1775
9f61903c 1776 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM
1777 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1778 bss_conf->bssid, bss_conf->assoc);
1779
62ae1aef 1780 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
cb35582a
SM
1781 avp->aid = bss_conf->aid;
1782 avp->assoc = bss_conf->assoc;
1783
9a9c4fbc 1784 ath9k_calculate_summary_state(sc, avp->chanctx);
c6089ccc 1785 }
2d0ddec5 1786
862a336c
JK
1787 if ((changed & BSS_CHANGED_IBSS) ||
1788 (changed & BSS_CHANGED_OCB)) {
2e5ef459
RM
1789 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1790 common->curaid = bss_conf->aid;
1791 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM
1792 }
1793
ef4ad633 1794 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
9198cf4a
RM
1795 (changed & BSS_CHANGED_BEACON_INT) ||
1796 (changed & BSS_CHANGED_BEACON_INFO)) {
cfda2d8e 1797 ath9k_calculate_summary_state(sc, avp->chanctx);
9a9c4fbc 1798 }
0005baf4 1799
9a9c4fbc
RM
1800 if ((avp->chanctx == sc->cur_chan) &&
1801 (changed & BSS_CHANGED_ERP_SLOT)) {
0005baf4
FF
1802 if (bss_conf->use_short_slot)
1803 slottime = 9;
1804 else
1805 slottime = 20;
11b0ac2e 1806
0005baf4
FF
1807 if (vif->type == NL80211_IFTYPE_AP) {
1808 /*
1809 * Defer update, so that connected stations can adjust
1810 * their settings at the same time.
1811 * See beacon.c for more details
1812 */
1813 sc->beacon.slottime = slottime;
1814 sc->beacon.updateslot = UPDATE;
1815 } else {
1816 ah->slottime = slottime;
1817 ath9k_hw_init_global_settings(ah);
1818 }
2d0ddec5
JB
1819 }
1820
c7dd40c9
SM
1821 if (changed & BSS_CHANGED_P2P_PS)
1822 ath9k_p2p_bss_info_changed(sc, vif);
d463af4a 1823
da0d45f7
SM
1824 if (changed & CHECK_ANI)
1825 ath_check_ani(sc);
1826
283dd119
LB
1827 if (changed & BSS_CHANGED_TXPOWER) {
1828 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1829 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1830 ath9k_set_txpower(sc, vif);
1831 }
1832
141b38b6 1833 mutex_unlock(&sc->mutex);
96f372c9 1834 ath9k_ps_restore(sc);
da0d45f7
SM
1835
1836#undef CHECK_ANI
8feceb67 1837}
f078f209 1838
37a41b4a 1839static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1840{
9ac58615 1841 struct ath_softc *sc = hw->priv;
9580cb88 1842 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1843 u64 tsf;
f078f209 1844
141b38b6 1845 mutex_lock(&sc->mutex);
9abbfb27 1846 ath9k_ps_wakeup(sc);
9580cb88
BB
1847 /* Get current TSF either from HW or kernel time. */
1848 if (sc->cur_chan == avp->chanctx) {
1849 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1850 } else {
1851 tsf = sc->cur_chan->tsf_val +
1852 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1853 }
7fde5122 1854 tsf += le64_to_cpu(avp->tsf_adjust);
9abbfb27 1855 ath9k_ps_restore(sc);
141b38b6 1856 mutex_unlock(&sc->mutex);
f078f209 1857
8feceb67
VT
1858 return tsf;
1859}
f078f209 1860
37a41b4a
EP
1861static void ath9k_set_tsf(struct ieee80211_hw *hw,
1862 struct ieee80211_vif *vif,
1863 u64 tsf)
3b5d665b 1864{
9ac58615 1865 struct ath_softc *sc = hw->priv;
9580cb88 1866 struct ath_vif *avp = (void *)vif->drv_priv;
3b5d665b 1867
141b38b6 1868 mutex_lock(&sc->mutex);
9abbfb27 1869 ath9k_ps_wakeup(sc);
7fde5122 1870 tsf -= le64_to_cpu(avp->tsf_adjust);
9580cb88
BB
1871 getrawmonotonic(&avp->chanctx->tsf_ts);
1872 if (sc->cur_chan == avp->chanctx)
1873 ath9k_hw_settsf64(sc->sc_ah, tsf);
1874 avp->chanctx->tsf_val = tsf;
9abbfb27 1875 ath9k_ps_restore(sc);
141b38b6 1876 mutex_unlock(&sc->mutex);
3b5d665b
AF
1877}
1878
37a41b4a 1879static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1880{
9ac58615 1881 struct ath_softc *sc = hw->priv;
9580cb88 1882 struct ath_vif *avp = (void *)vif->drv_priv;
c83be688 1883
141b38b6 1884 mutex_lock(&sc->mutex);
21526d57
LR
1885
1886 ath9k_ps_wakeup(sc);
9580cb88
BB
1887 getrawmonotonic(&avp->chanctx->tsf_ts);
1888 if (sc->cur_chan == avp->chanctx)
1889 ath9k_hw_reset_tsf(sc->sc_ah);
1890 avp->chanctx->tsf_val = 0;
21526d57
LR
1891 ath9k_ps_restore(sc);
1892
141b38b6 1893 mutex_unlock(&sc->mutex);
8feceb67 1894}
f078f209 1895
8feceb67 1896static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1897 struct ieee80211_vif *vif,
50ea05ef 1898 struct ieee80211_ampdu_params *params)
8feceb67 1899{
9ac58615 1900 struct ath_softc *sc = hw->priv;
1e929d3e 1901 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
16e23428 1902 bool flush = false;
8feceb67 1903 int ret = 0;
50ea05ef
SS
1904 struct ieee80211_sta *sta = params->sta;
1905 enum ieee80211_ampdu_mlme_action action = params->action;
1906 u16 tid = params->tid;
1907 u16 *ssn = &params->ssn;
f078f209 1908
7ca7c776 1909 mutex_lock(&sc->mutex);
85ad181e 1910
8feceb67
VT
1911 switch (action) {
1912 case IEEE80211_AMPDU_RX_START:
8feceb67
VT
1913 break;
1914 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1915 break;
1916 case IEEE80211_AMPDU_TX_START:
1e929d3e
SM
1917 if (ath9k_is_chanctx_enabled()) {
1918 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1919 ret = -EBUSY;
1920 break;
1921 }
1922 }
8b685ba9 1923 ath9k_ps_wakeup(sc);
231c3a1f
FF
1924 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1925 if (!ret)
1926 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1927 ath9k_ps_restore(sc);
8feceb67 1928 break;
18b559d5
JB
1929 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1930 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
16e23428
FF
1931 flush = true;
1932 case IEEE80211_AMPDU_TX_STOP_CONT:
8b685ba9 1933 ath9k_ps_wakeup(sc);
f83da965 1934 ath_tx_aggr_stop(sc, sta, tid);
08c96abd 1935 if (!flush)
16e23428 1936 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1937 ath9k_ps_restore(sc);
8feceb67 1938 break;
b1720231 1939 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1940 ath9k_ps_wakeup(sc);
8469cdef 1941 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1942 ath9k_ps_restore(sc);
8469cdef 1943 break;
8feceb67 1944 default:
3800276a 1945 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
1946 }
1947
7ca7c776 1948 mutex_unlock(&sc->mutex);
85ad181e 1949
8feceb67 1950 return ret;
f078f209
LR
1951}
1952
62dad5b0
BP
1953static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1954 struct survey_info *survey)
1955{
9ac58615 1956 struct ath_softc *sc = hw->priv;
3430098a 1957 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1958 struct ieee80211_supported_band *sband;
3430098a 1959 struct ieee80211_channel *chan;
3430098a
FF
1960 int pos;
1961
97f2645f 1962 if (IS_ENABLED(CONFIG_ATH9K_TX99))
89f927af
LR
1963 return -EOPNOTSUPP;
1964
b7cc9b97 1965 spin_lock_bh(&common->cc_lock);
3430098a
FF
1966 if (idx == 0)
1967 ath_update_survey_stats(sc);
39162dbe 1968
57fbcce3 1969 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
39162dbe
FF
1970 if (sband && idx >= sband->n_channels) {
1971 idx -= sband->n_channels;
1972 sband = NULL;
1973 }
62dad5b0 1974
39162dbe 1975 if (!sband)
57fbcce3 1976 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
62dad5b0 1977
3430098a 1978 if (!sband || idx >= sband->n_channels) {
b7cc9b97 1979 spin_unlock_bh(&common->cc_lock);
3430098a 1980 return -ENOENT;
4f1a5a4b 1981 }
62dad5b0 1982
3430098a
FF
1983 chan = &sband->channels[idx];
1984 pos = chan->hw_value;
1985 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1986 survey->channel = chan;
b7cc9b97 1987 spin_unlock_bh(&common->cc_lock);
3430098a 1988
62dad5b0
BP
1989 return 0;
1990}
1991
24a1936b
LB
1992static void ath9k_enable_dynack(struct ath_softc *sc)
1993{
1994#ifdef CONFIG_ATH9K_DYNACK
1995 u32 rfilt;
1996 struct ath_hw *ah = sc->sc_ah;
1997
1998 ath_dynack_reset(ah);
1999
2000 ah->dynack.enabled = true;
2001 rfilt = ath_calcrxfilter(sc);
2002 ath9k_hw_setrxfilter(ah, rfilt);
2003#endif
2004}
2005
a4bcaf55
LB
2006static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2007 s16 coverage_class)
e239d859 2008{
9ac58615 2009 struct ath_softc *sc = hw->priv;
e239d859
FF
2010 struct ath_hw *ah = sc->sc_ah;
2011
97f2645f 2012 if (IS_ENABLED(CONFIG_ATH9K_TX99))
89f927af
LR
2013 return;
2014
e239d859 2015 mutex_lock(&sc->mutex);
8b2a3827 2016
24a1936b
LB
2017 if (coverage_class >= 0) {
2018 ah->coverage_class = coverage_class;
2019 if (ah->dynack.enabled) {
2020 u32 rfilt;
2021
2022 ah->dynack.enabled = false;
2023 rfilt = ath_calcrxfilter(sc);
2024 ath9k_hw_setrxfilter(ah, rfilt);
2025 }
2026 ath9k_ps_wakeup(sc);
2027 ath9k_hw_init_global_settings(ah);
2028 ath9k_ps_restore(sc);
2029 } else if (!ah->dynack.enabled) {
2030 ath9k_enable_dynack(sc);
2031 }
8b2a3827 2032
e239d859
FF
2033 mutex_unlock(&sc->mutex);
2034}
2035
e2d389b5
SM
2036static bool ath9k_has_tx_pending(struct ath_softc *sc,
2037 bool sw_pending)
10e23181 2038{
f7838073 2039 int i, npend = 0;
10e23181
FF
2040
2041 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2042 if (!ATH_TXQ_SETUP(sc, i))
2043 continue;
2044
e2d389b5
SM
2045 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2046 sw_pending);
10e23181
FF
2047 if (npend)
2048 break;
2049 }
2050
2051 return !!npend;
2052}
2053
77be2c54
EG
2054static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2055 u32 queues, bool drop)
bff11766
FF
2056{
2057 struct ath_softc *sc = hw->priv;
25f3bc7d
SM
2058 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2059
2060 if (ath9k_is_chanctx_enabled()) {
2061 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2062 goto flush;
bff11766 2063
25f3bc7d
SM
2064 /*
2065 * If MCC is active, extend the flush timeout
2066 * and wait for the HW/SW queues to become
2067 * empty. This needs to be done outside the
2068 * sc->mutex lock to allow the channel scheduler
2069 * to switch channel contexts.
2070 *
2071 * The vif queues have been stopped in mac80211,
2072 * so there won't be any incoming frames.
2073 */
2074 __ath9k_flush(hw, queues, drop, true, true);
2075 return;
2076 }
2077flush:
bff11766 2078 mutex_lock(&sc->mutex);
25f3bc7d 2079 __ath9k_flush(hw, queues, drop, true, false);
bff11766
FF
2080 mutex_unlock(&sc->mutex);
2081}
2082
e2d389b5 2083void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
25f3bc7d 2084 bool sw_pending, bool timeout_override)
69081624 2085{
69081624 2086 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2087 struct ath_hw *ah = sc->sc_ah;
2088 struct ath_common *common = ath9k_hw_common(ah);
2fae0d9f 2089 int timeout;
2f6fc351 2090 bool drain_txq;
69081624 2091
69081624
VT
2092 cancel_delayed_work_sync(&sc->tx_complete_work);
2093
6a6b3f3e 2094 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 2095 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS
2096 return;
2097 }
2098
eefa01dd 2099 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 2100 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS
2101 return;
2102 }
2103
2fae0d9f 2104 spin_lock_bh(&sc->chan_lock);
25f3bc7d
SM
2105 if (timeout_override)
2106 timeout = HZ / 5;
2107 else
2108 timeout = sc->cur_chan->flush_timeout;
2fae0d9f
SM
2109 spin_unlock_bh(&sc->chan_lock);
2110
2111 ath_dbg(common, CHAN_CTX,
2112 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2113
e2d389b5 2114 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
10e23181
FF
2115 timeout) > 0)
2116 drop = false;
69081624 2117
9df0d6a2
FF
2118 if (drop) {
2119 ath9k_ps_wakeup(sc);
2120 spin_lock_bh(&sc->sc_pcu_lock);
1381559b 2121 drain_txq = ath_drain_all_txq(sc);
9df0d6a2 2122 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 2123
9df0d6a2 2124 if (!drain_txq)
5555c955 2125 ath_reset(sc, NULL);
9adcf440 2126
9df0d6a2 2127 ath9k_ps_restore(sc);
9df0d6a2 2128 }
d78f4b3e 2129
69081624 2130 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
69081624
VT
2131}
2132
15b91e83
VN
2133static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2134{
2135 struct ath_softc *sc = hw->priv;
15b91e83 2136
e2d389b5 2137 return ath9k_has_tx_pending(sc, true);
15b91e83
VN
2138}
2139
5595f119 2140static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2141{
2142 struct ath_softc *sc = hw->priv;
2143 struct ath_hw *ah = sc->sc_ah;
2144 struct ieee80211_vif *vif;
2145 struct ath_vif *avp;
2146 struct ath_buf *bf;
2147 struct ath_tx_status ts;
4286df60 2148 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF
2149 int status;
2150
2151 vif = sc->beacon.bslot[0];
2152 if (!vif)
2153 return 0;
2154
aa45fe96 2155 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF
2156 return 0;
2157
aa45fe96
SM
2158 avp = (void *)vif->drv_priv;
2159
4286df60 2160 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF
2161 tasklet_disable(&sc->bcon_tasklet);
2162
2163 bf = avp->av_bcbuf;
2164 if (!bf || !bf->bf_mpdu)
2165 goto skip;
2166
2167 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2168 if (status == -EINPROGRESS)
2169 goto skip;
2170
2171 sc->beacon.tx_processed = true;
2172 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2173
2174skip:
2175 tasklet_enable(&sc->bcon_tasklet);
2176 }
2177
2178 return sc->beacon.tx_last;
2179}
2180
52c94f41
MSS
2181static int ath9k_get_stats(struct ieee80211_hw *hw,
2182 struct ieee80211_low_level_stats *stats)
2183{
2184 struct ath_softc *sc = hw->priv;
2185 struct ath_hw *ah = sc->sc_ah;
2186 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2187
2188 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2189 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2190 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2191 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2192 return 0;
2193}
2194
43c35284
FF
2195static u32 fill_chainmask(u32 cap, u32 new)
2196{
2197 u32 filled = 0;
2198 int i;
2199
2200 for (i = 0; cap && new; i++, cap >>= 1) {
2201 if (!(cap & BIT(0)))
2202 continue;
2203
2204 if (new & BIT(0))
2205 filled |= BIT(i);
2206
2207 new >>= 1;
2208 }
2209
2210 return filled;
2211}
2212
5d9c7e3c
FF
2213static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2214{
fea92cbf
FF
2215 if (AR_SREV_9300_20_OR_LATER(ah))
2216 return true;
2217
5d9c7e3c
FF
2218 switch (val & 0x7) {
2219 case 0x1:
2220 case 0x3:
2221 case 0x7:
2222 return true;
2223 case 0x2:
2224 return (ah->caps.rx_chainmask == 1);
2225 default:
2226 return false;
2227 }
2228}
2229
43c35284
FF
2230static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2231{
2232 struct ath_softc *sc = hw->priv;
2233 struct ath_hw *ah = sc->sc_ah;
2234
5d9c7e3c
FF
2235 if (ah->caps.rx_chainmask != 1)
2236 rx_ant |= tx_ant;
2237
2238 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF
2239 return -EINVAL;
2240
2241 sc->ant_rx = rx_ant;
2242 sc->ant_tx = tx_ant;
2243
2244 if (ah->caps.rx_chainmask == 1)
2245 return 0;
2246
2247 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2248 if (AR_SREV_9100(ah))
2249 ah->rxchainmask = 0x7;
2250 else
2251 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2252
2253 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
b57ba3b2 2254 ath9k_cmn_reload_chainmask(ah);
43c35284
FF
2255
2256 return 0;
2257}
2258
2259static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2260{
2261 struct ath_softc *sc = hw->priv;
2262
2263 *tx_ant = sc->ant_tx;
2264 *rx_ant = sc->ant_rx;
2265 return 0;
2266}
2267
a344d677
JB
2268static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2269 struct ieee80211_vif *vif,
2270 const u8 *mac_addr)
e93d083f
SW
2271{
2272 struct ath_softc *sc = hw->priv;
eefa01dd
OR
2273 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2274 set_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f
SW
2275}
2276
a344d677
JB
2277static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2278 struct ieee80211_vif *vif)
e93d083f
SW
2279{
2280 struct ath_softc *sc = hw->priv;
eefa01dd
OR
2281 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2282 clear_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f 2283}
b11e640a 2284
499afacc
SM
2285#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2286
6185672a
SM
2287static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2288{
2289 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2290
2291 if (sc->offchannel.roc_vif) {
2292 ath_dbg(common, CHAN_CTX,
2293 "%s: Aborting RoC\n", __func__);
2294
2295 del_timer_sync(&sc->offchannel.timer);
2296 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
d83520b7 2297 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
6185672a
SM
2298 }
2299
2300 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2301 ath_dbg(common, CHAN_CTX,
2302 "%s: Aborting HW scan\n", __func__);
2303
2304 del_timer_sync(&sc->offchannel.timer);
2305 ath_scan_complete(sc, true);
2306 }
2307}
2308
78b21949 2309static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
855df36d 2310 struct ieee80211_scan_request *hw_req)
78b21949 2311{
855df36d 2312 struct cfg80211_scan_request *req = &hw_req->req;
78b21949
FF
2313 struct ath_softc *sc = hw->priv;
2314 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2315 int ret = 0;
2316
2317 mutex_lock(&sc->mutex);
2318
2319 if (WARN_ON(sc->offchannel.scan_req)) {
2320 ret = -EBUSY;
2321 goto out;
2322 }
2323
2324 ath9k_ps_wakeup(sc);
2325 set_bit(ATH_OP_SCANNING, &common->op_flags);
2326 sc->offchannel.scan_vif = vif;
2327 sc->offchannel.scan_req = req;
2328 sc->offchannel.scan_idx = 0;
78b21949 2329
bc81d43a
SM
2330 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2331 vif->addr);
2332
2333 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2334 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
405393cf 2335 ath_offchannel_next(sc);
bc81d43a 2336 }
78b21949
FF
2337
2338out:
2339 mutex_unlock(&sc->mutex);
2340
2341 return ret;
2342}
2343
2344static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2345 struct ieee80211_vif *vif)
2346{
2347 struct ath_softc *sc = hw->priv;
bc81d43a
SM
2348 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2349
2350 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
78b21949
FF
2351
2352 mutex_lock(&sc->mutex);
2353 del_timer_sync(&sc->offchannel.timer);
2354 ath_scan_complete(sc, true);
2355 mutex_unlock(&sc->mutex);
2356}
2357
405393cf
FF
2358static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2359 struct ieee80211_vif *vif,
2360 struct ieee80211_channel *chan, int duration,
2361 enum ieee80211_roc_type type)
2362{
2363 struct ath_softc *sc = hw->priv;
bc81d43a 2364 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF
2365 int ret = 0;
2366
2367 mutex_lock(&sc->mutex);
2368
2369 if (WARN_ON(sc->offchannel.roc_vif)) {
2370 ret = -EBUSY;
2371 goto out;
2372 }
2373
2374 ath9k_ps_wakeup(sc);
2375 sc->offchannel.roc_vif = vif;
2376 sc->offchannel.roc_chan = chan;
2377 sc->offchannel.roc_duration = duration;
2378
bc81d43a
SM
2379 ath_dbg(common, CHAN_CTX,
2380 "RoC request on vif: %pM, type: %d duration: %d\n",
2381 vif->addr, type, duration);
2382
2383 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2384 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
405393cf 2385 ath_offchannel_next(sc);
bc81d43a 2386 }
405393cf
FF
2387
2388out:
2389 mutex_unlock(&sc->mutex);
2390
2391 return ret;
2392}
2393
2394static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2395{
2396 struct ath_softc *sc = hw->priv;
bc81d43a 2397 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF
2398
2399 mutex_lock(&sc->mutex);
2400
bc81d43a 2401 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
405393cf
FF
2402 del_timer_sync(&sc->offchannel.timer);
2403
2404 if (sc->offchannel.roc_vif) {
2405 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
d83520b7 2406 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
405393cf
FF
2407 }
2408
2409 mutex_unlock(&sc->mutex);
2410
2411 return 0;
2412}
2413
39305635
FF
2414static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2415 struct ieee80211_chanctx_conf *conf)
2416{
2417 struct ath_softc *sc = hw->priv;
bc81d43a 2418 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635 2419 struct ath_chanctx *ctx, **ptr;
3ad9c386 2420 int pos;
39305635
FF
2421
2422 mutex_lock(&sc->mutex);
c4dc0d04
RM
2423
2424 ath_for_each_chanctx(sc, ctx) {
2425 if (ctx->assigned)
2426 continue;
2427
2428 ptr = (void *) conf->drv_priv;
2429 *ptr = ctx;
2430 ctx->assigned = true;
3ad9c386
RM
2431 pos = ctx - &sc->chanctx[0];
2432 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
bc81d43a
SM
2433
2434 ath_dbg(common, CHAN_CTX,
2435 "Add channel context: %d MHz\n",
2436 conf->def.chan->center_freq);
2437
c4dc0d04 2438 ath_chanctx_set_channel(sc, ctx, &conf->def);
4c7e9aee 2439
39305635 2440 mutex_unlock(&sc->mutex);
c4dc0d04 2441 return 0;
39305635 2442 }
bc81d43a 2443
39305635 2444 mutex_unlock(&sc->mutex);
c4dc0d04 2445 return -ENOSPC;
39305635
FF
2446}
2447
2448
2449static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2450 struct ieee80211_chanctx_conf *conf)
2451{
2452 struct ath_softc *sc = hw->priv;
bc81d43a 2453 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF
2454 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2455
2456 mutex_lock(&sc->mutex);
bc81d43a
SM
2457
2458 ath_dbg(common, CHAN_CTX,
2459 "Remove channel context: %d MHz\n",
2460 conf->def.chan->center_freq);
2461
39305635 2462 ctx->assigned = false;
b18111d9 2463 ctx->hw_queue_base = 0;
73fa2f26 2464 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
bc81d43a 2465
39305635
FF
2466 mutex_unlock(&sc->mutex);
2467}
2468
2469static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2470 struct ieee80211_chanctx_conf *conf,
2471 u32 changed)
2472{
2473 struct ath_softc *sc = hw->priv;
bc81d43a 2474 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF
2475 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2476
2477 mutex_lock(&sc->mutex);
bc81d43a
SM
2478 ath_dbg(common, CHAN_CTX,
2479 "Change channel context: %d MHz\n",
2480 conf->def.chan->center_freq);
39305635
FF
2481 ath_chanctx_set_channel(sc, ctx, &conf->def);
2482 mutex_unlock(&sc->mutex);
2483}
2484
2485static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2486 struct ieee80211_vif *vif,
2487 struct ieee80211_chanctx_conf *conf)
2488{
2489 struct ath_softc *sc = hw->priv;
bc81d43a 2490 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF
2491 struct ath_vif *avp = (void *)vif->drv_priv;
2492 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2493 int i;
39305635 2494
6185672a
SM
2495 ath9k_cancel_pending_offchannel(sc);
2496
39305635 2497 mutex_lock(&sc->mutex);
bc81d43a
SM
2498
2499 ath_dbg(common, CHAN_CTX,
2500 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2501 vif->addr, vif->type, vif->p2p,
2502 conf->def.chan->center_freq);
2503
39305635 2504 avp->chanctx = ctx;
2ce73c02 2505 ctx->nvifs_assigned++;
39305635 2506 list_add_tail(&avp->list, &ctx->vifs);
9a9c4fbc 2507 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM
2508 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2509 vif->hw_queue[i] = ctx->hw_queue_base + i;
bc81d43a 2510
39305635
FF
2511 mutex_unlock(&sc->mutex);
2512
2513 return 0;
2514}
2515
2516static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2517 struct ieee80211_vif *vif,
2518 struct ieee80211_chanctx_conf *conf)
2519{
2520 struct ath_softc *sc = hw->priv;
bc81d43a 2521 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF
2522 struct ath_vif *avp = (void *)vif->drv_priv;
2523 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2524 int ac;
39305635 2525
6185672a
SM
2526 ath9k_cancel_pending_offchannel(sc);
2527
39305635 2528 mutex_lock(&sc->mutex);
bc81d43a
SM
2529
2530 ath_dbg(common, CHAN_CTX,
2531 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2532 vif->addr, vif->type, vif->p2p,
2533 conf->def.chan->center_freq);
2534
39305635 2535 avp->chanctx = NULL;
2ce73c02 2536 ctx->nvifs_assigned--;
39305635 2537 list_del(&avp->list);
9a9c4fbc 2538 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM
2539 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2540 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
bc81d43a 2541
39305635
FF
2542 mutex_unlock(&sc->mutex);
2543}
2544
e20a854e
SM
2545static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2546 struct ieee80211_vif *vif)
2547{
2548 struct ath_softc *sc = hw->priv;
2549 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2550 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
c6500ea2
SM
2551 struct ath_beacon_config *cur_conf;
2552 struct ath_chanctx *go_ctx;
2553 unsigned long timeout;
e20a854e 2554 bool changed = false;
c6500ea2 2555 u32 beacon_int;
e20a854e
SM
2556
2557 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2558 return;
2559
2560 if (!avp->chanctx)
2561 return;
2562
2563 mutex_lock(&sc->mutex);
2564
2565 spin_lock_bh(&sc->chan_lock);
c6500ea2 2566 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
e20a854e 2567 changed = true;
c6500ea2
SM
2568 spin_unlock_bh(&sc->chan_lock);
2569
2570 if (!changed)
2571 goto out;
2572
6185672a 2573 ath9k_cancel_pending_offchannel(sc);
23aab0c2 2574
c6500ea2
SM
2575 go_ctx = ath_is_go_chanctx_present(sc);
2576
2577 if (go_ctx) {
2578 /*
2579 * Wait till the GO interface gets a chance
2580 * to send out an NoA.
2581 */
2582 spin_lock_bh(&sc->chan_lock);
2583 sc->sched.mgd_prepare_tx = true;
2584 cur_conf = &go_ctx->beacon;
2585 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2586 spin_unlock_bh(&sc->chan_lock);
2587
6185672a 2588 timeout = usecs_to_jiffies(beacon_int * 2);
c6500ea2
SM
2589 init_completion(&sc->go_beacon);
2590
6185672a 2591 mutex_unlock(&sc->mutex);
2c3634a8 2592
c6500ea2 2593 if (wait_for_completion_timeout(&sc->go_beacon,
2c3634a8 2594 timeout) == 0) {
c6500ea2
SM
2595 ath_dbg(common, CHAN_CTX,
2596 "Failed to send new NoA\n");
2c3634a8
SM
2597
2598 spin_lock_bh(&sc->chan_lock);
2599 sc->sched.mgd_prepare_tx = false;
2600 spin_unlock_bh(&sc->chan_lock);
2601 }
2602
6185672a 2603 mutex_lock(&sc->mutex);
e20a854e 2604 }
c6500ea2 2605
878066e7 2606 ath_dbg(common, CHAN_CTX,
c6500ea2
SM
2607 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2608 __func__, vif->addr);
2609
2610 spin_lock_bh(&sc->chan_lock);
2611 sc->next_chan = avp->chanctx;
e20a854e
SM
2612 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2613 spin_unlock_bh(&sc->chan_lock);
2614
c6500ea2
SM
2615 ath_chanctx_set_next(sc, true);
2616out:
e20a854e
SM
2617 mutex_unlock(&sc->mutex);
2618}
2619
78b21949
FF
2620void ath9k_fill_chanctx_ops(void)
2621{
499afacc 2622 if (!ath9k_is_chanctx_enabled())
78b21949
FF
2623 return;
2624
bc81d43a
SM
2625 ath9k_ops.hw_scan = ath9k_hw_scan;
2626 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2627 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
405393cf 2628 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
bc81d43a
SM
2629 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2630 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2631 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2632 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2633 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
e20a854e 2634 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
78b21949
FF
2635}
2636
499afacc
SM
2637#endif
2638
d385c5c2
FF
2639static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2640 int *dbm)
2641{
2642 struct ath_softc *sc = hw->priv;
2643 struct ath_vif *avp = (void *)vif->drv_priv;
2644
2645 mutex_lock(&sc->mutex);
2646 if (avp->chanctx)
2647 *dbm = avp->chanctx->cur_txpower;
2648 else
2649 *dbm = sc->cur_chan->cur_txpower;
2650 mutex_unlock(&sc->mutex);
2651
2652 *dbm /= 2;
2653
2654 return 0;
2655}
2656
6baff7f9 2657struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2658 .tx = ath9k_tx,
2659 .start = ath9k_start,
2660 .stop = ath9k_stop,
2661 .add_interface = ath9k_add_interface,
6b3b991d 2662 .change_interface = ath9k_change_interface,
8feceb67
VT
2663 .remove_interface = ath9k_remove_interface,
2664 .config = ath9k_config,
8feceb67 2665 .configure_filter = ath9k_configure_filter,
df3c6eb3 2666 .sta_state = ath9k_sta_state,
5519541d 2667 .sta_notify = ath9k_sta_notify,
8feceb67 2668 .conf_tx = ath9k_conf_tx,
8feceb67 2669 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2670 .set_key = ath9k_set_key,
8feceb67 2671 .get_tsf = ath9k_get_tsf,
3b5d665b 2672 .set_tsf = ath9k_set_tsf,
8feceb67 2673 .reset_tsf = ath9k_reset_tsf,
4233df6b 2674 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2675 .get_survey = ath9k_get_survey,
3b319aae 2676 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2677 .set_coverage_class = ath9k_set_coverage_class,
69081624 2678 .flush = ath9k_flush,
15b91e83 2679 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41 2680 .tx_last_beacon = ath9k_tx_last_beacon,
86a22acf 2681 .release_buffered_frames = ath9k_release_buffered_frames,
52c94f41 2682 .get_stats = ath9k_get_stats,
43c35284
FF
2683 .set_antenna = ath9k_set_antenna,
2684 .get_antenna = ath9k_get_antenna,
b90bd9d1 2685
e60001e7 2686#ifdef CONFIG_ATH9K_WOW
b11e640a
MSS
2687 .suspend = ath9k_suspend,
2688 .resume = ath9k_resume,
2689 .set_wakeup = ath9k_set_wakeup,
2690#endif
2691
b90bd9d1
BG
2692#ifdef CONFIG_ATH9K_DEBUGFS
2693 .get_et_sset_count = ath9k_get_et_sset_count,
a145daf7
SM
2694 .get_et_stats = ath9k_get_et_stats,
2695 .get_et_strings = ath9k_get_et_strings,
2696#endif
2697
1cdbaf0d 2698#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
a145daf7 2699 .sta_add_debugfs = ath9k_sta_add_debugfs,
b90bd9d1 2700#endif
e93d083f
SW
2701 .sw_scan_start = ath9k_sw_scan_start,
2702 .sw_scan_complete = ath9k_sw_scan_complete,
d385c5c2 2703 .get_txpower = ath9k_get_txpower,
8feceb67 2704};
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