[deliverable/linux.git] / drivers / net / wireless / b43legacy / dma.h

#ifndef B43legacy_DMA_H_
#define B43legacy_DMA_H_

#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/linkage.h>
#include <linux/atomic.h>

#include "b43legacy.h"


/* DMA-Interrupt reasons. */
#define B43legacy_DMAIRQ_FATALMASK	((1 << 10) | (1 << 11) | (1 << 12) \
					 | (1 << 14) | (1 << 15))
#define B43legacy_DMAIRQ_NONFATALMASK	(1 << 13)
#define B43legacy_DMAIRQ_RX_DONE		(1 << 16)


/*** 32-bit DMA Engine. ***/

/* 32-bit DMA controller registers. */
#define B43legacy_DMA32_TXCTL				0x00
#define		B43legacy_DMA32_TXENABLE		0x00000001
#define		B43legacy_DMA32_TXSUSPEND		0x00000002
#define		B43legacy_DMA32_TXLOOPBACK		0x00000004
#define		B43legacy_DMA32_TXFLUSH			0x00000010
#define		B43legacy_DMA32_TXADDREXT_MASK		0x00030000
#define		B43legacy_DMA32_TXADDREXT_SHIFT		16
#define B43legacy_DMA32_TXRING				0x04
#define B43legacy_DMA32_TXINDEX				0x08
#define B43legacy_DMA32_TXSTATUS			0x0C
#define		B43legacy_DMA32_TXDPTR			0x00000FFF
#define		B43legacy_DMA32_TXSTATE			0x0000F000
#define			B43legacy_DMA32_TXSTAT_DISABLED	0x00000000
#define			B43legacy_DMA32_TXSTAT_ACTIVE	0x00001000
#define			B43legacy_DMA32_TXSTAT_IDLEWAIT	0x00002000
#define			B43legacy_DMA32_TXSTAT_STOPPED	0x00003000
#define			B43legacy_DMA32_TXSTAT_SUSP	0x00004000
#define		B43legacy_DMA32_TXERROR			0x000F0000
#define			B43legacy_DMA32_TXERR_NOERR	0x00000000
#define			B43legacy_DMA32_TXERR_PROT	0x00010000
#define			B43legacy_DMA32_TXERR_UNDERRUN	0x00020000
#define			B43legacy_DMA32_TXERR_BUFREAD	0x00030000
#define			B43legacy_DMA32_TXERR_DESCREAD	0x00040000
#define		B43legacy_DMA32_TXACTIVE		0xFFF00000
#define B43legacy_DMA32_RXCTL				0x10
#define		B43legacy_DMA32_RXENABLE		0x00000001
#define		B43legacy_DMA32_RXFROFF_MASK		0x000000FE
#define		B43legacy_DMA32_RXFROFF_SHIFT		1
#define		B43legacy_DMA32_RXDIRECTFIFO		0x00000100
#define		B43legacy_DMA32_RXADDREXT_MASK		0x00030000
#define		B43legacy_DMA32_RXADDREXT_SHIFT		16
#define B43legacy_DMA32_RXRING				0x14
#define B43legacy_DMA32_RXINDEX				0x18
#define B43legacy_DMA32_RXSTATUS			0x1C
#define		B43legacy_DMA32_RXDPTR			0x00000FFF
#define		B43legacy_DMA32_RXSTATE			0x0000F000
#define			B43legacy_DMA32_RXSTAT_DISABLED	0x00000000
#define			B43legacy_DMA32_RXSTAT_ACTIVE	0x00001000
#define			B43legacy_DMA32_RXSTAT_IDLEWAIT	0x00002000
#define			B43legacy_DMA32_RXSTAT_STOPPED	0x00003000
#define		B43legacy_DMA32_RXERROR			0x000F0000
#define			B43legacy_DMA32_RXERR_NOERR	0x00000000
#define			B43legacy_DMA32_RXERR_PROT	0x00010000
#define			B43legacy_DMA32_RXERR_OVERFLOW	0x00020000
#define			B43legacy_DMA32_RXERR_BUFWRITE	0x00030000
#define			B43legacy_DMA32_RXERR_DESCREAD	0x00040000
#define		B43legacy_DMA32_RXACTIVE		0xFFF00000

/* 32-bit DMA descriptor. */
struct b43legacy_dmadesc32 {
	__le32 control;
	__le32 address;
} __packed;
#define B43legacy_DMA32_DCTL_BYTECNT		0x00001FFF
#define B43legacy_DMA32_DCTL_ADDREXT_MASK	0x00030000
#define B43legacy_DMA32_DCTL_ADDREXT_SHIFT	16
#define B43legacy_DMA32_DCTL_DTABLEEND		0x10000000
#define B43legacy_DMA32_DCTL_IRQ		0x20000000
#define B43legacy_DMA32_DCTL_FRAMEEND		0x40000000
#define B43legacy_DMA32_DCTL_FRAMESTART		0x80000000


/* Misc DMA constants */
#define B43legacy_DMA_RINGMEMSIZE	PAGE_SIZE
#define B43legacy_DMA0_RX_FRAMEOFFSET	30
#define B43legacy_DMA3_RX_FRAMEOFFSET	0


/* DMA engine tuning knobs */
#define B43legacy_TXRING_SLOTS		128
#define B43legacy_RXRING_SLOTS		64
#define B43legacy_DMA0_RX_BUFFERSIZE	(2304 + 100)
#define B43legacy_DMA3_RX_BUFFERSIZE	16


#ifdef CONFIG_B43LEGACY_DMA


struct sk_buff;
struct b43legacy_private;
struct b43legacy_txstatus;


struct b43legacy_dmadesc_meta {
	/* The kernel DMA-able buffer. */
	struct sk_buff *skb;
	/* DMA base bus-address of the descriptor buffer. */
	dma_addr_t dmaaddr;
	/* ieee80211 TX status. Only used once per 802.11 frag. */
	bool is_last_fragment;
};

enum b43legacy_dmatype {
	B43legacy_DMA_30BIT = 30,
	B43legacy_DMA_32BIT = 32,
};

struct b43legacy_dmaring {
	/* Kernel virtual base address of the ring memory. */
	void *descbase;
	/* Meta data about all descriptors. */
	struct b43legacy_dmadesc_meta *meta;
	/* Cache of TX headers for each slot.
	 * This is to avoid an allocation on each TX.
	 * This is NULL for an RX ring.
	 */
	u8 *txhdr_cache;
	/* (Unadjusted) DMA base bus-address of the ring memory. */
	dma_addr_t dmabase;
	/* Number of descriptor slots in the ring. */
	int nr_slots;
	/* Number of used descriptor slots. */
	int used_slots;
	/* Currently used slot in the ring. */
	int current_slot;
	/* Frameoffset in octets. */
	u32 frameoffset;
	/* Descriptor buffer size. */
	u16 rx_buffersize;
	/* The MMIO base register of the DMA controller. */
	u16 mmio_base;
	/* DMA controller index number (0-5). */
	int index;
	/* Boolean. Is this a TX ring? */
	bool tx;
	/* The type of DMA engine used. */
	enum b43legacy_dmatype type;
	/* Boolean. Is this ring stopped at ieee80211 level? */
	bool stopped;
	/* The QOS priority assigned to this ring. Only used for TX rings.
	 * This is the mac80211 "queue" value. */
	u8 queue_prio;
	struct b43legacy_wldev *dev;
#ifdef CONFIG_B43LEGACY_DEBUG
	/* Maximum number of used slots. */
	int max_used_slots;
	/* Last time we injected a ring overflow. */
	unsigned long last_injected_overflow;
#endif /* CONFIG_B43LEGACY_DEBUG*/
};


static inline
u32 b43legacy_dma_read(struct b43legacy_dmaring *ring,
		       u16 offset)
{
	return b43legacy_read32(ring->dev, ring->mmio_base + offset);
}

static inline
void b43legacy_dma_write(struct b43legacy_dmaring *ring,
			 u16 offset, u32 value)
{
	b43legacy_write32(ring->dev, ring->mmio_base + offset, value);
}


int b43legacy_dma_init(struct b43legacy_wldev *dev);
void b43legacy_dma_free(struct b43legacy_wldev *dev);

void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev);
void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev);

int b43legacy_dma_tx(struct b43legacy_wldev *dev,
		     struct sk_buff *skb);
void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
				   const struct b43legacy_txstatus *status);

void b43legacy_dma_rx(struct b43legacy_dmaring *ring);

#else /* CONFIG_B43LEGACY_DMA */


static inline
int b43legacy_dma_init(struct b43legacy_wldev *dev)
{
	return 0;
}
static inline
void b43legacy_dma_free(struct b43legacy_wldev *dev)
{
}
static inline
int b43legacy_dma_tx(struct b43legacy_wldev *dev,
		     struct sk_buff *skb)
{
	return 0;
}
static inline
void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
				   const struct b43legacy_txstatus *status)
{
}
static inline
void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
{
}
static inline
void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
{
}
static inline
void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
{
}

#endif /* CONFIG_B43LEGACY_DMA */
#endif /* B43legacy_DMA_H_ */
Commit	Line	Data
75388acd LF	1	#ifndef B43legacy_DMA_H_
	2	#define B43legacy_DMA_H_
	3
	4	#include <linux/list.h>
	5	#include <linux/spinlock.h>
	6	#include <linux/workqueue.h>
	7	#include <linux/linkage.h>
60063497	8	#include <linux/atomic.h>
75388acd LF	9
	10	#include "b43legacy.h"
	11
	12
	13	/* DMA-Interrupt reasons. */
	14	#define B43legacy_DMAIRQ_FATALMASK ((1 << 10) \| (1 << 11) \| (1 << 12) \
	15	\| (1 << 14) \| (1 << 15))
	16	#define B43legacy_DMAIRQ_NONFATALMASK (1 << 13)
	17	#define B43legacy_DMAIRQ_RX_DONE (1 << 16)
	18
	19
	20	/* 32-bit DMA Engine. */
	21
	22	/* 32-bit DMA controller registers. */
	23	#define B43legacy_DMA32_TXCTL 0x00
	24	#define B43legacy_DMA32_TXENABLE 0x00000001
	25	#define B43legacy_DMA32_TXSUSPEND 0x00000002
	26	#define B43legacy_DMA32_TXLOOPBACK 0x00000004
	27	#define B43legacy_DMA32_TXFLUSH 0x00000010
	28	#define B43legacy_DMA32_TXADDREXT_MASK 0x00030000
	29	#define B43legacy_DMA32_TXADDREXT_SHIFT 16
	30	#define B43legacy_DMA32_TXRING 0x04
	31	#define B43legacy_DMA32_TXINDEX 0x08
	32	#define B43legacy_DMA32_TXSTATUS 0x0C
	33	#define B43legacy_DMA32_TXDPTR 0x00000FFF
	34	#define B43legacy_DMA32_TXSTATE 0x0000F000
	35	#define B43legacy_DMA32_TXSTAT_DISABLED 0x00000000
	36	#define B43legacy_DMA32_TXSTAT_ACTIVE 0x00001000
	37	#define B43legacy_DMA32_TXSTAT_IDLEWAIT 0x00002000
	38	#define B43legacy_DMA32_TXSTAT_STOPPED 0x00003000
	39	#define B43legacy_DMA32_TXSTAT_SUSP 0x00004000
	40	#define B43legacy_DMA32_TXERROR 0x000F0000
	41	#define B43legacy_DMA32_TXERR_NOERR 0x00000000
	42	#define B43legacy_DMA32_TXERR_PROT 0x00010000
	43	#define B43legacy_DMA32_TXERR_UNDERRUN 0x00020000
	44	#define B43legacy_DMA32_TXERR_BUFREAD 0x00030000
	45	#define B43legacy_DMA32_TXERR_DESCREAD 0x00040000
	46	#define B43legacy_DMA32_TXACTIVE 0xFFF00000
	47	#define B43legacy_DMA32_RXCTL 0x10
	48	#define B43legacy_DMA32_RXENABLE 0x00000001
	49	#define B43legacy_DMA32_RXFROFF_MASK 0x000000FE
	50	#define B43legacy_DMA32_RXFROFF_SHIFT 1
	51	#define B43legacy_DMA32_RXDIRECTFIFO 0x00000100
	52	#define B43legacy_DMA32_RXADDREXT_MASK 0x00030000
	53	#define B43legacy_DMA32_RXADDREXT_SHIFT 16
	54	#define B43legacy_DMA32_RXRING 0x14
	55	#define B43legacy_DMA32_RXINDEX 0x18
	56	#define B43legacy_DMA32_RXSTATUS 0x1C
	57	#define B43legacy_DMA32_RXDPTR 0x00000FFF
	58	#define B43legacy_DMA32_RXSTATE 0x0000F000
	59	#define B43legacy_DMA32_RXSTAT_DISABLED 0x00000000
	60	#define B43legacy_DMA32_RXSTAT_ACTIVE 0x00001000
	61	#define B43legacy_DMA32_RXSTAT_IDLEWAIT 0x00002000
	62	#define B43legacy_DMA32_RXSTAT_STOPPED 0x00003000
	63	#define B43legacy_DMA32_RXERROR 0x000F0000
	64	#define B43legacy_DMA32_RXERR_NOERR 0x00000000
	65	#define B43legacy_DMA32_RXERR_PROT 0x00010000
	66	#define B43legacy_DMA32_RXERR_OVERFLOW 0x00020000
	67	#define B43legacy_DMA32_RXERR_BUFWRITE 0x00030000
	68	#define B43legacy_DMA32_RXERR_DESCREAD 0x00040000
	69	#define B43legacy_DMA32_RXACTIVE 0xFFF00000
	70
	71	/* 32-bit DMA descriptor. */
	72	struct b43legacy_dmadesc32 {
73	__le32 control;
74	__le32 address;
ba2d3587	75	} __packed;
75388acd LF	76	#define B43legacy_DMA32_DCTL_BYTECNT 0x00001FFF
	77	#define B43legacy_DMA32_DCTL_ADDREXT_MASK 0x00030000
	78	#define B43legacy_DMA32_DCTL_ADDREXT_SHIFT 16
	79	#define B43legacy_DMA32_DCTL_DTABLEEND 0x10000000
	80	#define B43legacy_DMA32_DCTL_IRQ 0x20000000
	81	#define B43legacy_DMA32_DCTL_FRAMEEND 0x40000000
	82	#define B43legacy_DMA32_DCTL_FRAMESTART 0x80000000
	83
	84
75388acd LF	85	/* Misc DMA constants */
	86	#define B43legacy_DMA_RINGMEMSIZE PAGE_SIZE
	87	#define B43legacy_DMA0_RX_FRAMEOFFSET 30
	88	#define B43legacy_DMA3_RX_FRAMEOFFSET 0
	89
	90
	91	/* DMA engine tuning knobs */
	92	#define B43legacy_TXRING_SLOTS 128
	93	#define B43legacy_RXRING_SLOTS 64
	94	#define B43legacy_DMA0_RX_BUFFERSIZE (2304 + 100)
	95	#define B43legacy_DMA3_RX_BUFFERSIZE 16
	96
	97
	98
	99	#ifdef CONFIG_B43LEGACY_DMA
	100
	101
	102	struct sk_buff;
	103	struct b43legacy_private;
	104	struct b43legacy_txstatus;
	105
	106
	107	struct b43legacy_dmadesc_meta {
	108	/* The kernel DMA-able buffer. */
	109	struct sk_buff *skb;
	110	/* DMA base bus-address of the descriptor buffer. */
	111	dma_addr_t dmaaddr;
	112	/* ieee80211 TX status. Only used once per 802.11 frag. */
	113	bool is_last_fragment;
75388acd LF	114	};
75388acd LF	115
8e118f0e SB	116	enum b43legacy_dmatype {
	117	B43legacy_DMA_30BIT = 30,
	118	B43legacy_DMA_32BIT = 32,
8e118f0e SB	119	};
8e118f0e SB	120
75388acd	121	struct b43legacy_dmaring {
75388acd LF	122	/* Kernel virtual base address of the ring memory. */
	123	void *descbase;
	124	/* Meta data about all descriptors. */
	125	struct b43legacy_dmadesc_meta *meta;
	126	/* Cache of TX headers for each slot.
	127	* This is to avoid an allocation on each TX.
	128	* This is NULL for an RX ring.
	129	*/
	130	u8 *txhdr_cache;
	131	/* (Unadjusted) DMA base bus-address of the ring memory. */
	132	dma_addr_t dmabase;
	133	/* Number of descriptor slots in the ring. */
	134	int nr_slots;
	135	/* Number of used descriptor slots. */
	136	int used_slots;
	137	/* Currently used slot in the ring. */
	138	int current_slot;
75388acd LF	139	/* Frameoffset in octets. */
	140	u32 frameoffset;
	141	/* Descriptor buffer size. */
	142	u16 rx_buffersize;
	143	/* The MMIO base register of the DMA controller. */
	144	u16 mmio_base;
	145	/* DMA controller index number (0-5). */
	146	int index;
	147	/* Boolean. Is this a TX ring? */
	148	bool tx;
8e118f0e SB	149	/* The type of DMA engine used. */
8e118f0e SB	150	enum b43legacy_dmatype type;
75388acd LF	151	/* Boolean. Is this ring stopped at ieee80211 level? */
75388acd LF	152	bool stopped;
5d07a3d6 LF	153	/* The QOS priority assigned to this ring. Only used for TX rings.
	154	* This is the mac80211 "queue" value. */
	155	u8 queue_prio;
75388acd LF	156	struct b43legacy_wldev *dev;
	157	#ifdef CONFIG_B43LEGACY_DEBUG
	158	/* Maximum number of used slots. */
	159	int max_used_slots;
	160	/* Last time we injected a ring overflow. */
	161	unsigned long last_injected_overflow;
	162	#endif /* CONFIG_B43LEGACY_DEBUG*/
	163	};
	164
	165
	166	static inline
	167	u32 b43legacy_dma_read(struct b43legacy_dmaring *ring,
	168	u16 offset)
	169	{
	170	return b43legacy_read32(ring->dev, ring->mmio_base + offset);
	171	}
	172
	173	static inline
	174	void b43legacy_dma_write(struct b43legacy_dmaring *ring,
	175	u16 offset, u32 value)
	176	{
	177	b43legacy_write32(ring->dev, ring->mmio_base + offset, value);
	178	}
	179
	180
	181	int b43legacy_dma_init(struct b43legacy_wldev *dev);
	182	void b43legacy_dma_free(struct b43legacy_wldev *dev);
	183
75388acd LF	184	void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev);
	185	void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev);
	186
75388acd	187	int b43legacy_dma_tx(struct b43legacy_wldev *dev,
e039fa4a	188	struct sk_buff *skb);
75388acd LF	189	void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
	190	const struct b43legacy_txstatus *status);
	191
	192	void b43legacy_dma_rx(struct b43legacy_dmaring *ring);
	193
	194	#else /* CONFIG_B43LEGACY_DMA */
	195
	196
	197	static inline
	198	int b43legacy_dma_init(struct b43legacy_wldev *dev)
	199	{
	200	return 0;
	201	}
	202	static inline
	203	void b43legacy_dma_free(struct b43legacy_wldev *dev)
	204	{
	205	}
	206	static inline
75388acd	207	int b43legacy_dma_tx(struct b43legacy_wldev *dev,
553381c4	208	struct sk_buff *skb)
75388acd LF	209	{
	210	return 0;
	211	}
	212	static inline
	213	void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
	214	const struct b43legacy_txstatus *status)
	215	{
	216	}
	217	static inline
	218	void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
	219	{
	220	}
	221	static inline
	222	void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
	223	{
	224	}
	225	static inline
	226	void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
	227	{
	228	}
	229
	230	#endif /* CONFIG_B43LEGACY_DMA */
	231	#endif /* B43legacy_DMA_H_ */