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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
43413a97 | 10 | * Copyright(c) 2016 Intel Deutschland GmbH |
8ca151b5 JB |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of version 2 of the GNU General Public License as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
24 | * USA | |
25 | * | |
26 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 27 | * in the file called COPYING. |
8ca151b5 JB |
28 | * |
29 | * Contact Information: | |
cb2f8277 | 30 | * Intel Linux Wireless <linuxwifi@intel.com> |
8ca151b5 JB |
31 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
32 | * | |
33 | * BSD LICENSE | |
34 | * | |
51368bf7 | 35 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 36 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
8ca151b5 JB |
37 | * All rights reserved. |
38 | * | |
39 | * Redistribution and use in source and binary forms, with or without | |
40 | * modification, are permitted provided that the following conditions | |
41 | * are met: | |
42 | * | |
43 | * * Redistributions of source code must retain the above copyright | |
44 | * notice, this list of conditions and the following disclaimer. | |
45 | * * Redistributions in binary form must reproduce the above copyright | |
46 | * notice, this list of conditions and the following disclaimer in | |
47 | * the documentation and/or other materials provided with the | |
48 | * distribution. | |
49 | * * Neither the name Intel Corporation nor the names of its | |
50 | * contributors may be used to endorse or promote products derived | |
51 | * from this software without specific prior written permission. | |
52 | * | |
53 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
54 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
55 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
56 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
57 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
58 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
59 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
60 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
61 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
62 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
63 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
64 | * | |
65 | *****************************************************************************/ | |
66 | #include <net/mac80211.h> | |
854d773e | 67 | #include <linux/netdevice.h> |
da2830ac | 68 | #include <linux/acpi.h> |
8ca151b5 JB |
69 | |
70 | #include "iwl-trans.h" | |
71 | #include "iwl-op-mode.h" | |
72 | #include "iwl-fw.h" | |
73 | #include "iwl-debug.h" | |
74 | #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ | |
75 | #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ | |
8c23f95c | 76 | #include "iwl-prph.h" |
8ca151b5 JB |
77 | #include "iwl-eeprom-parse.h" |
78 | ||
79 | #include "mvm.h" | |
2f89a5d7 | 80 | #include "fw-dbg.h" |
8ca151b5 JB |
81 | #include "iwl-phy-db.h" |
82 | ||
83 | #define MVM_UCODE_ALIVE_TIMEOUT HZ | |
84 | #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) | |
85 | ||
86 | #define UCODE_VALID_OK cpu_to_le32(0x1) | |
87 | ||
8ca151b5 JB |
88 | struct iwl_mvm_alive_data { |
89 | bool valid; | |
90 | u32 scd_base_addr; | |
91 | }; | |
92 | ||
93 | static inline const struct fw_img * | |
94 | iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type) | |
95 | { | |
96 | if (ucode_type >= IWL_UCODE_TYPE_MAX) | |
97 | return NULL; | |
98 | ||
99 | return &mvm->fw->img[ucode_type]; | |
100 | } | |
101 | ||
102 | static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) | |
103 | { | |
104 | struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { | |
105 | .valid = cpu_to_le32(valid_tx_ant), | |
106 | }; | |
107 | ||
33223542 | 108 | IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); |
a1022927 | 109 | return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
110 | sizeof(tx_ant_cmd), &tx_ant_cmd); |
111 | } | |
112 | ||
43413a97 SS |
113 | static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) |
114 | { | |
115 | int i; | |
116 | struct iwl_rss_config_cmd cmd = { | |
117 | .flags = cpu_to_le32(IWL_RSS_ENABLE), | |
118 | .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP | | |
854d773e | 119 | IWL_RSS_HASH_TYPE_IPV4_UDP | |
43413a97 SS |
120 | IWL_RSS_HASH_TYPE_IPV4_PAYLOAD | |
121 | IWL_RSS_HASH_TYPE_IPV6_TCP | | |
854d773e | 122 | IWL_RSS_HASH_TYPE_IPV6_UDP | |
43413a97 SS |
123 | IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, |
124 | }; | |
125 | ||
f43495fd SS |
126 | if (mvm->trans->num_rx_queues == 1) |
127 | return 0; | |
128 | ||
854d773e | 129 | /* Do not direct RSS traffic to Q 0 which is our fallback queue */ |
43413a97 | 130 | for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) |
854d773e SS |
131 | cmd.indirection_table[i] = |
132 | 1 + (i % (mvm->trans->num_rx_queues - 1)); | |
133 | netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); | |
43413a97 SS |
134 | |
135 | return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); | |
136 | } | |
137 | ||
97d5be7e LK |
138 | static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) |
139 | { | |
140 | struct iwl_dqa_enable_cmd dqa_cmd = { | |
141 | .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), | |
142 | }; | |
143 | u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); | |
144 | int ret; | |
145 | ||
146 | ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); | |
147 | if (ret) | |
148 | IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); | |
149 | else | |
150 | IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
905e36ae | 155 | void iwl_free_fw_paging(struct iwl_mvm *mvm) |
a6c4fb44 MG |
156 | { |
157 | int i; | |
158 | ||
159 | if (!mvm->fw_paging_db[0].fw_paging_block) | |
160 | return; | |
161 | ||
162 | for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) { | |
3edbc7da EG |
163 | struct iwl_fw_paging *paging = &mvm->fw_paging_db[i]; |
164 | ||
165 | if (!paging->fw_paging_block) { | |
a6c4fb44 MG |
166 | IWL_DEBUG_FW(mvm, |
167 | "Paging: block %d already freed, continue to next page\n", | |
168 | i); | |
169 | ||
170 | continue; | |
171 | } | |
3edbc7da EG |
172 | dma_unmap_page(mvm->trans->dev, paging->fw_paging_phys, |
173 | paging->fw_paging_size, DMA_BIDIRECTIONAL); | |
a6c4fb44 | 174 | |
3edbc7da EG |
175 | __free_pages(paging->fw_paging_block, |
176 | get_order(paging->fw_paging_size)); | |
177 | paging->fw_paging_block = NULL; | |
a6c4fb44 | 178 | } |
e1120187 | 179 | kfree(mvm->trans->paging_download_buf); |
905e36ae | 180 | mvm->trans->paging_download_buf = NULL; |
f742aaf3 | 181 | mvm->trans->paging_db = NULL; |
905e36ae | 182 | |
a6c4fb44 MG |
183 | memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db)); |
184 | } | |
185 | ||
186 | static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image) | |
187 | { | |
188 | int sec_idx, idx; | |
189 | u32 offset = 0; | |
190 | ||
191 | /* | |
192 | * find where is the paging image start point: | |
193 | * if CPU2 exist and it's in paging format, then the image looks like: | |
194 | * CPU1 sections (2 or more) | |
195 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2 | |
196 | * CPU2 sections (not paged) | |
197 | * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2 | |
198 | * non paged to CPU2 paging sec | |
199 | * CPU2 paging CSS | |
200 | * CPU2 paging image (including instruction and data) | |
201 | */ | |
202 | for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) { | |
203 | if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) { | |
204 | sec_idx++; | |
205 | break; | |
206 | } | |
207 | } | |
208 | ||
cd47a3d3 MG |
209 | /* |
210 | * If paging is enabled there should be at least 2 more sections left | |
211 | * (one for CSS and one for Paging data) | |
212 | */ | |
213 | if (sec_idx >= ARRAY_SIZE(image->sec) - 1) { | |
214 | IWL_ERR(mvm, "Paging: Missing CSS and/or paging sections\n"); | |
a6c4fb44 MG |
215 | iwl_free_fw_paging(mvm); |
216 | return -EINVAL; | |
217 | } | |
218 | ||
219 | /* copy the CSS block to the dram */ | |
220 | IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n", | |
221 | sec_idx); | |
222 | ||
223 | memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block), | |
224 | image->sec[sec_idx].data, | |
225 | mvm->fw_paging_db[0].fw_paging_size); | |
226 | ||
227 | IWL_DEBUG_FW(mvm, | |
228 | "Paging: copied %d CSS bytes to first block\n", | |
229 | mvm->fw_paging_db[0].fw_paging_size); | |
230 | ||
231 | sec_idx++; | |
232 | ||
233 | /* | |
234 | * copy the paging blocks to the dram | |
235 | * loop index start from 1 since that CSS block already copied to dram | |
236 | * and CSS index is 0. | |
237 | * loop stop at num_of_paging_blk since that last block is not full. | |
238 | */ | |
239 | for (idx = 1; idx < mvm->num_of_paging_blk; idx++) { | |
240 | memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), | |
241 | image->sec[sec_idx].data + offset, | |
242 | mvm->fw_paging_db[idx].fw_paging_size); | |
243 | ||
244 | IWL_DEBUG_FW(mvm, | |
245 | "Paging: copied %d paging bytes to block %d\n", | |
246 | mvm->fw_paging_db[idx].fw_paging_size, | |
247 | idx); | |
248 | ||
249 | offset += mvm->fw_paging_db[idx].fw_paging_size; | |
250 | } | |
251 | ||
252 | /* copy the last paging block */ | |
253 | if (mvm->num_of_pages_in_last_blk > 0) { | |
254 | memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), | |
255 | image->sec[sec_idx].data + offset, | |
256 | FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk); | |
257 | ||
258 | IWL_DEBUG_FW(mvm, | |
259 | "Paging: copied %d pages in the last block %d\n", | |
260 | mvm->num_of_pages_in_last_blk, idx); | |
261 | } | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm, | |
267 | const struct fw_img *image) | |
268 | { | |
269 | struct page *block; | |
270 | dma_addr_t phys = 0; | |
271 | int blk_idx = 0; | |
272 | int order, num_of_pages; | |
273 | int dma_enabled; | |
274 | ||
275 | if (mvm->fw_paging_db[0].fw_paging_block) | |
276 | return 0; | |
277 | ||
278 | dma_enabled = is_device_dma_capable(mvm->trans->dev); | |
279 | ||
280 | /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */ | |
281 | BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE); | |
282 | ||
283 | num_of_pages = image->paging_mem_size / FW_PAGING_SIZE; | |
284 | mvm->num_of_paging_blk = ((num_of_pages - 1) / | |
285 | NUM_OF_PAGE_PER_GROUP) + 1; | |
286 | ||
287 | mvm->num_of_pages_in_last_blk = | |
288 | num_of_pages - | |
289 | NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1); | |
290 | ||
291 | IWL_DEBUG_FW(mvm, | |
292 | "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n", | |
293 | mvm->num_of_paging_blk, | |
294 | mvm->num_of_pages_in_last_blk); | |
295 | ||
296 | /* allocate block of 4Kbytes for paging CSS */ | |
297 | order = get_order(FW_PAGING_SIZE); | |
298 | block = alloc_pages(GFP_KERNEL, order); | |
299 | if (!block) { | |
300 | /* free all the previous pages since we failed */ | |
301 | iwl_free_fw_paging(mvm); | |
302 | return -ENOMEM; | |
303 | } | |
304 | ||
305 | mvm->fw_paging_db[blk_idx].fw_paging_block = block; | |
306 | mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE; | |
307 | ||
308 | if (dma_enabled) { | |
309 | phys = dma_map_page(mvm->trans->dev, block, 0, | |
310 | PAGE_SIZE << order, DMA_BIDIRECTIONAL); | |
311 | if (dma_mapping_error(mvm->trans->dev, phys)) { | |
312 | /* | |
313 | * free the previous pages and the current one since | |
314 | * we failed to map_page. | |
315 | */ | |
316 | iwl_free_fw_paging(mvm); | |
317 | return -ENOMEM; | |
318 | } | |
319 | mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; | |
e1120187 MG |
320 | } else { |
321 | mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG | | |
322 | blk_idx << BLOCK_2_EXP_SIZE; | |
a6c4fb44 MG |
323 | } |
324 | ||
325 | IWL_DEBUG_FW(mvm, | |
326 | "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n", | |
327 | order); | |
328 | ||
329 | /* | |
330 | * allocate blocks in dram. | |
331 | * since that CSS allocated in fw_paging_db[0] loop start from index 1 | |
332 | */ | |
333 | for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { | |
334 | /* allocate block of PAGING_BLOCK_SIZE (32K) */ | |
335 | order = get_order(PAGING_BLOCK_SIZE); | |
336 | block = alloc_pages(GFP_KERNEL, order); | |
337 | if (!block) { | |
338 | /* free all the previous pages since we failed */ | |
339 | iwl_free_fw_paging(mvm); | |
340 | return -ENOMEM; | |
341 | } | |
342 | ||
343 | mvm->fw_paging_db[blk_idx].fw_paging_block = block; | |
344 | mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE; | |
345 | ||
346 | if (dma_enabled) { | |
347 | phys = dma_map_page(mvm->trans->dev, block, 0, | |
348 | PAGE_SIZE << order, | |
349 | DMA_BIDIRECTIONAL); | |
350 | if (dma_mapping_error(mvm->trans->dev, phys)) { | |
351 | /* | |
352 | * free the previous pages and the current one | |
353 | * since we failed to map_page. | |
354 | */ | |
355 | iwl_free_fw_paging(mvm); | |
356 | return -ENOMEM; | |
357 | } | |
358 | mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; | |
e1120187 MG |
359 | } else { |
360 | mvm->fw_paging_db[blk_idx].fw_paging_phys = | |
361 | PAGING_ADDR_SIG | | |
362 | blk_idx << BLOCK_2_EXP_SIZE; | |
a6c4fb44 MG |
363 | } |
364 | ||
365 | IWL_DEBUG_FW(mvm, | |
366 | "Paging: allocated 32K bytes (order %d) for firmware paging.\n", | |
367 | order); | |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static int iwl_save_fw_paging(struct iwl_mvm *mvm, | |
374 | const struct fw_img *fw) | |
375 | { | |
376 | int ret; | |
377 | ||
378 | ret = iwl_alloc_fw_paging_mem(mvm, fw); | |
379 | if (ret) | |
380 | return ret; | |
381 | ||
382 | return iwl_fill_paging_mem(mvm, fw); | |
383 | } | |
384 | ||
385 | /* send paging cmd to FW in case CPU2 has paging image */ | |
386 | static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw) | |
387 | { | |
d975d720 | 388 | struct iwl_fw_paging_cmd paging_cmd = { |
a6c4fb44 MG |
389 | .flags = |
390 | cpu_to_le32(PAGING_CMD_IS_SECURED | | |
391 | PAGING_CMD_IS_ENABLED | | |
392 | (mvm->num_of_pages_in_last_blk << | |
393 | PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)), | |
394 | .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE), | |
395 | .block_num = cpu_to_le32(mvm->num_of_paging_blk), | |
396 | }; | |
d975d720 SS |
397 | int blk_idx, size = sizeof(paging_cmd); |
398 | ||
399 | /* A bit hard coded - but this is the old API and will be deprecated */ | |
400 | if (!iwl_mvm_has_new_tx_api(mvm)) | |
401 | size -= NUM_OF_FW_PAGING_BLOCKS * 4; | |
a6c4fb44 MG |
402 | |
403 | /* loop for for all paging blocks + CSS block */ | |
404 | for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { | |
d975d720 SS |
405 | dma_addr_t addr = mvm->fw_paging_db[blk_idx].fw_paging_phys; |
406 | ||
407 | addr = addr >> PAGE_2_EXP_SIZE; | |
408 | ||
409 | if (iwl_mvm_has_new_tx_api(mvm)) { | |
410 | __le64 phy_addr = cpu_to_le64(addr); | |
411 | ||
412 | paging_cmd.device_phy_addr.addr64[blk_idx] = phy_addr; | |
413 | } else { | |
414 | __le32 phy_addr = cpu_to_le32(addr); | |
415 | ||
416 | paging_cmd.device_phy_addr.addr32[blk_idx] = phy_addr; | |
417 | } | |
a6c4fb44 MG |
418 | } |
419 | ||
420 | return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD, | |
421 | IWL_ALWAYS_LONG_GROUP, 0), | |
d975d720 | 422 | 0, size, &paging_cmd); |
a6c4fb44 MG |
423 | } |
424 | ||
e1120187 MG |
425 | /* |
426 | * Send paging item cmd to FW in case CPU2 has paging image | |
427 | */ | |
428 | static int iwl_trans_get_paging_item(struct iwl_mvm *mvm) | |
429 | { | |
430 | int ret; | |
431 | struct iwl_fw_get_item_cmd fw_get_item_cmd = { | |
432 | .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING), | |
433 | }; | |
434 | ||
435 | struct iwl_fw_get_item_resp *item_resp; | |
436 | struct iwl_host_cmd cmd = { | |
437 | .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0), | |
438 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, | |
439 | .data = { &fw_get_item_cmd, }, | |
440 | }; | |
441 | ||
442 | cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd); | |
443 | ||
444 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
445 | if (ret) { | |
446 | IWL_ERR(mvm, | |
447 | "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n", | |
448 | ret); | |
449 | return ret; | |
450 | } | |
451 | ||
452 | item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data; | |
453 | if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) { | |
454 | IWL_ERR(mvm, | |
455 | "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n", | |
456 | le32_to_cpu(item_resp->item_id)); | |
457 | ret = -EIO; | |
458 | goto exit; | |
459 | } | |
460 | ||
c94d7996 MG |
461 | /* Add an extra page for headers */ |
462 | mvm->trans->paging_download_buf = kzalloc(PAGING_BLOCK_SIZE + | |
463 | FW_PAGING_SIZE, | |
e1120187 MG |
464 | GFP_KERNEL); |
465 | if (!mvm->trans->paging_download_buf) { | |
466 | ret = -ENOMEM; | |
467 | goto exit; | |
468 | } | |
469 | mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val); | |
470 | mvm->trans->paging_db = mvm->fw_paging_db; | |
471 | IWL_DEBUG_FW(mvm, | |
472 | "Paging: got paging request address (paging_req_addr 0x%08x)\n", | |
473 | mvm->trans->paging_req_addr); | |
474 | ||
475 | exit: | |
476 | iwl_free_resp(&cmd); | |
477 | ||
478 | return ret; | |
479 | } | |
480 | ||
8ca151b5 JB |
481 | static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
482 | struct iwl_rx_packet *pkt, void *data) | |
483 | { | |
484 | struct iwl_mvm *mvm = | |
485 | container_of(notif_wait, struct iwl_mvm, notif_wait); | |
486 | struct iwl_mvm_alive_data *alive_data = data; | |
7e1223b5 | 487 | struct mvm_alive_resp_ver1 *palive1; |
01a9ca51 | 488 | struct mvm_alive_resp_ver2 *palive2; |
7e1223b5 | 489 | struct mvm_alive_resp *palive; |
01a9ca51 | 490 | |
7e1223b5 EG |
491 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) { |
492 | palive1 = (void *)pkt->data; | |
01a9ca51 EH |
493 | |
494 | mvm->support_umac_log = false; | |
495 | mvm->error_event_table = | |
7e1223b5 EG |
496 | le32_to_cpu(palive1->error_event_table_ptr); |
497 | mvm->log_event_table = | |
498 | le32_to_cpu(palive1->log_event_table_ptr); | |
499 | alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr); | |
01a9ca51 | 500 | |
7e1223b5 | 501 | alive_data->valid = le16_to_cpu(palive1->status) == |
01a9ca51 EH |
502 | IWL_ALIVE_STATUS_OK; |
503 | IWL_DEBUG_FW(mvm, | |
504 | "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
7e1223b5 EG |
505 | le16_to_cpu(palive1->status), palive1->ver_type, |
506 | palive1->ver_subtype, palive1->flags); | |
507 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) { | |
01a9ca51 EH |
508 | palive2 = (void *)pkt->data; |
509 | ||
01a9ca51 EH |
510 | mvm->error_event_table = |
511 | le32_to_cpu(palive2->error_event_table_ptr); | |
512 | mvm->log_event_table = | |
513 | le32_to_cpu(palive2->log_event_table_ptr); | |
514 | alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr); | |
515 | mvm->umac_error_event_table = | |
516 | le32_to_cpu(palive2->error_info_addr); | |
91479b64 EH |
517 | mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr); |
518 | mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size); | |
01a9ca51 EH |
519 | |
520 | alive_data->valid = le16_to_cpu(palive2->status) == | |
521 | IWL_ALIVE_STATUS_OK; | |
ffa70264 EG |
522 | if (mvm->umac_error_event_table) |
523 | mvm->support_umac_log = true; | |
524 | ||
01a9ca51 EH |
525 | IWL_DEBUG_FW(mvm, |
526 | "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
527 | le16_to_cpu(palive2->status), palive2->ver_type, | |
528 | palive2->ver_subtype, palive2->flags); | |
529 | ||
530 | IWL_DEBUG_FW(mvm, | |
531 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
532 | palive2->umac_major, palive2->umac_minor); | |
7e1223b5 EG |
533 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { |
534 | palive = (void *)pkt->data; | |
535 | ||
536 | mvm->error_event_table = | |
537 | le32_to_cpu(palive->error_event_table_ptr); | |
538 | mvm->log_event_table = | |
539 | le32_to_cpu(palive->log_event_table_ptr); | |
540 | alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr); | |
541 | mvm->umac_error_event_table = | |
542 | le32_to_cpu(palive->error_info_addr); | |
543 | mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr); | |
544 | mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size); | |
545 | ||
546 | alive_data->valid = le16_to_cpu(palive->status) == | |
547 | IWL_ALIVE_STATUS_OK; | |
548 | if (mvm->umac_error_event_table) | |
549 | mvm->support_umac_log = true; | |
550 | ||
551 | IWL_DEBUG_FW(mvm, | |
552 | "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
553 | le16_to_cpu(palive->status), palive->ver_type, | |
554 | palive->ver_subtype, palive->flags); | |
555 | ||
556 | IWL_DEBUG_FW(mvm, | |
557 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
558 | le32_to_cpu(palive->umac_major), | |
559 | le32_to_cpu(palive->umac_minor)); | |
01a9ca51 | 560 | } |
8ca151b5 JB |
561 | |
562 | return true; | |
563 | } | |
564 | ||
565 | static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, | |
566 | struct iwl_rx_packet *pkt, void *data) | |
567 | { | |
568 | struct iwl_phy_db *phy_db = data; | |
569 | ||
570 | if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { | |
571 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
572 | return true; | |
573 | } | |
574 | ||
ce1f2778 | 575 | WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); |
8ca151b5 JB |
576 | |
577 | return false; | |
578 | } | |
579 | ||
580 | static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, | |
581 | enum iwl_ucode_type ucode_type) | |
582 | { | |
583 | struct iwl_notification_wait alive_wait; | |
584 | struct iwl_mvm_alive_data alive_data; | |
585 | const struct fw_img *fw; | |
586 | int ret, i; | |
587 | enum iwl_ucode_type old_type = mvm->cur_ucode; | |
6eb031d2 | 588 | static const u16 alive_cmd[] = { MVM_ALIVE }; |
91479b64 | 589 | struct iwl_sf_region st_fwrd_space; |
8ca151b5 | 590 | |
61df750c | 591 | if (ucode_type == IWL_UCODE_REGULAR && |
3d2d4422 GBA |
592 | iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && |
593 | !(fw_has_capa(&mvm->fw->ucode_capa, | |
594 | IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) | |
61df750c EH |
595 | fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER); |
596 | else | |
597 | fw = iwl_get_ucode_image(mvm, ucode_type); | |
befe9b6f | 598 | if (WARN_ON(!fw)) |
8ca151b5 | 599 | return -EINVAL; |
befe9b6f JB |
600 | mvm->cur_ucode = ucode_type; |
601 | mvm->ucode_loaded = false; | |
8ca151b5 JB |
602 | |
603 | iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, | |
604 | alive_cmd, ARRAY_SIZE(alive_cmd), | |
605 | iwl_alive_fn, &alive_data); | |
606 | ||
607 | ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT); | |
608 | if (ret) { | |
609 | mvm->cur_ucode = old_type; | |
610 | iwl_remove_notification(&mvm->notif_wait, &alive_wait); | |
611 | return ret; | |
612 | } | |
613 | ||
614 | /* | |
615 | * Some things may run in the background now, but we | |
616 | * just wait for the ALIVE notification here. | |
617 | */ | |
618 | ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, | |
619 | MVM_UCODE_ALIVE_TIMEOUT); | |
620 | if (ret) { | |
192de2b4 DS |
621 | if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
622 | IWL_ERR(mvm, | |
623 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
624 | iwl_read_prph(mvm->trans, SB_CPU_1_STATUS), | |
625 | iwl_read_prph(mvm->trans, SB_CPU_2_STATUS)); | |
8ca151b5 JB |
626 | mvm->cur_ucode = old_type; |
627 | return ret; | |
628 | } | |
629 | ||
630 | if (!alive_data.valid) { | |
631 | IWL_ERR(mvm, "Loaded ucode is not valid!\n"); | |
632 | mvm->cur_ucode = old_type; | |
633 | return -EIO; | |
634 | } | |
635 | ||
91479b64 EH |
636 | /* |
637 | * update the sdio allocation according to the pointer we get in the | |
638 | * alive notification. | |
639 | */ | |
640 | st_fwrd_space.addr = mvm->sf_space.addr; | |
641 | st_fwrd_space.size = mvm->sf_space.size; | |
642 | ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space); | |
82e8aea0 ES |
643 | if (ret) { |
644 | IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret); | |
645 | return ret; | |
646 | } | |
91479b64 | 647 | |
8ca151b5 JB |
648 | iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); |
649 | ||
a6c4fb44 MG |
650 | /* |
651 | * configure and operate fw paging mechanism. | |
652 | * driver configures the paging flow only once, CPU2 paging image | |
653 | * included in the IWL_UCODE_INIT image. | |
654 | */ | |
655 | if (fw->paging_mem_size) { | |
e1120187 MG |
656 | /* |
657 | * When dma is not enabled, the driver needs to copy / write | |
658 | * the downloaded / uploaded page to / from the smem. | |
659 | * This gets the location of the place were the pages are | |
660 | * stored. | |
661 | */ | |
662 | if (!is_device_dma_capable(mvm->trans->dev)) { | |
663 | ret = iwl_trans_get_paging_item(mvm); | |
664 | if (ret) { | |
665 | IWL_ERR(mvm, "failed to get FW paging item\n"); | |
666 | return ret; | |
667 | } | |
668 | } | |
669 | ||
a6c4fb44 MG |
670 | ret = iwl_save_fw_paging(mvm, fw); |
671 | if (ret) { | |
672 | IWL_ERR(mvm, "failed to save the FW paging image\n"); | |
673 | return ret; | |
674 | } | |
675 | ||
676 | ret = iwl_send_paging_cmd(mvm, fw); | |
677 | if (ret) { | |
678 | IWL_ERR(mvm, "failed to send the paging cmd\n"); | |
679 | iwl_free_fw_paging(mvm); | |
680 | return ret; | |
681 | } | |
682 | } | |
683 | ||
8ca151b5 JB |
684 | /* |
685 | * Note: all the queues are enabled as part of the interface | |
686 | * initialization, but in firmware restart scenarios they | |
687 | * could be stopped, so wake them up. In firmware restart, | |
688 | * mac80211 will have the queues stopped as well until the | |
689 | * reconfiguration completes. During normal startup, they | |
690 | * will be empty. | |
691 | */ | |
692 | ||
4ecafae9 | 693 | memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); |
097129c9 LK |
694 | if (iwl_mvm_is_dqa_supported(mvm)) |
695 | mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].hw_queue_refcount = 1; | |
696 | else | |
697 | mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1; | |
8ca151b5 | 698 | |
df197c00 JB |
699 | for (i = 0; i < IEEE80211_MAX_QUEUES; i++) |
700 | atomic_set(&mvm->mac80211_queue_stop_count[i], 0); | |
8ca151b5 JB |
701 | |
702 | mvm->ucode_loaded = true; | |
703 | ||
704 | return 0; | |
705 | } | |
8ca151b5 JB |
706 | |
707 | static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) | |
708 | { | |
709 | struct iwl_phy_cfg_cmd phy_cfg_cmd; | |
710 | enum iwl_ucode_type ucode_type = mvm->cur_ucode; | |
711 | ||
712 | /* Set parameters */ | |
a0544272 | 713 | phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); |
8ca151b5 JB |
714 | phy_cfg_cmd.calib_control.event_trigger = |
715 | mvm->fw->default_calib[ucode_type].event_trigger; | |
716 | phy_cfg_cmd.calib_control.flow_trigger = | |
717 | mvm->fw->default_calib[ucode_type].flow_trigger; | |
718 | ||
719 | IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", | |
720 | phy_cfg_cmd.phy_cfg); | |
721 | ||
a1022927 | 722 | return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
723 | sizeof(phy_cfg_cmd), &phy_cfg_cmd); |
724 | } | |
725 | ||
8ca151b5 JB |
726 | int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) |
727 | { | |
728 | struct iwl_notification_wait calib_wait; | |
6eb031d2 | 729 | static const u16 init_complete[] = { |
8ca151b5 JB |
730 | INIT_COMPLETE_NOTIF, |
731 | CALIB_RES_NOTIF_PHY_DB | |
732 | }; | |
733 | int ret; | |
734 | ||
735 | lockdep_assert_held(&mvm->mutex); | |
736 | ||
8d193ca2 | 737 | if (WARN_ON_ONCE(mvm->calibrating)) |
8ca151b5 JB |
738 | return 0; |
739 | ||
740 | iwl_init_notification_wait(&mvm->notif_wait, | |
741 | &calib_wait, | |
742 | init_complete, | |
743 | ARRAY_SIZE(init_complete), | |
744 | iwl_wait_phy_db_entry, | |
745 | mvm->phy_db); | |
746 | ||
747 | /* Will also start the device */ | |
748 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); | |
749 | if (ret) { | |
750 | IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); | |
751 | goto error; | |
752 | } | |
753 | ||
ae397472 | 754 | ret = iwl_send_bt_init_conf(mvm); |
931d4160 EG |
755 | if (ret) |
756 | goto error; | |
757 | ||
81a67e32 | 758 | /* Read the NVM only at driver load time, no need to do this twice */ |
8ca151b5 JB |
759 | if (read_nvm) { |
760 | /* Read nvm */ | |
14b485f0 | 761 | ret = iwl_nvm_init(mvm, true); |
8ca151b5 JB |
762 | if (ret) { |
763 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
764 | goto error; | |
765 | } | |
766 | } | |
767 | ||
81a67e32 | 768 | /* In case we read the NVM from external file, load it to the NIC */ |
e02a9d60 | 769 | if (mvm->nvm_file_name) |
81a67e32 EL |
770 | iwl_mvm_load_nvm_to_nic(mvm); |
771 | ||
8ca151b5 JB |
772 | ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans); |
773 | WARN_ON(ret); | |
774 | ||
4f59334b EH |
775 | /* |
776 | * abort after reading the nvm in case RF Kill is on, we will complete | |
777 | * the init seq later when RF kill will switch to off | |
778 | */ | |
1a3fe0b2 | 779 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
4f59334b EH |
780 | IWL_DEBUG_RF_KILL(mvm, |
781 | "jump over all phy activities due to RF kill\n"); | |
782 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); | |
a4082843 AN |
783 | ret = 1; |
784 | goto out; | |
4f59334b EH |
785 | } |
786 | ||
31b8b343 EG |
787 | mvm->calibrating = true; |
788 | ||
e07cbb53 | 789 | /* Send TX valid antennas before triggering calibrations */ |
a0544272 | 790 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
e07cbb53 DS |
791 | if (ret) |
792 | goto error; | |
793 | ||
8ca151b5 JB |
794 | /* |
795 | * Send phy configurations command to init uCode | |
796 | * to start the 16.0 uCode init image internal calibrations. | |
797 | */ | |
798 | ret = iwl_send_phy_cfg_cmd(mvm); | |
799 | if (ret) { | |
800 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
801 | ret); | |
802 | goto error; | |
803 | } | |
804 | ||
805 | /* | |
806 | * Some things may run in the background now, but we | |
807 | * just wait for the calibration complete notification. | |
808 | */ | |
809 | ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, | |
810 | MVM_UCODE_CALIB_TIMEOUT); | |
31b8b343 | 811 | |
1a3fe0b2 | 812 | if (ret && iwl_mvm_is_radio_hw_killed(mvm)) { |
31b8b343 EG |
813 | IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); |
814 | ret = 1; | |
815 | } | |
8ca151b5 JB |
816 | goto out; |
817 | ||
818 | error: | |
819 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); | |
820 | out: | |
31b8b343 | 821 | mvm->calibrating = false; |
a4082843 | 822 | if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { |
8ca151b5 JB |
823 | /* we want to debug INIT and we have no NVM - fake */ |
824 | mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + | |
825 | sizeof(struct ieee80211_channel) + | |
826 | sizeof(struct ieee80211_rate), | |
827 | GFP_KERNEL); | |
828 | if (!mvm->nvm_data) | |
829 | return -ENOMEM; | |
8ca151b5 JB |
830 | mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; |
831 | mvm->nvm_data->bands[0].n_channels = 1; | |
832 | mvm->nvm_data->bands[0].n_bitrates = 1; | |
833 | mvm->nvm_data->bands[0].bitrates = | |
834 | (void *)mvm->nvm_data->channels + 1; | |
835 | mvm->nvm_data->bands[0].bitrates->hw_value = 10; | |
836 | } | |
837 | ||
838 | return ret; | |
839 | } | |
840 | ||
04fd2c28 LK |
841 | static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm) |
842 | { | |
843 | struct iwl_host_cmd cmd = { | |
04fd2c28 LK |
844 | .flags = CMD_WANT_SKB, |
845 | .data = { NULL, }, | |
846 | .len = { 0, }, | |
847 | }; | |
04fd2c28 | 848 | struct iwl_shared_mem_cfg *mem_cfg; |
5b086414 | 849 | struct iwl_rx_packet *pkt; |
04fd2c28 LK |
850 | u32 i; |
851 | ||
852 | lockdep_assert_held(&mvm->mutex); | |
853 | ||
5b086414 GBA |
854 | if (fw_has_capa(&mvm->fw->ucode_capa, |
855 | IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) | |
856 | cmd.id = iwl_cmd_id(SHARED_MEM_CFG_CMD, SYSTEM_GROUP, 0); | |
857 | else | |
858 | cmd.id = SHARED_MEM_CFG; | |
859 | ||
04fd2c28 LK |
860 | if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd))) |
861 | return; | |
862 | ||
863 | pkt = cmd.resp_pkt; | |
04fd2c28 LK |
864 | mem_cfg = (void *)pkt->data; |
865 | ||
866 | mvm->shared_mem_cfg.shared_mem_addr = | |
867 | le32_to_cpu(mem_cfg->shared_mem_addr); | |
868 | mvm->shared_mem_cfg.shared_mem_size = | |
869 | le32_to_cpu(mem_cfg->shared_mem_size); | |
870 | mvm->shared_mem_cfg.sample_buff_addr = | |
871 | le32_to_cpu(mem_cfg->sample_buff_addr); | |
872 | mvm->shared_mem_cfg.sample_buff_size = | |
873 | le32_to_cpu(mem_cfg->sample_buff_size); | |
874 | mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr); | |
875 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) | |
876 | mvm->shared_mem_cfg.txfifo_size[i] = | |
877 | le32_to_cpu(mem_cfg->txfifo_size[i]); | |
878 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) | |
879 | mvm->shared_mem_cfg.rxfifo_size[i] = | |
880 | le32_to_cpu(mem_cfg->rxfifo_size[i]); | |
881 | mvm->shared_mem_cfg.page_buff_addr = | |
882 | le32_to_cpu(mem_cfg->page_buff_addr); | |
883 | mvm->shared_mem_cfg.page_buff_size = | |
884 | le32_to_cpu(mem_cfg->page_buff_size); | |
5b086414 GBA |
885 | |
886 | /* new API has more data */ | |
887 | if (fw_has_capa(&mvm->fw->ucode_capa, | |
888 | IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { | |
889 | mvm->shared_mem_cfg.rxfifo_addr = | |
890 | le32_to_cpu(mem_cfg->rxfifo_addr); | |
891 | mvm->shared_mem_cfg.internal_txfifo_addr = | |
892 | le32_to_cpu(mem_cfg->internal_txfifo_addr); | |
893 | ||
894 | BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) != | |
895 | sizeof(mem_cfg->internal_txfifo_size)); | |
896 | ||
897 | for (i = 0; | |
898 | i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size); | |
899 | i++) | |
900 | mvm->shared_mem_cfg.internal_txfifo_size[i] = | |
901 | le32_to_cpu(mem_cfg->internal_txfifo_size[i]); | |
902 | } | |
903 | ||
04fd2c28 LK |
904 | IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n"); |
905 | ||
04fd2c28 LK |
906 | iwl_free_resp(&cmd); |
907 | } | |
908 | ||
84bfffa9 EG |
909 | static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) |
910 | { | |
911 | struct iwl_ltr_config_cmd cmd = { | |
912 | .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), | |
913 | }; | |
914 | ||
915 | if (!mvm->trans->ltr_enabled) | |
916 | return 0; | |
917 | ||
84bfffa9 EG |
918 | return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, |
919 | sizeof(cmd), &cmd); | |
920 | } | |
921 | ||
da2830ac LC |
922 | #define ACPI_WRDS_METHOD "WRDS" |
923 | #define ACPI_WRDS_WIFI (0x07) | |
924 | #define ACPI_WRDS_TABLE_SIZE 10 | |
925 | ||
926 | struct iwl_mvm_sar_table { | |
927 | bool enabled; | |
928 | u8 values[ACPI_WRDS_TABLE_SIZE]; | |
929 | }; | |
930 | ||
931 | #ifdef CONFIG_ACPI | |
932 | static int iwl_mvm_sar_get_wrds(struct iwl_mvm *mvm, union acpi_object *wrds, | |
933 | struct iwl_mvm_sar_table *sar_table) | |
934 | { | |
935 | union acpi_object *data_pkg; | |
936 | u32 i; | |
937 | ||
938 | /* We need at least two packages, one for the revision and one | |
939 | * for the data itself. Also check that the revision is valid | |
940 | * (i.e. it is an integer set to 0). | |
941 | */ | |
942 | if (wrds->type != ACPI_TYPE_PACKAGE || | |
943 | wrds->package.count < 2 || | |
944 | wrds->package.elements[0].type != ACPI_TYPE_INTEGER || | |
945 | wrds->package.elements[0].integer.value != 0) { | |
946 | IWL_DEBUG_RADIO(mvm, "Unsupported wrds structure\n"); | |
947 | return -EINVAL; | |
948 | } | |
949 | ||
950 | /* loop through all the packages to find the one for WiFi */ | |
951 | for (i = 1; i < wrds->package.count; i++) { | |
952 | union acpi_object *domain; | |
953 | ||
954 | data_pkg = &wrds->package.elements[i]; | |
955 | ||
956 | /* Skip anything that is not a package with the right | |
957 | * amount of elements (i.e. domain_type, | |
958 | * enabled/disabled plus the sar table size. | |
959 | */ | |
960 | if (data_pkg->type != ACPI_TYPE_PACKAGE || | |
961 | data_pkg->package.count != ACPI_WRDS_TABLE_SIZE + 2) | |
962 | continue; | |
963 | ||
964 | domain = &data_pkg->package.elements[0]; | |
965 | if (domain->type == ACPI_TYPE_INTEGER && | |
966 | domain->integer.value == ACPI_WRDS_WIFI) | |
967 | break; | |
968 | ||
969 | data_pkg = NULL; | |
970 | } | |
971 | ||
972 | if (!data_pkg) | |
973 | return -ENOENT; | |
974 | ||
975 | if (data_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) | |
976 | return -EINVAL; | |
977 | ||
978 | sar_table->enabled = !!(data_pkg->package.elements[1].integer.value); | |
979 | ||
980 | for (i = 0; i < ACPI_WRDS_TABLE_SIZE; i++) { | |
981 | union acpi_object *entry; | |
982 | ||
983 | entry = &data_pkg->package.elements[i + 2]; | |
984 | if ((entry->type != ACPI_TYPE_INTEGER) || | |
985 | (entry->integer.value > U8_MAX)) | |
986 | return -EINVAL; | |
987 | ||
988 | sar_table->values[i] = entry->integer.value; | |
989 | } | |
990 | ||
991 | return 0; | |
992 | } | |
993 | ||
994 | static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm, | |
995 | struct iwl_mvm_sar_table *sar_table) | |
996 | { | |
997 | acpi_handle root_handle; | |
998 | acpi_handle handle; | |
999 | struct acpi_buffer wrds = {ACPI_ALLOCATE_BUFFER, NULL}; | |
1000 | acpi_status status; | |
1001 | int ret; | |
1002 | ||
1003 | root_handle = ACPI_HANDLE(mvm->dev); | |
1004 | if (!root_handle) { | |
1005 | IWL_DEBUG_RADIO(mvm, | |
1006 | "Could not retrieve root port ACPI handle\n"); | |
1007 | return -ENOENT; | |
1008 | } | |
1009 | ||
1010 | /* Get the method's handle */ | |
1011 | status = acpi_get_handle(root_handle, (acpi_string)ACPI_WRDS_METHOD, | |
1012 | &handle); | |
1013 | if (ACPI_FAILURE(status)) { | |
1014 | IWL_DEBUG_RADIO(mvm, "WRDS method not found\n"); | |
1015 | return -ENOENT; | |
1016 | } | |
1017 | ||
1018 | /* Call WRDS with no arguments */ | |
1019 | status = acpi_evaluate_object(handle, NULL, NULL, &wrds); | |
1020 | if (ACPI_FAILURE(status)) { | |
1021 | IWL_DEBUG_RADIO(mvm, "WRDS invocation failed (0x%x)\n", status); | |
1022 | return -ENOENT; | |
1023 | } | |
1024 | ||
1025 | ret = iwl_mvm_sar_get_wrds(mvm, wrds.pointer, sar_table); | |
1026 | kfree(wrds.pointer); | |
1027 | ||
1028 | return ret; | |
1029 | } | |
1030 | #else /* CONFIG_ACPI */ | |
1031 | static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm, | |
1032 | struct iwl_mvm_sar_table *sar_table) | |
1033 | { | |
1034 | return -ENOENT; | |
1035 | } | |
1036 | #endif /* CONFIG_ACPI */ | |
1037 | ||
1038 | static int iwl_mvm_sar_init(struct iwl_mvm *mvm) | |
1039 | { | |
1040 | struct iwl_mvm_sar_table sar_table; | |
1041 | struct iwl_dev_tx_power_cmd cmd = { | |
55bfa4b9 | 1042 | .v3.v2.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS), |
da2830ac LC |
1043 | }; |
1044 | int ret, i, j, idx; | |
55bfa4b9 | 1045 | int len = sizeof(cmd); |
da2830ac LC |
1046 | |
1047 | /* we can't do anything with the table if the FW doesn't support it */ | |
1048 | if (!fw_has_api(&mvm->fw->ucode_capa, | |
1049 | IWL_UCODE_TLV_API_TX_POWER_CHAIN)) { | |
1050 | IWL_DEBUG_RADIO(mvm, | |
1051 | "FW doesn't support per-chain TX power settings.\n"); | |
1052 | return 0; | |
1053 | } | |
1054 | ||
55bfa4b9 LC |
1055 | if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) |
1056 | len = sizeof(cmd.v3); | |
1057 | ||
da2830ac LC |
1058 | ret = iwl_mvm_sar_get_table(mvm, &sar_table); |
1059 | if (ret < 0) { | |
1060 | IWL_DEBUG_RADIO(mvm, | |
1061 | "SAR BIOS table invalid or unavailable. (%d)\n", | |
1062 | ret); | |
1063 | /* we don't fail if the table is not available */ | |
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | if (!sar_table.enabled) | |
1068 | return 0; | |
1069 | ||
1070 | IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); | |
1071 | ||
1072 | BUILD_BUG_ON(IWL_NUM_CHAIN_LIMITS * IWL_NUM_SUB_BANDS != | |
1073 | ACPI_WRDS_TABLE_SIZE); | |
1074 | ||
1075 | for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) { | |
1076 | IWL_DEBUG_RADIO(mvm, " Chain[%d]:\n", i); | |
1077 | for (j = 0; j < IWL_NUM_SUB_BANDS; j++) { | |
1078 | idx = (i * IWL_NUM_SUB_BANDS) + j; | |
55bfa4b9 | 1079 | cmd.v3.per_chain_restriction[i][j] = |
da2830ac LC |
1080 | cpu_to_le16(sar_table.values[idx]); |
1081 | IWL_DEBUG_RADIO(mvm, " Band[%d] = %d * .125dBm\n", | |
1082 | j, sar_table.values[idx]); | |
1083 | } | |
1084 | } | |
1085 | ||
55bfa4b9 | 1086 | ret = iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd); |
da2830ac LC |
1087 | if (ret) |
1088 | IWL_ERR(mvm, "failed to set per-chain TX power: %d\n", ret); | |
1089 | ||
1090 | return ret; | |
1091 | } | |
1092 | ||
8ca151b5 JB |
1093 | int iwl_mvm_up(struct iwl_mvm *mvm) |
1094 | { | |
1095 | int ret, i; | |
53a9d61e IP |
1096 | struct ieee80211_channel *chan; |
1097 | struct cfg80211_chan_def chandef; | |
8ca151b5 JB |
1098 | |
1099 | lockdep_assert_held(&mvm->mutex); | |
1100 | ||
1101 | ret = iwl_trans_start_hw(mvm->trans); | |
1102 | if (ret) | |
1103 | return ret; | |
1104 | ||
ff116373 EL |
1105 | /* |
1106 | * If we haven't completed the run of the init ucode during | |
1107 | * module loading, load init ucode now | |
1108 | * (for example, if we were in RFKILL) | |
1109 | */ | |
8d193ca2 EH |
1110 | ret = iwl_run_init_mvm_ucode(mvm, false); |
1111 | if (ret && !iwlmvm_mod_params.init_dbg) { | |
1112 | IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); | |
1113 | /* this can't happen */ | |
1114 | if (WARN_ON(ret > 0)) | |
1115 | ret = -ERFKILL; | |
1116 | goto error; | |
1117 | } | |
1118 | if (!iwlmvm_mod_params.init_dbg) { | |
1119 | /* | |
1120 | * Stop and start the transport without entering low power | |
1121 | * mode. This will save the state of other components on the | |
1122 | * device that are triggered by the INIT firwmare (MFUART). | |
1123 | */ | |
1124 | _iwl_trans_stop_device(mvm->trans, false); | |
d643c432 | 1125 | ret = _iwl_trans_start_hw(mvm->trans, false); |
8d193ca2 | 1126 | if (ret) |
d643c432 | 1127 | goto error; |
8ca151b5 JB |
1128 | } |
1129 | ||
1130 | if (iwlmvm_mod_params.init_dbg) | |
1131 | return 0; | |
1132 | ||
1133 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); | |
1134 | if (ret) { | |
1135 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
1136 | goto error; | |
1137 | } | |
1138 | ||
6c7d32cf | 1139 | iwl_mvm_get_shared_mem_conf(mvm); |
04fd2c28 | 1140 | |
1f3b0ff8 LE |
1141 | ret = iwl_mvm_sf_update(mvm, NULL, false); |
1142 | if (ret) | |
1143 | IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); | |
1144 | ||
6a951267 | 1145 | mvm->fw_dbg_conf = FW_DBG_INVALID; |
945d4202 EG |
1146 | /* if we have a destination, assume EARLY START */ |
1147 | if (mvm->fw->dbg_dest_tlv) | |
1148 | mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE; | |
d2709ad7 | 1149 | iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE); |
6a951267 | 1150 | |
a0544272 | 1151 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1152 | if (ret) |
1153 | goto error; | |
1154 | ||
931d4160 EG |
1155 | ret = iwl_send_bt_init_conf(mvm); |
1156 | if (ret) | |
1157 | goto error; | |
1158 | ||
8ca151b5 JB |
1159 | /* Send phy db control command and then phy db calibration*/ |
1160 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1161 | if (ret) | |
1162 | goto error; | |
1163 | ||
1164 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1165 | if (ret) | |
1166 | goto error; | |
1167 | ||
43413a97 SS |
1168 | /* Init RSS configuration */ |
1169 | if (iwl_mvm_has_new_rx_api(mvm)) { | |
1170 | ret = iwl_send_rss_cfg_cmd(mvm); | |
1171 | if (ret) { | |
1172 | IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", | |
1173 | ret); | |
1174 | goto error; | |
1175 | } | |
1176 | } | |
1177 | ||
8ca151b5 JB |
1178 | /* init the fw <-> mac80211 STA mapping */ |
1179 | for (i = 0; i < IWL_MVM_STATION_COUNT; i++) | |
1180 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); | |
1181 | ||
1d3c3f63 AN |
1182 | mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT; |
1183 | ||
b2b7875b JB |
1184 | /* reset quota debouncing buffer - 0xff will yield invalid data */ |
1185 | memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); | |
1186 | ||
97d5be7e LK |
1187 | /* Enable DQA-mode if required */ |
1188 | if (iwl_mvm_is_dqa_supported(mvm)) { | |
1189 | ret = iwl_mvm_send_dqa_cmd(mvm); | |
1190 | if (ret) | |
1191 | goto error; | |
1192 | } else { | |
1193 | IWL_DEBUG_FW(mvm, "Working in non-DQA mode\n"); | |
1194 | } | |
1195 | ||
8ca151b5 JB |
1196 | /* Add auxiliary station for scanning */ |
1197 | ret = iwl_mvm_add_aux_sta(mvm); | |
1198 | if (ret) | |
1199 | goto error; | |
1200 | ||
53a9d61e | 1201 | /* Add all the PHY contexts */ |
57fbcce3 | 1202 | chan = &mvm->hw->wiphy->bands[NL80211_BAND_2GHZ]->channels[0]; |
53a9d61e IP |
1203 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); |
1204 | for (i = 0; i < NUM_PHY_CTX; i++) { | |
1205 | /* | |
1206 | * The channel used here isn't relevant as it's | |
1207 | * going to be overwritten in the other flows. | |
1208 | * For now use the first channel we have. | |
1209 | */ | |
1210 | ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], | |
1211 | &chandef, 1, 1); | |
1212 | if (ret) | |
1213 | goto error; | |
1214 | } | |
8ca151b5 | 1215 | |
c221daf2 CRI |
1216 | #ifdef CONFIG_THERMAL |
1217 | if (iwl_mvm_is_tt_in_fw(mvm)) { | |
1218 | /* in order to give the responsibility of ct-kill and | |
1219 | * TX backoff to FW we need to send empty temperature reporting | |
1220 | * cmd during init time | |
1221 | */ | |
1222 | iwl_mvm_send_temp_report_ths_cmd(mvm); | |
1223 | } else { | |
1224 | /* Initialize tx backoffs to the minimal possible */ | |
1225 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
1226 | } | |
5c89e7bc CRI |
1227 | |
1228 | /* TODO: read the budget from BIOS / Platform NVM */ | |
1229 | if (iwl_mvm_is_ctdp_supported(mvm) && mvm->cooling_dev.cur_state > 0) | |
1230 | ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, | |
1231 | mvm->cooling_dev.cur_state); | |
c221daf2 | 1232 | #else |
0c0e2c71 IY |
1233 | /* Initialize tx backoffs to the minimal possible */ |
1234 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
c221daf2 | 1235 | #endif |
0c0e2c71 | 1236 | |
84bfffa9 | 1237 | WARN_ON(iwl_mvm_config_ltr(mvm)); |
9180ac50 | 1238 | |
c1cb92fc | 1239 | ret = iwl_mvm_power_update_device(mvm); |
64b928c4 AB |
1240 | if (ret) |
1241 | goto error; | |
1242 | ||
35af15d1 AN |
1243 | /* |
1244 | * RTNL is not taken during Ct-kill, but we don't need to scan/Tx | |
1245 | * anyway, so don't init MCC. | |
1246 | */ | |
1247 | if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { | |
1248 | ret = iwl_mvm_init_mcc(mvm); | |
1249 | if (ret) | |
1250 | goto error; | |
1251 | } | |
90d4f7db | 1252 | |
859d914c | 1253 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { |
4ca87a5f | 1254 | mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; |
d2496221 DS |
1255 | ret = iwl_mvm_config_scan(mvm); |
1256 | if (ret) | |
1257 | goto error; | |
1258 | } | |
1259 | ||
93190fb0 AA |
1260 | if (iwl_mvm_is_csum_supported(mvm) && |
1261 | mvm->cfg->features & NETIF_F_RXCSUM) | |
1262 | iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3); | |
1263 | ||
7498cf4c EP |
1264 | /* allow FW/transport low power modes if not during restart */ |
1265 | if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) | |
1266 | iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN); | |
1267 | ||
da2830ac LC |
1268 | ret = iwl_mvm_sar_init(mvm); |
1269 | if (ret) | |
1270 | goto error; | |
1271 | ||
53a9d61e | 1272 | IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); |
8ca151b5 JB |
1273 | return 0; |
1274 | error: | |
fcb6b92a | 1275 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1276 | return ret; |
1277 | } | |
1278 | ||
1279 | int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) | |
1280 | { | |
1281 | int ret, i; | |
1282 | ||
1283 | lockdep_assert_held(&mvm->mutex); | |
1284 | ||
1285 | ret = iwl_trans_start_hw(mvm->trans); | |
1286 | if (ret) | |
1287 | return ret; | |
1288 | ||
1289 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); | |
1290 | if (ret) { | |
1291 | IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); | |
1292 | goto error; | |
1293 | } | |
1294 | ||
a0544272 | 1295 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1296 | if (ret) |
1297 | goto error; | |
1298 | ||
1299 | /* Send phy db control command and then phy db calibration*/ | |
1300 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1301 | if (ret) | |
1302 | goto error; | |
1303 | ||
1304 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1305 | if (ret) | |
1306 | goto error; | |
1307 | ||
1308 | /* init the fw <-> mac80211 STA mapping */ | |
1309 | for (i = 0; i < IWL_MVM_STATION_COUNT; i++) | |
1310 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); | |
1311 | ||
1312 | /* Add auxiliary station for scanning */ | |
1313 | ret = iwl_mvm_add_aux_sta(mvm); | |
1314 | if (ret) | |
1315 | goto error; | |
1316 | ||
1317 | return 0; | |
1318 | error: | |
fcb6b92a | 1319 | iwl_mvm_stop_device(mvm); |
8ca151b5 JB |
1320 | return ret; |
1321 | } | |
1322 | ||
0416841d JB |
1323 | void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, |
1324 | struct iwl_rx_cmd_buffer *rxb) | |
8ca151b5 JB |
1325 | { |
1326 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1327 | struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; | |
1328 | u32 flags = le32_to_cpu(card_state_notif->flags); | |
1329 | ||
1330 | IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", | |
1331 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
1332 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
1333 | (flags & CT_KILL_CARD_DISABLED) ? | |
1334 | "Reached" : "Not reached"); | |
8ca151b5 JB |
1335 | } |
1336 | ||
0416841d JB |
1337 | void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, |
1338 | struct iwl_rx_cmd_buffer *rxb) | |
30269c12 CRI |
1339 | { |
1340 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1341 | struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; | |
1342 | ||
1343 | IWL_DEBUG_INFO(mvm, | |
1344 | "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", | |
1345 | le32_to_cpu(mfuart_notif->installed_ver), | |
1346 | le32_to_cpu(mfuart_notif->external_ver), | |
1347 | le32_to_cpu(mfuart_notif->status), | |
1348 | le32_to_cpu(mfuart_notif->duration)); | |
30269c12 | 1349 | } |