projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: pcie: add infrastructure for multi-queue rx
[deliverable/linux.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 10 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 37 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
e6bb4c9c 75
82575102 76#include "iwl-drv.h"
c85eb619 77#include "iwl-trans.h"
522376d2
EG		 78#include "iwl-csr.h"
79#include "iwl-prph.h"
cb6bb128 80#include "iwl-scd.h"
7a10e3e4 81#include "iwl-agn-hw.h"
4d075007 82#include "iwl-fw-error-dump.h"
6468a01a 83#include "internal.h"
06d51e0d 84#include "iwl-fh.h"
0439bb62 85
fe45773b
AN		 86/* extended range in FW SRAM */
87#define IWL_FW_MEM_EXTENDED_START 0x40000
88#define IWL_FW_MEM_EXTENDED_END 0x57FFF
89
c2d20201
EG		 90static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
91{
92 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
93
94 if (!trans_pcie->fw_mon_page)
95 return;
96
97 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
98 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
99 __free_pages(trans_pcie->fw_mon_page,
100 get_order(trans_pcie->fw_mon_size));
101 trans_pcie->fw_mon_page = NULL;
102 trans_pcie->fw_mon_phys = 0;
103 trans_pcie->fw_mon_size = 0;
104}
105
96c285da 106static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 107{
108 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 109 struct page *page = NULL;
c2d20201 110 dma_addr_t phys;
96c285da 111 u32 size = 0;
c2d20201
EG		 112 u8 power;
113
96c285da
EG		 114 if (!max_power) {
115 /* default max_power is maximum */
116 max_power = 26;
117 } else {
118 max_power += 11;
119 }
120
121 if (WARN(max_power > 26,
122 "External buffer size for monitor is too big %d, check the FW TLV\n",
123 max_power))
124 return;
125
c2d20201
EG		 126 if (trans_pcie->fw_mon_page) {
127 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
128 trans_pcie->fw_mon_size,
129 DMA_FROM_DEVICE);
130 return;
131 }
132
133 phys = 0;
96c285da 134 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 135 int order;
136
137 size = BIT(power);
138 order = get_order(size);
139 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
140 order);
141 if (!page)
142 continue;
143
144 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
145 DMA_FROM_DEVICE);
146 if (dma_mapping_error(trans->dev, phys)) {
147 __free_pages(page, order);
553452e5 148 page = NULL;
c2d20201
EG		 149 continue;
150 }
151 IWL_INFO(trans,
152 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
153 size, order);
154 break;
155 }
156
40a76905 157 if (WARN_ON_ONCE(!page))
c2d20201
EG		 158 return;
159
96c285da
EG		 160 if (power != max_power)
161 IWL_ERR(trans,
162 "Sorry - debug buffer is only %luK while you requested %luK\n",
163 (unsigned long)BIT(power - 10),
164 (unsigned long)BIT(max_power - 10));
165
c2d20201
EG		 166 trans_pcie->fw_mon_page = page;
167 trans_pcie->fw_mon_phys = phys;
168 trans_pcie->fw_mon_size = size;
169}
170
a812cba9
AB		 171static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
172{
173 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
174 ((reg & 0x0000ffff) | (2 << 28)));
175 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
176}
177
178static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
179{
180 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
182 ((reg & 0x0000ffff) | (3 << 28)));
183}
184
ddaf5a5b 185static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 186{
66337b7c 187 if (trans->cfg->apmg_not_supported)
95411d04
AA		 188 return;
189
ddaf5a5b
JB		 190 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
191 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
192 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
193 ~APMG_PS_CTRL_MSK_PWR_SRC);
194 else
195 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
196 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
197 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 198}
199
af634bee
EG		 200/* PCI registers */
201#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 202
7afe3705 203static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 204{
20d3b647 205 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 206 u16 lctl;
9180ac50 207 u16 cap;
af634bee 208
af634bee
EG		 209 /*
210 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
211 * Check if BIOS (or OS) enabled L1-ASPM on this device.
212 * If so (likely), disable L0S, so device moves directly L0->L1;
213 * costs negligible amount of power savings.
214 * If not (unlikely), enable L0S, so there is at least some
215 * power savings, even without L1.
216 */
7afe3705 217 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 218 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 219 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 220 else
af634bee 221 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 222 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 223
224 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
225 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
226 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
227 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
228 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 229}
230
a6c684ee
EG		 231/*
232 * Start up NIC's basic functionality after it has been reset
7afe3705 233 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 234 * NOTE: This does not load uCode nor start the embedded processor
235 */
7afe3705 236static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 237{
238 int ret = 0;
239 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
240
241 /*
242 * Use "set_bit" below rather than "write", to preserve any hardware
243 * bits already set by default after reset.
244 */
245
246 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 247 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
248 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
249 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 250
251 /*
252 * Disable L0s without affecting L1;
253 * don't wait for ICH L0s (ICH bug W/A)
254 */
255 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 256 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 257
258 /* Set FH wait threshold to maximum (HW error during stress W/A) */
259 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
260
261 /*
262 * Enable HAP INTA (interrupt from management bus) to
263 * wake device's PCI Express link L1a -> L0s
264 */
265 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 266 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 267
7afe3705 268 iwl_pcie_apm_config(trans);
a6c684ee
EG		 269
270 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 271 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 272 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 273 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
2d93aee1
EG		 294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
a6c684ee
EG		 316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
3073d8c0
EH		 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 322 */
95411d04 323 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
889b1696 336
eb7ff77e 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 338
339out:
340 return ret;
341}
342
a812cba9
AB		 343/*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
350static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351{
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
363
364 udelay(10);
365
366 /*
367 * Set "initialization complete" bit to move adapter from
368 * D0U* --> D0A* (powered-up active) state.
369 */
370 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
371
372 /*
373 * Wait for clock stabilization; once stabilized, access to
374 * device-internal resources is possible.
375 */
376 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
379 25000);
380 if (WARN_ON(ret < 0)) {
381 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
382 /* Release XTAL ON request */
383 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
384 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
385 return;
386 }
387
388 /*
389 * Clear "disable persistence" to avoid LP XTAL resetting when
390 * SHRD_HW_RST is applied in S3.
391 */
392 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
393 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
394
395 /*
396 * Force APMG XTAL to be active to prevent its disabling by HW
397 * caused by APMG idle state.
398 */
399 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
400 SHR_APMG_XTAL_CFG_REG);
401 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
402 apmg_xtal_cfg_reg |
403 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
404
405 /*
406 * Reset entire device again - do controller reset (results in
407 * SHRD_HW_RST). Turn MAC off before proceeding.
408 */
409 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
410
411 udelay(10);
412
413 /* Enable LP XTAL by indirect access through CSR */
414 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
415 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
416 SHR_APMG_GP1_WF_XTAL_LP_EN |
417 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
418
419 /* Clear delay line clock power up */
420 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
421 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
422 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
423
424 /*
425 * Enable persistence mode to avoid LP XTAL resetting when
426 * SHRD_HW_RST is applied in S3.
427 */
428 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
429 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
430
431 /*
432 * Clear "initialization complete" bit to move adapter from
433 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
434 */
435 iwl_clear_bit(trans, CSR_GP_CNTRL,
436 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
437
438 /* Activates XTAL resources monitor */
439 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
440 CSR_MONITOR_XTAL_RESOURCES);
441
442 /* Release XTAL ON request */
443 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
444 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
445 udelay(10);
446
447 /* Release APMG XTAL */
448 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
449 apmg_xtal_cfg_reg &
450 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
451}
452
7afe3705 453static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 454{
455 int ret = 0;
456
457 /* stop device's busmaster DMA activity */
458 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
459
460 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 461 CSR_RESET_REG_FLAG_MASTER_DISABLED,
462 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 463 if (ret < 0)
cc56feb2
EG		 464 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
465
466 IWL_DEBUG_INFO(trans, "stop master\n");
467
468 return ret;
469}
470
b7aaeae4 471static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 472{
473 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
474
b7aaeae4
EG		 475 if (op_mode_leave) {
476 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
477 iwl_pcie_apm_init(trans);
478
479 /* inform ME that we are leaving */
480 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
481 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
482 APMG_PCIDEV_STT_VAL_WAKE_ME);
c9fdec9f
EG		 483 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
484 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
485 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 486 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
487 CSR_HW_IF_CONFIG_REG_PREPARE |
488 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 489 mdelay(1);
490 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
491 CSR_RESET_LINK_PWR_MGMT_DISABLED);
492 }
b7aaeae4
EG		 493 mdelay(5);
494 }
495
eb7ff77e 496 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 497
498 /* Stop device's DMA activity */
7afe3705 499 iwl_pcie_apm_stop_master(trans);
cc56feb2 500
a812cba9
AB		 501 if (trans->cfg->lp_xtal_workaround) {
502 iwl_pcie_apm_lp_xtal_enable(trans);
503 return;
504 }
505
cc56feb2
EG		 506 /* Reset the entire device */
507 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
508
509 udelay(10);
510
511 /*
512 * Clear "initialization complete" bit to move adapter from
513 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
514 */
515 iwl_clear_bit(trans, CSR_GP_CNTRL,
516 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
517}
518
7afe3705 519static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 520{
7b11488f 521 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 522
523 /* nic_init */
7b70bd63 524 spin_lock(&trans_pcie->irq_lock);
7afe3705 525 iwl_pcie_apm_init(trans);
392f8b78 526
7b70bd63 527 spin_unlock(&trans_pcie->irq_lock);
392f8b78 528
95411d04 529 iwl_pcie_set_pwr(trans, false);
392f8b78 530
ecdb975c 531 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 532
533 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 534 iwl_pcie_rx_init(trans);
392f8b78
EG		 535
536 /* Allocate or reset and init all Tx and Command queues */
f02831be 537 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 538 return -ENOMEM;
539
035f7ff2 540 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 541 /* enable shadow regs in HW */
20d3b647 542 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 543 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 544 }
545
392f8b78
EG		 546 return 0;
547}
548
549#define HW_READY_TIMEOUT (50)
550
551/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 552static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 553{
554 int ret;
555
1042db2a 556 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 557 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 558
559 /* See if we got it */
1042db2a 560 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 561 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
562 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
563 HW_READY_TIMEOUT);
392f8b78 564
6a08f514
EG		 565 if (ret >= 0)
566 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
567
6d8f6eeb 568 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 569 return ret;
570}
571
572/* Note: returns standard 0/-ERROR code */
7afe3705 573static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 574{
575 int ret;
289e5501 576 int t = 0;
501fd989 577 int iter;
392f8b78 578
6d8f6eeb 579 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 580
7afe3705 581 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 582 /* If the card is ready, exit 0 */
392f8b78
EG		 583 if (ret >= 0)
584 return 0;
585
c9fdec9f
EG		 586 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
587 CSR_RESET_LINK_PWR_MGMT_DISABLED);
588 msleep(1);
589
501fd989
EG		 590 for (iter = 0; iter < 10; iter++) {
591 /* If HW is not ready, prepare the conditions to check again */
592 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
593 CSR_HW_IF_CONFIG_REG_PREPARE);
594
595 do {
596 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 597 if (ret >= 0)
598 return 0;
392f8b78 599
501fd989
EG		 600 usleep_range(200, 1000);
601 t += 200;
602 } while (t < 150000);
603 msleep(25);
604 }
392f8b78 605
7f2ac8fb 606 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 607
392f8b78
EG		 608 return ret;
609}
610
cf614297
EG		 611/*
612 * ucode
613 */
7afe3705 614static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 615 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 616{
13df1aab 617 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 618 int ret;
619
13df1aab 620 trans_pcie->ucode_write_complete = false;
cf614297
EG		 621
622 iwl_write_direct32(trans,
20d3b647
JB		 623 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
624 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 625
626 iwl_write_direct32(trans,
20d3b647
JB		 627 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
628 dst_addr);
cf614297
EG		 629
630 iwl_write_direct32(trans,
83f84d7b
JB		 631 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
632 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 633
634 iwl_write_direct32(trans,
20d3b647
JB		 635 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
636 (iwl_get_dma_hi_addr(phy_addr)
637 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 638
639 iwl_write_direct32(trans,
20d3b647
JB		 640 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
641 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
642 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
643 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 644
645 iwl_write_direct32(trans,
20d3b647
JB		 646 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
647 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
648 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
649 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 650
13df1aab
JB		 651 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
652 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 653 if (!ret) {
83f84d7b 654 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 655 return -ETIMEDOUT;
656 }
657
658 return 0;
659}
660
7afe3705 661static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 662 const struct fw_desc *section)
cf614297 663{
83f84d7b
JB		 664 u8 *v_addr;
665 dma_addr_t p_addr;
baa21e83 666 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 667 int ret = 0;
668
83f84d7b
JB		 669 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
670 section_num);
671
c571573a
EG		 672 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
673 GFP_KERNEL | __GFP_NOWARN);
674 if (!v_addr) {
675 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
676 chunk_sz = PAGE_SIZE;
677 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
678 &p_addr, GFP_KERNEL);
679 if (!v_addr)
680 return -ENOMEM;
681 }
83f84d7b 682
c571573a 683 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 684 u32 copy_size, dst_addr;
685 bool extended_addr = false;
83f84d7b 686
c571573a 687 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 688 dst_addr = section->offset + offset;
689
690 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
691 dst_addr <= IWL_FW_MEM_EXTENDED_END)
692 extended_addr = true;
693
694 if (extended_addr)
695 iwl_set_bits_prph(trans, LMPM_CHICK,
696 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 697
83f84d7b 698 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 699 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
700 copy_size);
701
702 if (extended_addr)
703 iwl_clear_bits_prph(trans, LMPM_CHICK,
704 LMPM_CHICK_EXTENDED_ADDR_SPACE);
705
83f84d7b
JB		 706 if (ret) {
707 IWL_ERR(trans,
708 "Could not load the [%d] uCode section\n",
709 section_num);
710 break;
6dfa8d01 711 }
83f84d7b
JB		 712 }
713
c571573a 714 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 715 return ret;
716}
717
16bc119b
EH		 718/*
719 * Driver Takes the ownership on secure machine before FW load
720 * and prevent race with the BT load.
721 * W/A for ROM bug. (should be remove in the next Si step)
722 */
723static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
724{
725 u32 val, loop = 1000;
726
1e167071
EH		 727 /*
728 * Check the RSA semaphore is accessible.
729 * If the HW isn't locked and the rsa semaphore isn't accessible,
730 * we are in trouble.
731 */
16bc119b
EH		 732 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
733 if (val & (BIT(1) | BIT(17))) {
1e167071
EH		 734 IWL_INFO(trans,
735 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 736 return 0;
737 }
738
739 /* take ownership on the AUX IF */
740 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
741 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
742
743 do {
744 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
745 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
746 if (val == 0x1) {
747 iwl_write_prph(trans, RSA_ENABLE, 0);
748 return 0;
749 }
750
751 udelay(10);
752 loop--;
753 } while (loop > 0);
754
755 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
756 return -EIO;
757}
758
5dd9c68a
EG		 759static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
760 const struct fw_img *image,
761 int cpu,
762 int *first_ucode_section)
e2d6f4e7
EH		 763{
764 int shift_param;
dcab8ecd
EH		 765 int i, ret = 0, sec_num = 0x1;
766 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 767
768 if (cpu == 1) {
769 shift_param = 0;
034846cf 770 *first_ucode_section = 0;
e2d6f4e7
EH		 771 } else {
772 shift_param = 16;
034846cf 773 (*first_ucode_section)++;
e2d6f4e7
EH		 774 }
775
034846cf
EH		 776 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
777 last_read_idx = i;
778
a6c4fb44
MG		 779 /*
780 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
781 * CPU1 to CPU2.
782 * PAGING_SEPARATOR_SECTION delimiter - separate between
783 * CPU2 non paged to CPU2 paging sec.
784 */
034846cf 785 if (!image->sec[i].data ||
a6c4fb44
MG		 786 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
787 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 788 IWL_DEBUG_FW(trans,
789 "Break since Data not valid or Empty section, sec = %d\n",
790 i);
189fa2fa 791 break;
034846cf
EH		 792 }
793
189fa2fa
EH		 794 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
795 if (ret)
796 return ret;
dcab8ecd
EH		 797
798 /* Notify the ucode of the loaded section number and status */
799 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
800 val = val | (sec_num << shift_param);
801 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
802 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 803 }
804
034846cf
EH		 805 *first_ucode_section = last_read_idx;
806
afb88917
EH		 807 if (cpu == 1)
808 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
809 else
810 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
811
189fa2fa
EH		 812 return 0;
813}
e2d6f4e7 814
189fa2fa
EH		 815static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
816 const struct fw_img *image,
034846cf
EH		 817 int cpu,
818 int *first_ucode_section)
189fa2fa
EH		 819{
820 int shift_param;
189fa2fa 821 int i, ret = 0;
034846cf 822 u32 last_read_idx = 0;
189fa2fa
EH		 823
824 if (cpu == 1) {
825 shift_param = 0;
034846cf 826 *first_ucode_section = 0;
189fa2fa
EH		 827 } else {
828 shift_param = 16;
034846cf 829 (*first_ucode_section)++;
189fa2fa
EH		 830 }
831
034846cf
EH		 832 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
833 last_read_idx = i;
834
a6c4fb44
MG		 835 /*
836 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
837 * CPU1 to CPU2.
838 * PAGING_SEPARATOR_SECTION delimiter - separate between
839 * CPU2 non paged to CPU2 paging sec.
840 */
034846cf 841 if (!image->sec[i].data ||
a6c4fb44
MG		 842 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
843 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 844 IWL_DEBUG_FW(trans,
845 "Break since Data not valid or Empty section, sec = %d\n",
846 i);
189fa2fa 847 break;
034846cf
EH		 848 }
849
189fa2fa
EH		 850 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
851 if (ret)
852 return ret;
e2d6f4e7
EH		 853 }
854
189fa2fa
EH		 855 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
856 iwl_set_bits_prph(trans,
857 CSR_UCODE_LOAD_STATUS_ADDR,
858 (LMPM_CPU_UCODE_LOADING_COMPLETED |
859 LMPM_CPU_HDRS_LOADING_COMPLETED |
860 LMPM_CPU_UCODE_LOADING_STARTED) <<
861 shift_param);
862
034846cf
EH		 863 *first_ucode_section = last_read_idx;
864
e2d6f4e7
EH		 865 return 0;
866}
867
09e350f7
LK		 868static void iwl_pcie_apply_destination(struct iwl_trans *trans)
869{
870 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
871 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
872 int i;
873
874 if (dest->version)
875 IWL_ERR(trans,
876 "DBG DEST version is %d - expect issues\n",
877 dest->version);
878
879 IWL_INFO(trans, "Applying debug destination %s\n",
880 get_fw_dbg_mode_string(dest->monitor_mode));
881
882 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 883 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 884 else
885 IWL_WARN(trans, "PCI should have external buffer debug\n");
886
887 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
888 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
889 u32 val = le32_to_cpu(dest->reg_ops[i].val);
890
891 switch (dest->reg_ops[i].op) {
892 case CSR_ASSIGN:
893 iwl_write32(trans, addr, val);
894 break;
895 case CSR_SETBIT:
896 iwl_set_bit(trans, addr, BIT(val));
897 break;
898 case CSR_CLEARBIT:
899 iwl_clear_bit(trans, addr, BIT(val));
900 break;
901 case PRPH_ASSIGN:
902 iwl_write_prph(trans, addr, val);
903 break;
904 case PRPH_SETBIT:
905 iwl_set_bits_prph(trans, addr, BIT(val));
906 break;
907 case PRPH_CLEARBIT:
908 iwl_clear_bits_prph(trans, addr, BIT(val));
909 break;
869f3b15
HD		 910 case PRPH_BLOCKBIT:
911 if (iwl_read_prph(trans, addr) & BIT(val)) {
912 IWL_ERR(trans,
913 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
914 val, addr);
915 goto monitor;
916 }
917 break;
09e350f7
LK		 918 default:
919 IWL_ERR(trans, "FW debug - unknown OP %d\n",
920 dest->reg_ops[i].op);
921 break;
922 }
923 }
924
869f3b15 925monitor:
09e350f7
LK		 926 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
927 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
928 trans_pcie->fw_mon_phys >> dest->base_shift);
62d7476d
EG		 929 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
930 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
931 (trans_pcie->fw_mon_phys +
932 trans_pcie->fw_mon_size - 256) >>
933 dest->end_shift);
934 else
935 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
936 (trans_pcie->fw_mon_phys +
937 trans_pcie->fw_mon_size) >>
938 dest->end_shift);
09e350f7
LK		 939 }
940}
941
7afe3705 942static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 943 const struct fw_img *image)
cf614297 944{
c2d20201 945 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 946 int ret = 0;
034846cf 947 int first_ucode_section;
cf614297 948
dcab8ecd 949 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 950 image->is_dual_cpus ? "Dual" : "Single");
951
dcab8ecd
EH		 952 /* load to FW the binary non secured sections of CPU1 */
953 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
954 if (ret)
955 return ret;
e2d6f4e7
EH		 956
957 if (image->is_dual_cpus) {
189fa2fa
EH		 958 /* set CPU2 header address */
959 iwl_write_prph(trans,
960 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
961 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 962
189fa2fa 963 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 964 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
965 &first_ucode_section);
189fa2fa
EH		 966 if (ret)
967 return ret;
e2d6f4e7 968 }
cf614297 969
c2d20201
EG		 970 /* supported for 7000 only for the moment */
971 if (iwlwifi_mod_params.fw_monitor &&
972 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 973 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 974
975 if (trans_pcie->fw_mon_size) {
976 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
977 trans_pcie->fw_mon_phys >> 4);
978 iwl_write_prph(trans, MON_BUFF_END_ADDR,
979 (trans_pcie->fw_mon_phys +
980 trans_pcie->fw_mon_size) >> 4);
981 }
09e350f7
LK		 982 } else if (trans->dbg_dest_tlv) {
983 iwl_pcie_apply_destination(trans);
c2d20201
EG		 984 }
985
e12ba844 986 /* release CPU reset */
5dd9c68a 987 iwl_write32(trans, CSR_RESET, 0);
e12ba844 988
dcab8ecd
EH		 989 return 0;
990}
189fa2fa 991
5dd9c68a
EG		 992static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
993 const struct fw_img *image)
dcab8ecd
EH		 994{
995 int ret = 0;
996 int first_ucode_section;
dcab8ecd
EH		 997
998 IWL_DEBUG_FW(trans, "working with %s CPU\n",
999 image->is_dual_cpus ? "Dual" : "Single");
1000
a2227ce2
EG		 1001 if (trans->dbg_dest_tlv)
1002 iwl_pcie_apply_destination(trans);
1003
16bc119b
EH		 1004 /* TODO: remove in the next Si step */
1005 ret = iwl_pcie_rsa_race_bug_wa(trans);
1006 if (ret)
1007 return ret;
1008
dcab8ecd
EH		 1009 /* configure the ucode to be ready to get the secured image */
1010 /* release CPU reset */
1011 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1012
1013 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1014 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1015 &first_ucode_section);
dcab8ecd
EH		 1016 if (ret)
1017 return ret;
1018
1019 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1020 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1021 &first_ucode_section);
cf614297
EG		 1022}
1023
0692fe41 1024static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 1025 const struct fw_img *fw, bool run_in_rfkill)
392f8b78 1026{
fa9f3281 1027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1028 bool hw_rfkill;
fa9f3281
EG		 1029 int ret;
1030
1031 mutex_lock(&trans_pcie->mutex);
1032
1033 /* Someone called stop_device, don't try to start_fw */
1034 if (trans_pcie->is_down) {
1035 IWL_WARN(trans,
1036 "Can't start_fw since the HW hasn't been started\n");
1037 ret = EIO;
1038 goto out;
1039 }
392f8b78 1040
496bab39 1041 /* This may fail if AMT took ownership of the device */
7afe3705 1042 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 1043 IWL_WARN(trans, "Exit HW not ready\n");
fa9f3281
EG		 1044 ret = -EIO;
1045 goto out;
392f8b78
EG		 1046 }
1047
8c46bb70
EG		 1048 iwl_enable_rfkill_int(trans);
1049
392f8b78 1050 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 1051 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1052 if (hw_rfkill)
eb7ff77e 1053 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1054 else
eb7ff77e 1055 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1056 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
fa9f3281
EG		 1057 if (hw_rfkill && !run_in_rfkill) {
1058 ret = -ERFKILL;
1059 goto out;
1060 }
392f8b78 1061
1042db2a 1062 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 1063
7afe3705 1064 ret = iwl_pcie_nic_init(trans);
392f8b78 1065 if (ret) {
6d8f6eeb 1066 IWL_ERR(trans, "Unable to init nic\n");
fa9f3281 1067 goto out;
392f8b78
EG		 1068 }
1069
1070 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 1071 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1072 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 1073 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1074
1075 /* clear (again), then enable host interrupts */
1042db2a 1076 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 1077 iwl_enable_interrupts(trans);
392f8b78
EG		 1078
1079 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 1080 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1081 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 1082
cf614297 1083 /* Load the given image to the HW */
5dd9c68a 1084 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
fa9f3281 1085 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
dcab8ecd 1086 else
fa9f3281
EG		 1087 ret = iwl_pcie_load_given_ucode(trans, fw);
1088
1089out:
1090 mutex_unlock(&trans_pcie->mutex);
1091 return ret;
b3c2ce13
EG		 1092}
1093
adca1235 1094static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 1095{
990aa6d7 1096 iwl_pcie_reset_ict(trans);
f02831be 1097 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 1098}
1099
fa9f3281 1100static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1101{
43e58856 1102 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1103 bool hw_rfkill, was_hw_rfkill;
1104
fa9f3281
EG		 1105 lockdep_assert_held(&trans_pcie->mutex);
1106
1107 if (trans_pcie->is_down)
1108 return;
1109
1110 trans_pcie->is_down = true;
1111
3dc3374f 1112 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1113
43e58856 1114 /* tell the device to stop sending interrupts */
7b70bd63 1115 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1116 iwl_disable_interrupts(trans);
7b70bd63 1117 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1118
ab6cf8e8 1119 /* device going down, Stop using ICT table */
990aa6d7 1120 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1121
1122 /*
1123 * If a HW restart happens during firmware loading,
1124 * then the firmware loading might call this function
1125 * and later it might be called again due to the
1126 * restart. So don't process again if the device is
1127 * already dead.
1128 */
31b8b343
EG		 1129 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1130 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1131 iwl_pcie_tx_stop(trans);
9805c446 1132 iwl_pcie_rx_stop(trans);
6379103e 1133
ab6cf8e8 1134 /* Power-down device's busmaster DMA clocks */
95411d04 1135 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1136 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1137 APMG_CLK_VAL_DMA_CLK_RQT);
1138 udelay(5);
1139 }
ab6cf8e8
EG		 1140 }
1141
1142 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1143 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1144 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1145
1146 /* Stop the device, and put it in low power state */
b7aaeae4 1147 iwl_pcie_apm_stop(trans, false);
43e58856 1148
03d6c3b0
EG		 1149 /* stop and reset the on-board processor */
1150 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1151 udelay(20);
1152
1153 /*
1154 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1155 * This is a bug in certain verions of the hardware.
1156 * Certain devices also keep sending HW RF kill interrupt all
1157 * the time, unless the interrupt is ACKed even if the interrupt
1158 * should be masked. Re-ACK all the interrupts here.
43e58856 1159 */
7b70bd63 1160 spin_lock(&trans_pcie->irq_lock);
43e58856 1161 iwl_disable_interrupts(trans);
7b70bd63 1162 spin_unlock(&trans_pcie->irq_lock);
43e58856 1163
74fda971
DF		 1164
1165 /* clear all status bits */
eb7ff77e
AN		 1166 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1167 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1168 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1169 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1170
1171 /*
1172 * Even if we stop the HW, we still want the RF kill
1173 * interrupt
1174 */
1175 iwl_enable_rfkill_int(trans);
1176
1177 /*
1178 * Check again since the RF kill state may have changed while
1179 * all the interrupts were disabled, in this case we couldn't
1180 * receive the RF kill interrupt and update the state in the
1181 * op_mode.
3dc3374f
EG		 1182 * Don't call the op_mode if the rkfill state hasn't changed.
1183 * This allows the op_mode to call stop_device from the rfkill
1184 * notification without endless recursion. Under very rare
1185 * circumstances, we might have a small recursion if the rfkill
1186 * state changed exactly now while we were called from stop_device.
1187 * This is very unlikely but can happen and is supported.
a4082843
AN		 1188 */
1189 hw_rfkill = iwl_is_rfkill_set(trans);
1190 if (hw_rfkill)
eb7ff77e 1191 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1192 else
eb7ff77e 1193 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1194 if (hw_rfkill != was_hw_rfkill)
14cfca71 1195 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1196
1197 /* re-take ownership to prevent other users from stealing the deivce */
1198 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1199}
1200
fa9f3281
EG		 1201static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1202{
1203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1204
1205 mutex_lock(&trans_pcie->mutex);
1206 _iwl_trans_pcie_stop_device(trans, low_power);
1207 mutex_unlock(&trans_pcie->mutex);
1208}
1209
14cfca71
JB		 1210void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1211{
fa9f3281
EG		 1212 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1213 IWL_TRANS_GET_PCIE_TRANS(trans);
1214
1215 lockdep_assert_held(&trans_pcie->mutex);
1216
14cfca71 1217 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1218 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1219}
1220
debff618 1221static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1222{
33b56af1
EG		 1223 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1224
b7282643 1225 if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3) {
6dfb36c8
EP		 1226 /* Enable persistence mode to avoid reset */
1227 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1228 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1229 }
1230
2dd4f9f7 1231 iwl_disable_interrupts(trans);
debff618
JB		 1232
1233 /*
1234 * in testing mode, the host stays awake and the
1235 * hardware won't be reset (not even partially)
1236 */
1237 if (test)
1238 return;
1239
ddaf5a5b
JB		 1240 iwl_pcie_disable_ict(trans);
1241
33b56af1
EG		 1242 synchronize_irq(trans_pcie->pci_dev->irq);
1243
2dd4f9f7
JB		 1244 iwl_clear_bit(trans, CSR_GP_CNTRL,
1245 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1246 iwl_clear_bit(trans, CSR_GP_CNTRL,
1247 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1248
b7282643 1249 if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D3) {
6dfb36c8
EP		 1250 /*
1251 * reset TX queues -- some of their registers reset during S3
1252 * so if we don't reset everything here the D3 image would try
1253 * to execute some invalid memory upon resume
1254 */
1255 iwl_trans_pcie_tx_reset(trans);
1256 }
ddaf5a5b
JB		 1257
1258 iwl_pcie_set_pwr(trans, true);
1259}
1260
1261static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1262 enum iwl_d3_status *status,
1263 bool test)
ddaf5a5b
JB		 1264{
1265 u32 val;
1266 int ret;
1267
debff618
JB		 1268 if (test) {
1269 iwl_enable_interrupts(trans);
1270 *status = IWL_D3_STATUS_ALIVE;
1271 return 0;
1272 }
1273
ddaf5a5b
JB		 1274 /*
1275 * Also enables interrupts - none will happen as the device doesn't
1276 * know we're waking it up, only when the opmode actually tells it
1277 * after this call.
1278 */
1279 iwl_pcie_reset_ict(trans);
1280
1281 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1282 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1283
01e58a28
EG		 1284 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1285 udelay(2);
1286
ddaf5a5b
JB		 1287 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1289 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1290 25000);
7f2ac8fb 1291 if (ret < 0) {
ddaf5a5b
JB		 1292 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1293 return ret;
1294 }
1295
a3ead656
EG		 1296 iwl_pcie_set_pwr(trans, false);
1297
b7282643 1298 if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3) {
6dfb36c8
EP		 1299 iwl_clear_bit(trans, CSR_GP_CNTRL,
1300 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1301 } else {
1302 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1303
6dfb36c8
EP		 1304 ret = iwl_pcie_rx_init(trans);
1305 if (ret) {
1306 IWL_ERR(trans,
1307 "Failed to resume the device (RX reset)\n");
1308 return ret;
1309 }
ddaf5a5b
JB		 1310 }
1311
a3ead656
EG		 1312 val = iwl_read32(trans, CSR_RESET);
1313 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1314 *status = IWL_D3_STATUS_RESET;
1315 else
1316 *status = IWL_D3_STATUS_ALIVE;
1317
ddaf5a5b 1318 return 0;
2dd4f9f7
JB		 1319}
1320
fa9f3281 1321static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1322{
fa9f3281 1323 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1324 bool hw_rfkill;
a8b691e6 1325 int err;
e6bb4c9c 1326
fa9f3281
EG		 1327 lockdep_assert_held(&trans_pcie->mutex);
1328
7afe3705 1329 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1330 if (err) {
d6f1c316 1331 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1332 return err;
ebb7678d 1333 }
a6c684ee 1334
2997494f 1335 /* Reset the entire device */
ce836c76 1336 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1337
1338 usleep_range(10, 15);
1339
7afe3705 1340 iwl_pcie_apm_init(trans);
a6c684ee 1341
226c02ca
EG		 1342 /* From now on, the op_mode will be kept updated about RF kill state */
1343 iwl_enable_rfkill_int(trans);
1344
fa9f3281
EG		 1345 /* Set is_down to false here so that...*/
1346 trans_pcie->is_down = false;
1347
8d425517 1348 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1349 if (hw_rfkill)
eb7ff77e 1350 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1351 else
eb7ff77e 1352 clear_bit(STATUS_RFKILL, &trans->status);
fa9f3281 1353 /* ... rfkill can call stop_device and set it false if needed */
14cfca71 1354 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1355
a8b691e6 1356 return 0;
e6bb4c9c
EG		 1357}
1358
fa9f3281
EG		 1359static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1360{
1361 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1362 int ret;
1363
1364 mutex_lock(&trans_pcie->mutex);
1365 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1366 mutex_unlock(&trans_pcie->mutex);
1367
1368 return ret;
1369}
1370
a4082843 1371static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1372{
20d3b647 1373 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1374
fa9f3281
EG		 1375 mutex_lock(&trans_pcie->mutex);
1376
a4082843 1377 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1378 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1379 iwl_disable_interrupts(trans);
7b70bd63 1380 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1381
b7aaeae4 1382 iwl_pcie_apm_stop(trans, true);
cc56feb2 1383
7b70bd63 1384 spin_lock(&trans_pcie->irq_lock);
218733cf 1385 iwl_disable_interrupts(trans);
7b70bd63 1386 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1387
8d96bb61 1388 iwl_pcie_disable_ict(trans);
33b56af1 1389
fa9f3281 1390 mutex_unlock(&trans_pcie->mutex);
33b56af1
EG		 1391
1392 synchronize_irq(trans_pcie->pci_dev->irq);
cc56feb2
EG		 1393}
1394
03905495
EG		 1395static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1396{
05f5b97e 1397 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1398}
1399
1400static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1401{
05f5b97e 1402 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1403}
1404
1405static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1406{
05f5b97e 1407 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1408}
1409
6a06b6c1
EG		 1410static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1411{
f9477c17
AP		 1412 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1413 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1414 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1415}
1416
1417static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1418 u32 val)
1419{
1420 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1421 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1422 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1423}
1424
f14d6b39
JB		 1425static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1426{
1427 WARN_ON(1);
1428 return 0;
1429}
1430
c6f600fc 1431static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1432 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1433{
1434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1435
1436 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1437 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1438 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1439 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1440 trans_pcie->n_no_reclaim_cmds = 0;
1441 else
1442 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1443 if (trans_pcie->n_no_reclaim_cmds)
1444 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1445 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1446
6c4fbcbc
EG		 1447 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1448 trans_pcie->rx_page_order =
1449 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1450
ab02165c 1451 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
046db346 1452 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1453 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1454 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1455
39bdb17e
SD		 1456 trans->command_groups = trans_cfg->command_groups;
1457 trans->command_groups_size = trans_cfg->command_groups_size;
1458
483f3ab1
EP		 1459 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1460 trans_pcie->ref_count = 1;
1461
f14d6b39
JB		 1462 /* Initialize NAPI here - it should be before registering to mac80211
1463 * in the opmode but after the HW struct is allocated.
1464 * As this function may be called again in some corner cases don't
1465 * do anything if NAPI was already initialized.
1466 */
1be5d8cc 1467 if (!trans_pcie->napi.poll) {
f14d6b39 1468 init_dummy_netdev(&trans_pcie->napi_dev);
1be5d8cc
JB		 1469 netif_napi_add(&trans_pcie->napi_dev, &trans_pcie->napi,
1470 iwl_pcie_dummy_napi_poll, 64);
f14d6b39 1471 }
c6f600fc
MV		 1472}
1473
d1ff5253 1474void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1475{
20d3b647 1476 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1477 int i;
a42a1844 1478
0aa86df6 1479 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1480
f02831be 1481 iwl_pcie_tx_free(trans);
9805c446 1482 iwl_pcie_rx_free(trans);
6379103e 1483
a8b691e6
JB		 1484 free_irq(trans_pcie->pci_dev->irq, trans);
1485 iwl_pcie_free_ict(trans);
a42a1844
EG		 1486
1487 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1488 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1489 pci_release_regions(trans_pcie->pci_dev);
1490 pci_disable_device(trans_pcie->pci_dev);
1491
f14d6b39
JB		 1492 if (trans_pcie->napi.poll)
1493 netif_napi_del(&trans_pcie->napi);
1494
c2d20201
EG		 1495 iwl_pcie_free_fw_monitor(trans);
1496
6eb5e529
EG		 1497 for_each_possible_cpu(i) {
1498 struct iwl_tso_hdr_page *p =
1499 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1500
1501 if (p->page)
1502 __free_page(p->page);
1503 }
1504
1505 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 1506 iwl_trans_free(trans);
34c1b7ba
EG		 1507}
1508
47107e84
DF		 1509static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1510{
47107e84 1511 if (state)
eb7ff77e 1512 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1513 else
eb7ff77e 1514 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1515}
1516
23ba9340
EG		 1517static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1518 unsigned long *flags)
7a65d170
EG		 1519{
1520 int ret;
cfb4e624
JB		 1521 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1522
1523 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1524
fc8a350d 1525 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1526 goto out;
1527
7a65d170 1528 /* this bit wakes up the NIC */
e139dc4a
LE		 1529 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1530 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1531 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1532 udelay(2);
7a65d170
EG		 1533
1534 /*
1535 * These bits say the device is running, and should keep running for
1536 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1537 * but they do not indicate that embedded SRAM is restored yet;
1538 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1539 * to/from host DRAM when sleeping/waking for power-saving.
1540 * Each direction takes approximately 1/4 millisecond; with this
1541 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1542 * series of register accesses are expected (e.g. reading Event Log),
1543 * to keep device from sleeping.
1544 *
1545 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1546 * SRAM is okay/restored. We don't check that here because this call
1547 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1548 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1549 *
1550 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1551 * and do not save/restore SRAM when power cycling.
1552 */
1553 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1554 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1555 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1556 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1557 if (unlikely(ret < 0)) {
1558 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1559 WARN_ONCE(1,
1560 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1561 iwl_read32(trans, CSR_GP_CNTRL));
1562 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1563 return false;
7a65d170
EG		 1564 }
1565
b9439491 1566out:
e56b04ef
LE		 1567 /*
1568 * Fool sparse by faking we release the lock - sparse will
1569 * track nic_access anyway.
1570 */
cfb4e624 1571 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1572 return true;
1573}
1574
e56b04ef
LE		 1575static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1576 unsigned long *flags)
7a65d170 1577{
cfb4e624 1578 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1579
cfb4e624 1580 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1581
1582 /*
1583 * Fool sparse by faking we acquiring the lock - sparse will
1584 * track nic_access anyway.
1585 */
cfb4e624 1586 __acquire(&trans_pcie->reg_lock);
e56b04ef 1587
fc8a350d 1588 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1589 goto out;
1590
e139dc4a
LE		 1591 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1592 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1593 /*
1594 * Above we read the CSR_GP_CNTRL register, which will flush
1595 * any previous writes, but we need the write that clears the
1596 * MAC_ACCESS_REQ bit to be performed before any other writes
1597 * scheduled on different CPUs (after we drop reg_lock).
1598 */
1599 mmiowb();
b9439491 1600out:
cfb4e624 1601 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1602}
1603
4fd442db
EG		 1604static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1605 void *buf, int dwords)
1606{
1607 unsigned long flags;
1608 int offs, ret = 0;
1609 u32 *vals = buf;
1610
23ba9340 1611 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1612 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1613 for (offs = 0; offs < dwords; offs++)
1614 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1615 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1616 } else {
1617 ret = -EBUSY;
1618 }
4fd442db
EG		 1619 return ret;
1620}
1621
1622static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1623 const void *buf, int dwords)
4fd442db
EG		 1624{
1625 unsigned long flags;
1626 int offs, ret = 0;
bf0fd5da 1627 const u32 *vals = buf;
4fd442db 1628
23ba9340 1629 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1630 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1631 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1632 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1633 vals ? vals[offs] : 0);
e56b04ef 1634 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1635 } else {
1636 ret = -EBUSY;
1637 }
4fd442db
EG		 1638 return ret;
1639}
7a65d170 1640
e0b8d405
EG		 1641static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1642 unsigned long txqs,
1643 bool freeze)
1644{
1645 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1646 int queue;
1647
1648 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1649 struct iwl_txq *txq = &trans_pcie->txq[queue];
1650 unsigned long now;
1651
1652 spin_lock_bh(&txq->lock);
1653
1654 now = jiffies;
1655
1656 if (txq->frozen == freeze)
1657 goto next_queue;
1658
1659 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1660 freeze ? "Freezing" : "Waking", queue);
1661
1662 txq->frozen = freeze;
1663
1664 if (txq->q.read_ptr == txq->q.write_ptr)
1665 goto next_queue;
1666
1667 if (freeze) {
1668 if (unlikely(time_after(now,
1669 txq->stuck_timer.expires))) {
1670 /*
1671 * The timer should have fired, maybe it is
1672 * spinning right now on the lock.
1673 */
1674 goto next_queue;
1675 }
1676 /* remember how long until the timer fires */
1677 txq->frozen_expiry_remainder =
1678 txq->stuck_timer.expires - now;
1679 del_timer(&txq->stuck_timer);
1680 goto next_queue;
1681 }
1682
1683 /*
1684 * Wake a non-empty queue -> arm timer with the
1685 * remainder before it froze
1686 */
1687 mod_timer(&txq->stuck_timer,
1688 now + txq->frozen_expiry_remainder);
1689
1690next_queue:
1691 spin_unlock_bh(&txq->lock);
1692 }
1693}
1694
0cd58eaa
EG		 1695static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1696{
1697 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1698 int i;
1699
1700 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1701 struct iwl_txq *txq = &trans_pcie->txq[i];
1702
1703 if (i == trans_pcie->cmd_queue)
1704 continue;
1705
1706 spin_lock_bh(&txq->lock);
1707
1708 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1709 txq->block--;
1710 if (!txq->block) {
1711 iwl_write32(trans, HBUS_TARG_WRPTR,
1712 txq->q.write_ptr | (i << 8));
1713 }
1714 } else if (block) {
1715 txq->block++;
1716 }
1717
1718 spin_unlock_bh(&txq->lock);
1719 }
1720}
1721
5f178cd2
EG		 1722#define IWL_FLUSH_WAIT_MS 2000
1723
3cafdbe6 1724static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1725{
8ad71bef 1726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1727 struct iwl_txq *txq;
5f178cd2
EG		 1728 struct iwl_queue *q;
1729 int cnt;
1730 unsigned long now = jiffies;
1c3fea82
EG		 1731 u32 scd_sram_addr;
1732 u8 buf[16];
5f178cd2
EG		 1733 int ret = 0;
1734
1735 /* waiting for all the tx frames complete might take a while */
035f7ff2 1736 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1737 u8 wr_ptr;
1738
9ba1947a 1739 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1740 continue;
3cafdbe6
EG		 1741 if (!test_bit(cnt, trans_pcie->queue_used))
1742 continue;
1743 if (!(BIT(cnt) & txq_bm))
1744 continue;
748fa67c
EG		 1745
1746 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1747 txq = &trans_pcie->txq[cnt];
5f178cd2 1748 q = &txq->q;
fa1a91fd
EG		 1749 wr_ptr = ACCESS_ONCE(q->write_ptr);
1750
1751 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1752 !time_after(jiffies,
1753 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1754 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1755
1756 if (WARN_ONCE(wr_ptr != write_ptr,
1757 "WR pointer moved while flushing %d -> %d\n",
1758 wr_ptr, write_ptr))
1759 return -ETIMEDOUT;
5f178cd2 1760 msleep(1);
fa1a91fd 1761 }
5f178cd2
EG		 1762
1763 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1764 IWL_ERR(trans,
1765 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1766 ret = -ETIMEDOUT;
1767 break;
1768 }
748fa67c 1769 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1770 }
1c3fea82
EG		 1771
1772 if (!ret)
1773 return 0;
1774
1775 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1776 txq->q.read_ptr, txq->q.write_ptr);
1777
1778 scd_sram_addr = trans_pcie->scd_base_addr +
1779 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1780 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1781
1782 iwl_print_hex_error(trans, buf, sizeof(buf));
1783
1784 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1785 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1786 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1787
1788 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1789 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1790 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1791 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1792 u32 tbl_dw =
1793 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1794 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1795
1796 if (cnt & 0x1)
1797 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1798 else
1799 tbl_dw = tbl_dw & 0x0000FFFF;
1800
1801 IWL_ERR(trans,
1802 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1803 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1804 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1805 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1806 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1807 }
1808
5f178cd2
EG		 1809 return ret;
1810}
1811
e139dc4a
LE		 1812static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1813 u32 mask, u32 value)
1814{
e56b04ef 1815 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1816 unsigned long flags;
1817
e56b04ef 1818 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1819 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1820 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1821}
1822
7616f334
EP		 1823void iwl_trans_pcie_ref(struct iwl_trans *trans)
1824{
1825 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1826 unsigned long flags;
1827
1828 if (iwlwifi_mod_params.d0i3_disable)
1829 return;
1830
1831 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1832 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1833 trans_pcie->ref_count++;
1834 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1835}
1836
1837void iwl_trans_pcie_unref(struct iwl_trans *trans)
1838{
1839 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1840 unsigned long flags;
1841
1842 if (iwlwifi_mod_params.d0i3_disable)
1843 return;
1844
1845 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1846 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1847 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1848 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1849 return;
1850 }
1851 trans_pcie->ref_count--;
1852 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1853}
1854
ff620849
EG		 1855static const char *get_csr_string(int cmd)
1856{
d9fb6465 1857#define IWL_CMD(x) case x: return #x
ff620849
EG		 1858 switch (cmd) {
1859 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1860 IWL_CMD(CSR_INT_COALESCING);
1861 IWL_CMD(CSR_INT);
1862 IWL_CMD(CSR_INT_MASK);
1863 IWL_CMD(CSR_FH_INT_STATUS);
1864 IWL_CMD(CSR_GPIO_IN);
1865 IWL_CMD(CSR_RESET);
1866 IWL_CMD(CSR_GP_CNTRL);
1867 IWL_CMD(CSR_HW_REV);
1868 IWL_CMD(CSR_EEPROM_REG);
1869 IWL_CMD(CSR_EEPROM_GP);
1870 IWL_CMD(CSR_OTP_GP_REG);
1871 IWL_CMD(CSR_GIO_REG);
1872 IWL_CMD(CSR_GP_UCODE_REG);
1873 IWL_CMD(CSR_GP_DRIVER_REG);
1874 IWL_CMD(CSR_UCODE_DRV_GP1);
1875 IWL_CMD(CSR_UCODE_DRV_GP2);
1876 IWL_CMD(CSR_LED_REG);
1877 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1878 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1879 IWL_CMD(CSR_ANA_PLL_CFG);
1880 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1881 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1882 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1883 default:
1884 return "UNKNOWN";
1885 }
d9fb6465 1886#undef IWL_CMD
ff620849
EG		 1887}
1888
990aa6d7 1889void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1890{
1891 int i;
1892 static const u32 csr_tbl[] = {
1893 CSR_HW_IF_CONFIG_REG,
1894 CSR_INT_COALESCING,
1895 CSR_INT,
1896 CSR_INT_MASK,
1897 CSR_FH_INT_STATUS,
1898 CSR_GPIO_IN,
1899 CSR_RESET,
1900 CSR_GP_CNTRL,
1901 CSR_HW_REV,
1902 CSR_EEPROM_REG,
1903 CSR_EEPROM_GP,
1904 CSR_OTP_GP_REG,
1905 CSR_GIO_REG,
1906 CSR_GP_UCODE_REG,
1907 CSR_GP_DRIVER_REG,
1908 CSR_UCODE_DRV_GP1,
1909 CSR_UCODE_DRV_GP2,
1910 CSR_LED_REG,
1911 CSR_DRAM_INT_TBL_REG,
1912 CSR_GIO_CHICKEN_BITS,
1913 CSR_ANA_PLL_CFG,
a812cba9 1914 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1915 CSR_HW_REV_WA_REG,
1916 CSR_DBG_HPET_MEM_REG
1917 };
1918 IWL_ERR(trans, "CSR values:\n");
1919 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1920 "CSR_INT_PERIODIC_REG)\n");
1921 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1922 IWL_ERR(trans, " %25s: 0X%08x\n",
1923 get_csr_string(csr_tbl[i]),
1042db2a 1924 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1925 }
1926}
1927
87e5666c
EG		 1928#ifdef CONFIG_IWLWIFI_DEBUGFS
1929/* create and remove of files */
1930#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1931 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1932 &iwl_dbgfs_##name##_ops)) \
9da987ac 1933 goto err; \
87e5666c
EG		 1934} while (0)
1935
1936/* file operation */
87e5666c 1937#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1938static const struct file_operations iwl_dbgfs_##name##_ops = { \
1939 .read = iwl_dbgfs_##name##_read, \
234e3405 1940 .open = simple_open, \
87e5666c
EG		 1941 .llseek = generic_file_llseek, \
1942};
1943
16db88ba 1944#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1945static const struct file_operations iwl_dbgfs_##name##_ops = { \
1946 .write = iwl_dbgfs_##name##_write, \
234e3405 1947 .open = simple_open, \
16db88ba
EG		 1948 .llseek = generic_file_llseek, \
1949};
1950
87e5666c 1951#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1952static const struct file_operations iwl_dbgfs_##name##_ops = { \
1953 .write = iwl_dbgfs_##name##_write, \
1954 .read = iwl_dbgfs_##name##_read, \
234e3405 1955 .open = simple_open, \
87e5666c
EG		 1956 .llseek = generic_file_llseek, \
1957};
1958
87e5666c 1959static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1960 char __user *user_buf,
1961 size_t count, loff_t *ppos)
8ad71bef 1962{
5a878bf6 1963 struct iwl_trans *trans = file->private_data;
8ad71bef 1964 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1965 struct iwl_txq *txq;
87e5666c
EG		 1966 struct iwl_queue *q;
1967 char *buf;
1968 int pos = 0;
1969 int cnt;
1970 int ret;
1745e440
WYG		 1971 size_t bufsz;
1972
e0b8d405 1973 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 1974
f9e75447 1975 if (!trans_pcie->txq)
87e5666c 1976 return -EAGAIN;
f9e75447 1977
87e5666c
EG		 1978 buf = kzalloc(bufsz, GFP_KERNEL);
1979 if (!buf)
1980 return -ENOMEM;
1981
035f7ff2 1982 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1983 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1984 q = &txq->q;
1985 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 1986 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 1987 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1988 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 1989 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 1990 txq->need_update, txq->frozen,
f40faf62 1991 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1992 }
1993 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1994 kfree(buf);
1995 return ret;
1996}
1997
1998static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1999 char __user *user_buf,
2000 size_t count, loff_t *ppos)
2001{
5a878bf6 2002 struct iwl_trans *trans = file->private_data;
20d3b647 2003 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2004 char *buf;
2005 int pos = 0, i, ret;
2006 size_t bufsz = sizeof(buf);
2007
2008 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2009
2010 if (!trans_pcie->rxq)
2011 return -EAGAIN;
2012
2013 buf = kzalloc(bufsz, GFP_KERNEL);
2014 if (!buf)
2015 return -ENOMEM;
2016
2017 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2018 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2019
2020 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2021 i);
2022 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2023 rxq->read);
2024 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2025 rxq->write);
2026 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2027 rxq->write_actual);
2028 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2029 rxq->need_update);
2030 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2031 rxq->free_count);
2032 if (rxq->rb_stts) {
2033 pos += scnprintf(buf + pos, bufsz - pos,
2034 "\tclosed_rb_num: %u\n",
2035 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2036 0x0FFF);
2037 } else {
2038 pos += scnprintf(buf + pos, bufsz - pos,
2039 "\tclosed_rb_num: Not Allocated\n");
2040 }
87e5666c 2041 }
78485054
SS		 2042 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2043 kfree(buf);
2044
2045 return ret;
87e5666c
EG		 2046}
2047
1f7b6172
EG		 2048static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2049 char __user *user_buf,
20d3b647
JB		 2050 size_t count, loff_t *ppos)
2051{
1f7b6172 2052 struct iwl_trans *trans = file->private_data;
20d3b647 2053 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2054 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2055
2056 int pos = 0;
2057 char *buf;
2058 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2059 ssize_t ret;
2060
2061 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2062 if (!buf)
1f7b6172 2063 return -ENOMEM;
1f7b6172
EG		 2064
2065 pos += scnprintf(buf + pos, bufsz - pos,
2066 "Interrupt Statistics Report:\n");
2067
2068 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2069 isr_stats->hw);
2070 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2071 isr_stats->sw);
2072 if (isr_stats->sw || isr_stats->hw) {
2073 pos += scnprintf(buf + pos, bufsz - pos,
2074 "\tLast Restarting Code: 0x%X\n",
2075 isr_stats->err_code);
2076 }
2077#ifdef CONFIG_IWLWIFI_DEBUG
2078 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2079 isr_stats->sch);
2080 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2081 isr_stats->alive);
2082#endif
2083 pos += scnprintf(buf + pos, bufsz - pos,
2084 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2085
2086 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2087 isr_stats->ctkill);
2088
2089 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2090 isr_stats->wakeup);
2091
2092 pos += scnprintf(buf + pos, bufsz - pos,
2093 "Rx command responses:\t\t %u\n", isr_stats->rx);
2094
2095 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2096 isr_stats->tx);
2097
2098 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2099 isr_stats->unhandled);
2100
2101 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2102 kfree(buf);
2103 return ret;
2104}
2105
2106static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2107 const char __user *user_buf,
2108 size_t count, loff_t *ppos)
2109{
2110 struct iwl_trans *trans = file->private_data;
20d3b647 2111 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2112 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2113
2114 char buf[8];
2115 int buf_size;
2116 u32 reset_flag;
2117
2118 memset(buf, 0, sizeof(buf));
2119 buf_size = min(count, sizeof(buf) - 1);
2120 if (copy_from_user(buf, user_buf, buf_size))
2121 return -EFAULT;
2122 if (sscanf(buf, "%x", &reset_flag) != 1)
2123 return -EFAULT;
2124 if (reset_flag == 0)
2125 memset(isr_stats, 0, sizeof(*isr_stats));
2126
2127 return count;
2128}
2129
16db88ba 2130static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2131 const char __user *user_buf,
2132 size_t count, loff_t *ppos)
16db88ba
EG		 2133{
2134 struct iwl_trans *trans = file->private_data;
2135 char buf[8];
2136 int buf_size;
2137 int csr;
2138
2139 memset(buf, 0, sizeof(buf));
2140 buf_size = min(count, sizeof(buf) - 1);
2141 if (copy_from_user(buf, user_buf, buf_size))
2142 return -EFAULT;
2143 if (sscanf(buf, "%d", &csr) != 1)
2144 return -EFAULT;
2145
990aa6d7 2146 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2147
2148 return count;
2149}
2150
16db88ba 2151static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2152 char __user *user_buf,
2153 size_t count, loff_t *ppos)
16db88ba
EG		 2154{
2155 struct iwl_trans *trans = file->private_data;
94543a8d 2156 char *buf = NULL;
56c2477f 2157 ssize_t ret;
16db88ba 2158
56c2477f
JB		 2159 ret = iwl_dump_fh(trans, &buf);
2160 if (ret < 0)
2161 return ret;
2162 if (!buf)
2163 return -EINVAL;
2164 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2165 kfree(buf);
16db88ba
EG		 2166 return ret;
2167}
2168
1f7b6172 2169DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2170DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2171DEBUGFS_READ_FILE_OPS(rx_queue);
2172DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2173DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c 2174
f8a1edb7
JB		 2175/* Create the debugfs files and directories */
2176int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2177{
f8a1edb7
JB		 2178 struct dentry *dir = trans->dbgfs_dir;
2179
87e5666c
EG		 2180 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2181 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2182 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2183 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2184 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2185 return 0;
9da987ac
MV		 2186
2187err:
2188 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2189 return -ENOMEM;
87e5666c 2190}
aadede6e 2191#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2192
2193static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2194{
2195 u32 cmdlen = 0;
2196 int i;
2197
2198 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2199 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2200
2201 return cmdlen;
2202}
2203
bd7fc617
EG		 2204static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2205 struct iwl_fw_error_dump_data **data,
2206 int allocated_rb_nums)
2207{
2208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2209 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2210 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2211 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2212 u32 i, r, j, rb_len = 0;
2213
2214 spin_lock(&rxq->lock);
2215
2216 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2217
2218 for (i = rxq->read, j = 0;
2219 i != r && j < allocated_rb_nums;
2220 i = (i + 1) & RX_QUEUE_MASK, j++) {
2221 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2222 struct iwl_fw_error_dump_rb *rb;
2223
2224 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2225 DMA_FROM_DEVICE);
2226
2227 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2228
2229 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2230 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2231 rb = (void *)(*data)->data;
2232 rb->index = cpu_to_le32(i);
2233 memcpy(rb->data, page_address(rxb->page), max_len);
2234 /* remap the page for the free benefit */
2235 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2236 max_len,
2237 DMA_FROM_DEVICE);
2238
2239 *data = iwl_fw_error_next_data(*data);
2240 }
2241
2242 spin_unlock(&rxq->lock);
2243
2244 return rb_len;
2245}
473ad712
EG		 2246#define IWL_CSR_TO_DUMP (0x250)
2247
2248static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2249 struct iwl_fw_error_dump_data **data)
2250{
2251 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2252 __le32 *val;
2253 int i;
2254
2255 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2256 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2257 val = (void *)(*data)->data;
2258
2259 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2260 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2261
2262 *data = iwl_fw_error_next_data(*data);
2263
2264 return csr_len;
2265}
2266
06d51e0d
LK		 2267static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2268 struct iwl_fw_error_dump_data **data)
2269{
2270 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2271 unsigned long flags;
2272 __le32 *val;
2273 int i;
2274
23ba9340 2275 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2276 return 0;
2277
2278 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2279 (*data)->len = cpu_to_le32(fh_regs_len);
2280 val = (void *)(*data)->data;
2281
2282 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2283 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2284
2285 iwl_trans_release_nic_access(trans, &flags);
2286
2287 *data = iwl_fw_error_next_data(*data);
2288
2289 return sizeof(**data) + fh_regs_len;
2290}
2291
cc79ef66
LK		 2292static u32
2293iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2294 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2295 u32 monitor_len)
2296{
2297 u32 buf_size_in_dwords = (monitor_len >> 2);
2298 u32 *buffer = (u32 *)fw_mon_data->data;
2299 unsigned long flags;
2300 u32 i;
2301
23ba9340 2302 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2303 return 0;
2304
14ef1b43 2305 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2306 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2307 buffer[i] = iwl_read_prph_no_grab(trans,
2308 MON_DMARB_RD_DATA_ADDR);
2309 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2310
2311 iwl_trans_release_nic_access(trans, &flags);
2312
2313 return monitor_len;
2314}
2315
36fb9017
OG		 2316static u32
2317iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2318 struct iwl_fw_error_dump_data **data,
2319 u32 monitor_len)
2320{
2321 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2322 u32 len = 0;
2323
2324 if ((trans_pcie->fw_mon_page &&
2325 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2326 trans->dbg_dest_tlv) {
2327 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2328 u32 base, write_ptr, wrap_cnt;
2329
2330 /* If there was a dest TLV - use the values from there */
2331 if (trans->dbg_dest_tlv) {
2332 write_ptr =
2333 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2334 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2335 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2336 } else {
2337 base = MON_BUFF_BASE_ADDR;
2338 write_ptr = MON_BUFF_WRPTR;
2339 wrap_cnt = MON_BUFF_CYCLE_CNT;
2340 }
2341
2342 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2343 fw_mon_data = (void *)(*data)->data;
2344 fw_mon_data->fw_mon_wr_ptr =
2345 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2346 fw_mon_data->fw_mon_cycle_cnt =
2347 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2348 fw_mon_data->fw_mon_base_ptr =
2349 cpu_to_le32(iwl_read_prph(trans, base));
2350
2351 len += sizeof(**data) + sizeof(*fw_mon_data);
2352 if (trans_pcie->fw_mon_page) {
2353 /*
2354 * The firmware is now asserted, it won't write anything
2355 * to the buffer. CPU can take ownership to fetch the
2356 * data. The buffer will be handed back to the device
2357 * before the firmware will be restarted.
2358 */
2359 dma_sync_single_for_cpu(trans->dev,
2360 trans_pcie->fw_mon_phys,
2361 trans_pcie->fw_mon_size,
2362 DMA_FROM_DEVICE);
2363 memcpy(fw_mon_data->data,
2364 page_address(trans_pcie->fw_mon_page),
2365 trans_pcie->fw_mon_size);
2366
2367 monitor_len = trans_pcie->fw_mon_size;
2368 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2369 /*
2370 * Update pointers to reflect actual values after
2371 * shifting
2372 */
2373 base = iwl_read_prph(trans, base) <<
2374 trans->dbg_dest_tlv->base_shift;
2375 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2376 monitor_len / sizeof(u32));
2377 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2378 monitor_len =
2379 iwl_trans_pci_dump_marbh_monitor(trans,
2380 fw_mon_data,
2381 monitor_len);
2382 } else {
2383 /* Didn't match anything - output no monitor data */
2384 monitor_len = 0;
2385 }
2386
2387 len += monitor_len;
2388 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2389 }
2390
2391 return len;
2392}
2393
2394static struct iwl_trans_dump_data
2395*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2396 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2397{
2398 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2399 struct iwl_fw_error_dump_data *data;
2400 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2401 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2402 struct iwl_trans_dump_data *dump_data;
bd7fc617 2403 u32 len, num_rbs;
99684ae3 2404 u32 monitor_len;
4d075007 2405 int i, ptr;
bd7fc617 2406 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status);
4d075007 2407
473ad712
EG		 2408 /* transport dump header */
2409 len = sizeof(*dump_data);
2410
2411 /* host commands */
2412 len += sizeof(*data) +
c2d20201
EG		 2413 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2414
473ad712 2415 /* FW monitor */
99684ae3 2416 if (trans_pcie->fw_mon_page) {
c544e9c4 2417 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2418 trans_pcie->fw_mon_size;
2419 monitor_len = trans_pcie->fw_mon_size;
2420 } else if (trans->dbg_dest_tlv) {
2421 u32 base, end;
2422
2423 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2424 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2425
2426 base = iwl_read_prph(trans, base) <<
2427 trans->dbg_dest_tlv->base_shift;
2428 end = iwl_read_prph(trans, end) <<
2429 trans->dbg_dest_tlv->end_shift;
2430
2431 /* Make "end" point to the actual end */
cc79ef66
LK		 2432 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2433 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2434 end += (1 << trans->dbg_dest_tlv->end_shift);
2435 monitor_len = end - base;
2436 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2437 monitor_len;
2438 } else {
2439 monitor_len = 0;
2440 }
c2d20201 2441
36fb9017
OG		 2442 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2443 dump_data = vzalloc(len);
2444 if (!dump_data)
2445 return NULL;
2446
2447 data = (void *)dump_data->data;
2448 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2449 dump_data->len = len;
2450
2451 return dump_data;
2452 }
2453
2454 /* CSR registers */
2455 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2456
36fb9017
OG		 2457 /* FH registers */
2458 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2459
2460 if (dump_rbs) {
78485054
SS		 2461 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2462 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2463 /* RBs */
78485054 2464 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2465 & 0x0FFF;
78485054 2466 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2467 len += num_rbs * (sizeof(*data) +
2468 sizeof(struct iwl_fw_error_dump_rb) +
2469 (PAGE_SIZE << trans_pcie->rx_page_order));
2470 }
2471
48eb7b34
EG		 2472 dump_data = vzalloc(len);
2473 if (!dump_data)
2474 return NULL;
4d075007
JB		 2475
2476 len = 0;
48eb7b34 2477 data = (void *)dump_data->data;
4d075007
JB		 2478 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2479 txcmd = (void *)data->data;
2480 spin_lock_bh(&cmdq->lock);
2481 ptr = cmdq->q.write_ptr;
2482 for (i = 0; i < cmdq->q.n_window; i++) {
2483 u8 idx = get_cmd_index(&cmdq->q, ptr);
2484 u32 caplen, cmdlen;
2485
2486 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2487 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2488
2489 if (cmdlen) {
2490 len += sizeof(*txcmd) + caplen;
2491 txcmd->cmdlen = cpu_to_le32(cmdlen);
2492 txcmd->caplen = cpu_to_le32(caplen);
2493 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2494 txcmd = (void *)((u8 *)txcmd->data + caplen);
2495 }
2496
2497 ptr = iwl_queue_dec_wrap(ptr);
2498 }
2499 spin_unlock_bh(&cmdq->lock);
2500
2501 data->len = cpu_to_le32(len);
c2d20201 2502 len += sizeof(*data);
67c65f2c
EG		 2503 data = iwl_fw_error_next_data(data);
2504
473ad712 2505 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2506 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2507 if (dump_rbs)
2508 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2509
36fb9017 2510 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2511
48eb7b34
EG		 2512 dump_data->len = len;
2513
2514 return dump_data;
4d075007 2515}
87e5666c 2516
d1ff5253 2517static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2518 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2519 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2520 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2521 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2522 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2523
ddaf5a5b
JB		 2524 .d3_suspend = iwl_trans_pcie_d3_suspend,
2525 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2526
f02831be 2527 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2528
e6bb4c9c 2529 .tx = iwl_trans_pcie_tx,
a0eaad71 2530 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2531
d0624be6 2532 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2533 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2534
990aa6d7 2535 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2536 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
0cd58eaa 2537 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
5f178cd2 2538
03905495
EG		 2539 .write8 = iwl_trans_pcie_write8,
2540 .write32 = iwl_trans_pcie_write32,
2541 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2542 .read_prph = iwl_trans_pcie_read_prph,
2543 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2544 .read_mem = iwl_trans_pcie_read_mem,
2545 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2546 .configure = iwl_trans_pcie_configure,
47107e84 2547 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2548 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2549 .release_nic_access = iwl_trans_pcie_release_nic_access,
2550 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2551
7616f334
EP		 2552 .ref = iwl_trans_pcie_ref,
2553 .unref = iwl_trans_pcie_unref,
2554
4d075007 2555 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2556};
a42a1844 2557
87ce05a2 2558struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2559 const struct pci_device_id *ent,
2560 const struct iwl_cfg *cfg)
a42a1844 2561{
a42a1844
EG		 2562 struct iwl_trans_pcie *trans_pcie;
2563 struct iwl_trans *trans;
2564 u16 pci_cmd;
af3f2f74 2565 int ret;
a42a1844 2566
7b501d10
JB		 2567 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2568 &pdev->dev, cfg, &trans_ops_pcie, 0);
2569 if (!trans)
2570 return ERR_PTR(-ENOMEM);
a42a1844 2571
206eea78
JB		 2572 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2573
a42a1844
EG		 2574 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2575
a42a1844 2576 trans_pcie->trans = trans;
7b11488f 2577 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2578 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2579 spin_lock_init(&trans_pcie->ref_lock);
fa9f3281 2580 mutex_init(&trans_pcie->mutex);
13df1aab 2581 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 2582 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2583 if (!trans_pcie->tso_hdr_page) {
2584 ret = -ENOMEM;
2585 goto out_no_pci;
2586 }
a42a1844 2587
af3f2f74
EG		 2588 ret = pci_enable_device(pdev);
2589 if (ret)
d819c6cf
JB		 2590 goto out_no_pci;
2591
f2532b04
EG		 2592 if (!cfg->base_params->pcie_l1_allowed) {
2593 /*
2594 * W/A - seems to solve weird behavior. We need to remove this
2595 * if we don't want to stay in L1 all the time. This wastes a
2596 * lot of power.
2597 */
2598 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2599 PCIE_LINK_STATE_L1 |
2600 PCIE_LINK_STATE_CLKPM);
2601 }
a42a1844 2602
a42a1844
EG		 2603 pci_set_master(pdev);
2604
af3f2f74
EG		 2605 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2606 if (!ret)
2607 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2608 if (ret) {
2609 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2610 if (!ret)
2611 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2612 DMA_BIT_MASK(32));
a42a1844 2613 /* both attempts failed: */
af3f2f74 2614 if (ret) {
6a4b09f8 2615 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2616 goto out_pci_disable_device;
2617 }
2618 }
2619
af3f2f74
EG		 2620 ret = pci_request_regions(pdev, DRV_NAME);
2621 if (ret) {
6a4b09f8 2622 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2623 goto out_pci_disable_device;
2624 }
2625
05f5b97e 2626 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2627 if (!trans_pcie->hw_base) {
6a4b09f8 2628 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
af3f2f74 2629 ret = -ENODEV;
a42a1844
EG		 2630 goto out_pci_release_regions;
2631 }
2632
a42a1844
EG		 2633 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2634 * PCI Tx retries from interfering with C3 CPU state */
2635 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2636
83f7a85f
EG		 2637 trans->dev = &pdev->dev;
2638 trans_pcie->pci_dev = pdev;
2639 iwl_disable_interrupts(trans);
2640
af3f2f74
EG		 2641 ret = pci_enable_msi(pdev);
2642 if (ret) {
2643 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
9f904b38
EG		 2644 /* enable rfkill interrupt: hw bug w/a */
2645 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2646 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2647 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2648 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2649 }
2650 }
a42a1844 2651
08079a49 2652 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2653 /*
2654 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2655 * changed, and now the revision step also includes bit 0-1 (no more
2656 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2657 * in the old format.
2658 */
7a42baa6
EH		 2659 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2660 unsigned long flags;
7a42baa6 2661
b513ee7f 2662 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2663 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2664
f9e5554c
EG		 2665 ret = iwl_pcie_prepare_card_hw(trans);
2666 if (ret) {
2667 IWL_WARN(trans, "Exit HW not ready\n");
2668 goto out_pci_disable_msi;
2669 }
2670
7a42baa6
EH		 2671 /*
2672 * in-order to recognize C step driver should read chip version
2673 * id located at the AUX bus MISC address space.
2674 */
2675 iwl_set_bit(trans, CSR_GP_CNTRL,
2676 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2677 udelay(2);
2678
2679 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2680 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2681 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2682 25000);
2683 if (ret < 0) {
2684 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2685 goto out_pci_disable_msi;
2686 }
2687
23ba9340 2688 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 2689 u32 hw_step;
2690
14ef1b43 2691 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 2692 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 2693 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2694 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 2695 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2696 if (hw_step == 0x3)
2697 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2698 (SILICON_C_STEP << 2);
2699 iwl_trans_release_nic_access(trans, &flags);
2700 }
2701 }
2702
99673ee5 2703 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2704 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2705 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2706
69a10b29 2707 /* Initialize the wait queue for commands */
f946b529 2708 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2709
af3f2f74
EG		 2710 ret = iwl_pcie_alloc_ict(trans);
2711 if (ret)
7b501d10 2712 goto out_pci_disable_msi;
a8b691e6 2713
af3f2f74 2714 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2715 iwl_pcie_irq_handler,
2716 IRQF_SHARED, DRV_NAME, trans);
af3f2f74 2717 if (ret) {
a8b691e6
JB		 2718 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2719 goto out_free_ict;
2720 }
2721
83f7a85f
EG		 2722 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2723
a42a1844
EG		 2724 return trans;
2725
a8b691e6
JB		 2726out_free_ict:
2727 iwl_pcie_free_ict(trans);
59c647b6
EG		 2728out_pci_disable_msi:
2729 pci_disable_msi(pdev);
a42a1844
EG		 2730out_pci_release_regions:
2731 pci_release_regions(pdev);
2732out_pci_disable_device:
2733 pci_disable_device(pdev);
2734out_no_pci:
6eb5e529 2735 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 2736 iwl_trans_free(trans);
af3f2f74 2737 return ERR_PTR(ret);
a42a1844 2738}
Linux kernel - Deliverables
This page took 0.535301 seconds and 5 git commands to generate.