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iwlwifi: nvm: fix up phy section when reading it
[deliverable/linux.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
553452e5
LK		 34 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
cb6bb128 78#include "iwl-scd.h"
7a10e3e4 79#include "iwl-agn-hw.h"
4d075007 80#include "iwl-fw-error-dump.h"
6468a01a 81#include "internal.h"
06d51e0d 82#include "iwl-fh.h"
0439bb62 83
fe45773b
AN		 84/* extended range in FW SRAM */
85#define IWL_FW_MEM_EXTENDED_START 0x40000
86#define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
c2d20201
EG		 88static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89{
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102}
103
96c285da 104static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 105{
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 107 struct page *page = NULL;
c2d20201 108 dma_addr_t phys;
96c285da 109 u32 size = 0;
c2d20201
EG		 110 u8 power;
111
96c285da
EG		 112 if (!max_power) {
113 /* default max_power is maximum */
114 max_power = 26;
115 } else {
116 max_power += 11;
117 }
118
119 if (WARN(max_power > 26,
120 "External buffer size for monitor is too big %d, check the FW TLV\n",
121 max_power))
122 return;
123
c2d20201
EG		 124 if (trans_pcie->fw_mon_page) {
125 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
126 trans_pcie->fw_mon_size,
127 DMA_FROM_DEVICE);
128 return;
129 }
130
131 phys = 0;
96c285da 132 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 133 int order;
134
135 size = BIT(power);
136 order = get_order(size);
137 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
138 order);
139 if (!page)
140 continue;
141
142 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
143 DMA_FROM_DEVICE);
144 if (dma_mapping_error(trans->dev, phys)) {
145 __free_pages(page, order);
553452e5 146 page = NULL;
c2d20201
EG		 147 continue;
148 }
149 IWL_INFO(trans,
150 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
151 size, order);
152 break;
153 }
154
40a76905 155 if (WARN_ON_ONCE(!page))
c2d20201
EG		 156 return;
157
96c285da
EG		 158 if (power != max_power)
159 IWL_ERR(trans,
160 "Sorry - debug buffer is only %luK while you requested %luK\n",
161 (unsigned long)BIT(power - 10),
162 (unsigned long)BIT(max_power - 10));
163
c2d20201
EG		 164 trans_pcie->fw_mon_page = page;
165 trans_pcie->fw_mon_phys = phys;
166 trans_pcie->fw_mon_size = size;
167}
168
a812cba9
AB		 169static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
170{
171 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
172 ((reg & 0x0000ffff) | (2 << 28)));
173 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
174}
175
176static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
177{
178 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
179 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
180 ((reg & 0x0000ffff) | (3 << 28)));
181}
182
ddaf5a5b 183static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 184{
66337b7c 185 if (trans->cfg->apmg_not_supported)
95411d04
AA		 186 return;
187
ddaf5a5b
JB		 188 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
189 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
190 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
191 ~APMG_PS_CTRL_MSK_PWR_SRC);
192 else
193 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
194 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
195 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 196}
197
af634bee
EG		 198/* PCI registers */
199#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 200
7afe3705 201static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 202{
20d3b647 203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 204 u16 lctl;
9180ac50 205 u16 cap;
af634bee 206
af634bee
EG		 207 /*
208 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
209 * Check if BIOS (or OS) enabled L1-ASPM on this device.
210 * If so (likely), disable L0S, so device moves directly L0->L1;
211 * costs negligible amount of power savings.
212 * If not (unlikely), enable L0S, so there is at least some
213 * power savings, even without L1.
214 */
7afe3705 215 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 216 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 217 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 218 else
af634bee 219 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 220 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 221
222 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
223 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
224 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
225 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
226 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 227}
228
a6c684ee
EG		 229/*
230 * Start up NIC's basic functionality after it has been reset
7afe3705 231 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 232 * NOTE: This does not load uCode nor start the embedded processor
233 */
7afe3705 234static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 235{
236 int ret = 0;
237 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
238
239 /*
240 * Use "set_bit" below rather than "write", to preserve any hardware
241 * bits already set by default after reset.
242 */
243
244 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 245 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
246 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
247 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 248
249 /*
250 * Disable L0s without affecting L1;
251 * don't wait for ICH L0s (ICH bug W/A)
252 */
253 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 254 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 255
256 /* Set FH wait threshold to maximum (HW error during stress W/A) */
257 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
258
259 /*
260 * Enable HAP INTA (interrupt from management bus) to
261 * wake device's PCI Express link L1a -> L0s
262 */
263 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 264 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 265
7afe3705 266 iwl_pcie_apm_config(trans);
a6c684ee
EG		 267
268 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 269 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 270 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 271 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 272
273 /*
274 * Set "initialization complete" bit to move adapter from
275 * D0U* --> D0A* (powered-up active) state.
276 */
277 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
278
279 /*
280 * Wait for clock stabilization; once stabilized, access to
281 * device-internal resources is supported, e.g. iwl_write_prph()
282 * and accesses to uCode SRAM.
283 */
284 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 285 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
286 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 287 if (ret < 0) {
288 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
289 goto out;
290 }
291
2d93aee1
EG		 292 if (trans->cfg->host_interrupt_operation_mode) {
293 /*
294 * This is a bit of an abuse - This is needed for 7260 / 3160
295 * only check host_interrupt_operation_mode even if this is
296 * not related to host_interrupt_operation_mode.
297 *
298 * Enable the oscillator to count wake up time for L1 exit. This
299 * consumes slightly more power (100uA) - but allows to be sure
300 * that we wake up from L1 on time.
301 *
302 * This looks weird: read twice the same register, discard the
303 * value, set a bit, and yet again, read that same register
304 * just to discard the value. But that's the way the hardware
305 * seems to like it.
306 */
307 iwl_read_prph(trans, OSC_CLK);
308 iwl_read_prph(trans, OSC_CLK);
309 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 }
313
a6c684ee
EG		 314 /*
315 * Enable DMA clock and wait for it to stabilize.
316 *
3073d8c0
EH		 317 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
318 * bits do not disable clocks. This preserves any hardware
319 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 320 */
95411d04 321 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 322 iwl_write_prph(trans, APMG_CLK_EN_REG,
323 APMG_CLK_VAL_DMA_CLK_RQT);
324 udelay(20);
325
326 /* Disable L1-Active */
327 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
328 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
329
330 /* Clear the interrupt in APMG if the NIC is in RFKILL */
331 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
332 APMG_RTC_INT_STT_RFKILL);
333 }
889b1696 334
eb7ff77e 335 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 336
337out:
338 return ret;
339}
340
a812cba9
AB		 341/*
342 * Enable LP XTAL to avoid HW bug where device may consume much power if
343 * FW is not loaded after device reset. LP XTAL is disabled by default
344 * after device HW reset. Do it only if XTAL is fed by internal source.
345 * Configure device's "persistence" mode to avoid resetting XTAL again when
346 * SHRD_HW_RST occurs in S3.
347 */
348static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
349{
350 int ret;
351 u32 apmg_gp1_reg;
352 u32 apmg_xtal_cfg_reg;
353 u32 dl_cfg_reg;
354
355 /* Force XTAL ON */
356 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
357 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
358
359 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
360 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
361
362 udelay(10);
363
364 /*
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
367 */
368 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
369
370 /*
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is possible.
373 */
374 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 25000);
378 if (WARN_ON(ret < 0)) {
379 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
380 /* Release XTAL ON request */
381 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383 return;
384 }
385
386 /*
387 * Clear "disable persistence" to avoid LP XTAL resetting when
388 * SHRD_HW_RST is applied in S3.
389 */
390 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
391 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
392
393 /*
394 * Force APMG XTAL to be active to prevent its disabling by HW
395 * caused by APMG idle state.
396 */
397 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
398 SHR_APMG_XTAL_CFG_REG);
399 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
400 apmg_xtal_cfg_reg |
401 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
402
403 /*
404 * Reset entire device again - do controller reset (results in
405 * SHRD_HW_RST). Turn MAC off before proceeding.
406 */
407 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
408
409 udelay(10);
410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
7afe3705 451static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
b7aaeae4 469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
b7aaeae4
EG		 473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
c9fdec9f
EG		 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
483 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PREPARE |
486 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 487 mdelay(1);
488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
489 CSR_RESET_LINK_PWR_MGMT_DISABLED);
490 }
b7aaeae4
EG		 491 mdelay(5);
492 }
493
eb7ff77e 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 495
496 /* Stop device's DMA activity */
7afe3705 497 iwl_pcie_apm_stop_master(trans);
cc56feb2 498
a812cba9
AB		 499 if (trans->cfg->lp_xtal_workaround) {
500 iwl_pcie_apm_lp_xtal_enable(trans);
501 return;
502 }
503
cc56feb2
EG		 504 /* Reset the entire device */
505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
506
507 udelay(10);
508
509 /*
510 * Clear "initialization complete" bit to move adapter from
511 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
512 */
513 iwl_clear_bit(trans, CSR_GP_CNTRL,
514 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
515}
516
7afe3705 517static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 518{
7b11488f 519 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 520
521 /* nic_init */
7b70bd63 522 spin_lock(&trans_pcie->irq_lock);
7afe3705 523 iwl_pcie_apm_init(trans);
392f8b78 524
7b70bd63 525 spin_unlock(&trans_pcie->irq_lock);
392f8b78 526
95411d04 527 iwl_pcie_set_pwr(trans, false);
392f8b78 528
ecdb975c 529 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 530
531 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 532 iwl_pcie_rx_init(trans);
392f8b78
EG		 533
534 /* Allocate or reset and init all Tx and Command queues */
f02831be 535 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 536 return -ENOMEM;
537
035f7ff2 538 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 539 /* enable shadow regs in HW */
20d3b647 540 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 541 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 542 }
543
392f8b78
EG		 544 return 0;
545}
546
547#define HW_READY_TIMEOUT (50)
548
549/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 550static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 551{
552 int ret;
553
1042db2a 554 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 555 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 556
557 /* See if we got it */
1042db2a 558 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
560 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
561 HW_READY_TIMEOUT);
392f8b78 562
6a08f514
EG		 563 if (ret >= 0)
564 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
565
6d8f6eeb 566 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 567 return ret;
568}
569
570/* Note: returns standard 0/-ERROR code */
7afe3705 571static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 572{
573 int ret;
289e5501 574 int t = 0;
501fd989 575 int iter;
392f8b78 576
6d8f6eeb 577 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 578
7afe3705 579 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 580 /* If the card is ready, exit 0 */
392f8b78
EG		 581 if (ret >= 0)
582 return 0;
583
c9fdec9f
EG		 584 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
585 CSR_RESET_LINK_PWR_MGMT_DISABLED);
586 msleep(1);
587
501fd989
EG		 588 for (iter = 0; iter < 10; iter++) {
589 /* If HW is not ready, prepare the conditions to check again */
590 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
591 CSR_HW_IF_CONFIG_REG_PREPARE);
592
593 do {
594 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 595 if (ret >= 0)
596 return 0;
392f8b78 597
501fd989
EG		 598 usleep_range(200, 1000);
599 t += 200;
600 } while (t < 150000);
601 msleep(25);
602 }
392f8b78 603
7f2ac8fb 604 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 605
392f8b78
EG		 606 return ret;
607}
608
cf614297
EG		 609/*
610 * ucode
611 */
7afe3705 612static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 613 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 614{
13df1aab 615 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 616 int ret;
617
13df1aab 618 trans_pcie->ucode_write_complete = false;
cf614297
EG		 619
620 iwl_write_direct32(trans,
20d3b647
JB		 621 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
622 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 623
624 iwl_write_direct32(trans,
20d3b647
JB		 625 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
626 dst_addr);
cf614297
EG		 627
628 iwl_write_direct32(trans,
83f84d7b
JB		 629 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
630 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 631
632 iwl_write_direct32(trans,
20d3b647
JB		 633 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
634 (iwl_get_dma_hi_addr(phy_addr)
635 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 636
637 iwl_write_direct32(trans,
20d3b647
JB		 638 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
639 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
640 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
641 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 642
643 iwl_write_direct32(trans,
20d3b647
JB		 644 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
645 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
646 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
647 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 648
13df1aab
JB		 649 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
650 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 651 if (!ret) {
83f84d7b 652 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 653 return -ETIMEDOUT;
654 }
655
656 return 0;
657}
658
7afe3705 659static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 660 const struct fw_desc *section)
cf614297 661{
83f84d7b
JB		 662 u8 *v_addr;
663 dma_addr_t p_addr;
baa21e83 664 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 665 int ret = 0;
666
83f84d7b
JB		 667 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
668 section_num);
669
c571573a
EG		 670 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
671 GFP_KERNEL | __GFP_NOWARN);
672 if (!v_addr) {
673 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
674 chunk_sz = PAGE_SIZE;
675 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
676 &p_addr, GFP_KERNEL);
677 if (!v_addr)
678 return -ENOMEM;
679 }
83f84d7b 680
c571573a 681 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 682 u32 copy_size, dst_addr;
683 bool extended_addr = false;
83f84d7b 684
c571573a 685 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 686 dst_addr = section->offset + offset;
687
688 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
689 dst_addr <= IWL_FW_MEM_EXTENDED_END)
690 extended_addr = true;
691
692 if (extended_addr)
693 iwl_set_bits_prph(trans, LMPM_CHICK,
694 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 695
83f84d7b 696 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 697 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
698 copy_size);
699
700 if (extended_addr)
701 iwl_clear_bits_prph(trans, LMPM_CHICK,
702 LMPM_CHICK_EXTENDED_ADDR_SPACE);
703
83f84d7b
JB		 704 if (ret) {
705 IWL_ERR(trans,
706 "Could not load the [%d] uCode section\n",
707 section_num);
708 break;
6dfa8d01 709 }
83f84d7b
JB		 710 }
711
c571573a 712 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 713 return ret;
714}
715
16bc119b
EH		 716/*
717 * Driver Takes the ownership on secure machine before FW load
718 * and prevent race with the BT load.
719 * W/A for ROM bug. (should be remove in the next Si step)
720 */
721static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
722{
723 u32 val, loop = 1000;
724
1e167071
EH		 725 /*
726 * Check the RSA semaphore is accessible.
727 * If the HW isn't locked and the rsa semaphore isn't accessible,
728 * we are in trouble.
729 */
16bc119b
EH		 730 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
731 if (val & (BIT(1) | BIT(17))) {
1e167071
EH		 732 IWL_INFO(trans,
733 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 734 return 0;
735 }
736
737 /* take ownership on the AUX IF */
738 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
739 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
740
741 do {
742 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
743 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
744 if (val == 0x1) {
745 iwl_write_prph(trans, RSA_ENABLE, 0);
746 return 0;
747 }
748
749 udelay(10);
750 loop--;
751 } while (loop > 0);
752
753 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
754 return -EIO;
755}
756
5dd9c68a
EG		 757static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
758 const struct fw_img *image,
759 int cpu,
760 int *first_ucode_section)
e2d6f4e7
EH		 761{
762 int shift_param;
dcab8ecd
EH		 763 int i, ret = 0, sec_num = 0x1;
764 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 765
766 if (cpu == 1) {
767 shift_param = 0;
034846cf 768 *first_ucode_section = 0;
e2d6f4e7
EH		 769 } else {
770 shift_param = 16;
034846cf 771 (*first_ucode_section)++;
e2d6f4e7
EH		 772 }
773
034846cf
EH		 774 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
775 last_read_idx = i;
776
a6c4fb44
MG		 777 /*
778 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
779 * CPU1 to CPU2.
780 * PAGING_SEPARATOR_SECTION delimiter - separate between
781 * CPU2 non paged to CPU2 paging sec.
782 */
034846cf 783 if (!image->sec[i].data ||
a6c4fb44
MG		 784 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
785 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 786 IWL_DEBUG_FW(trans,
787 "Break since Data not valid or Empty section, sec = %d\n",
788 i);
189fa2fa 789 break;
034846cf
EH		 790 }
791
189fa2fa
EH		 792 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
793 if (ret)
794 return ret;
dcab8ecd
EH		 795
796 /* Notify the ucode of the loaded section number and status */
797 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
798 val = val | (sec_num << shift_param);
799 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
800 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 801 }
802
034846cf
EH		 803 *first_ucode_section = last_read_idx;
804
afb88917
EH		 805 if (cpu == 1)
806 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
807 else
808 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
809
189fa2fa
EH		 810 return 0;
811}
e2d6f4e7 812
189fa2fa
EH		 813static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
814 const struct fw_img *image,
034846cf
EH		 815 int cpu,
816 int *first_ucode_section)
189fa2fa
EH		 817{
818 int shift_param;
189fa2fa 819 int i, ret = 0;
034846cf 820 u32 last_read_idx = 0;
189fa2fa
EH		 821
822 if (cpu == 1) {
823 shift_param = 0;
034846cf 824 *first_ucode_section = 0;
189fa2fa
EH		 825 } else {
826 shift_param = 16;
034846cf 827 (*first_ucode_section)++;
189fa2fa
EH		 828 }
829
034846cf
EH		 830 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
831 last_read_idx = i;
832
a6c4fb44
MG		 833 /*
834 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
835 * CPU1 to CPU2.
836 * PAGING_SEPARATOR_SECTION delimiter - separate between
837 * CPU2 non paged to CPU2 paging sec.
838 */
034846cf 839 if (!image->sec[i].data ||
a6c4fb44
MG		 840 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
841 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 842 IWL_DEBUG_FW(trans,
843 "Break since Data not valid or Empty section, sec = %d\n",
844 i);
189fa2fa 845 break;
034846cf
EH		 846 }
847
189fa2fa
EH		 848 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
849 if (ret)
850 return ret;
e2d6f4e7
EH		 851 }
852
189fa2fa
EH		 853 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
854 iwl_set_bits_prph(trans,
855 CSR_UCODE_LOAD_STATUS_ADDR,
856 (LMPM_CPU_UCODE_LOADING_COMPLETED |
857 LMPM_CPU_HDRS_LOADING_COMPLETED |
858 LMPM_CPU_UCODE_LOADING_STARTED) <<
859 shift_param);
860
034846cf
EH		 861 *first_ucode_section = last_read_idx;
862
e2d6f4e7
EH		 863 return 0;
864}
865
09e350f7
LK		 866static void iwl_pcie_apply_destination(struct iwl_trans *trans)
867{
868 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
869 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
870 int i;
871
872 if (dest->version)
873 IWL_ERR(trans,
874 "DBG DEST version is %d - expect issues\n",
875 dest->version);
876
877 IWL_INFO(trans, "Applying debug destination %s\n",
878 get_fw_dbg_mode_string(dest->monitor_mode));
879
880 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 881 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 882 else
883 IWL_WARN(trans, "PCI should have external buffer debug\n");
884
885 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
886 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
887 u32 val = le32_to_cpu(dest->reg_ops[i].val);
888
889 switch (dest->reg_ops[i].op) {
890 case CSR_ASSIGN:
891 iwl_write32(trans, addr, val);
892 break;
893 case CSR_SETBIT:
894 iwl_set_bit(trans, addr, BIT(val));
895 break;
896 case CSR_CLEARBIT:
897 iwl_clear_bit(trans, addr, BIT(val));
898 break;
899 case PRPH_ASSIGN:
900 iwl_write_prph(trans, addr, val);
901 break;
902 case PRPH_SETBIT:
903 iwl_set_bits_prph(trans, addr, BIT(val));
904 break;
905 case PRPH_CLEARBIT:
906 iwl_clear_bits_prph(trans, addr, BIT(val));
907 break;
869f3b15
HD		 908 case PRPH_BLOCKBIT:
909 if (iwl_read_prph(trans, addr) & BIT(val)) {
910 IWL_ERR(trans,
911 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
912 val, addr);
913 goto monitor;
914 }
915 break;
09e350f7
LK		 916 default:
917 IWL_ERR(trans, "FW debug - unknown OP %d\n",
918 dest->reg_ops[i].op);
919 break;
920 }
921 }
922
869f3b15 923monitor:
09e350f7
LK		 924 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
925 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
926 trans_pcie->fw_mon_phys >> dest->base_shift);
927 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
928 (trans_pcie->fw_mon_phys +
929 trans_pcie->fw_mon_size) >> dest->end_shift);
930 }
931}
932
7afe3705 933static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 934 const struct fw_img *image)
cf614297 935{
c2d20201 936 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 937 int ret = 0;
034846cf 938 int first_ucode_section;
cf614297 939
dcab8ecd 940 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 941 image->is_dual_cpus ? "Dual" : "Single");
942
dcab8ecd
EH		 943 /* load to FW the binary non secured sections of CPU1 */
944 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
945 if (ret)
946 return ret;
e2d6f4e7
EH		 947
948 if (image->is_dual_cpus) {
189fa2fa
EH		 949 /* set CPU2 header address */
950 iwl_write_prph(trans,
951 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
952 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 953
189fa2fa 954 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 955 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
956 &first_ucode_section);
189fa2fa
EH		 957 if (ret)
958 return ret;
e2d6f4e7 959 }
cf614297 960
c2d20201
EG		 961 /* supported for 7000 only for the moment */
962 if (iwlwifi_mod_params.fw_monitor &&
963 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 964 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 965
966 if (trans_pcie->fw_mon_size) {
967 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
968 trans_pcie->fw_mon_phys >> 4);
969 iwl_write_prph(trans, MON_BUFF_END_ADDR,
970 (trans_pcie->fw_mon_phys +
971 trans_pcie->fw_mon_size) >> 4);
972 }
09e350f7
LK		 973 } else if (trans->dbg_dest_tlv) {
974 iwl_pcie_apply_destination(trans);
c2d20201
EG		 975 }
976
e12ba844 977 /* release CPU reset */
5dd9c68a 978 iwl_write32(trans, CSR_RESET, 0);
e12ba844 979
dcab8ecd
EH		 980 return 0;
981}
189fa2fa 982
5dd9c68a
EG		 983static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
984 const struct fw_img *image)
dcab8ecd
EH		 985{
986 int ret = 0;
987 int first_ucode_section;
dcab8ecd
EH		 988
989 IWL_DEBUG_FW(trans, "working with %s CPU\n",
990 image->is_dual_cpus ? "Dual" : "Single");
991
a2227ce2
EG		 992 if (trans->dbg_dest_tlv)
993 iwl_pcie_apply_destination(trans);
994
16bc119b
EH		 995 /* TODO: remove in the next Si step */
996 ret = iwl_pcie_rsa_race_bug_wa(trans);
997 if (ret)
998 return ret;
999
dcab8ecd
EH		 1000 /* configure the ucode to be ready to get the secured image */
1001 /* release CPU reset */
1002 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1003
1004 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1005 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1006 &first_ucode_section);
dcab8ecd
EH		 1007 if (ret)
1008 return ret;
1009
1010 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1011 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1012 &first_ucode_section);
cf614297
EG		 1013}
1014
0692fe41 1015static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 1016 const struct fw_img *fw, bool run_in_rfkill)
392f8b78 1017{
fa9f3281 1018 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1019 bool hw_rfkill;
fa9f3281
EG		 1020 int ret;
1021
1022 mutex_lock(&trans_pcie->mutex);
1023
1024 /* Someone called stop_device, don't try to start_fw */
1025 if (trans_pcie->is_down) {
1026 IWL_WARN(trans,
1027 "Can't start_fw since the HW hasn't been started\n");
1028 ret = EIO;
1029 goto out;
1030 }
392f8b78 1031
496bab39 1032 /* This may fail if AMT took ownership of the device */
7afe3705 1033 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 1034 IWL_WARN(trans, "Exit HW not ready\n");
fa9f3281
EG		 1035 ret = -EIO;
1036 goto out;
392f8b78
EG		 1037 }
1038
8c46bb70
EG		 1039 iwl_enable_rfkill_int(trans);
1040
392f8b78 1041 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 1042 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1043 if (hw_rfkill)
eb7ff77e 1044 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1045 else
eb7ff77e 1046 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1047 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
fa9f3281
EG		 1048 if (hw_rfkill && !run_in_rfkill) {
1049 ret = -ERFKILL;
1050 goto out;
1051 }
392f8b78 1052
1042db2a 1053 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 1054
7afe3705 1055 ret = iwl_pcie_nic_init(trans);
392f8b78 1056 if (ret) {
6d8f6eeb 1057 IWL_ERR(trans, "Unable to init nic\n");
fa9f3281 1058 goto out;
392f8b78
EG		 1059 }
1060
1061 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 1062 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1063 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 1064 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1065
1066 /* clear (again), then enable host interrupts */
1042db2a 1067 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 1068 iwl_enable_interrupts(trans);
392f8b78
EG		 1069
1070 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 1071 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1072 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 1073
cf614297 1074 /* Load the given image to the HW */
5dd9c68a 1075 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
fa9f3281 1076 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
dcab8ecd 1077 else
fa9f3281
EG		 1078 ret = iwl_pcie_load_given_ucode(trans, fw);
1079
1080out:
1081 mutex_unlock(&trans_pcie->mutex);
1082 return ret;
b3c2ce13
EG		 1083}
1084
adca1235 1085static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 1086{
990aa6d7 1087 iwl_pcie_reset_ict(trans);
f02831be 1088 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 1089}
1090
fa9f3281 1091static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1092{
43e58856 1093 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1094 bool hw_rfkill, was_hw_rfkill;
1095
fa9f3281
EG		 1096 lockdep_assert_held(&trans_pcie->mutex);
1097
1098 if (trans_pcie->is_down)
1099 return;
1100
1101 trans_pcie->is_down = true;
1102
3dc3374f 1103 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1104
43e58856 1105 /* tell the device to stop sending interrupts */
7b70bd63 1106 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1107 iwl_disable_interrupts(trans);
7b70bd63 1108 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1109
ab6cf8e8 1110 /* device going down, Stop using ICT table */
990aa6d7 1111 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1112
1113 /*
1114 * If a HW restart happens during firmware loading,
1115 * then the firmware loading might call this function
1116 * and later it might be called again due to the
1117 * restart. So don't process again if the device is
1118 * already dead.
1119 */
31b8b343
EG		 1120 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1121 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1122 iwl_pcie_tx_stop(trans);
9805c446 1123 iwl_pcie_rx_stop(trans);
6379103e 1124
ab6cf8e8 1125 /* Power-down device's busmaster DMA clocks */
95411d04 1126 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1127 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1128 APMG_CLK_VAL_DMA_CLK_RQT);
1129 udelay(5);
1130 }
ab6cf8e8
EG		 1131 }
1132
1133 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1134 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1135 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1136
1137 /* Stop the device, and put it in low power state */
b7aaeae4 1138 iwl_pcie_apm_stop(trans, false);
43e58856 1139
03d6c3b0
EG		 1140 /* stop and reset the on-board processor */
1141 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1142 udelay(20);
1143
1144 /*
1145 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1146 * This is a bug in certain verions of the hardware.
1147 * Certain devices also keep sending HW RF kill interrupt all
1148 * the time, unless the interrupt is ACKed even if the interrupt
1149 * should be masked. Re-ACK all the interrupts here.
43e58856 1150 */
7b70bd63 1151 spin_lock(&trans_pcie->irq_lock);
43e58856 1152 iwl_disable_interrupts(trans);
7b70bd63 1153 spin_unlock(&trans_pcie->irq_lock);
43e58856 1154
74fda971
DF		 1155
1156 /* clear all status bits */
eb7ff77e
AN		 1157 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1158 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1159 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1160 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1161
1162 /*
1163 * Even if we stop the HW, we still want the RF kill
1164 * interrupt
1165 */
1166 iwl_enable_rfkill_int(trans);
1167
1168 /*
1169 * Check again since the RF kill state may have changed while
1170 * all the interrupts were disabled, in this case we couldn't
1171 * receive the RF kill interrupt and update the state in the
1172 * op_mode.
3dc3374f
EG		 1173 * Don't call the op_mode if the rkfill state hasn't changed.
1174 * This allows the op_mode to call stop_device from the rfkill
1175 * notification without endless recursion. Under very rare
1176 * circumstances, we might have a small recursion if the rfkill
1177 * state changed exactly now while we were called from stop_device.
1178 * This is very unlikely but can happen and is supported.
a4082843
AN		 1179 */
1180 hw_rfkill = iwl_is_rfkill_set(trans);
1181 if (hw_rfkill)
eb7ff77e 1182 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1183 else
eb7ff77e 1184 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1185 if (hw_rfkill != was_hw_rfkill)
14cfca71 1186 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1187
1188 /* re-take ownership to prevent other users from stealing the deivce */
1189 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1190}
1191
fa9f3281
EG		 1192static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1193{
1194 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1195
1196 mutex_lock(&trans_pcie->mutex);
1197 _iwl_trans_pcie_stop_device(trans, low_power);
1198 mutex_unlock(&trans_pcie->mutex);
1199}
1200
14cfca71
JB		 1201void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1202{
fa9f3281
EG		 1203 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1204 IWL_TRANS_GET_PCIE_TRANS(trans);
1205
1206 lockdep_assert_held(&trans_pcie->mutex);
1207
14cfca71 1208 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1209 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1210}
1211
debff618 1212static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1213{
33b56af1
EG		 1214 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1215
6dfb36c8
EP		 1216 if (trans->wowlan_d0i3) {
1217 /* Enable persistence mode to avoid reset */
1218 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1219 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1220 }
1221
2dd4f9f7 1222 iwl_disable_interrupts(trans);
debff618
JB		 1223
1224 /*
1225 * in testing mode, the host stays awake and the
1226 * hardware won't be reset (not even partially)
1227 */
1228 if (test)
1229 return;
1230
ddaf5a5b
JB		 1231 iwl_pcie_disable_ict(trans);
1232
33b56af1
EG		 1233 synchronize_irq(trans_pcie->pci_dev->irq);
1234
2dd4f9f7
JB		 1235 iwl_clear_bit(trans, CSR_GP_CNTRL,
1236 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1237 iwl_clear_bit(trans, CSR_GP_CNTRL,
1238 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1239
6dfb36c8
EP		 1240 if (!trans->wowlan_d0i3) {
1241 /*
1242 * reset TX queues -- some of their registers reset during S3
1243 * so if we don't reset everything here the D3 image would try
1244 * to execute some invalid memory upon resume
1245 */
1246 iwl_trans_pcie_tx_reset(trans);
1247 }
ddaf5a5b
JB		 1248
1249 iwl_pcie_set_pwr(trans, true);
1250}
1251
1252static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1253 enum iwl_d3_status *status,
1254 bool test)
ddaf5a5b
JB		 1255{
1256 u32 val;
1257 int ret;
1258
debff618
JB		 1259 if (test) {
1260 iwl_enable_interrupts(trans);
1261 *status = IWL_D3_STATUS_ALIVE;
1262 return 0;
1263 }
1264
ddaf5a5b
JB		 1265 /*
1266 * Also enables interrupts - none will happen as the device doesn't
1267 * know we're waking it up, only when the opmode actually tells it
1268 * after this call.
1269 */
1270 iwl_pcie_reset_ict(trans);
1271
1272 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1273 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1274
01e58a28
EG		 1275 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1276 udelay(2);
1277
ddaf5a5b
JB		 1278 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1279 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1280 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1281 25000);
7f2ac8fb 1282 if (ret < 0) {
ddaf5a5b
JB		 1283 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1284 return ret;
1285 }
1286
a3ead656
EG		 1287 iwl_pcie_set_pwr(trans, false);
1288
6dfb36c8
EP		 1289 if (trans->wowlan_d0i3) {
1290 iwl_clear_bit(trans, CSR_GP_CNTRL,
1291 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1292 } else {
1293 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1294
6dfb36c8
EP		 1295 ret = iwl_pcie_rx_init(trans);
1296 if (ret) {
1297 IWL_ERR(trans,
1298 "Failed to resume the device (RX reset)\n");
1299 return ret;
1300 }
ddaf5a5b
JB		 1301 }
1302
a3ead656
EG		 1303 val = iwl_read32(trans, CSR_RESET);
1304 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1305 *status = IWL_D3_STATUS_RESET;
1306 else
1307 *status = IWL_D3_STATUS_ALIVE;
1308
ddaf5a5b 1309 return 0;
2dd4f9f7
JB		 1310}
1311
fa9f3281 1312static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1313{
fa9f3281 1314 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1315 bool hw_rfkill;
a8b691e6 1316 int err;
e6bb4c9c 1317
fa9f3281
EG		 1318 lockdep_assert_held(&trans_pcie->mutex);
1319
7afe3705 1320 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1321 if (err) {
d6f1c316 1322 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1323 return err;
ebb7678d 1324 }
a6c684ee 1325
2997494f 1326 /* Reset the entire device */
ce836c76 1327 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1328
1329 usleep_range(10, 15);
1330
7afe3705 1331 iwl_pcie_apm_init(trans);
a6c684ee 1332
226c02ca
EG		 1333 /* From now on, the op_mode will be kept updated about RF kill state */
1334 iwl_enable_rfkill_int(trans);
1335
fa9f3281
EG		 1336 /* Set is_down to false here so that...*/
1337 trans_pcie->is_down = false;
1338
8d425517 1339 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1340 if (hw_rfkill)
eb7ff77e 1341 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1342 else
eb7ff77e 1343 clear_bit(STATUS_RFKILL, &trans->status);
fa9f3281 1344 /* ... rfkill can call stop_device and set it false if needed */
14cfca71 1345 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1346
a8b691e6 1347 return 0;
e6bb4c9c
EG		 1348}
1349
fa9f3281
EG		 1350static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1351{
1352 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1353 int ret;
1354
1355 mutex_lock(&trans_pcie->mutex);
1356 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1357 mutex_unlock(&trans_pcie->mutex);
1358
1359 return ret;
1360}
1361
a4082843 1362static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1363{
20d3b647 1364 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1365
fa9f3281
EG		 1366 mutex_lock(&trans_pcie->mutex);
1367
a4082843 1368 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1369 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1370 iwl_disable_interrupts(trans);
7b70bd63 1371 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1372
b7aaeae4 1373 iwl_pcie_apm_stop(trans, true);
cc56feb2 1374
7b70bd63 1375 spin_lock(&trans_pcie->irq_lock);
218733cf 1376 iwl_disable_interrupts(trans);
7b70bd63 1377 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1378
8d96bb61 1379 iwl_pcie_disable_ict(trans);
33b56af1 1380
fa9f3281 1381 mutex_unlock(&trans_pcie->mutex);
33b56af1
EG		 1382
1383 synchronize_irq(trans_pcie->pci_dev->irq);
cc56feb2
EG		 1384}
1385
03905495
EG		 1386static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1387{
05f5b97e 1388 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1389}
1390
1391static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1392{
05f5b97e 1393 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1394}
1395
1396static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1397{
05f5b97e 1398 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1399}
1400
6a06b6c1
EG		 1401static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1402{
f9477c17
AP		 1403 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1404 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1405 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1406}
1407
1408static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1409 u32 val)
1410{
1411 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1412 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1413 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1414}
1415
f14d6b39
JB		 1416static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1417{
1418 WARN_ON(1);
1419 return 0;
1420}
1421
c6f600fc 1422static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1423 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1424{
1425 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1426
1427 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1428 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1429 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1430 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1431 trans_pcie->n_no_reclaim_cmds = 0;
1432 else
1433 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1434 if (trans_pcie->n_no_reclaim_cmds)
1435 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1436 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1437
b2cf410c
JB		 1438 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1439 if (trans_pcie->rx_buf_size_8k)
1440 trans_pcie->rx_page_order = get_order(8 * 1024);
1441 else
1442 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8 1443
ab02165c 1444 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
d9fb6465 1445 trans_pcie->command_names = trans_cfg->command_names;
046db346 1446 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1447 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39 1448
483f3ab1
EP		 1449 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1450 trans_pcie->ref_count = 1;
1451
f14d6b39
JB		 1452 /* Initialize NAPI here - it should be before registering to mac80211
1453 * in the opmode but after the HW struct is allocated.
1454 * As this function may be called again in some corner cases don't
1455 * do anything if NAPI was already initialized.
1456 */
1be5d8cc 1457 if (!trans_pcie->napi.poll) {
f14d6b39 1458 init_dummy_netdev(&trans_pcie->napi_dev);
1be5d8cc
JB		 1459 netif_napi_add(&trans_pcie->napi_dev, &trans_pcie->napi,
1460 iwl_pcie_dummy_napi_poll, 64);
f14d6b39 1461 }
c6f600fc
MV		 1462}
1463
d1ff5253 1464void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1465{
20d3b647 1466 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1467
0aa86df6 1468 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1469
f02831be 1470 iwl_pcie_tx_free(trans);
9805c446 1471 iwl_pcie_rx_free(trans);
6379103e 1472
a8b691e6
JB		 1473 free_irq(trans_pcie->pci_dev->irq, trans);
1474 iwl_pcie_free_ict(trans);
a42a1844
EG		 1475
1476 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1477 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1478 pci_release_regions(trans_pcie->pci_dev);
1479 pci_disable_device(trans_pcie->pci_dev);
1480
f14d6b39
JB		 1481 if (trans_pcie->napi.poll)
1482 netif_napi_del(&trans_pcie->napi);
1483
c2d20201
EG		 1484 iwl_pcie_free_fw_monitor(trans);
1485
7b501d10 1486 iwl_trans_free(trans);
34c1b7ba
EG		 1487}
1488
47107e84
DF		 1489static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1490{
47107e84 1491 if (state)
eb7ff77e 1492 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1493 else
eb7ff77e 1494 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1495}
1496
e56b04ef
LE		 1497static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1498 unsigned long *flags)
7a65d170
EG		 1499{
1500 int ret;
cfb4e624
JB		 1501 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1502
1503 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1504
fc8a350d 1505 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1506 goto out;
1507
7a65d170 1508 /* this bit wakes up the NIC */
e139dc4a
LE		 1509 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1510 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1511 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1512 udelay(2);
7a65d170
EG		 1513
1514 /*
1515 * These bits say the device is running, and should keep running for
1516 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1517 * but they do not indicate that embedded SRAM is restored yet;
1518 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1519 * to/from host DRAM when sleeping/waking for power-saving.
1520 * Each direction takes approximately 1/4 millisecond; with this
1521 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1522 * series of register accesses are expected (e.g. reading Event Log),
1523 * to keep device from sleeping.
1524 *
1525 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1526 * SRAM is okay/restored. We don't check that here because this call
1527 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1528 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1529 *
1530 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1531 * and do not save/restore SRAM when power cycling.
1532 */
1533 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1534 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1535 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1536 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1537 if (unlikely(ret < 0)) {
1538 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1539 if (!silent) {
1540 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1541 WARN_ONCE(1,
1542 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1543 val);
cfb4e624 1544 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1545 return false;
1546 }
1547 }
1548
b9439491 1549out:
e56b04ef
LE		 1550 /*
1551 * Fool sparse by faking we release the lock - sparse will
1552 * track nic_access anyway.
1553 */
cfb4e624 1554 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1555 return true;
1556}
1557
e56b04ef
LE		 1558static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1559 unsigned long *flags)
7a65d170 1560{
cfb4e624 1561 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1562
cfb4e624 1563 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1564
1565 /*
1566 * Fool sparse by faking we acquiring the lock - sparse will
1567 * track nic_access anyway.
1568 */
cfb4e624 1569 __acquire(&trans_pcie->reg_lock);
e56b04ef 1570
fc8a350d 1571 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1572 goto out;
1573
e139dc4a
LE		 1574 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1575 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1576 /*
1577 * Above we read the CSR_GP_CNTRL register, which will flush
1578 * any previous writes, but we need the write that clears the
1579 * MAC_ACCESS_REQ bit to be performed before any other writes
1580 * scheduled on different CPUs (after we drop reg_lock).
1581 */
1582 mmiowb();
b9439491 1583out:
cfb4e624 1584 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1585}
1586
4fd442db
EG		 1587static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1588 void *buf, int dwords)
1589{
1590 unsigned long flags;
1591 int offs, ret = 0;
1592 u32 *vals = buf;
1593
e56b04ef 1594 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1595 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1596 for (offs = 0; offs < dwords; offs++)
1597 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1598 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1599 } else {
1600 ret = -EBUSY;
1601 }
4fd442db
EG		 1602 return ret;
1603}
1604
1605static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1606 const void *buf, int dwords)
4fd442db
EG		 1607{
1608 unsigned long flags;
1609 int offs, ret = 0;
bf0fd5da 1610 const u32 *vals = buf;
4fd442db 1611
e56b04ef 1612 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1613 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1614 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1615 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1616 vals ? vals[offs] : 0);
e56b04ef 1617 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1618 } else {
1619 ret = -EBUSY;
1620 }
4fd442db
EG		 1621 return ret;
1622}
7a65d170 1623
e0b8d405
EG		 1624static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1625 unsigned long txqs,
1626 bool freeze)
1627{
1628 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1629 int queue;
1630
1631 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1632 struct iwl_txq *txq = &trans_pcie->txq[queue];
1633 unsigned long now;
1634
1635 spin_lock_bh(&txq->lock);
1636
1637 now = jiffies;
1638
1639 if (txq->frozen == freeze)
1640 goto next_queue;
1641
1642 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1643 freeze ? "Freezing" : "Waking", queue);
1644
1645 txq->frozen = freeze;
1646
1647 if (txq->q.read_ptr == txq->q.write_ptr)
1648 goto next_queue;
1649
1650 if (freeze) {
1651 if (unlikely(time_after(now,
1652 txq->stuck_timer.expires))) {
1653 /*
1654 * The timer should have fired, maybe it is
1655 * spinning right now on the lock.
1656 */
1657 goto next_queue;
1658 }
1659 /* remember how long until the timer fires */
1660 txq->frozen_expiry_remainder =
1661 txq->stuck_timer.expires - now;
1662 del_timer(&txq->stuck_timer);
1663 goto next_queue;
1664 }
1665
1666 /*
1667 * Wake a non-empty queue -> arm timer with the
1668 * remainder before it froze
1669 */
1670 mod_timer(&txq->stuck_timer,
1671 now + txq->frozen_expiry_remainder);
1672
1673next_queue:
1674 spin_unlock_bh(&txq->lock);
1675 }
1676}
1677
5f178cd2
EG		 1678#define IWL_FLUSH_WAIT_MS 2000
1679
3cafdbe6 1680static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1681{
8ad71bef 1682 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1683 struct iwl_txq *txq;
5f178cd2
EG		 1684 struct iwl_queue *q;
1685 int cnt;
1686 unsigned long now = jiffies;
1c3fea82
EG		 1687 u32 scd_sram_addr;
1688 u8 buf[16];
5f178cd2
EG		 1689 int ret = 0;
1690
1691 /* waiting for all the tx frames complete might take a while */
035f7ff2 1692 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1693 u8 wr_ptr;
1694
9ba1947a 1695 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1696 continue;
3cafdbe6
EG		 1697 if (!test_bit(cnt, trans_pcie->queue_used))
1698 continue;
1699 if (!(BIT(cnt) & txq_bm))
1700 continue;
748fa67c
EG		 1701
1702 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1703 txq = &trans_pcie->txq[cnt];
5f178cd2 1704 q = &txq->q;
fa1a91fd
EG		 1705 wr_ptr = ACCESS_ONCE(q->write_ptr);
1706
1707 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1708 !time_after(jiffies,
1709 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1710 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1711
1712 if (WARN_ONCE(wr_ptr != write_ptr,
1713 "WR pointer moved while flushing %d -> %d\n",
1714 wr_ptr, write_ptr))
1715 return -ETIMEDOUT;
5f178cd2 1716 msleep(1);
fa1a91fd 1717 }
5f178cd2
EG		 1718
1719 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1720 IWL_ERR(trans,
1721 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1722 ret = -ETIMEDOUT;
1723 break;
1724 }
748fa67c 1725 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1726 }
1c3fea82
EG		 1727
1728 if (!ret)
1729 return 0;
1730
1731 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1732 txq->q.read_ptr, txq->q.write_ptr);
1733
1734 scd_sram_addr = trans_pcie->scd_base_addr +
1735 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1736 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1737
1738 iwl_print_hex_error(trans, buf, sizeof(buf));
1739
1740 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1741 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1742 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1743
1744 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1745 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1746 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1747 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1748 u32 tbl_dw =
1749 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1750 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1751
1752 if (cnt & 0x1)
1753 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1754 else
1755 tbl_dw = tbl_dw & 0x0000FFFF;
1756
1757 IWL_ERR(trans,
1758 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1759 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1760 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1761 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1762 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1763 }
1764
5f178cd2
EG		 1765 return ret;
1766}
1767
e139dc4a
LE		 1768static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1769 u32 mask, u32 value)
1770{
e56b04ef 1771 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1772 unsigned long flags;
1773
e56b04ef 1774 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1775 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1776 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1777}
1778
7616f334
EP		 1779void iwl_trans_pcie_ref(struct iwl_trans *trans)
1780{
1781 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1782 unsigned long flags;
1783
1784 if (iwlwifi_mod_params.d0i3_disable)
1785 return;
1786
1787 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1788 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1789 trans_pcie->ref_count++;
1790 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1791}
1792
1793void iwl_trans_pcie_unref(struct iwl_trans *trans)
1794{
1795 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1796 unsigned long flags;
1797
1798 if (iwlwifi_mod_params.d0i3_disable)
1799 return;
1800
1801 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1802 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1803 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1804 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1805 return;
1806 }
1807 trans_pcie->ref_count--;
1808 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1809}
1810
ff620849
EG		 1811static const char *get_csr_string(int cmd)
1812{
d9fb6465 1813#define IWL_CMD(x) case x: return #x
ff620849
EG		 1814 switch (cmd) {
1815 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1816 IWL_CMD(CSR_INT_COALESCING);
1817 IWL_CMD(CSR_INT);
1818 IWL_CMD(CSR_INT_MASK);
1819 IWL_CMD(CSR_FH_INT_STATUS);
1820 IWL_CMD(CSR_GPIO_IN);
1821 IWL_CMD(CSR_RESET);
1822 IWL_CMD(CSR_GP_CNTRL);
1823 IWL_CMD(CSR_HW_REV);
1824 IWL_CMD(CSR_EEPROM_REG);
1825 IWL_CMD(CSR_EEPROM_GP);
1826 IWL_CMD(CSR_OTP_GP_REG);
1827 IWL_CMD(CSR_GIO_REG);
1828 IWL_CMD(CSR_GP_UCODE_REG);
1829 IWL_CMD(CSR_GP_DRIVER_REG);
1830 IWL_CMD(CSR_UCODE_DRV_GP1);
1831 IWL_CMD(CSR_UCODE_DRV_GP2);
1832 IWL_CMD(CSR_LED_REG);
1833 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1834 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1835 IWL_CMD(CSR_ANA_PLL_CFG);
1836 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1837 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1838 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1839 default:
1840 return "UNKNOWN";
1841 }
d9fb6465 1842#undef IWL_CMD
ff620849
EG		 1843}
1844
990aa6d7 1845void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1846{
1847 int i;
1848 static const u32 csr_tbl[] = {
1849 CSR_HW_IF_CONFIG_REG,
1850 CSR_INT_COALESCING,
1851 CSR_INT,
1852 CSR_INT_MASK,
1853 CSR_FH_INT_STATUS,
1854 CSR_GPIO_IN,
1855 CSR_RESET,
1856 CSR_GP_CNTRL,
1857 CSR_HW_REV,
1858 CSR_EEPROM_REG,
1859 CSR_EEPROM_GP,
1860 CSR_OTP_GP_REG,
1861 CSR_GIO_REG,
1862 CSR_GP_UCODE_REG,
1863 CSR_GP_DRIVER_REG,
1864 CSR_UCODE_DRV_GP1,
1865 CSR_UCODE_DRV_GP2,
1866 CSR_LED_REG,
1867 CSR_DRAM_INT_TBL_REG,
1868 CSR_GIO_CHICKEN_BITS,
1869 CSR_ANA_PLL_CFG,
a812cba9 1870 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1871 CSR_HW_REV_WA_REG,
1872 CSR_DBG_HPET_MEM_REG
1873 };
1874 IWL_ERR(trans, "CSR values:\n");
1875 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1876 "CSR_INT_PERIODIC_REG)\n");
1877 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1878 IWL_ERR(trans, " %25s: 0X%08x\n",
1879 get_csr_string(csr_tbl[i]),
1042db2a 1880 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1881 }
1882}
1883
87e5666c
EG		 1884#ifdef CONFIG_IWLWIFI_DEBUGFS
1885/* create and remove of files */
1886#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1887 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1888 &iwl_dbgfs_##name##_ops)) \
9da987ac 1889 goto err; \
87e5666c
EG		 1890} while (0)
1891
1892/* file operation */
87e5666c 1893#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1894static const struct file_operations iwl_dbgfs_##name##_ops = { \
1895 .read = iwl_dbgfs_##name##_read, \
234e3405 1896 .open = simple_open, \
87e5666c
EG		 1897 .llseek = generic_file_llseek, \
1898};
1899
16db88ba 1900#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1901static const struct file_operations iwl_dbgfs_##name##_ops = { \
1902 .write = iwl_dbgfs_##name##_write, \
234e3405 1903 .open = simple_open, \
16db88ba
EG		 1904 .llseek = generic_file_llseek, \
1905};
1906
87e5666c 1907#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1908static const struct file_operations iwl_dbgfs_##name##_ops = { \
1909 .write = iwl_dbgfs_##name##_write, \
1910 .read = iwl_dbgfs_##name##_read, \
234e3405 1911 .open = simple_open, \
87e5666c
EG		 1912 .llseek = generic_file_llseek, \
1913};
1914
87e5666c 1915static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1916 char __user *user_buf,
1917 size_t count, loff_t *ppos)
8ad71bef 1918{
5a878bf6 1919 struct iwl_trans *trans = file->private_data;
8ad71bef 1920 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1921 struct iwl_txq *txq;
87e5666c
EG		 1922 struct iwl_queue *q;
1923 char *buf;
1924 int pos = 0;
1925 int cnt;
1926 int ret;
1745e440
WYG		 1927 size_t bufsz;
1928
e0b8d405 1929 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 1930
f9e75447 1931 if (!trans_pcie->txq)
87e5666c 1932 return -EAGAIN;
f9e75447 1933
87e5666c
EG		 1934 buf = kzalloc(bufsz, GFP_KERNEL);
1935 if (!buf)
1936 return -ENOMEM;
1937
035f7ff2 1938 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1939 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1940 q = &txq->q;
1941 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 1942 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 1943 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1944 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 1945 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 1946 txq->need_update, txq->frozen,
f40faf62 1947 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1948 }
1949 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1950 kfree(buf);
1951 return ret;
1952}
1953
1954static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1955 char __user *user_buf,
1956 size_t count, loff_t *ppos)
1957{
5a878bf6 1958 struct iwl_trans *trans = file->private_data;
20d3b647 1959 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1960 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1961 char buf[256];
1962 int pos = 0;
1963 const size_t bufsz = sizeof(buf);
1964
1965 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1966 rxq->read);
1967 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1968 rxq->write);
f40faf62
AL		 1969 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1970 rxq->write_actual);
1971 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1972 rxq->need_update);
87e5666c
EG		 1973 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1974 rxq->free_count);
1975 if (rxq->rb_stts) {
1976 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1977 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1978 } else {
1979 pos += scnprintf(buf + pos, bufsz - pos,
1980 "closed_rb_num: Not Allocated\n");
1981 }
1982 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1983}
1984
1f7b6172
EG		 1985static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1986 char __user *user_buf,
20d3b647
JB		 1987 size_t count, loff_t *ppos)
1988{
1f7b6172 1989 struct iwl_trans *trans = file->private_data;
20d3b647 1990 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1991 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1992
1993 int pos = 0;
1994 char *buf;
1995 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1996 ssize_t ret;
1997
1998 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1999 if (!buf)
1f7b6172 2000 return -ENOMEM;
1f7b6172
EG		 2001
2002 pos += scnprintf(buf + pos, bufsz - pos,
2003 "Interrupt Statistics Report:\n");
2004
2005 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2006 isr_stats->hw);
2007 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2008 isr_stats->sw);
2009 if (isr_stats->sw || isr_stats->hw) {
2010 pos += scnprintf(buf + pos, bufsz - pos,
2011 "\tLast Restarting Code: 0x%X\n",
2012 isr_stats->err_code);
2013 }
2014#ifdef CONFIG_IWLWIFI_DEBUG
2015 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2016 isr_stats->sch);
2017 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2018 isr_stats->alive);
2019#endif
2020 pos += scnprintf(buf + pos, bufsz - pos,
2021 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2022
2023 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2024 isr_stats->ctkill);
2025
2026 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2027 isr_stats->wakeup);
2028
2029 pos += scnprintf(buf + pos, bufsz - pos,
2030 "Rx command responses:\t\t %u\n", isr_stats->rx);
2031
2032 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2033 isr_stats->tx);
2034
2035 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2036 isr_stats->unhandled);
2037
2038 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2039 kfree(buf);
2040 return ret;
2041}
2042
2043static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2044 const char __user *user_buf,
2045 size_t count, loff_t *ppos)
2046{
2047 struct iwl_trans *trans = file->private_data;
20d3b647 2048 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2049 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2050
2051 char buf[8];
2052 int buf_size;
2053 u32 reset_flag;
2054
2055 memset(buf, 0, sizeof(buf));
2056 buf_size = min(count, sizeof(buf) - 1);
2057 if (copy_from_user(buf, user_buf, buf_size))
2058 return -EFAULT;
2059 if (sscanf(buf, "%x", &reset_flag) != 1)
2060 return -EFAULT;
2061 if (reset_flag == 0)
2062 memset(isr_stats, 0, sizeof(*isr_stats));
2063
2064 return count;
2065}
2066
16db88ba 2067static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2068 const char __user *user_buf,
2069 size_t count, loff_t *ppos)
16db88ba
EG		 2070{
2071 struct iwl_trans *trans = file->private_data;
2072 char buf[8];
2073 int buf_size;
2074 int csr;
2075
2076 memset(buf, 0, sizeof(buf));
2077 buf_size = min(count, sizeof(buf) - 1);
2078 if (copy_from_user(buf, user_buf, buf_size))
2079 return -EFAULT;
2080 if (sscanf(buf, "%d", &csr) != 1)
2081 return -EFAULT;
2082
990aa6d7 2083 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2084
2085 return count;
2086}
2087
16db88ba 2088static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2089 char __user *user_buf,
2090 size_t count, loff_t *ppos)
16db88ba
EG		 2091{
2092 struct iwl_trans *trans = file->private_data;
94543a8d 2093 char *buf = NULL;
56c2477f 2094 ssize_t ret;
16db88ba 2095
56c2477f
JB		 2096 ret = iwl_dump_fh(trans, &buf);
2097 if (ret < 0)
2098 return ret;
2099 if (!buf)
2100 return -EINVAL;
2101 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2102 kfree(buf);
16db88ba
EG		 2103 return ret;
2104}
2105
1f7b6172 2106DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2107DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2108DEBUGFS_READ_FILE_OPS(rx_queue);
2109DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2110DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 2111
2112/*
2113 * Create the debugfs files and directories
2114 *
2115 */
2116static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 2117 struct dentry *dir)
87e5666c 2118{
87e5666c
EG		 2119 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2120 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2121 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2122 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2123 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2124 return 0;
9da987ac
MV		 2125
2126err:
2127 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2128 return -ENOMEM;
87e5666c 2129}
aadede6e
JB		 2130#else
2131static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2132 struct dentry *dir)
2133{
2134 return 0;
2135}
2136#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2137
2138static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2139{
2140 u32 cmdlen = 0;
2141 int i;
2142
2143 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2144 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2145
2146 return cmdlen;
2147}
2148
67c65f2c
EG		 2149static const struct {
2150 u32 start, end;
2151} iwl_prph_dump_addr[] = {
2152 { .start = 0x00a00000, .end = 0x00a00000 },
2153 { .start = 0x00a0000c, .end = 0x00a00024 },
2154 { .start = 0x00a0002c, .end = 0x00a0003c },
2155 { .start = 0x00a00410, .end = 0x00a00418 },
2156 { .start = 0x00a00420, .end = 0x00a00420 },
2157 { .start = 0x00a00428, .end = 0x00a00428 },
2158 { .start = 0x00a00430, .end = 0x00a0043c },
2159 { .start = 0x00a00444, .end = 0x00a00444 },
2160 { .start = 0x00a004c0, .end = 0x00a004cc },
2161 { .start = 0x00a004d8, .end = 0x00a004d8 },
2162 { .start = 0x00a004e0, .end = 0x00a004f0 },
2163 { .start = 0x00a00840, .end = 0x00a00840 },
2164 { .start = 0x00a00850, .end = 0x00a00858 },
2165 { .start = 0x00a01004, .end = 0x00a01008 },
2166 { .start = 0x00a01010, .end = 0x00a01010 },
2167 { .start = 0x00a01018, .end = 0x00a01018 },
2168 { .start = 0x00a01024, .end = 0x00a01024 },
2169 { .start = 0x00a0102c, .end = 0x00a01034 },
2170 { .start = 0x00a0103c, .end = 0x00a01040 },
2171 { .start = 0x00a01048, .end = 0x00a01094 },
2172 { .start = 0x00a01c00, .end = 0x00a01c20 },
2173 { .start = 0x00a01c58, .end = 0x00a01c58 },
2174 { .start = 0x00a01c7c, .end = 0x00a01c7c },
2175 { .start = 0x00a01c28, .end = 0x00a01c54 },
2176 { .start = 0x00a01c5c, .end = 0x00a01c5c },
6a65bd53 2177 { .start = 0x00a01c60, .end = 0x00a01cdc },
67c65f2c
EG		 2178 { .start = 0x00a01ce0, .end = 0x00a01d0c },
2179 { .start = 0x00a01d18, .end = 0x00a01d20 },
2180 { .start = 0x00a01d2c, .end = 0x00a01d30 },
2181 { .start = 0x00a01d40, .end = 0x00a01d5c },
2182 { .start = 0x00a01d80, .end = 0x00a01d80 },
6a65bd53
EG		 2183 { .start = 0x00a01d98, .end = 0x00a01d9c },
2184 { .start = 0x00a01da8, .end = 0x00a01da8 },
2185 { .start = 0x00a01db8, .end = 0x00a01df4 },
67c65f2c
EG		 2186 { .start = 0x00a01dc0, .end = 0x00a01dfc },
2187 { .start = 0x00a01e00, .end = 0x00a01e2c },
2188 { .start = 0x00a01e40, .end = 0x00a01e60 },
6a65bd53
EG		 2189 { .start = 0x00a01e68, .end = 0x00a01e6c },
2190 { .start = 0x00a01e74, .end = 0x00a01e74 },
67c65f2c
EG		 2191 { .start = 0x00a01e84, .end = 0x00a01e90 },
2192 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
6a65bd53
EG		 2193 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2194 { .start = 0x00a01f00, .end = 0x00a01f1c },
2195 { .start = 0x00a01f44, .end = 0x00a01ffc },
67c65f2c
EG		 2196 { .start = 0x00a02000, .end = 0x00a02048 },
2197 { .start = 0x00a02068, .end = 0x00a020f0 },
2198 { .start = 0x00a02100, .end = 0x00a02118 },
2199 { .start = 0x00a02140, .end = 0x00a0214c },
2200 { .start = 0x00a02168, .end = 0x00a0218c },
2201 { .start = 0x00a021c0, .end = 0x00a021c0 },
2202 { .start = 0x00a02400, .end = 0x00a02410 },
2203 { .start = 0x00a02418, .end = 0x00a02420 },
2204 { .start = 0x00a02428, .end = 0x00a0242c },
2205 { .start = 0x00a02434, .end = 0x00a02434 },
2206 { .start = 0x00a02440, .end = 0x00a02460 },
2207 { .start = 0x00a02468, .end = 0x00a024b0 },
2208 { .start = 0x00a024c8, .end = 0x00a024cc },
2209 { .start = 0x00a02500, .end = 0x00a02504 },
2210 { .start = 0x00a0250c, .end = 0x00a02510 },
2211 { .start = 0x00a02540, .end = 0x00a02554 },
2212 { .start = 0x00a02580, .end = 0x00a025f4 },
2213 { .start = 0x00a02600, .end = 0x00a0260c },
2214 { .start = 0x00a02648, .end = 0x00a02650 },
2215 { .start = 0x00a02680, .end = 0x00a02680 },
2216 { .start = 0x00a026c0, .end = 0x00a026d0 },
2217 { .start = 0x00a02700, .end = 0x00a0270c },
2218 { .start = 0x00a02804, .end = 0x00a02804 },
2219 { .start = 0x00a02818, .end = 0x00a0281c },
2220 { .start = 0x00a02c00, .end = 0x00a02db4 },
2221 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2222 { .start = 0x00a03000, .end = 0x00a03014 },
2223 { .start = 0x00a0301c, .end = 0x00a0302c },
2224 { .start = 0x00a03034, .end = 0x00a03038 },
2225 { .start = 0x00a03040, .end = 0x00a03048 },
2226 { .start = 0x00a03060, .end = 0x00a03068 },
2227 { .start = 0x00a03070, .end = 0x00a03074 },
2228 { .start = 0x00a0307c, .end = 0x00a0307c },
2229 { .start = 0x00a03080, .end = 0x00a03084 },
2230 { .start = 0x00a0308c, .end = 0x00a03090 },
2231 { .start = 0x00a03098, .end = 0x00a03098 },
2232 { .start = 0x00a030a0, .end = 0x00a030a0 },
2233 { .start = 0x00a030a8, .end = 0x00a030b4 },
2234 { .start = 0x00a030bc, .end = 0x00a030bc },
2235 { .start = 0x00a030c0, .end = 0x00a0312c },
2236 { .start = 0x00a03c00, .end = 0x00a03c5c },
2237 { .start = 0x00a04400, .end = 0x00a04454 },
2238 { .start = 0x00a04460, .end = 0x00a04474 },
2239 { .start = 0x00a044c0, .end = 0x00a044ec },
2240 { .start = 0x00a04500, .end = 0x00a04504 },
2241 { .start = 0x00a04510, .end = 0x00a04538 },
2242 { .start = 0x00a04540, .end = 0x00a04548 },
2243 { .start = 0x00a04560, .end = 0x00a0457c },
2244 { .start = 0x00a04590, .end = 0x00a04598 },
2245 { .start = 0x00a045c0, .end = 0x00a045f4 },
2246};
2247
2248static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2249 struct iwl_fw_error_dump_data **data)
2250{
2251 struct iwl_fw_error_dump_prph *prph;
2252 unsigned long flags;
2253 u32 prph_len = 0, i;
2254
2255 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2256 return 0;
2257
2258 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2259 /* The range includes both boundaries */
2260 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2261 iwl_prph_dump_addr[i].start + 4;
2262 int reg;
2263 __le32 *val;
2264
87dd634a 2265 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 2266
2267 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2268 (*data)->len = cpu_to_le32(sizeof(*prph) +
2269 num_bytes_in_chunk);
2270 prph = (void *)(*data)->data;
2271 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2272 val = (void *)prph->data;
2273
2274 for (reg = iwl_prph_dump_addr[i].start;
2275 reg <= iwl_prph_dump_addr[i].end;
2276 reg += 4)
2277 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2278 reg));
2279 *data = iwl_fw_error_next_data(*data);
2280 }
2281
2282 iwl_trans_release_nic_access(trans, &flags);
2283
2284 return prph_len;
2285}
2286
bd7fc617
EG		 2287static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2288 struct iwl_fw_error_dump_data **data,
2289 int allocated_rb_nums)
2290{
2291 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2292 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2293 struct iwl_rxq *rxq = &trans_pcie->rxq;
2294 u32 i, r, j, rb_len = 0;
2295
2296 spin_lock(&rxq->lock);
2297
2298 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2299
2300 for (i = rxq->read, j = 0;
2301 i != r && j < allocated_rb_nums;
2302 i = (i + 1) & RX_QUEUE_MASK, j++) {
2303 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2304 struct iwl_fw_error_dump_rb *rb;
2305
2306 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2307 DMA_FROM_DEVICE);
2308
2309 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2310
2311 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2312 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2313 rb = (void *)(*data)->data;
2314 rb->index = cpu_to_le32(i);
2315 memcpy(rb->data, page_address(rxb->page), max_len);
2316 /* remap the page for the free benefit */
2317 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2318 max_len,
2319 DMA_FROM_DEVICE);
2320
2321 *data = iwl_fw_error_next_data(*data);
2322 }
2323
2324 spin_unlock(&rxq->lock);
2325
2326 return rb_len;
2327}
473ad712
EG		 2328#define IWL_CSR_TO_DUMP (0x250)
2329
2330static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2331 struct iwl_fw_error_dump_data **data)
2332{
2333 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2334 __le32 *val;
2335 int i;
2336
2337 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2338 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2339 val = (void *)(*data)->data;
2340
2341 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2342 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2343
2344 *data = iwl_fw_error_next_data(*data);
2345
2346 return csr_len;
2347}
2348
06d51e0d
LK		 2349static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2350 struct iwl_fw_error_dump_data **data)
2351{
2352 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2353 unsigned long flags;
2354 __le32 *val;
2355 int i;
2356
2357 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2358 return 0;
2359
2360 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2361 (*data)->len = cpu_to_le32(fh_regs_len);
2362 val = (void *)(*data)->data;
2363
2364 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2365 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2366
2367 iwl_trans_release_nic_access(trans, &flags);
2368
2369 *data = iwl_fw_error_next_data(*data);
2370
2371 return sizeof(**data) + fh_regs_len;
2372}
2373
cc79ef66
LK		 2374static u32
2375iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2376 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2377 u32 monitor_len)
2378{
2379 u32 buf_size_in_dwords = (monitor_len >> 2);
2380 u32 *buffer = (u32 *)fw_mon_data->data;
2381 unsigned long flags;
2382 u32 i;
2383
2384 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2385 return 0;
2386
2387 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2388 for (i = 0; i < buf_size_in_dwords; i++)
2389 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2390 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2391
2392 iwl_trans_release_nic_access(trans, &flags);
2393
2394 return monitor_len;
2395}
2396
36fb9017
OG		 2397static u32
2398iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2399 struct iwl_fw_error_dump_data **data,
2400 u32 monitor_len)
2401{
2402 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2403 u32 len = 0;
2404
2405 if ((trans_pcie->fw_mon_page &&
2406 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2407 trans->dbg_dest_tlv) {
2408 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2409 u32 base, write_ptr, wrap_cnt;
2410
2411 /* If there was a dest TLV - use the values from there */
2412 if (trans->dbg_dest_tlv) {
2413 write_ptr =
2414 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2415 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2416 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2417 } else {
2418 base = MON_BUFF_BASE_ADDR;
2419 write_ptr = MON_BUFF_WRPTR;
2420 wrap_cnt = MON_BUFF_CYCLE_CNT;
2421 }
2422
2423 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2424 fw_mon_data = (void *)(*data)->data;
2425 fw_mon_data->fw_mon_wr_ptr =
2426 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2427 fw_mon_data->fw_mon_cycle_cnt =
2428 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2429 fw_mon_data->fw_mon_base_ptr =
2430 cpu_to_le32(iwl_read_prph(trans, base));
2431
2432 len += sizeof(**data) + sizeof(*fw_mon_data);
2433 if (trans_pcie->fw_mon_page) {
2434 /*
2435 * The firmware is now asserted, it won't write anything
2436 * to the buffer. CPU can take ownership to fetch the
2437 * data. The buffer will be handed back to the device
2438 * before the firmware will be restarted.
2439 */
2440 dma_sync_single_for_cpu(trans->dev,
2441 trans_pcie->fw_mon_phys,
2442 trans_pcie->fw_mon_size,
2443 DMA_FROM_DEVICE);
2444 memcpy(fw_mon_data->data,
2445 page_address(trans_pcie->fw_mon_page),
2446 trans_pcie->fw_mon_size);
2447
2448 monitor_len = trans_pcie->fw_mon_size;
2449 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2450 /*
2451 * Update pointers to reflect actual values after
2452 * shifting
2453 */
2454 base = iwl_read_prph(trans, base) <<
2455 trans->dbg_dest_tlv->base_shift;
2456 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2457 monitor_len / sizeof(u32));
2458 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2459 monitor_len =
2460 iwl_trans_pci_dump_marbh_monitor(trans,
2461 fw_mon_data,
2462 monitor_len);
2463 } else {
2464 /* Didn't match anything - output no monitor data */
2465 monitor_len = 0;
2466 }
2467
2468 len += monitor_len;
2469 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2470 }
2471
2472 return len;
2473}
2474
2475static struct iwl_trans_dump_data
2476*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2477 struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2478{
2479 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2480 struct iwl_fw_error_dump_data *data;
2481 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2482 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2483 struct iwl_trans_dump_data *dump_data;
bd7fc617 2484 u32 len, num_rbs;
99684ae3 2485 u32 monitor_len;
4d075007 2486 int i, ptr;
bd7fc617 2487 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status);
4d075007 2488
473ad712
EG		 2489 /* transport dump header */
2490 len = sizeof(*dump_data);
2491
2492 /* host commands */
2493 len += sizeof(*data) +
c2d20201
EG		 2494 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2495
473ad712 2496 /* FW monitor */
99684ae3 2497 if (trans_pcie->fw_mon_page) {
c544e9c4 2498 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2499 trans_pcie->fw_mon_size;
2500 monitor_len = trans_pcie->fw_mon_size;
2501 } else if (trans->dbg_dest_tlv) {
2502 u32 base, end;
2503
2504 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2505 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2506
2507 base = iwl_read_prph(trans, base) <<
2508 trans->dbg_dest_tlv->base_shift;
2509 end = iwl_read_prph(trans, end) <<
2510 trans->dbg_dest_tlv->end_shift;
2511
2512 /* Make "end" point to the actual end */
cc79ef66
LK		 2513 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2514 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2515 end += (1 << trans->dbg_dest_tlv->end_shift);
2516 monitor_len = end - base;
2517 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2518 monitor_len;
2519 } else {
2520 monitor_len = 0;
2521 }
c2d20201 2522
36fb9017
OG		 2523 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2524 dump_data = vzalloc(len);
2525 if (!dump_data)
2526 return NULL;
2527
2528 data = (void *)dump_data->data;
2529 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2530 dump_data->len = len;
2531
2532 return dump_data;
2533 }
2534
2535 /* CSR registers */
2536 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2537
2538 /* PRPH registers */
2539 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2540 /* The range includes both boundaries */
2541 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2542 iwl_prph_dump_addr[i].start + 4;
2543
2544 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2545 num_bytes_in_chunk;
2546 }
2547
2548 /* FH registers */
2549 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2550
2551 if (dump_rbs) {
2552 /* RBs */
2553 num_rbs = le16_to_cpu(ACCESS_ONCE(
2554 trans_pcie->rxq.rb_stts->closed_rb_num))
2555 & 0x0FFF;
2556 num_rbs = (num_rbs - trans_pcie->rxq.read) & RX_QUEUE_MASK;
2557 len += num_rbs * (sizeof(*data) +
2558 sizeof(struct iwl_fw_error_dump_rb) +
2559 (PAGE_SIZE << trans_pcie->rx_page_order));
2560 }
2561
48eb7b34
EG		 2562 dump_data = vzalloc(len);
2563 if (!dump_data)
2564 return NULL;
4d075007
JB		 2565
2566 len = 0;
48eb7b34 2567 data = (void *)dump_data->data;
4d075007
JB		 2568 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2569 txcmd = (void *)data->data;
2570 spin_lock_bh(&cmdq->lock);
2571 ptr = cmdq->q.write_ptr;
2572 for (i = 0; i < cmdq->q.n_window; i++) {
2573 u8 idx = get_cmd_index(&cmdq->q, ptr);
2574 u32 caplen, cmdlen;
2575
2576 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2577 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2578
2579 if (cmdlen) {
2580 len += sizeof(*txcmd) + caplen;
2581 txcmd->cmdlen = cpu_to_le32(cmdlen);
2582 txcmd->caplen = cpu_to_le32(caplen);
2583 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2584 txcmd = (void *)((u8 *)txcmd->data + caplen);
2585 }
2586
2587 ptr = iwl_queue_dec_wrap(ptr);
2588 }
2589 spin_unlock_bh(&cmdq->lock);
2590
2591 data->len = cpu_to_le32(len);
c2d20201 2592 len += sizeof(*data);
67c65f2c
EG		 2593 data = iwl_fw_error_next_data(data);
2594
2595 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2596 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2597 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2598 if (dump_rbs)
2599 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2600
36fb9017 2601 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2602
48eb7b34
EG		 2603 dump_data->len = len;
2604
2605 return dump_data;
4d075007 2606}
87e5666c 2607
d1ff5253 2608static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2609 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2610 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2611 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2612 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2613 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2614
ddaf5a5b
JB		 2615 .d3_suspend = iwl_trans_pcie_d3_suspend,
2616 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2617
f02831be 2618 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2619
e6bb4c9c 2620 .tx = iwl_trans_pcie_tx,
a0eaad71 2621 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2622
d0624be6 2623 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2624 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2625
87e5666c 2626 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2627
990aa6d7 2628 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2629 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
5f178cd2 2630
03905495
EG		 2631 .write8 = iwl_trans_pcie_write8,
2632 .write32 = iwl_trans_pcie_write32,
2633 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2634 .read_prph = iwl_trans_pcie_read_prph,
2635 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2636 .read_mem = iwl_trans_pcie_read_mem,
2637 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2638 .configure = iwl_trans_pcie_configure,
47107e84 2639 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2640 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2641 .release_nic_access = iwl_trans_pcie_release_nic_access,
2642 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2643
7616f334
EP		 2644 .ref = iwl_trans_pcie_ref,
2645 .unref = iwl_trans_pcie_unref,
2646
4d075007 2647 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2648};
a42a1844 2649
87ce05a2 2650struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2651 const struct pci_device_id *ent,
2652 const struct iwl_cfg *cfg)
a42a1844 2653{
a42a1844
EG		 2654 struct iwl_trans_pcie *trans_pcie;
2655 struct iwl_trans *trans;
2656 u16 pci_cmd;
af3f2f74 2657 int ret;
a42a1844 2658
7b501d10
JB		 2659 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2660 &pdev->dev, cfg, &trans_ops_pcie, 0);
2661 if (!trans)
2662 return ERR_PTR(-ENOMEM);
a42a1844 2663
206eea78
JB		 2664 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2665
a42a1844
EG		 2666 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2667
a42a1844 2668 trans_pcie->trans = trans;
7b11488f 2669 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2670 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2671 spin_lock_init(&trans_pcie->ref_lock);
fa9f3281 2672 mutex_init(&trans_pcie->mutex);
13df1aab 2673 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2674
af3f2f74
EG		 2675 ret = pci_enable_device(pdev);
2676 if (ret)
d819c6cf
JB		 2677 goto out_no_pci;
2678
f2532b04
EG		 2679 if (!cfg->base_params->pcie_l1_allowed) {
2680 /*
2681 * W/A - seems to solve weird behavior. We need to remove this
2682 * if we don't want to stay in L1 all the time. This wastes a
2683 * lot of power.
2684 */
2685 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2686 PCIE_LINK_STATE_L1 |
2687 PCIE_LINK_STATE_CLKPM);
2688 }
a42a1844 2689
a42a1844
EG		 2690 pci_set_master(pdev);
2691
af3f2f74
EG		 2692 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2693 if (!ret)
2694 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2695 if (ret) {
2696 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2697 if (!ret)
2698 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2699 DMA_BIT_MASK(32));
a42a1844 2700 /* both attempts failed: */
af3f2f74 2701 if (ret) {
6a4b09f8 2702 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2703 goto out_pci_disable_device;
2704 }
2705 }
2706
af3f2f74
EG		 2707 ret = pci_request_regions(pdev, DRV_NAME);
2708 if (ret) {
6a4b09f8 2709 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2710 goto out_pci_disable_device;
2711 }
2712
05f5b97e 2713 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2714 if (!trans_pcie->hw_base) {
6a4b09f8 2715 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
af3f2f74 2716 ret = -ENODEV;
a42a1844
EG		 2717 goto out_pci_release_regions;
2718 }
2719
a42a1844
EG		 2720 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2721 * PCI Tx retries from interfering with C3 CPU state */
2722 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2723
83f7a85f
EG		 2724 trans->dev = &pdev->dev;
2725 trans_pcie->pci_dev = pdev;
2726 iwl_disable_interrupts(trans);
2727
af3f2f74
EG		 2728 ret = pci_enable_msi(pdev);
2729 if (ret) {
2730 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
9f904b38
EG		 2731 /* enable rfkill interrupt: hw bug w/a */
2732 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2733 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2734 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2735 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2736 }
2737 }
a42a1844 2738
08079a49 2739 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2740 /*
2741 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2742 * changed, and now the revision step also includes bit 0-1 (no more
2743 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2744 * in the old format.
2745 */
7a42baa6
EH		 2746 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2747 unsigned long flags;
7a42baa6 2748
b513ee7f 2749 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2750 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2751
f9e5554c
EG		 2752 ret = iwl_pcie_prepare_card_hw(trans);
2753 if (ret) {
2754 IWL_WARN(trans, "Exit HW not ready\n");
2755 goto out_pci_disable_msi;
2756 }
2757
7a42baa6
EH		 2758 /*
2759 * in-order to recognize C step driver should read chip version
2760 * id located at the AUX bus MISC address space.
2761 */
2762 iwl_set_bit(trans, CSR_GP_CNTRL,
2763 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2764 udelay(2);
2765
2766 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2767 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2768 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2769 25000);
2770 if (ret < 0) {
2771 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2772 goto out_pci_disable_msi;
2773 }
2774
2775 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2776 u32 hw_step;
2777
2778 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2779 hw_step |= ENABLE_WFPM;
2780 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2781 hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2782 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2783 if (hw_step == 0x3)
2784 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2785 (SILICON_C_STEP << 2);
2786 iwl_trans_release_nic_access(trans, &flags);
2787 }
2788 }
2789
99673ee5 2790 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2791 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2792 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2793
69a10b29 2794 /* Initialize the wait queue for commands */
f946b529 2795 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2796
af3f2f74
EG		 2797 ret = iwl_pcie_alloc_ict(trans);
2798 if (ret)
7b501d10 2799 goto out_pci_disable_msi;
a8b691e6 2800
af3f2f74 2801 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2802 iwl_pcie_irq_handler,
2803 IRQF_SHARED, DRV_NAME, trans);
af3f2f74 2804 if (ret) {
a8b691e6
JB		 2805 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2806 goto out_free_ict;
2807 }
2808
83f7a85f 2809 trans_pcie->inta_mask = CSR_INI_SET_MASK;
6735943f 2810 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
83f7a85f 2811
a42a1844
EG		 2812 return trans;
2813
a8b691e6
JB		 2814out_free_ict:
2815 iwl_pcie_free_ict(trans);
59c647b6
EG		 2816out_pci_disable_msi:
2817 pci_disable_msi(pdev);
a42a1844
EG		 2818out_pci_release_regions:
2819 pci_release_regions(pdev);
2820out_pci_disable_device:
2821 pci_disable_device(pdev);
2822out_no_pci:
7b501d10 2823 iwl_trans_free(trans);
af3f2f74 2824 return ERR_PTR(ret);
a42a1844 2825}
Linux kernel - Deliverables
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