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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
4e318262 | 8 | * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
4e318262 | 33 | * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
82575102 | 71 | #include "iwl-drv.h" |
c85eb619 | 72 | #include "iwl-trans.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
7a10e3e4 | 75 | #include "iwl-agn-hw.h" |
6468a01a | 76 | #include "internal.h" |
02aca585 | 77 | |
7afe3705 | 78 | static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans) |
392f8b78 EG |
79 | { |
80 | /* | |
81 | * (for documentation purposes) | |
82 | * to set power to V_AUX, do: | |
83 | ||
84 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
1042db2a | 85 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
86 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
87 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
88 | */ | |
89 | ||
1042db2a | 90 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
91 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
92 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
93 | } | |
94 | ||
af634bee EG |
95 | /* PCI registers */ |
96 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
97 | #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 | |
98 | #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 | |
99 | ||
7afe3705 | 100 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 101 | { |
20d3b647 | 102 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 103 | u16 lctl; |
af634bee | 104 | |
af634bee EG |
105 | /* |
106 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
107 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
108 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
109 | * costs negligible amount of power savings. | |
110 | * If not (unlikely), enable L0S, so there is at least some | |
111 | * power savings, even without L1. | |
112 | */ | |
7afe3705 | 113 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
af634bee EG |
114 | |
115 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == | |
116 | PCI_CFG_LINK_CTRL_VAL_L1_EN) { | |
117 | /* L1-ASPM enabled; disable(!) L0S */ | |
118 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
119 | dev_printk(KERN_INFO, trans->dev, | |
120 | "L1 Enabled; Disabling L0S\n"); | |
121 | } else { | |
122 | /* L1-ASPM disabled; enable(!) L0S */ | |
123 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
124 | dev_printk(KERN_INFO, trans->dev, | |
125 | "L1 Disabled; Enabling L0S\n"); | |
126 | } | |
f6d0e9be | 127 | trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); |
af634bee EG |
128 | } |
129 | ||
a6c684ee EG |
130 | /* |
131 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 132 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
133 | * NOTE: This does not load uCode nor start the embedded processor |
134 | */ | |
7afe3705 | 135 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee | 136 | { |
83626404 | 137 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a6c684ee EG |
138 | int ret = 0; |
139 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
140 | ||
141 | /* | |
142 | * Use "set_bit" below rather than "write", to preserve any hardware | |
143 | * bits already set by default after reset. | |
144 | */ | |
145 | ||
146 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
147 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 148 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
a6c684ee EG |
149 | |
150 | /* | |
151 | * Disable L0s without affecting L1; | |
152 | * don't wait for ICH L0s (ICH bug W/A) | |
153 | */ | |
154 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 155 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
156 | |
157 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
158 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
159 | ||
160 | /* | |
161 | * Enable HAP INTA (interrupt from management bus) to | |
162 | * wake device's PCI Express link L1a -> L0s | |
163 | */ | |
164 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 165 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 166 | |
7afe3705 | 167 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
168 | |
169 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 170 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 171 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 172 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
173 | |
174 | /* | |
175 | * Set "initialization complete" bit to move adapter from | |
176 | * D0U* --> D0A* (powered-up active) state. | |
177 | */ | |
178 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
179 | ||
180 | /* | |
181 | * Wait for clock stabilization; once stabilized, access to | |
182 | * device-internal resources is supported, e.g. iwl_write_prph() | |
183 | * and accesses to uCode SRAM. | |
184 | */ | |
185 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
186 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
187 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
188 | if (ret < 0) { |
189 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
190 | goto out; | |
191 | } | |
192 | ||
193 | /* | |
194 | * Enable DMA clock and wait for it to stabilize. | |
195 | * | |
196 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
197 | * do not disable clocks. This preserves any hardware bits already | |
198 | * set by default in "CLK_CTRL_REG" after reset. | |
199 | */ | |
200 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
201 | udelay(20); | |
202 | ||
203 | /* Disable L1-Active */ | |
204 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
205 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
206 | ||
83626404 | 207 | set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
a6c684ee EG |
208 | |
209 | out: | |
210 | return ret; | |
211 | } | |
212 | ||
7afe3705 | 213 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
214 | { |
215 | int ret = 0; | |
216 | ||
217 | /* stop device's busmaster DMA activity */ | |
218 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
219 | ||
220 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
221 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
222 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
cc56feb2 EG |
223 | if (ret) |
224 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
225 | ||
226 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
7afe3705 | 231 | static void iwl_pcie_apm_stop(struct iwl_trans *trans) |
cc56feb2 | 232 | { |
83626404 | 233 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cc56feb2 EG |
234 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); |
235 | ||
83626404 | 236 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
cc56feb2 EG |
237 | |
238 | /* Stop device's DMA activity */ | |
7afe3705 | 239 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 EG |
240 | |
241 | /* Reset the entire device */ | |
242 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
243 | ||
244 | udelay(10); | |
245 | ||
246 | /* | |
247 | * Clear "initialization complete" bit to move adapter from | |
248 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
249 | */ | |
250 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
251 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
252 | } | |
253 | ||
7afe3705 | 254 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 255 | { |
7b11488f | 256 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
257 | unsigned long flags; |
258 | ||
259 | /* nic_init */ | |
7b11488f | 260 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
7afe3705 | 261 | iwl_pcie_apm_init(trans); |
392f8b78 EG |
262 | |
263 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
20d3b647 | 264 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
392f8b78 | 265 | |
7b11488f | 266 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 267 | |
7afe3705 | 268 | iwl_pcie_set_pwr_vmain(trans); |
392f8b78 | 269 | |
ecdb975c | 270 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
271 | |
272 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 273 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
274 | |
275 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 276 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
277 | return -ENOMEM; |
278 | ||
035f7ff2 | 279 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 280 | /* enable shadow regs in HW */ |
20d3b647 | 281 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 282 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
283 | } |
284 | ||
392f8b78 EG |
285 | return 0; |
286 | } | |
287 | ||
288 | #define HW_READY_TIMEOUT (50) | |
289 | ||
290 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 291 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
292 | { |
293 | int ret; | |
294 | ||
1042db2a | 295 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 296 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
297 | |
298 | /* See if we got it */ | |
1042db2a | 299 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
300 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
301 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
302 | HW_READY_TIMEOUT); | |
392f8b78 | 303 | |
6d8f6eeb | 304 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
305 | return ret; |
306 | } | |
307 | ||
308 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 309 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
310 | { |
311 | int ret; | |
289e5501 | 312 | int t = 0; |
392f8b78 | 313 | |
6d8f6eeb | 314 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 315 | |
7afe3705 | 316 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 317 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
318 | if (ret >= 0) |
319 | return 0; | |
320 | ||
321 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 322 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 323 | CSR_HW_IF_CONFIG_REG_PREPARE); |
392f8b78 | 324 | |
289e5501 | 325 | do { |
7afe3705 | 326 | ret = iwl_pcie_set_hw_ready(trans); |
289e5501 EG |
327 | if (ret >= 0) |
328 | return 0; | |
392f8b78 | 329 | |
289e5501 EG |
330 | usleep_range(200, 1000); |
331 | t += 200; | |
332 | } while (t < 150000); | |
392f8b78 | 333 | |
392f8b78 EG |
334 | return ret; |
335 | } | |
336 | ||
cf614297 EG |
337 | /* |
338 | * ucode | |
339 | */ | |
7afe3705 | 340 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 341 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 342 | { |
13df1aab | 343 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
344 | int ret; |
345 | ||
13df1aab | 346 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
347 | |
348 | iwl_write_direct32(trans, | |
20d3b647 JB |
349 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
350 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
351 | |
352 | iwl_write_direct32(trans, | |
20d3b647 JB |
353 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
354 | dst_addr); | |
cf614297 EG |
355 | |
356 | iwl_write_direct32(trans, | |
83f84d7b JB |
357 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
358 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
359 | |
360 | iwl_write_direct32(trans, | |
20d3b647 JB |
361 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
362 | (iwl_get_dma_hi_addr(phy_addr) | |
363 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
364 | |
365 | iwl_write_direct32(trans, | |
20d3b647 JB |
366 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
367 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
368 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
369 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
370 | |
371 | iwl_write_direct32(trans, | |
20d3b647 JB |
372 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
373 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
374 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
375 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 376 | |
13df1aab JB |
377 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
378 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 379 | if (!ret) { |
83f84d7b | 380 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
381 | return -ETIMEDOUT; |
382 | } | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
7afe3705 | 387 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 388 | const struct fw_desc *section) |
cf614297 | 389 | { |
83f84d7b JB |
390 | u8 *v_addr; |
391 | dma_addr_t p_addr; | |
392 | u32 offset; | |
cf614297 EG |
393 | int ret = 0; |
394 | ||
83f84d7b JB |
395 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
396 | section_num); | |
397 | ||
398 | v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL); | |
399 | if (!v_addr) | |
400 | return -ENOMEM; | |
401 | ||
402 | for (offset = 0; offset < section->len; offset += PAGE_SIZE) { | |
403 | u32 copy_size; | |
404 | ||
405 | copy_size = min_t(u32, PAGE_SIZE, section->len - offset); | |
cf614297 | 406 | |
83f84d7b | 407 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
7afe3705 EG |
408 | ret = iwl_pcie_load_firmware_chunk(trans, |
409 | section->offset + offset, | |
410 | p_addr, copy_size); | |
83f84d7b JB |
411 | if (ret) { |
412 | IWL_ERR(trans, | |
413 | "Could not load the [%d] uCode section\n", | |
414 | section_num); | |
415 | break; | |
6dfa8d01 | 416 | } |
83f84d7b JB |
417 | } |
418 | ||
419 | dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr); | |
420 | return ret; | |
421 | } | |
422 | ||
7afe3705 | 423 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 424 | const struct fw_img *image) |
cf614297 | 425 | { |
2d1c0044 | 426 | int i, ret = 0; |
cf614297 | 427 | |
2d1c0044 | 428 | for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) { |
83f84d7b | 429 | if (!image->sec[i].data) |
2d1c0044 | 430 | break; |
cf614297 | 431 | |
7afe3705 | 432 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
2d1c0044 JB |
433 | if (ret) |
434 | return ret; | |
435 | } | |
cf614297 EG |
436 | |
437 | /* Remove all resets to allow NIC to operate */ | |
438 | iwl_write32(trans, CSR_RESET, 0); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
0692fe41 JB |
443 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
444 | const struct fw_img *fw) | |
392f8b78 | 445 | { |
d18aa87f | 446 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 | 447 | int ret; |
c9eec95c | 448 | bool hw_rfkill; |
392f8b78 | 449 | |
496bab39 | 450 | /* This may fail if AMT took ownership of the device */ |
7afe3705 | 451 | if (iwl_pcie_prepare_card_hw(trans)) { |
6d8f6eeb | 452 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
453 | return -EIO; |
454 | } | |
455 | ||
d18aa87f JB |
456 | clear_bit(STATUS_FW_ERROR, &trans_pcie->status); |
457 | ||
8c46bb70 EG |
458 | iwl_enable_rfkill_int(trans); |
459 | ||
392f8b78 | 460 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 461 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 462 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8c46bb70 | 463 | if (hw_rfkill) |
392f8b78 | 464 | return -ERFKILL; |
392f8b78 | 465 | |
1042db2a | 466 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 467 | |
7afe3705 | 468 | ret = iwl_pcie_nic_init(trans); |
392f8b78 | 469 | if (ret) { |
6d8f6eeb | 470 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
471 | return ret; |
472 | } | |
473 | ||
474 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
475 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
476 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
477 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
478 | ||
479 | /* clear (again), then enable host interrupts */ | |
1042db2a | 480 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 481 | iwl_enable_interrupts(trans); |
392f8b78 EG |
482 | |
483 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
484 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
485 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 486 | |
cf614297 | 487 | /* Load the given image to the HW */ |
7afe3705 | 488 | return iwl_pcie_load_given_ucode(trans, fw); |
392f8b78 EG |
489 | } |
490 | ||
adca1235 | 491 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 492 | { |
990aa6d7 | 493 | iwl_pcie_reset_ict(trans); |
f02831be | 494 | iwl_pcie_tx_start(trans, scd_addr); |
c170b867 EG |
495 | } |
496 | ||
43e58856 | 497 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 498 | { |
43e58856 | 499 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
20d3b647 | 500 | unsigned long flags; |
ae2c30bf | 501 | |
43e58856 | 502 | /* tell the device to stop sending interrupts */ |
7b11488f | 503 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 504 | iwl_disable_interrupts(trans); |
7b11488f | 505 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 506 | |
ab6cf8e8 | 507 | /* device going down, Stop using ICT table */ |
990aa6d7 | 508 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
509 | |
510 | /* | |
511 | * If a HW restart happens during firmware loading, | |
512 | * then the firmware loading might call this function | |
513 | * and later it might be called again due to the | |
514 | * restart. So don't process again if the device is | |
515 | * already dead. | |
516 | */ | |
83626404 | 517 | if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) { |
f02831be | 518 | iwl_pcie_tx_stop(trans); |
9805c446 | 519 | iwl_pcie_rx_stop(trans); |
6379103e | 520 | |
ab6cf8e8 | 521 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 522 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
523 | APMG_CLK_VAL_DMA_CLK_RQT); |
524 | udelay(5); | |
525 | } | |
526 | ||
527 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 528 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 529 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
530 | |
531 | /* Stop the device, and put it in low power state */ | |
7afe3705 | 532 | iwl_pcie_apm_stop(trans); |
43e58856 EG |
533 | |
534 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
535 | * Clean again the interrupt here | |
536 | */ | |
7b11488f | 537 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 538 | iwl_disable_interrupts(trans); |
7b11488f | 539 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 | 540 | |
218733cf EG |
541 | iwl_enable_rfkill_int(trans); |
542 | ||
43e58856 | 543 | /* wait to make sure we flush pending tasklet*/ |
75595536 | 544 | synchronize_irq(trans_pcie->irq); |
43e58856 EG |
545 | tasklet_kill(&trans_pcie->irq_tasklet); |
546 | ||
1ee158d8 JB |
547 | cancel_work_sync(&trans_pcie->rx_replenish); |
548 | ||
43e58856 | 549 | /* stop and reset the on-board processor */ |
1042db2a | 550 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
74fda971 DF |
551 | |
552 | /* clear all status bits */ | |
553 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); | |
554 | clear_bit(STATUS_INT_ENABLED, &trans_pcie->status); | |
555 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); | |
01d651d4 | 556 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
f946b529 | 557 | clear_bit(STATUS_RFKILL, &trans_pcie->status); |
ab6cf8e8 EG |
558 | } |
559 | ||
2dd4f9f7 JB |
560 | static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans) |
561 | { | |
562 | /* let the ucode operate on its own */ | |
563 | iwl_write32(trans, CSR_UCODE_DRV_GP1_SET, | |
564 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
565 | ||
566 | iwl_disable_interrupts(trans); | |
567 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
568 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
569 | } | |
570 | ||
57a1dc89 | 571 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 572 | { |
20d3b647 | 573 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e6bb4c9c | 574 | int err; |
c9eec95c | 575 | bool hw_rfkill; |
e6bb4c9c | 576 | |
0c325769 EG |
577 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
578 | ||
57a1dc89 EG |
579 | if (!trans_pcie->irq_requested) { |
580 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
990aa6d7 | 581 | iwl_pcie_tasklet, (unsigned long)trans); |
e6bb4c9c | 582 | |
990aa6d7 | 583 | iwl_pcie_alloc_ict(trans); |
e6bb4c9c | 584 | |
990aa6d7 EG |
585 | err = request_irq(trans_pcie->irq, iwl_pcie_isr_ict, |
586 | IRQF_SHARED, DRV_NAME, trans); | |
57a1dc89 EG |
587 | if (err) { |
588 | IWL_ERR(trans, "Error allocating IRQ %d\n", | |
75595536 | 589 | trans_pcie->irq); |
ebb7678d | 590 | goto error; |
57a1dc89 EG |
591 | } |
592 | ||
57a1dc89 | 593 | trans_pcie->irq_requested = true; |
e6bb4c9c EG |
594 | } |
595 | ||
7afe3705 | 596 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 597 | if (err) { |
d6f1c316 | 598 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
f057ac4e | 599 | goto err_free_irq; |
ebb7678d | 600 | } |
a6c684ee | 601 | |
7afe3705 | 602 | iwl_pcie_apm_init(trans); |
a6c684ee | 603 | |
226c02ca EG |
604 | /* From now on, the op_mode will be kept updated about RF kill state */ |
605 | iwl_enable_rfkill_int(trans); | |
606 | ||
8d425517 | 607 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 608 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
d48e2074 | 609 | |
ebb7678d EG |
610 | return err; |
611 | ||
f057ac4e | 612 | err_free_irq: |
a7be50b7 | 613 | trans_pcie->irq_requested = false; |
75595536 | 614 | free_irq(trans_pcie->irq, trans); |
ebb7678d | 615 | error: |
990aa6d7 | 616 | iwl_pcie_free_ict(trans); |
ebb7678d EG |
617 | tasklet_kill(&trans_pcie->irq_tasklet); |
618 | return err; | |
e6bb4c9c EG |
619 | } |
620 | ||
218733cf EG |
621 | static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans, |
622 | bool op_mode_leaving) | |
cc56feb2 | 623 | { |
20d3b647 | 624 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 625 | bool hw_rfkill; |
218733cf | 626 | unsigned long flags; |
d23f78e6 | 627 | |
ee7d737c DS |
628 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
629 | iwl_disable_interrupts(trans); | |
630 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
631 | ||
7afe3705 | 632 | iwl_pcie_apm_stop(trans); |
cc56feb2 | 633 | |
218733cf EG |
634 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
635 | iwl_disable_interrupts(trans); | |
636 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1df06bdc | 637 | |
218733cf EG |
638 | if (!op_mode_leaving) { |
639 | /* | |
640 | * Even if we stop the HW, we still want the RF kill | |
641 | * interrupt | |
642 | */ | |
643 | iwl_enable_rfkill_int(trans); | |
644 | ||
645 | /* | |
646 | * Check again since the RF kill state may have changed while | |
647 | * all the interrupts were disabled, in this case we couldn't | |
648 | * receive the RF kill interrupt and update the state in the | |
649 | * op_mode. | |
650 | */ | |
651 | hw_rfkill = iwl_is_rfkill_set(trans); | |
652 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
653 | } | |
cc56feb2 EG |
654 | } |
655 | ||
03905495 EG |
656 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
657 | { | |
05f5b97e | 658 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
659 | } |
660 | ||
661 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
662 | { | |
05f5b97e | 663 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
664 | } |
665 | ||
666 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
667 | { | |
05f5b97e | 668 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
669 | } |
670 | ||
6a06b6c1 EG |
671 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
672 | { | |
673 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); | |
674 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); | |
675 | } | |
676 | ||
677 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
678 | u32 val) | |
679 | { | |
680 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
681 | ((addr & 0x0000FFFF) | (3 << 24))); | |
682 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); | |
683 | } | |
684 | ||
c6f600fc | 685 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 686 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
687 | { |
688 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
689 | ||
690 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 691 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
d663ee73 JB |
692 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
693 | trans_pcie->n_no_reclaim_cmds = 0; | |
694 | else | |
695 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
696 | if (trans_pcie->n_no_reclaim_cmds) | |
697 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
698 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 699 | |
b2cf410c JB |
700 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
701 | if (trans_pcie->rx_buf_size_8k) | |
702 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
703 | else | |
704 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
705 | |
706 | trans_pcie->wd_timeout = | |
707 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
708 | |
709 | trans_pcie->command_names = trans_cfg->command_names; | |
c6f600fc MV |
710 | } |
711 | ||
d1ff5253 | 712 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 713 | { |
20d3b647 | 714 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 715 | |
f02831be | 716 | iwl_pcie_tx_free(trans); |
9805c446 | 717 | iwl_pcie_rx_free(trans); |
6379103e | 718 | |
57a1dc89 | 719 | if (trans_pcie->irq_requested == true) { |
75595536 | 720 | free_irq(trans_pcie->irq, trans); |
990aa6d7 | 721 | iwl_pcie_free_ict(trans); |
57a1dc89 | 722 | } |
a42a1844 EG |
723 | |
724 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 725 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
726 | pci_release_regions(trans_pcie->pci_dev); |
727 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 728 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 729 | |
6d8f6eeb | 730 | kfree(trans); |
34c1b7ba EG |
731 | } |
732 | ||
47107e84 DF |
733 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
734 | { | |
735 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
736 | ||
737 | if (state) | |
01d651d4 | 738 | set_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 | 739 | else |
01d651d4 | 740 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 DF |
741 | } |
742 | ||
c01a4047 | 743 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
744 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
745 | { | |
57210f7c EG |
746 | return 0; |
747 | } | |
748 | ||
749 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
750 | { | |
c9eec95c | 751 | bool hw_rfkill; |
57210f7c | 752 | |
8c46bb70 EG |
753 | iwl_enable_rfkill_int(trans); |
754 | ||
8d425517 | 755 | hw_rfkill = iwl_is_rfkill_set(trans); |
8c46bb70 | 756 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8722c899 | 757 | |
8c46bb70 | 758 | if (!hw_rfkill) |
8722c899 SG |
759 | iwl_enable_interrupts(trans); |
760 | ||
57210f7c EG |
761 | return 0; |
762 | } | |
c01a4047 | 763 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 764 | |
5f178cd2 EG |
765 | #define IWL_FLUSH_WAIT_MS 2000 |
766 | ||
990aa6d7 | 767 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans) |
5f178cd2 | 768 | { |
8ad71bef | 769 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 770 | struct iwl_txq *txq; |
5f178cd2 EG |
771 | struct iwl_queue *q; |
772 | int cnt; | |
773 | unsigned long now = jiffies; | |
774 | int ret = 0; | |
775 | ||
776 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 777 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
9ba1947a | 778 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 779 | continue; |
8ad71bef | 780 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
781 | q = &txq->q; |
782 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
783 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
784 | msleep(1); | |
785 | ||
786 | if (q->read_ptr != q->write_ptr) { | |
787 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); | |
788 | ret = -ETIMEDOUT; | |
789 | break; | |
790 | } | |
791 | } | |
792 | return ret; | |
793 | } | |
794 | ||
ff620849 EG |
795 | static const char *get_fh_string(int cmd) |
796 | { | |
d9fb6465 | 797 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
798 | switch (cmd) { |
799 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
800 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
801 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
802 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
803 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
804 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
805 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
806 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
807 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
808 | default: | |
809 | return "UNKNOWN"; | |
810 | } | |
d9fb6465 | 811 | #undef IWL_CMD |
ff620849 EG |
812 | } |
813 | ||
990aa6d7 | 814 | int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf) |
ff620849 EG |
815 | { |
816 | int i; | |
ff620849 EG |
817 | static const u32 fh_tbl[] = { |
818 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
819 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
820 | FH_RSCSR_CHNL0_WPTR, | |
821 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
822 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
823 | FH_MEM_RSSR_RX_STATUS_REG, | |
824 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
825 | FH_TSSR_TX_STATUS_REG, | |
826 | FH_TSSR_TX_ERROR_REG | |
827 | }; | |
94543a8d JB |
828 | |
829 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
830 | if (buf) { | |
831 | int pos = 0; | |
832 | size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
833 | ||
ff620849 EG |
834 | *buf = kmalloc(bufsz, GFP_KERNEL); |
835 | if (!*buf) | |
836 | return -ENOMEM; | |
94543a8d | 837 | |
ff620849 EG |
838 | pos += scnprintf(*buf + pos, bufsz - pos, |
839 | "FH register values:\n"); | |
94543a8d JB |
840 | |
841 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) | |
ff620849 EG |
842 | pos += scnprintf(*buf + pos, bufsz - pos, |
843 | " %34s: 0X%08x\n", | |
844 | get_fh_string(fh_tbl[i]), | |
1042db2a | 845 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 846 | |
ff620849 EG |
847 | return pos; |
848 | } | |
849 | #endif | |
94543a8d | 850 | |
ff620849 | 851 | IWL_ERR(trans, "FH register values:\n"); |
94543a8d | 852 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) |
ff620849 EG |
853 | IWL_ERR(trans, " %34s: 0X%08x\n", |
854 | get_fh_string(fh_tbl[i]), | |
1042db2a | 855 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 856 | |
ff620849 EG |
857 | return 0; |
858 | } | |
859 | ||
860 | static const char *get_csr_string(int cmd) | |
861 | { | |
d9fb6465 | 862 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
863 | switch (cmd) { |
864 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
865 | IWL_CMD(CSR_INT_COALESCING); | |
866 | IWL_CMD(CSR_INT); | |
867 | IWL_CMD(CSR_INT_MASK); | |
868 | IWL_CMD(CSR_FH_INT_STATUS); | |
869 | IWL_CMD(CSR_GPIO_IN); | |
870 | IWL_CMD(CSR_RESET); | |
871 | IWL_CMD(CSR_GP_CNTRL); | |
872 | IWL_CMD(CSR_HW_REV); | |
873 | IWL_CMD(CSR_EEPROM_REG); | |
874 | IWL_CMD(CSR_EEPROM_GP); | |
875 | IWL_CMD(CSR_OTP_GP_REG); | |
876 | IWL_CMD(CSR_GIO_REG); | |
877 | IWL_CMD(CSR_GP_UCODE_REG); | |
878 | IWL_CMD(CSR_GP_DRIVER_REG); | |
879 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
880 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
881 | IWL_CMD(CSR_LED_REG); | |
882 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
883 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
884 | IWL_CMD(CSR_ANA_PLL_CFG); | |
885 | IWL_CMD(CSR_HW_REV_WA_REG); | |
886 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
887 | default: | |
888 | return "UNKNOWN"; | |
889 | } | |
d9fb6465 | 890 | #undef IWL_CMD |
ff620849 EG |
891 | } |
892 | ||
990aa6d7 | 893 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
894 | { |
895 | int i; | |
896 | static const u32 csr_tbl[] = { | |
897 | CSR_HW_IF_CONFIG_REG, | |
898 | CSR_INT_COALESCING, | |
899 | CSR_INT, | |
900 | CSR_INT_MASK, | |
901 | CSR_FH_INT_STATUS, | |
902 | CSR_GPIO_IN, | |
903 | CSR_RESET, | |
904 | CSR_GP_CNTRL, | |
905 | CSR_HW_REV, | |
906 | CSR_EEPROM_REG, | |
907 | CSR_EEPROM_GP, | |
908 | CSR_OTP_GP_REG, | |
909 | CSR_GIO_REG, | |
910 | CSR_GP_UCODE_REG, | |
911 | CSR_GP_DRIVER_REG, | |
912 | CSR_UCODE_DRV_GP1, | |
913 | CSR_UCODE_DRV_GP2, | |
914 | CSR_LED_REG, | |
915 | CSR_DRAM_INT_TBL_REG, | |
916 | CSR_GIO_CHICKEN_BITS, | |
917 | CSR_ANA_PLL_CFG, | |
918 | CSR_HW_REV_WA_REG, | |
919 | CSR_DBG_HPET_MEM_REG | |
920 | }; | |
921 | IWL_ERR(trans, "CSR values:\n"); | |
922 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
923 | "CSR_INT_PERIODIC_REG)\n"); | |
924 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
925 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
926 | get_csr_string(csr_tbl[i]), | |
1042db2a | 927 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
928 | } |
929 | } | |
930 | ||
87e5666c EG |
931 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
932 | /* create and remove of files */ | |
933 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 934 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 935 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 936 | goto err; \ |
87e5666c EG |
937 | } while (0) |
938 | ||
939 | /* file operation */ | |
940 | #define DEBUGFS_READ_FUNC(name) \ | |
941 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
942 | char __user *user_buf, \ | |
943 | size_t count, loff_t *ppos); | |
944 | ||
945 | #define DEBUGFS_WRITE_FUNC(name) \ | |
946 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
947 | const char __user *user_buf, \ | |
948 | size_t count, loff_t *ppos); | |
949 | ||
87e5666c EG |
950 | #define DEBUGFS_READ_FILE_OPS(name) \ |
951 | DEBUGFS_READ_FUNC(name); \ | |
952 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
953 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 954 | .open = simple_open, \ |
87e5666c EG |
955 | .llseek = generic_file_llseek, \ |
956 | }; | |
957 | ||
16db88ba EG |
958 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
959 | DEBUGFS_WRITE_FUNC(name); \ | |
960 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
961 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 962 | .open = simple_open, \ |
16db88ba EG |
963 | .llseek = generic_file_llseek, \ |
964 | }; | |
965 | ||
87e5666c EG |
966 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
967 | DEBUGFS_READ_FUNC(name); \ | |
968 | DEBUGFS_WRITE_FUNC(name); \ | |
969 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
970 | .write = iwl_dbgfs_##name##_write, \ | |
971 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 972 | .open = simple_open, \ |
87e5666c EG |
973 | .llseek = generic_file_llseek, \ |
974 | }; | |
975 | ||
87e5666c | 976 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
977 | char __user *user_buf, |
978 | size_t count, loff_t *ppos) | |
8ad71bef | 979 | { |
5a878bf6 | 980 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 981 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 982 | struct iwl_txq *txq; |
87e5666c EG |
983 | struct iwl_queue *q; |
984 | char *buf; | |
985 | int pos = 0; | |
986 | int cnt; | |
987 | int ret; | |
1745e440 WYG |
988 | size_t bufsz; |
989 | ||
035f7ff2 | 990 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 991 | |
f9e75447 | 992 | if (!trans_pcie->txq) |
87e5666c | 993 | return -EAGAIN; |
f9e75447 | 994 | |
87e5666c EG |
995 | buf = kzalloc(bufsz, GFP_KERNEL); |
996 | if (!buf) | |
997 | return -ENOMEM; | |
998 | ||
035f7ff2 | 999 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1000 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1001 | q = &txq->q; |
1002 | pos += scnprintf(buf + pos, bufsz - pos, | |
9eae88fa | 1003 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", |
87e5666c | 1004 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa JB |
1005 | !!test_bit(cnt, trans_pcie->queue_used), |
1006 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
87e5666c EG |
1007 | } |
1008 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1009 | kfree(buf); | |
1010 | return ret; | |
1011 | } | |
1012 | ||
1013 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1014 | char __user *user_buf, |
1015 | size_t count, loff_t *ppos) | |
1016 | { | |
5a878bf6 | 1017 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1018 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1019 | struct iwl_rxq *rxq = &trans_pcie->rxq; |
87e5666c EG |
1020 | char buf[256]; |
1021 | int pos = 0; | |
1022 | const size_t bufsz = sizeof(buf); | |
1023 | ||
1024 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1025 | rxq->read); | |
1026 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1027 | rxq->write); | |
1028 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1029 | rxq->free_count); | |
1030 | if (rxq->rb_stts) { | |
1031 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1032 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1033 | } else { | |
1034 | pos += scnprintf(buf + pos, bufsz - pos, | |
1035 | "closed_rb_num: Not Allocated\n"); | |
1036 | } | |
1037 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1038 | } | |
1039 | ||
1f7b6172 EG |
1040 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1041 | char __user *user_buf, | |
20d3b647 JB |
1042 | size_t count, loff_t *ppos) |
1043 | { | |
1f7b6172 | 1044 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1045 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1046 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1047 | ||
1048 | int pos = 0; | |
1049 | char *buf; | |
1050 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1051 | ssize_t ret; | |
1052 | ||
1053 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1054 | if (!buf) |
1f7b6172 | 1055 | return -ENOMEM; |
1f7b6172 EG |
1056 | |
1057 | pos += scnprintf(buf + pos, bufsz - pos, | |
1058 | "Interrupt Statistics Report:\n"); | |
1059 | ||
1060 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1061 | isr_stats->hw); | |
1062 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1063 | isr_stats->sw); | |
1064 | if (isr_stats->sw || isr_stats->hw) { | |
1065 | pos += scnprintf(buf + pos, bufsz - pos, | |
1066 | "\tLast Restarting Code: 0x%X\n", | |
1067 | isr_stats->err_code); | |
1068 | } | |
1069 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1070 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1071 | isr_stats->sch); | |
1072 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1073 | isr_stats->alive); | |
1074 | #endif | |
1075 | pos += scnprintf(buf + pos, bufsz - pos, | |
1076 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1077 | ||
1078 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1079 | isr_stats->ctkill); | |
1080 | ||
1081 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1082 | isr_stats->wakeup); | |
1083 | ||
1084 | pos += scnprintf(buf + pos, bufsz - pos, | |
1085 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1086 | ||
1087 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1088 | isr_stats->tx); | |
1089 | ||
1090 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1091 | isr_stats->unhandled); | |
1092 | ||
1093 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1094 | kfree(buf); | |
1095 | return ret; | |
1096 | } | |
1097 | ||
1098 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1099 | const char __user *user_buf, | |
1100 | size_t count, loff_t *ppos) | |
1101 | { | |
1102 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1103 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1104 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1105 | ||
1106 | char buf[8]; | |
1107 | int buf_size; | |
1108 | u32 reset_flag; | |
1109 | ||
1110 | memset(buf, 0, sizeof(buf)); | |
1111 | buf_size = min(count, sizeof(buf) - 1); | |
1112 | if (copy_from_user(buf, user_buf, buf_size)) | |
1113 | return -EFAULT; | |
1114 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1115 | return -EFAULT; | |
1116 | if (reset_flag == 0) | |
1117 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1118 | ||
1119 | return count; | |
1120 | } | |
1121 | ||
16db88ba | 1122 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1123 | const char __user *user_buf, |
1124 | size_t count, loff_t *ppos) | |
16db88ba EG |
1125 | { |
1126 | struct iwl_trans *trans = file->private_data; | |
1127 | char buf[8]; | |
1128 | int buf_size; | |
1129 | int csr; | |
1130 | ||
1131 | memset(buf, 0, sizeof(buf)); | |
1132 | buf_size = min(count, sizeof(buf) - 1); | |
1133 | if (copy_from_user(buf, user_buf, buf_size)) | |
1134 | return -EFAULT; | |
1135 | if (sscanf(buf, "%d", &csr) != 1) | |
1136 | return -EFAULT; | |
1137 | ||
990aa6d7 | 1138 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
1139 | |
1140 | return count; | |
1141 | } | |
1142 | ||
16db88ba | 1143 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1144 | char __user *user_buf, |
1145 | size_t count, loff_t *ppos) | |
16db88ba EG |
1146 | { |
1147 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 1148 | char *buf = NULL; |
16db88ba EG |
1149 | int pos = 0; |
1150 | ssize_t ret = -EFAULT; | |
1151 | ||
990aa6d7 | 1152 | ret = pos = iwl_pcie_dump_fh(trans, &buf); |
16db88ba EG |
1153 | if (buf) { |
1154 | ret = simple_read_from_buffer(user_buf, | |
1155 | count, ppos, buf, pos); | |
1156 | kfree(buf); | |
1157 | } | |
1158 | ||
1159 | return ret; | |
1160 | } | |
1161 | ||
48dffd39 JB |
1162 | static ssize_t iwl_dbgfs_fw_restart_write(struct file *file, |
1163 | const char __user *user_buf, | |
1164 | size_t count, loff_t *ppos) | |
1165 | { | |
1166 | struct iwl_trans *trans = file->private_data; | |
1167 | ||
1168 | if (!trans->op_mode) | |
1169 | return -EAGAIN; | |
1170 | ||
24172f39 | 1171 | local_bh_disable(); |
48dffd39 | 1172 | iwl_op_mode_nic_error(trans->op_mode); |
24172f39 | 1173 | local_bh_enable(); |
48dffd39 JB |
1174 | |
1175 | return count; | |
1176 | } | |
1177 | ||
1f7b6172 | 1178 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1179 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1180 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1181 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1182 | DEBUGFS_WRITE_FILE_OPS(csr); |
48dffd39 | 1183 | DEBUGFS_WRITE_FILE_OPS(fw_restart); |
87e5666c EG |
1184 | |
1185 | /* | |
1186 | * Create the debugfs files and directories | |
1187 | * | |
1188 | */ | |
1189 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 1190 | struct dentry *dir) |
87e5666c | 1191 | { |
87e5666c EG |
1192 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1193 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 1194 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1195 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1196 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
48dffd39 | 1197 | DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR); |
87e5666c | 1198 | return 0; |
9da987ac MV |
1199 | |
1200 | err: | |
1201 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1202 | return -ENOMEM; | |
87e5666c EG |
1203 | } |
1204 | #else | |
1205 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 JB |
1206 | struct dentry *dir) |
1207 | { | |
1208 | return 0; | |
1209 | } | |
87e5666c EG |
1210 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
1211 | ||
d1ff5253 | 1212 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 1213 | .start_hw = iwl_trans_pcie_start_hw, |
cc56feb2 | 1214 | .stop_hw = iwl_trans_pcie_stop_hw, |
ed6a3803 | 1215 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 1216 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 1217 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 1218 | |
2dd4f9f7 JB |
1219 | .wowlan_suspend = iwl_trans_pcie_wowlan_suspend, |
1220 | ||
f02831be | 1221 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 1222 | |
e6bb4c9c | 1223 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 1224 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1225 | |
f02831be EG |
1226 | .txq_disable = iwl_trans_pcie_txq_disable, |
1227 | .txq_enable = iwl_trans_pcie_txq_enable, | |
34c1b7ba | 1228 | |
87e5666c | 1229 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 | 1230 | |
990aa6d7 | 1231 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
5f178cd2 | 1232 | |
c01a4047 | 1233 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1234 | .suspend = iwl_trans_pcie_suspend, |
1235 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 1236 | #endif |
03905495 EG |
1237 | .write8 = iwl_trans_pcie_write8, |
1238 | .write32 = iwl_trans_pcie_write32, | |
1239 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
1240 | .read_prph = iwl_trans_pcie_read_prph, |
1241 | .write_prph = iwl_trans_pcie_write_prph, | |
c6f600fc | 1242 | .configure = iwl_trans_pcie_configure, |
47107e84 | 1243 | .set_pmi = iwl_trans_pcie_set_pmi, |
e6bb4c9c | 1244 | }; |
a42a1844 | 1245 | |
87ce05a2 | 1246 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
1247 | const struct pci_device_id *ent, |
1248 | const struct iwl_cfg *cfg) | |
a42a1844 | 1249 | { |
a42a1844 EG |
1250 | struct iwl_trans_pcie *trans_pcie; |
1251 | struct iwl_trans *trans; | |
1252 | u16 pci_cmd; | |
1253 | int err; | |
1254 | ||
1255 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 1256 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
a42a1844 | 1257 | |
dbeca583 | 1258 | if (!trans) |
a42a1844 EG |
1259 | return NULL; |
1260 | ||
1261 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1262 | ||
1263 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 1264 | trans->cfg = cfg; |
a42a1844 | 1265 | trans_pcie->trans = trans; |
7b11488f | 1266 | spin_lock_init(&trans_pcie->irq_lock); |
13df1aab | 1267 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 EG |
1268 | |
1269 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
1270 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
1271 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
20d3b647 | 1272 | PCIE_LINK_STATE_CLKPM); |
a42a1844 EG |
1273 | |
1274 | if (pci_enable_device(pdev)) { | |
1275 | err = -ENODEV; | |
1276 | goto out_no_pci; | |
1277 | } | |
1278 | ||
1279 | pci_set_master(pdev); | |
1280 | ||
1281 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1282 | if (!err) | |
1283 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1284 | if (err) { | |
1285 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1286 | if (!err) | |
1287 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 1288 | DMA_BIT_MASK(32)); |
a42a1844 EG |
1289 | /* both attempts failed: */ |
1290 | if (err) { | |
1291 | dev_printk(KERN_ERR, &pdev->dev, | |
1292 | "No suitable DMA available.\n"); | |
1293 | goto out_pci_disable_device; | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | err = pci_request_regions(pdev, DRV_NAME); | |
1298 | if (err) { | |
d6f1c316 JB |
1299 | dev_printk(KERN_ERR, &pdev->dev, |
1300 | "pci_request_regions failed\n"); | |
a42a1844 EG |
1301 | goto out_pci_disable_device; |
1302 | } | |
1303 | ||
05f5b97e | 1304 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 1305 | if (!trans_pcie->hw_base) { |
d6f1c316 | 1306 | dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
1307 | err = -ENODEV; |
1308 | goto out_pci_release_regions; | |
1309 | } | |
1310 | ||
a42a1844 EG |
1311 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
1312 | * PCI Tx retries from interfering with C3 CPU state */ | |
1313 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
1314 | ||
1315 | err = pci_enable_msi(pdev); | |
9f904b38 | 1316 | if (err) { |
a42a1844 | 1317 | dev_printk(KERN_ERR, &pdev->dev, |
d6f1c316 | 1318 | "pci_enable_msi failed(0X%x)\n", err); |
9f904b38 EG |
1319 | /* enable rfkill interrupt: hw bug w/a */ |
1320 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1321 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1322 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1323 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1324 | } | |
1325 | } | |
a42a1844 EG |
1326 | |
1327 | trans->dev = &pdev->dev; | |
75595536 | 1328 | trans_pcie->irq = pdev->irq; |
a42a1844 | 1329 | trans_pcie->pci_dev = pdev; |
08079a49 | 1330 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 1331 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
1332 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
1333 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 1334 | |
69a10b29 | 1335 | /* Initialize the wait queue for commands */ |
f946b529 | 1336 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
8b5bed90 | 1337 | spin_lock_init(&trans->reg_lock); |
69a10b29 | 1338 | |
3ec45882 JB |
1339 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
1340 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
1341 | |
1342 | trans->dev_cmd_headroom = 0; | |
1343 | trans->dev_cmd_pool = | |
3ec45882 | 1344 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
1345 | sizeof(struct iwl_device_cmd) |
1346 | + trans->dev_cmd_headroom, | |
1347 | sizeof(void *), | |
1348 | SLAB_HWCACHE_ALIGN, | |
1349 | NULL); | |
1350 | ||
1351 | if (!trans->dev_cmd_pool) | |
1352 | goto out_pci_disable_msi; | |
1353 | ||
a42a1844 EG |
1354 | return trans; |
1355 | ||
59c647b6 EG |
1356 | out_pci_disable_msi: |
1357 | pci_disable_msi(pdev); | |
a42a1844 EG |
1358 | out_pci_release_regions: |
1359 | pci_release_regions(pdev); | |
1360 | out_pci_disable_device: | |
1361 | pci_disable_device(pdev); | |
1362 | out_no_pci: | |
1363 | kfree(trans); | |
1364 | return NULL; | |
1365 | } |