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iwlwifi: mvm: support LnP 1x1 antenna configuration
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
8b4139dc 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
8b4139dc 35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
7a10e3e4 78#include "iwl-agn-hw.h"
4d075007 79#include "iwl-fw-error-dump.h"
6468a01a 80#include "internal.h"
06d51e0d 81#include "iwl-fh.h"
0439bb62 82
fe45773b
AN		 83/* extended range in FW SRAM */
84#define IWL_FW_MEM_EXTENDED_START 0x40000
85#define IWL_FW_MEM_EXTENDED_END 0x57FFF
86
c2d20201
EG		 87static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
88{
89 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
90
91 if (!trans_pcie->fw_mon_page)
92 return;
93
94 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
95 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
96 __free_pages(trans_pcie->fw_mon_page,
97 get_order(trans_pcie->fw_mon_size));
98 trans_pcie->fw_mon_page = NULL;
99 trans_pcie->fw_mon_phys = 0;
100 trans_pcie->fw_mon_size = 0;
101}
102
103static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
104{
105 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
106 struct page *page;
107 dma_addr_t phys;
108 u32 size;
109 u8 power;
110
111 if (trans_pcie->fw_mon_page) {
112 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
113 trans_pcie->fw_mon_size,
114 DMA_FROM_DEVICE);
115 return;
116 }
117
118 phys = 0;
119 for (power = 26; power >= 11; power--) {
120 int order;
121
122 size = BIT(power);
123 order = get_order(size);
124 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
125 order);
126 if (!page)
127 continue;
128
129 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
130 DMA_FROM_DEVICE);
131 if (dma_mapping_error(trans->dev, phys)) {
132 __free_pages(page, order);
133 continue;
134 }
135 IWL_INFO(trans,
136 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
137 size, order);
138 break;
139 }
140
40a76905 141 if (WARN_ON_ONCE(!page))
c2d20201
EG		 142 return;
143
144 trans_pcie->fw_mon_page = page;
145 trans_pcie->fw_mon_phys = phys;
146 trans_pcie->fw_mon_size = size;
147}
148
a812cba9
AB		 149static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
150{
151 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
152 ((reg & 0x0000ffff) | (2 << 28)));
153 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
154}
155
156static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
157{
158 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
159 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
160 ((reg & 0x0000ffff) | (3 << 28)));
161}
162
ddaf5a5b 163static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 164{
ddaf5a5b
JB		 165 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
166 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
167 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
168 ~APMG_PS_CTRL_MSK_PWR_SRC);
169 else
170 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
171 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
172 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 173}
174
af634bee
EG		 175/* PCI registers */
176#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 177
7afe3705 178static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 179{
20d3b647 180 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 181 u16 lctl;
9180ac50 182 u16 cap;
af634bee 183
af634bee
EG		 184 /*
185 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
186 * Check if BIOS (or OS) enabled L1-ASPM on this device.
187 * If so (likely), disable L0S, so device moves directly L0->L1;
188 * costs negligible amount of power savings.
189 * If not (unlikely), enable L0S, so there is at least some
190 * power savings, even without L1.
191 */
7afe3705 192 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 193 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 194 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 195 else
af634bee 196 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 197 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 198
199 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
200 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
201 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
202 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
203 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 204}
205
a6c684ee
EG		 206/*
207 * Start up NIC's basic functionality after it has been reset
7afe3705 208 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 209 * NOTE: This does not load uCode nor start the embedded processor
210 */
7afe3705 211static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 212{
213 int ret = 0;
214 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
215
216 /*
217 * Use "set_bit" below rather than "write", to preserve any hardware
218 * bits already set by default after reset.
219 */
220
221 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 222 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
223 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
224 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 225
226 /*
227 * Disable L0s without affecting L1;
228 * don't wait for ICH L0s (ICH bug W/A)
229 */
230 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 231 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 232
233 /* Set FH wait threshold to maximum (HW error during stress W/A) */
234 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
235
236 /*
237 * Enable HAP INTA (interrupt from management bus) to
238 * wake device's PCI Express link L1a -> L0s
239 */
240 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 241 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 242
7afe3705 243 iwl_pcie_apm_config(trans);
a6c684ee
EG		 244
245 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 246 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 247 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 248 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 249
250 /*
251 * Set "initialization complete" bit to move adapter from
252 * D0U* --> D0A* (powered-up active) state.
253 */
254 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
255
256 /*
257 * Wait for clock stabilization; once stabilized, access to
258 * device-internal resources is supported, e.g. iwl_write_prph()
259 * and accesses to uCode SRAM.
260 */
261 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 262 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
263 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 264 if (ret < 0) {
265 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
266 goto out;
267 }
268
2d93aee1
EG		 269 if (trans->cfg->host_interrupt_operation_mode) {
270 /*
271 * This is a bit of an abuse - This is needed for 7260 / 3160
272 * only check host_interrupt_operation_mode even if this is
273 * not related to host_interrupt_operation_mode.
274 *
275 * Enable the oscillator to count wake up time for L1 exit. This
276 * consumes slightly more power (100uA) - but allows to be sure
277 * that we wake up from L1 on time.
278 *
279 * This looks weird: read twice the same register, discard the
280 * value, set a bit, and yet again, read that same register
281 * just to discard the value. But that's the way the hardware
282 * seems to like it.
283 */
284 iwl_read_prph(trans, OSC_CLK);
285 iwl_read_prph(trans, OSC_CLK);
286 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
287 iwl_read_prph(trans, OSC_CLK);
288 iwl_read_prph(trans, OSC_CLK);
289 }
290
a6c684ee
EG		 291 /*
292 * Enable DMA clock and wait for it to stabilize.
293 *
3073d8c0
EH		 294 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
295 * bits do not disable clocks. This preserves any hardware
296 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 297 */
3073d8c0
EH		 298 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
299 iwl_write_prph(trans, APMG_CLK_EN_REG,
300 APMG_CLK_VAL_DMA_CLK_RQT);
301 udelay(20);
302
303 /* Disable L1-Active */
304 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
305 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
306
307 /* Clear the interrupt in APMG if the NIC is in RFKILL */
308 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
309 APMG_RTC_INT_STT_RFKILL);
310 }
889b1696 311
eb7ff77e 312 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 313
314out:
315 return ret;
316}
317
a812cba9
AB		 318/*
319 * Enable LP XTAL to avoid HW bug where device may consume much power if
320 * FW is not loaded after device reset. LP XTAL is disabled by default
321 * after device HW reset. Do it only if XTAL is fed by internal source.
322 * Configure device's "persistence" mode to avoid resetting XTAL again when
323 * SHRD_HW_RST occurs in S3.
324 */
325static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
326{
327 int ret;
328 u32 apmg_gp1_reg;
329 u32 apmg_xtal_cfg_reg;
330 u32 dl_cfg_reg;
331
332 /* Force XTAL ON */
333 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
334 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
335
336 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
337 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
338
339 udelay(10);
340
341 /*
342 * Set "initialization complete" bit to move adapter from
343 * D0U* --> D0A* (powered-up active) state.
344 */
345 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
346
347 /*
348 * Wait for clock stabilization; once stabilized, access to
349 * device-internal resources is possible.
350 */
351 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
352 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
354 25000);
355 if (WARN_ON(ret < 0)) {
356 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
357 /* Release XTAL ON request */
358 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360 return;
361 }
362
363 /*
364 * Clear "disable persistence" to avoid LP XTAL resetting when
365 * SHRD_HW_RST is applied in S3.
366 */
367 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
368 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
369
370 /*
371 * Force APMG XTAL to be active to prevent its disabling by HW
372 * caused by APMG idle state.
373 */
374 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
375 SHR_APMG_XTAL_CFG_REG);
376 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
377 apmg_xtal_cfg_reg |
378 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
379
380 /*
381 * Reset entire device again - do controller reset (results in
382 * SHRD_HW_RST). Turn MAC off before proceeding.
383 */
384 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
385
386 udelay(10);
387
388 /* Enable LP XTAL by indirect access through CSR */
389 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
390 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
391 SHR_APMG_GP1_WF_XTAL_LP_EN |
392 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
393
394 /* Clear delay line clock power up */
395 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
396 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
397 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
398
399 /*
400 * Enable persistence mode to avoid LP XTAL resetting when
401 * SHRD_HW_RST is applied in S3.
402 */
403 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
404 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
405
406 /*
407 * Clear "initialization complete" bit to move adapter from
408 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
409 */
410 iwl_clear_bit(trans, CSR_GP_CNTRL,
411 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
412
413 /* Activates XTAL resources monitor */
414 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
415 CSR_MONITOR_XTAL_RESOURCES);
416
417 /* Release XTAL ON request */
418 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
419 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
420 udelay(10);
421
422 /* Release APMG XTAL */
423 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
424 apmg_xtal_cfg_reg &
425 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
426}
427
7afe3705 428static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 429{
430 int ret = 0;
431
432 /* stop device's busmaster DMA activity */
433 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
434
435 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 436 CSR_RESET_REG_FLAG_MASTER_DISABLED,
437 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 438 if (ret < 0)
cc56feb2
EG		 439 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
440
441 IWL_DEBUG_INFO(trans, "stop master\n");
442
443 return ret;
444}
445
7afe3705 446static void iwl_pcie_apm_stop(struct iwl_trans *trans)
cc56feb2
EG		 447{
448 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
449
eb7ff77e 450 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 451
452 /* Stop device's DMA activity */
7afe3705 453 iwl_pcie_apm_stop_master(trans);
cc56feb2 454
a812cba9
AB		 455 if (trans->cfg->lp_xtal_workaround) {
456 iwl_pcie_apm_lp_xtal_enable(trans);
457 return;
458 }
459
cc56feb2
EG		 460 /* Reset the entire device */
461 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
462
463 udelay(10);
464
465 /*
466 * Clear "initialization complete" bit to move adapter from
467 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
468 */
469 iwl_clear_bit(trans, CSR_GP_CNTRL,
470 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
471}
472
7afe3705 473static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 474{
7b11488f 475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 476
477 /* nic_init */
7b70bd63 478 spin_lock(&trans_pcie->irq_lock);
7afe3705 479 iwl_pcie_apm_init(trans);
392f8b78 480
7b70bd63 481 spin_unlock(&trans_pcie->irq_lock);
392f8b78 482
3073d8c0
EH		 483 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
484 iwl_pcie_set_pwr(trans, false);
392f8b78 485
ecdb975c 486 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 487
488 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 489 iwl_pcie_rx_init(trans);
392f8b78
EG		 490
491 /* Allocate or reset and init all Tx and Command queues */
f02831be 492 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 493 return -ENOMEM;
494
035f7ff2 495 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 496 /* enable shadow regs in HW */
20d3b647 497 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 498 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 499 }
500
392f8b78
EG		 501 return 0;
502}
503
504#define HW_READY_TIMEOUT (50)
505
506/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 507static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 508{
509 int ret;
510
1042db2a 511 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 512 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 513
514 /* See if we got it */
1042db2a 515 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 516 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
517 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
518 HW_READY_TIMEOUT);
392f8b78 519
6a08f514
EG		 520 if (ret >= 0)
521 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
522
6d8f6eeb 523 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 524 return ret;
525}
526
527/* Note: returns standard 0/-ERROR code */
7afe3705 528static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 529{
530 int ret;
289e5501 531 int t = 0;
501fd989 532 int iter;
392f8b78 533
6d8f6eeb 534 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 535
7afe3705 536 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 537 /* If the card is ready, exit 0 */
392f8b78
EG		 538 if (ret >= 0)
539 return 0;
540
501fd989
EG		 541 for (iter = 0; iter < 10; iter++) {
542 /* If HW is not ready, prepare the conditions to check again */
543 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
544 CSR_HW_IF_CONFIG_REG_PREPARE);
545
546 do {
547 ret = iwl_pcie_set_hw_ready(trans);
548 if (ret >= 0)
549 return 0;
392f8b78 550
501fd989
EG		 551 usleep_range(200, 1000);
552 t += 200;
553 } while (t < 150000);
554 msleep(25);
555 }
392f8b78 556
7f2ac8fb 557 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 558
392f8b78
EG		 559 return ret;
560}
561
cf614297
EG		 562/*
563 * ucode
564 */
7afe3705 565static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 566 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 567{
13df1aab 568 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 569 int ret;
570
13df1aab 571 trans_pcie->ucode_write_complete = false;
cf614297
EG		 572
573 iwl_write_direct32(trans,
20d3b647
JB		 574 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
575 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 576
577 iwl_write_direct32(trans,
20d3b647
JB		 578 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
579 dst_addr);
cf614297
EG		 580
581 iwl_write_direct32(trans,
83f84d7b
JB		 582 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
583 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 584
585 iwl_write_direct32(trans,
20d3b647
JB		 586 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
587 (iwl_get_dma_hi_addr(phy_addr)
588 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 589
590 iwl_write_direct32(trans,
20d3b647
JB		 591 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
592 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
593 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
594 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 595
596 iwl_write_direct32(trans,
20d3b647
JB		 597 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
598 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
599 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
600 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 601
13df1aab
JB		 602 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
603 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 604 if (!ret) {
83f84d7b 605 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 606 return -ETIMEDOUT;
607 }
608
609 return 0;
610}
611
7afe3705 612static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 613 const struct fw_desc *section)
cf614297 614{
83f84d7b
JB		 615 u8 *v_addr;
616 dma_addr_t p_addr;
c571573a 617 u32 offset, chunk_sz = section->len;
cf614297
EG		 618 int ret = 0;
619
83f84d7b
JB		 620 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
621 section_num);
622
c571573a
EG		 623 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
624 GFP_KERNEL | __GFP_NOWARN);
625 if (!v_addr) {
626 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
627 chunk_sz = PAGE_SIZE;
628 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
629 &p_addr, GFP_KERNEL);
630 if (!v_addr)
631 return -ENOMEM;
632 }
83f84d7b 633
c571573a 634 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 635 u32 copy_size, dst_addr;
636 bool extended_addr = false;
83f84d7b 637
c571573a 638 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 639 dst_addr = section->offset + offset;
640
641 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
642 dst_addr <= IWL_FW_MEM_EXTENDED_END)
643 extended_addr = true;
644
645 if (extended_addr)
646 iwl_set_bits_prph(trans, LMPM_CHICK,
647 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 648
83f84d7b 649 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 650 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
651 copy_size);
652
653 if (extended_addr)
654 iwl_clear_bits_prph(trans, LMPM_CHICK,
655 LMPM_CHICK_EXTENDED_ADDR_SPACE);
656
83f84d7b
JB		 657 if (ret) {
658 IWL_ERR(trans,
659 "Could not load the [%d] uCode section\n",
660 section_num);
661 break;
6dfa8d01 662 }
83f84d7b
JB		 663 }
664
c571573a 665 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 666 return ret;
667}
668
dcab8ecd
EH		 669static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans,
670 const struct fw_img *image,
671 int cpu,
672 int *first_ucode_section)
e2d6f4e7
EH		 673{
674 int shift_param;
dcab8ecd
EH		 675 int i, ret = 0, sec_num = 0x1;
676 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 677
678 if (cpu == 1) {
679 shift_param = 0;
034846cf 680 *first_ucode_section = 0;
e2d6f4e7
EH		 681 } else {
682 shift_param = 16;
034846cf 683 (*first_ucode_section)++;
e2d6f4e7
EH		 684 }
685
034846cf
EH		 686 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
687 last_read_idx = i;
688
689 if (!image->sec[i].data ||
690 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
691 IWL_DEBUG_FW(trans,
692 "Break since Data not valid or Empty section, sec = %d\n",
693 i);
189fa2fa 694 break;
034846cf
EH		 695 }
696
189fa2fa
EH		 697 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
698 if (ret)
699 return ret;
dcab8ecd
EH		 700
701 /* Notify the ucode of the loaded section number and status */
702 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
703 val = val | (sec_num << shift_param);
704 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
705 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 706 }
707
034846cf
EH		 708 *first_ucode_section = last_read_idx;
709
189fa2fa
EH		 710 return 0;
711}
e2d6f4e7 712
189fa2fa
EH		 713static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
714 const struct fw_img *image,
034846cf
EH		 715 int cpu,
716 int *first_ucode_section)
189fa2fa
EH		 717{
718 int shift_param;
189fa2fa 719 int i, ret = 0;
034846cf 720 u32 last_read_idx = 0;
189fa2fa
EH		 721
722 if (cpu == 1) {
723 shift_param = 0;
034846cf 724 *first_ucode_section = 0;
189fa2fa
EH		 725 } else {
726 shift_param = 16;
034846cf 727 (*first_ucode_section)++;
189fa2fa
EH		 728 }
729
034846cf
EH		 730 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
731 last_read_idx = i;
732
733 if (!image->sec[i].data ||
734 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
735 IWL_DEBUG_FW(trans,
736 "Break since Data not valid or Empty section, sec = %d\n",
737 i);
189fa2fa 738 break;
034846cf
EH		 739 }
740
189fa2fa
EH		 741 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
742 if (ret)
743 return ret;
e2d6f4e7
EH		 744 }
745
189fa2fa
EH		 746 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
747 iwl_set_bits_prph(trans,
748 CSR_UCODE_LOAD_STATUS_ADDR,
749 (LMPM_CPU_UCODE_LOADING_COMPLETED |
750 LMPM_CPU_HDRS_LOADING_COMPLETED |
751 LMPM_CPU_UCODE_LOADING_STARTED) <<
752 shift_param);
753
034846cf
EH		 754 *first_ucode_section = last_read_idx;
755
e2d6f4e7
EH		 756 return 0;
757}
758
09e350f7
LK		 759static void iwl_pcie_apply_destination(struct iwl_trans *trans)
760{
761 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
762 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
763 int i;
764
765 if (dest->version)
766 IWL_ERR(trans,
767 "DBG DEST version is %d - expect issues\n",
768 dest->version);
769
770 IWL_INFO(trans, "Applying debug destination %s\n",
771 get_fw_dbg_mode_string(dest->monitor_mode));
772
773 if (dest->monitor_mode == EXTERNAL_MODE)
774 iwl_pcie_alloc_fw_monitor(trans);
775 else
776 IWL_WARN(trans, "PCI should have external buffer debug\n");
777
778 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
779 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
780 u32 val = le32_to_cpu(dest->reg_ops[i].val);
781
782 switch (dest->reg_ops[i].op) {
783 case CSR_ASSIGN:
784 iwl_write32(trans, addr, val);
785 break;
786 case CSR_SETBIT:
787 iwl_set_bit(trans, addr, BIT(val));
788 break;
789 case CSR_CLEARBIT:
790 iwl_clear_bit(trans, addr, BIT(val));
791 break;
792 case PRPH_ASSIGN:
793 iwl_write_prph(trans, addr, val);
794 break;
795 case PRPH_SETBIT:
796 iwl_set_bits_prph(trans, addr, BIT(val));
797 break;
798 case PRPH_CLEARBIT:
799 iwl_clear_bits_prph(trans, addr, BIT(val));
800 break;
801 default:
802 IWL_ERR(trans, "FW debug - unknown OP %d\n",
803 dest->reg_ops[i].op);
804 break;
805 }
806 }
807
808 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
809 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
810 trans_pcie->fw_mon_phys >> dest->base_shift);
811 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
812 (trans_pcie->fw_mon_phys +
813 trans_pcie->fw_mon_size) >> dest->end_shift);
814 }
815}
816
7afe3705 817static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 818 const struct fw_img *image)
cf614297 819{
c2d20201 820 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 821 int ret = 0;
034846cf 822 int first_ucode_section;
cf614297 823
dcab8ecd 824 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 825 image->is_dual_cpus ? "Dual" : "Single");
826
dcab8ecd
EH		 827 /* load to FW the binary non secured sections of CPU1 */
828 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
829 if (ret)
830 return ret;
e2d6f4e7
EH		 831
832 if (image->is_dual_cpus) {
189fa2fa
EH		 833 /* set CPU2 header address */
834 iwl_write_prph(trans,
835 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
836 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 837
189fa2fa 838 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 839 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
840 &first_ucode_section);
189fa2fa
EH		 841 if (ret)
842 return ret;
e2d6f4e7 843 }
cf614297 844
c2d20201
EG		 845 /* supported for 7000 only for the moment */
846 if (iwlwifi_mod_params.fw_monitor &&
847 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
848 iwl_pcie_alloc_fw_monitor(trans);
849
850 if (trans_pcie->fw_mon_size) {
851 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
852 trans_pcie->fw_mon_phys >> 4);
853 iwl_write_prph(trans, MON_BUFF_END_ADDR,
854 (trans_pcie->fw_mon_phys +
855 trans_pcie->fw_mon_size) >> 4);
856 }
09e350f7
LK		 857 } else if (trans->dbg_dest_tlv) {
858 iwl_pcie_apply_destination(trans);
c2d20201
EG		 859 }
860
e12ba844
EH		 861 /* release CPU reset */
862 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
863 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
864 else
865 iwl_write32(trans, CSR_RESET, 0);
866
dcab8ecd
EH		 867 return 0;
868}
189fa2fa 869
dcab8ecd
EH		 870static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans,
871 const struct fw_img *image)
872{
873 int ret = 0;
874 int first_ucode_section;
875 u32 reg;
876
877 IWL_DEBUG_FW(trans, "working with %s CPU\n",
878 image->is_dual_cpus ? "Dual" : "Single");
879
880 /* configure the ucode to be ready to get the secured image */
881 /* release CPU reset */
882 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
883
884 /* load to FW the binary Secured sections of CPU1 */
885 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1,
886 &first_ucode_section);
887 if (ret)
888 return ret;
889
890 /* load to FW the binary sections of CPU2 */
891 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2,
892 &first_ucode_section);
893 if (ret)
894 return ret;
895
896 /* Notify FW loading is done */
897 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
898
899 /* wait for image verification to complete */
900 ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
901 LMPM_SECURE_BOOT_STATUS_SUCCESS,
902 LMPM_SECURE_BOOT_STATUS_SUCCESS,
903 LMPM_SECURE_TIME_OUT);
904 if (ret < 0) {
905 reg = iwl_read_prph(trans,
906 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
907
908 IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
909 reg);
910 return ret;
189fa2fa
EH		 911 }
912
cf614297
EG		 913 return 0;
914}
915
0692fe41 916static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 917 const struct fw_img *fw, bool run_in_rfkill)
392f8b78
EG		 918{
919 int ret;
c9eec95c 920 bool hw_rfkill;
392f8b78 921
496bab39 922 /* This may fail if AMT took ownership of the device */
7afe3705 923 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 924 IWL_WARN(trans, "Exit HW not ready\n");
392f8b78
EG		 925 return -EIO;
926 }
927
8c46bb70
EG		 928 iwl_enable_rfkill_int(trans);
929
392f8b78 930 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 931 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 932 if (hw_rfkill)
eb7ff77e 933 set_bit(STATUS_RFKILL, &trans->status);
4620020b 934 else
eb7ff77e 935 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 936 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
6ae02f3e 937 if (hw_rfkill && !run_in_rfkill)
392f8b78 938 return -ERFKILL;
392f8b78 939
1042db2a 940 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 941
7afe3705 942 ret = iwl_pcie_nic_init(trans);
392f8b78 943 if (ret) {
6d8f6eeb 944 IWL_ERR(trans, "Unable to init nic\n");
392f8b78
EG		 945 return ret;
946 }
947
948 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 949 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
950 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 951 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
952
953 /* clear (again), then enable host interrupts */
1042db2a 954 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 955 iwl_enable_interrupts(trans);
392f8b78
EG		 956
957 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 958 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
959 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 960
cf614297 961 /* Load the given image to the HW */
dcab8ecd
EH		 962 if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) &&
963 (CSR_HW_REV_STEP(trans->hw_rev) == SILICON_B_STEP))
964 return iwl_pcie_load_given_ucode_8000b(trans, fw);
965 else
966 return iwl_pcie_load_given_ucode(trans, fw);
b3c2ce13
EG		 967}
968
adca1235 969static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 970{
990aa6d7 971 iwl_pcie_reset_ict(trans);
f02831be 972 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 973}
974
43e58856 975static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 976{
43e58856 977 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 978 bool hw_rfkill, was_hw_rfkill;
979
980 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 981
43e58856 982 /* tell the device to stop sending interrupts */
7b70bd63 983 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 984 iwl_disable_interrupts(trans);
7b70bd63 985 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 986
ab6cf8e8 987 /* device going down, Stop using ICT table */
990aa6d7 988 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 989
990 /*
991 * If a HW restart happens during firmware loading,
992 * then the firmware loading might call this function
993 * and later it might be called again due to the
994 * restart. So don't process again if the device is
995 * already dead.
996 */
31b8b343
EG		 997 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
998 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 999 iwl_pcie_tx_stop(trans);
9805c446 1000 iwl_pcie_rx_stop(trans);
6379103e 1001
ab6cf8e8 1002 /* Power-down device's busmaster DMA clocks */
1042db2a 1003 iwl_write_prph(trans, APMG_CLK_DIS_REG,
ab6cf8e8
EG		 1004 APMG_CLK_VAL_DMA_CLK_RQT);
1005 udelay(5);
1006 }
1007
1008 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1009 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1010 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1011
1012 /* Stop the device, and put it in low power state */
7afe3705 1013 iwl_pcie_apm_stop(trans);
43e58856
EG		 1014
1015 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1016 * Clean again the interrupt here
1017 */
7b70bd63 1018 spin_lock(&trans_pcie->irq_lock);
43e58856 1019 iwl_disable_interrupts(trans);
7b70bd63 1020 spin_unlock(&trans_pcie->irq_lock);
43e58856 1021
43e58856 1022 /* stop and reset the on-board processor */
522713c8
EG		 1023 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1024 udelay(20);
74fda971
DF		 1025
1026 /* clear all status bits */
eb7ff77e
AN		 1027 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1028 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1029 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1030 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1031
1032 /*
1033 * Even if we stop the HW, we still want the RF kill
1034 * interrupt
1035 */
1036 iwl_enable_rfkill_int(trans);
1037
1038 /*
1039 * Check again since the RF kill state may have changed while
1040 * all the interrupts were disabled, in this case we couldn't
1041 * receive the RF kill interrupt and update the state in the
1042 * op_mode.
3dc3374f
EG		 1043 * Don't call the op_mode if the rkfill state hasn't changed.
1044 * This allows the op_mode to call stop_device from the rfkill
1045 * notification without endless recursion. Under very rare
1046 * circumstances, we might have a small recursion if the rfkill
1047 * state changed exactly now while we were called from stop_device.
1048 * This is very unlikely but can happen and is supported.
a4082843
AN		 1049 */
1050 hw_rfkill = iwl_is_rfkill_set(trans);
1051 if (hw_rfkill)
eb7ff77e 1052 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1053 else
eb7ff77e 1054 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1055 if (hw_rfkill != was_hw_rfkill)
14cfca71 1056 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1057
1058 /* re-take ownership to prevent other users from stealing the deivce */
1059 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1060}
1061
1062void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1063{
1064 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1065 iwl_trans_pcie_stop_device(trans);
ab6cf8e8
EG		 1066}
1067
debff618 1068static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1069{
2dd4f9f7 1070 iwl_disable_interrupts(trans);
debff618
JB		 1071
1072 /*
1073 * in testing mode, the host stays awake and the
1074 * hardware won't be reset (not even partially)
1075 */
1076 if (test)
1077 return;
1078
ddaf5a5b
JB		 1079 iwl_pcie_disable_ict(trans);
1080
2dd4f9f7
JB		 1081 iwl_clear_bit(trans, CSR_GP_CNTRL,
1082 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1083 iwl_clear_bit(trans, CSR_GP_CNTRL,
1084 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1085
1086 /*
1087 * reset TX queues -- some of their registers reset during S3
1088 * so if we don't reset everything here the D3 image would try
1089 * to execute some invalid memory upon resume
1090 */
1091 iwl_trans_pcie_tx_reset(trans);
1092
1093 iwl_pcie_set_pwr(trans, true);
1094}
1095
1096static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1097 enum iwl_d3_status *status,
1098 bool test)
ddaf5a5b
JB		 1099{
1100 u32 val;
1101 int ret;
1102
debff618
JB		 1103 if (test) {
1104 iwl_enable_interrupts(trans);
1105 *status = IWL_D3_STATUS_ALIVE;
1106 return 0;
1107 }
1108
ddaf5a5b
JB		 1109 /*
1110 * Also enables interrupts - none will happen as the device doesn't
1111 * know we're waking it up, only when the opmode actually tells it
1112 * after this call.
1113 */
1114 iwl_pcie_reset_ict(trans);
1115
1116 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1117 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1118
01e58a28
EG		 1119 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1120 udelay(2);
1121
ddaf5a5b
JB		 1122 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1123 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1124 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1125 25000);
7f2ac8fb 1126 if (ret < 0) {
ddaf5a5b
JB		 1127 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1128 return ret;
1129 }
1130
a3ead656
EG		 1131 iwl_pcie_set_pwr(trans, false);
1132
ddaf5a5b
JB		 1133 iwl_trans_pcie_tx_reset(trans);
1134
1135 ret = iwl_pcie_rx_init(trans);
1136 if (ret) {
1137 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1138 return ret;
1139 }
1140
a3ead656
EG		 1141 val = iwl_read32(trans, CSR_RESET);
1142 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1143 *status = IWL_D3_STATUS_RESET;
1144 else
1145 *status = IWL_D3_STATUS_ALIVE;
1146
ddaf5a5b 1147 return 0;
2dd4f9f7
JB		 1148}
1149
57a1dc89 1150static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
e6bb4c9c 1151{
c9eec95c 1152 bool hw_rfkill;
a8b691e6 1153 int err;
e6bb4c9c 1154
7afe3705 1155 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1156 if (err) {
d6f1c316 1157 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1158 return err;
ebb7678d 1159 }
a6c684ee 1160
2997494f 1161 /* Reset the entire device */
ce836c76 1162 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1163
1164 usleep_range(10, 15);
1165
7afe3705 1166 iwl_pcie_apm_init(trans);
a6c684ee 1167
226c02ca
EG		 1168 /* From now on, the op_mode will be kept updated about RF kill state */
1169 iwl_enable_rfkill_int(trans);
1170
8d425517 1171 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1172 if (hw_rfkill)
eb7ff77e 1173 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1174 else
eb7ff77e 1175 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1176 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1177
a8b691e6 1178 return 0;
e6bb4c9c
EG		 1179}
1180
a4082843 1181static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1182{
20d3b647 1183 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1184
a4082843 1185 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1186 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1187 iwl_disable_interrupts(trans);
7b70bd63 1188 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1189
7afe3705 1190 iwl_pcie_apm_stop(trans);
cc56feb2 1191
7b70bd63 1192 spin_lock(&trans_pcie->irq_lock);
218733cf 1193 iwl_disable_interrupts(trans);
7b70bd63 1194 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1195
8d96bb61 1196 iwl_pcie_disable_ict(trans);
cc56feb2
EG		 1197}
1198
03905495
EG		 1199static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1200{
05f5b97e 1201 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1202}
1203
1204static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1205{
05f5b97e 1206 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1207}
1208
1209static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1210{
05f5b97e 1211 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1212}
1213
6a06b6c1
EG		 1214static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1215{
f9477c17
AP		 1216 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1217 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1218 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1219}
1220
1221static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1222 u32 val)
1223{
1224 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1225 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1226 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1227}
1228
f14d6b39
JB		 1229static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1230{
1231 WARN_ON(1);
1232 return 0;
1233}
1234
c6f600fc 1235static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1236 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1237{
1238 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1239
1240 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1241 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
d663ee73
JB		 1242 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1243 trans_pcie->n_no_reclaim_cmds = 0;
1244 else
1245 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1246 if (trans_pcie->n_no_reclaim_cmds)
1247 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1248 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1249
b2cf410c
JB		 1250 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1251 if (trans_pcie->rx_buf_size_8k)
1252 trans_pcie->rx_page_order = get_order(8 * 1024);
1253 else
1254 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8
JB		 1255
1256 trans_pcie->wd_timeout =
1257 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
d9fb6465
JB		 1258
1259 trans_pcie->command_names = trans_cfg->command_names;
046db346 1260 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1261 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39
JB		 1262
1263 /* Initialize NAPI here - it should be before registering to mac80211
1264 * in the opmode but after the HW struct is allocated.
1265 * As this function may be called again in some corner cases don't
1266 * do anything if NAPI was already initialized.
1267 */
1268 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1269 init_dummy_netdev(&trans_pcie->napi_dev);
1270 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1271 &trans_pcie->napi_dev,
1272 iwl_pcie_dummy_napi_poll, 64);
1273 }
c6f600fc
MV		 1274}
1275
d1ff5253 1276void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1277{
20d3b647 1278 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1279
0aa86df6 1280 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1281
f02831be 1282 iwl_pcie_tx_free(trans);
9805c446 1283 iwl_pcie_rx_free(trans);
6379103e 1284
a8b691e6
JB		 1285 free_irq(trans_pcie->pci_dev->irq, trans);
1286 iwl_pcie_free_ict(trans);
a42a1844
EG		 1287
1288 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1289 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1290 pci_release_regions(trans_pcie->pci_dev);
1291 pci_disable_device(trans_pcie->pci_dev);
59c647b6 1292 kmem_cache_destroy(trans->dev_cmd_pool);
a42a1844 1293
f14d6b39
JB		 1294 if (trans_pcie->napi.poll)
1295 netif_napi_del(&trans_pcie->napi);
1296
c2d20201
EG		 1297 iwl_pcie_free_fw_monitor(trans);
1298
6d8f6eeb 1299 kfree(trans);
34c1b7ba
EG		 1300}
1301
47107e84
DF		 1302static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1303{
47107e84 1304 if (state)
eb7ff77e 1305 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1306 else
eb7ff77e 1307 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1308}
1309
e56b04ef
LE		 1310static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1311 unsigned long *flags)
7a65d170
EG		 1312{
1313 int ret;
cfb4e624
JB		 1314 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1315
1316 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1317
b9439491
EG		 1318 if (trans_pcie->cmd_in_flight)
1319 goto out;
1320
7a65d170 1321 /* this bit wakes up the NIC */
e139dc4a
LE		 1322 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1323 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1324 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1325 udelay(2);
7a65d170
EG		 1326
1327 /*
1328 * These bits say the device is running, and should keep running for
1329 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1330 * but they do not indicate that embedded SRAM is restored yet;
1331 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1332 * to/from host DRAM when sleeping/waking for power-saving.
1333 * Each direction takes approximately 1/4 millisecond; with this
1334 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1335 * series of register accesses are expected (e.g. reading Event Log),
1336 * to keep device from sleeping.
1337 *
1338 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1339 * SRAM is okay/restored. We don't check that here because this call
1340 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1341 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1342 *
1343 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1344 * and do not save/restore SRAM when power cycling.
1345 */
1346 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1347 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1348 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1349 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1350 if (unlikely(ret < 0)) {
1351 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1352 if (!silent) {
1353 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1354 WARN_ONCE(1,
1355 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1356 val);
cfb4e624 1357 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1358 return false;
1359 }
1360 }
1361
b9439491 1362out:
e56b04ef
LE		 1363 /*
1364 * Fool sparse by faking we release the lock - sparse will
1365 * track nic_access anyway.
1366 */
cfb4e624 1367 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1368 return true;
1369}
1370
e56b04ef
LE		 1371static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1372 unsigned long *flags)
7a65d170 1373{
cfb4e624 1374 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1375
cfb4e624 1376 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1377
1378 /*
1379 * Fool sparse by faking we acquiring the lock - sparse will
1380 * track nic_access anyway.
1381 */
cfb4e624 1382 __acquire(&trans_pcie->reg_lock);
e56b04ef 1383
b9439491
EG		 1384 if (trans_pcie->cmd_in_flight)
1385 goto out;
1386
e139dc4a
LE		 1387 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1388 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1389 /*
1390 * Above we read the CSR_GP_CNTRL register, which will flush
1391 * any previous writes, but we need the write that clears the
1392 * MAC_ACCESS_REQ bit to be performed before any other writes
1393 * scheduled on different CPUs (after we drop reg_lock).
1394 */
1395 mmiowb();
b9439491 1396out:
cfb4e624 1397 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1398}
1399
4fd442db
EG		 1400static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1401 void *buf, int dwords)
1402{
1403 unsigned long flags;
1404 int offs, ret = 0;
1405 u32 *vals = buf;
1406
e56b04ef 1407 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1408 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1409 for (offs = 0; offs < dwords; offs++)
1410 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1411 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1412 } else {
1413 ret = -EBUSY;
1414 }
4fd442db
EG		 1415 return ret;
1416}
1417
1418static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1419 const void *buf, int dwords)
4fd442db
EG		 1420{
1421 unsigned long flags;
1422 int offs, ret = 0;
bf0fd5da 1423 const u32 *vals = buf;
4fd442db 1424
e56b04ef 1425 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1426 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1427 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1428 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1429 vals ? vals[offs] : 0);
e56b04ef 1430 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1431 } else {
1432 ret = -EBUSY;
1433 }
4fd442db
EG		 1434 return ret;
1435}
7a65d170 1436
5f178cd2
EG		 1437#define IWL_FLUSH_WAIT_MS 2000
1438
3cafdbe6 1439static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1440{
8ad71bef 1441 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1442 struct iwl_txq *txq;
5f178cd2
EG		 1443 struct iwl_queue *q;
1444 int cnt;
1445 unsigned long now = jiffies;
1c3fea82
EG		 1446 u32 scd_sram_addr;
1447 u8 buf[16];
5f178cd2
EG		 1448 int ret = 0;
1449
1450 /* waiting for all the tx frames complete might take a while */
035f7ff2 1451 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1452 u8 wr_ptr;
1453
9ba1947a 1454 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1455 continue;
3cafdbe6
EG		 1456 if (!test_bit(cnt, trans_pcie->queue_used))
1457 continue;
1458 if (!(BIT(cnt) & txq_bm))
1459 continue;
748fa67c
EG		 1460
1461 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1462 txq = &trans_pcie->txq[cnt];
5f178cd2 1463 q = &txq->q;
fa1a91fd
EG		 1464 wr_ptr = ACCESS_ONCE(q->write_ptr);
1465
1466 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1467 !time_after(jiffies,
1468 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1469 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1470
1471 if (WARN_ONCE(wr_ptr != write_ptr,
1472 "WR pointer moved while flushing %d -> %d\n",
1473 wr_ptr, write_ptr))
1474 return -ETIMEDOUT;
5f178cd2 1475 msleep(1);
fa1a91fd 1476 }
5f178cd2
EG		 1477
1478 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1479 IWL_ERR(trans,
1480 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1481 ret = -ETIMEDOUT;
1482 break;
1483 }
748fa67c 1484 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1485 }
1c3fea82
EG		 1486
1487 if (!ret)
1488 return 0;
1489
1490 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1491 txq->q.read_ptr, txq->q.write_ptr);
1492
1493 scd_sram_addr = trans_pcie->scd_base_addr +
1494 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1495 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1496
1497 iwl_print_hex_error(trans, buf, sizeof(buf));
1498
1499 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1500 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1501 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1502
1503 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1504 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1505 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1506 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1507 u32 tbl_dw =
1508 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1509 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1510
1511 if (cnt & 0x1)
1512 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1513 else
1514 tbl_dw = tbl_dw & 0x0000FFFF;
1515
1516 IWL_ERR(trans,
1517 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1518 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1519 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1520 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1521 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1522 }
1523
5f178cd2
EG		 1524 return ret;
1525}
1526
e139dc4a
LE		 1527static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1528 u32 mask, u32 value)
1529{
e56b04ef 1530 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1531 unsigned long flags;
1532
e56b04ef 1533 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1534 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1535 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1536}
1537
ff620849
EG		 1538static const char *get_csr_string(int cmd)
1539{
d9fb6465 1540#define IWL_CMD(x) case x: return #x
ff620849
EG		 1541 switch (cmd) {
1542 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1543 IWL_CMD(CSR_INT_COALESCING);
1544 IWL_CMD(CSR_INT);
1545 IWL_CMD(CSR_INT_MASK);
1546 IWL_CMD(CSR_FH_INT_STATUS);
1547 IWL_CMD(CSR_GPIO_IN);
1548 IWL_CMD(CSR_RESET);
1549 IWL_CMD(CSR_GP_CNTRL);
1550 IWL_CMD(CSR_HW_REV);
1551 IWL_CMD(CSR_EEPROM_REG);
1552 IWL_CMD(CSR_EEPROM_GP);
1553 IWL_CMD(CSR_OTP_GP_REG);
1554 IWL_CMD(CSR_GIO_REG);
1555 IWL_CMD(CSR_GP_UCODE_REG);
1556 IWL_CMD(CSR_GP_DRIVER_REG);
1557 IWL_CMD(CSR_UCODE_DRV_GP1);
1558 IWL_CMD(CSR_UCODE_DRV_GP2);
1559 IWL_CMD(CSR_LED_REG);
1560 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1561 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1562 IWL_CMD(CSR_ANA_PLL_CFG);
1563 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1564 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1565 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1566 default:
1567 return "UNKNOWN";
1568 }
d9fb6465 1569#undef IWL_CMD
ff620849
EG		 1570}
1571
990aa6d7 1572void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1573{
1574 int i;
1575 static const u32 csr_tbl[] = {
1576 CSR_HW_IF_CONFIG_REG,
1577 CSR_INT_COALESCING,
1578 CSR_INT,
1579 CSR_INT_MASK,
1580 CSR_FH_INT_STATUS,
1581 CSR_GPIO_IN,
1582 CSR_RESET,
1583 CSR_GP_CNTRL,
1584 CSR_HW_REV,
1585 CSR_EEPROM_REG,
1586 CSR_EEPROM_GP,
1587 CSR_OTP_GP_REG,
1588 CSR_GIO_REG,
1589 CSR_GP_UCODE_REG,
1590 CSR_GP_DRIVER_REG,
1591 CSR_UCODE_DRV_GP1,
1592 CSR_UCODE_DRV_GP2,
1593 CSR_LED_REG,
1594 CSR_DRAM_INT_TBL_REG,
1595 CSR_GIO_CHICKEN_BITS,
1596 CSR_ANA_PLL_CFG,
a812cba9 1597 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1598 CSR_HW_REV_WA_REG,
1599 CSR_DBG_HPET_MEM_REG
1600 };
1601 IWL_ERR(trans, "CSR values:\n");
1602 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1603 "CSR_INT_PERIODIC_REG)\n");
1604 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1605 IWL_ERR(trans, " %25s: 0X%08x\n",
1606 get_csr_string(csr_tbl[i]),
1042db2a 1607 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1608 }
1609}
1610
87e5666c
EG		 1611#ifdef CONFIG_IWLWIFI_DEBUGFS
1612/* create and remove of files */
1613#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1614 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1615 &iwl_dbgfs_##name##_ops)) \
9da987ac 1616 goto err; \
87e5666c
EG		 1617} while (0)
1618
1619/* file operation */
87e5666c 1620#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1621static const struct file_operations iwl_dbgfs_##name##_ops = { \
1622 .read = iwl_dbgfs_##name##_read, \
234e3405 1623 .open = simple_open, \
87e5666c
EG		 1624 .llseek = generic_file_llseek, \
1625};
1626
16db88ba 1627#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1628static const struct file_operations iwl_dbgfs_##name##_ops = { \
1629 .write = iwl_dbgfs_##name##_write, \
234e3405 1630 .open = simple_open, \
16db88ba
EG		 1631 .llseek = generic_file_llseek, \
1632};
1633
87e5666c 1634#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1635static const struct file_operations iwl_dbgfs_##name##_ops = { \
1636 .write = iwl_dbgfs_##name##_write, \
1637 .read = iwl_dbgfs_##name##_read, \
234e3405 1638 .open = simple_open, \
87e5666c
EG		 1639 .llseek = generic_file_llseek, \
1640};
1641
87e5666c 1642static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1643 char __user *user_buf,
1644 size_t count, loff_t *ppos)
8ad71bef 1645{
5a878bf6 1646 struct iwl_trans *trans = file->private_data;
8ad71bef 1647 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1648 struct iwl_txq *txq;
87e5666c
EG		 1649 struct iwl_queue *q;
1650 char *buf;
1651 int pos = 0;
1652 int cnt;
1653 int ret;
1745e440
WYG		 1654 size_t bufsz;
1655
035f7ff2 1656 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
87e5666c 1657
f9e75447 1658 if (!trans_pcie->txq)
87e5666c 1659 return -EAGAIN;
f9e75447 1660
87e5666c
EG		 1661 buf = kzalloc(bufsz, GFP_KERNEL);
1662 if (!buf)
1663 return -ENOMEM;
1664
035f7ff2 1665 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1666 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1667 q = &txq->q;
1668 pos += scnprintf(buf + pos, bufsz - pos,
f40faf62 1669 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
87e5666c 1670 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1671 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62
AL		 1672 !!test_bit(cnt, trans_pcie->queue_stopped),
1673 txq->need_update,
1674 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1675 }
1676 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1677 kfree(buf);
1678 return ret;
1679}
1680
1681static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1682 char __user *user_buf,
1683 size_t count, loff_t *ppos)
1684{
5a878bf6 1685 struct iwl_trans *trans = file->private_data;
20d3b647 1686 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1687 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1688 char buf[256];
1689 int pos = 0;
1690 const size_t bufsz = sizeof(buf);
1691
1692 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1693 rxq->read);
1694 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1695 rxq->write);
f40faf62
AL		 1696 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1697 rxq->write_actual);
1698 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1699 rxq->need_update);
87e5666c
EG		 1700 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1701 rxq->free_count);
1702 if (rxq->rb_stts) {
1703 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1704 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1705 } else {
1706 pos += scnprintf(buf + pos, bufsz - pos,
1707 "closed_rb_num: Not Allocated\n");
1708 }
1709 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1710}
1711
1f7b6172
EG		 1712static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1713 char __user *user_buf,
20d3b647
JB		 1714 size_t count, loff_t *ppos)
1715{
1f7b6172 1716 struct iwl_trans *trans = file->private_data;
20d3b647 1717 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1718 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1719
1720 int pos = 0;
1721 char *buf;
1722 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1723 ssize_t ret;
1724
1725 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1726 if (!buf)
1f7b6172 1727 return -ENOMEM;
1f7b6172
EG		 1728
1729 pos += scnprintf(buf + pos, bufsz - pos,
1730 "Interrupt Statistics Report:\n");
1731
1732 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1733 isr_stats->hw);
1734 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1735 isr_stats->sw);
1736 if (isr_stats->sw || isr_stats->hw) {
1737 pos += scnprintf(buf + pos, bufsz - pos,
1738 "\tLast Restarting Code: 0x%X\n",
1739 isr_stats->err_code);
1740 }
1741#ifdef CONFIG_IWLWIFI_DEBUG
1742 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1743 isr_stats->sch);
1744 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1745 isr_stats->alive);
1746#endif
1747 pos += scnprintf(buf + pos, bufsz - pos,
1748 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1749
1750 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1751 isr_stats->ctkill);
1752
1753 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1754 isr_stats->wakeup);
1755
1756 pos += scnprintf(buf + pos, bufsz - pos,
1757 "Rx command responses:\t\t %u\n", isr_stats->rx);
1758
1759 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1760 isr_stats->tx);
1761
1762 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1763 isr_stats->unhandled);
1764
1765 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1766 kfree(buf);
1767 return ret;
1768}
1769
1770static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1771 const char __user *user_buf,
1772 size_t count, loff_t *ppos)
1773{
1774 struct iwl_trans *trans = file->private_data;
20d3b647 1775 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1776 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1777
1778 char buf[8];
1779 int buf_size;
1780 u32 reset_flag;
1781
1782 memset(buf, 0, sizeof(buf));
1783 buf_size = min(count, sizeof(buf) - 1);
1784 if (copy_from_user(buf, user_buf, buf_size))
1785 return -EFAULT;
1786 if (sscanf(buf, "%x", &reset_flag) != 1)
1787 return -EFAULT;
1788 if (reset_flag == 0)
1789 memset(isr_stats, 0, sizeof(*isr_stats));
1790
1791 return count;
1792}
1793
16db88ba 1794static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 1795 const char __user *user_buf,
1796 size_t count, loff_t *ppos)
16db88ba
EG		 1797{
1798 struct iwl_trans *trans = file->private_data;
1799 char buf[8];
1800 int buf_size;
1801 int csr;
1802
1803 memset(buf, 0, sizeof(buf));
1804 buf_size = min(count, sizeof(buf) - 1);
1805 if (copy_from_user(buf, user_buf, buf_size))
1806 return -EFAULT;
1807 if (sscanf(buf, "%d", &csr) != 1)
1808 return -EFAULT;
1809
990aa6d7 1810 iwl_pcie_dump_csr(trans);
16db88ba
EG		 1811
1812 return count;
1813}
1814
16db88ba 1815static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 1816 char __user *user_buf,
1817 size_t count, loff_t *ppos)
16db88ba
EG		 1818{
1819 struct iwl_trans *trans = file->private_data;
94543a8d 1820 char *buf = NULL;
56c2477f 1821 ssize_t ret;
16db88ba 1822
56c2477f
JB		 1823 ret = iwl_dump_fh(trans, &buf);
1824 if (ret < 0)
1825 return ret;
1826 if (!buf)
1827 return -EINVAL;
1828 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1829 kfree(buf);
16db88ba
EG		 1830 return ret;
1831}
1832
1f7b6172 1833DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 1834DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 1835DEBUGFS_READ_FILE_OPS(rx_queue);
1836DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 1837DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 1838
1839/*
1840 * Create the debugfs files and directories
1841 *
1842 */
1843static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 1844 struct dentry *dir)
87e5666c 1845{
87e5666c
EG		 1846 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1847 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 1848 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 1849 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1850 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 1851 return 0;
9da987ac
MV		 1852
1853err:
1854 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1855 return -ENOMEM;
87e5666c 1856}
aadede6e
JB		 1857#else
1858static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1859 struct dentry *dir)
1860{
1861 return 0;
1862}
1863#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 1864
1865static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1866{
1867 u32 cmdlen = 0;
1868 int i;
1869
1870 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1871 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1872
1873 return cmdlen;
1874}
1875
67c65f2c
EG		 1876static const struct {
1877 u32 start, end;
1878} iwl_prph_dump_addr[] = {
1879 { .start = 0x00a00000, .end = 0x00a00000 },
1880 { .start = 0x00a0000c, .end = 0x00a00024 },
1881 { .start = 0x00a0002c, .end = 0x00a0003c },
1882 { .start = 0x00a00410, .end = 0x00a00418 },
1883 { .start = 0x00a00420, .end = 0x00a00420 },
1884 { .start = 0x00a00428, .end = 0x00a00428 },
1885 { .start = 0x00a00430, .end = 0x00a0043c },
1886 { .start = 0x00a00444, .end = 0x00a00444 },
1887 { .start = 0x00a004c0, .end = 0x00a004cc },
1888 { .start = 0x00a004d8, .end = 0x00a004d8 },
1889 { .start = 0x00a004e0, .end = 0x00a004f0 },
1890 { .start = 0x00a00840, .end = 0x00a00840 },
1891 { .start = 0x00a00850, .end = 0x00a00858 },
1892 { .start = 0x00a01004, .end = 0x00a01008 },
1893 { .start = 0x00a01010, .end = 0x00a01010 },
1894 { .start = 0x00a01018, .end = 0x00a01018 },
1895 { .start = 0x00a01024, .end = 0x00a01024 },
1896 { .start = 0x00a0102c, .end = 0x00a01034 },
1897 { .start = 0x00a0103c, .end = 0x00a01040 },
1898 { .start = 0x00a01048, .end = 0x00a01094 },
1899 { .start = 0x00a01c00, .end = 0x00a01c20 },
1900 { .start = 0x00a01c58, .end = 0x00a01c58 },
1901 { .start = 0x00a01c7c, .end = 0x00a01c7c },
1902 { .start = 0x00a01c28, .end = 0x00a01c54 },
1903 { .start = 0x00a01c5c, .end = 0x00a01c5c },
1904 { .start = 0x00a01c84, .end = 0x00a01c84 },
1905 { .start = 0x00a01ce0, .end = 0x00a01d0c },
1906 { .start = 0x00a01d18, .end = 0x00a01d20 },
1907 { .start = 0x00a01d2c, .end = 0x00a01d30 },
1908 { .start = 0x00a01d40, .end = 0x00a01d5c },
1909 { .start = 0x00a01d80, .end = 0x00a01d80 },
1910 { .start = 0x00a01d98, .end = 0x00a01d98 },
1911 { .start = 0x00a01dc0, .end = 0x00a01dfc },
1912 { .start = 0x00a01e00, .end = 0x00a01e2c },
1913 { .start = 0x00a01e40, .end = 0x00a01e60 },
1914 { .start = 0x00a01e84, .end = 0x00a01e90 },
1915 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1916 { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1917 { .start = 0x00a01f00, .end = 0x00a01f14 },
1918 { .start = 0x00a01f44, .end = 0x00a01f58 },
1919 { .start = 0x00a01f80, .end = 0x00a01fa8 },
1920 { .start = 0x00a01fb0, .end = 0x00a01fbc },
1921 { .start = 0x00a01ff8, .end = 0x00a01ffc },
1922 { .start = 0x00a02000, .end = 0x00a02048 },
1923 { .start = 0x00a02068, .end = 0x00a020f0 },
1924 { .start = 0x00a02100, .end = 0x00a02118 },
1925 { .start = 0x00a02140, .end = 0x00a0214c },
1926 { .start = 0x00a02168, .end = 0x00a0218c },
1927 { .start = 0x00a021c0, .end = 0x00a021c0 },
1928 { .start = 0x00a02400, .end = 0x00a02410 },
1929 { .start = 0x00a02418, .end = 0x00a02420 },
1930 { .start = 0x00a02428, .end = 0x00a0242c },
1931 { .start = 0x00a02434, .end = 0x00a02434 },
1932 { .start = 0x00a02440, .end = 0x00a02460 },
1933 { .start = 0x00a02468, .end = 0x00a024b0 },
1934 { .start = 0x00a024c8, .end = 0x00a024cc },
1935 { .start = 0x00a02500, .end = 0x00a02504 },
1936 { .start = 0x00a0250c, .end = 0x00a02510 },
1937 { .start = 0x00a02540, .end = 0x00a02554 },
1938 { .start = 0x00a02580, .end = 0x00a025f4 },
1939 { .start = 0x00a02600, .end = 0x00a0260c },
1940 { .start = 0x00a02648, .end = 0x00a02650 },
1941 { .start = 0x00a02680, .end = 0x00a02680 },
1942 { .start = 0x00a026c0, .end = 0x00a026d0 },
1943 { .start = 0x00a02700, .end = 0x00a0270c },
1944 { .start = 0x00a02804, .end = 0x00a02804 },
1945 { .start = 0x00a02818, .end = 0x00a0281c },
1946 { .start = 0x00a02c00, .end = 0x00a02db4 },
1947 { .start = 0x00a02df4, .end = 0x00a02fb0 },
1948 { .start = 0x00a03000, .end = 0x00a03014 },
1949 { .start = 0x00a0301c, .end = 0x00a0302c },
1950 { .start = 0x00a03034, .end = 0x00a03038 },
1951 { .start = 0x00a03040, .end = 0x00a03048 },
1952 { .start = 0x00a03060, .end = 0x00a03068 },
1953 { .start = 0x00a03070, .end = 0x00a03074 },
1954 { .start = 0x00a0307c, .end = 0x00a0307c },
1955 { .start = 0x00a03080, .end = 0x00a03084 },
1956 { .start = 0x00a0308c, .end = 0x00a03090 },
1957 { .start = 0x00a03098, .end = 0x00a03098 },
1958 { .start = 0x00a030a0, .end = 0x00a030a0 },
1959 { .start = 0x00a030a8, .end = 0x00a030b4 },
1960 { .start = 0x00a030bc, .end = 0x00a030bc },
1961 { .start = 0x00a030c0, .end = 0x00a0312c },
1962 { .start = 0x00a03c00, .end = 0x00a03c5c },
1963 { .start = 0x00a04400, .end = 0x00a04454 },
1964 { .start = 0x00a04460, .end = 0x00a04474 },
1965 { .start = 0x00a044c0, .end = 0x00a044ec },
1966 { .start = 0x00a04500, .end = 0x00a04504 },
1967 { .start = 0x00a04510, .end = 0x00a04538 },
1968 { .start = 0x00a04540, .end = 0x00a04548 },
1969 { .start = 0x00a04560, .end = 0x00a0457c },
1970 { .start = 0x00a04590, .end = 0x00a04598 },
1971 { .start = 0x00a045c0, .end = 0x00a045f4 },
1972};
1973
1974static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1975 struct iwl_fw_error_dump_data **data)
1976{
1977 struct iwl_fw_error_dump_prph *prph;
1978 unsigned long flags;
1979 u32 prph_len = 0, i;
1980
1981 if (!iwl_trans_grab_nic_access(trans, false, &flags))
1982 return 0;
1983
1984 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1985 /* The range includes both boundaries */
1986 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1987 iwl_prph_dump_addr[i].start + 4;
1988 int reg;
1989 __le32 *val;
1990
87dd634a 1991 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 1992
1993 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
1994 (*data)->len = cpu_to_le32(sizeof(*prph) +
1995 num_bytes_in_chunk);
1996 prph = (void *)(*data)->data;
1997 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
1998 val = (void *)prph->data;
1999
2000 for (reg = iwl_prph_dump_addr[i].start;
2001 reg <= iwl_prph_dump_addr[i].end;
2002 reg += 4)
2003 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2004 reg));
2005 *data = iwl_fw_error_next_data(*data);
2006 }
2007
2008 iwl_trans_release_nic_access(trans, &flags);
2009
2010 return prph_len;
2011}
2012
473ad712
EG		 2013#define IWL_CSR_TO_DUMP (0x250)
2014
2015static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2016 struct iwl_fw_error_dump_data **data)
2017{
2018 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2019 __le32 *val;
2020 int i;
2021
2022 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2023 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2024 val = (void *)(*data)->data;
2025
2026 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2027 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2028
2029 *data = iwl_fw_error_next_data(*data);
2030
2031 return csr_len;
2032}
2033
06d51e0d
LK		 2034static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2035 struct iwl_fw_error_dump_data **data)
2036{
2037 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2038 unsigned long flags;
2039 __le32 *val;
2040 int i;
2041
2042 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2043 return 0;
2044
2045 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2046 (*data)->len = cpu_to_le32(fh_regs_len);
2047 val = (void *)(*data)->data;
2048
2049 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2050 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2051
2052 iwl_trans_release_nic_access(trans, &flags);
2053
2054 *data = iwl_fw_error_next_data(*data);
2055
2056 return sizeof(**data) + fh_regs_len;
2057}
2058
48eb7b34
EG		 2059static
2060struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
4d075007
JB		 2061{
2062 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2063 struct iwl_fw_error_dump_data *data;
2064 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2065 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2066 struct iwl_trans_dump_data *dump_data;
4d075007 2067 u32 len;
99684ae3 2068 u32 monitor_len;
4d075007
JB		 2069 int i, ptr;
2070
473ad712
EG		 2071 /* transport dump header */
2072 len = sizeof(*dump_data);
2073
2074 /* host commands */
2075 len += sizeof(*data) +
c2d20201
EG		 2076 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2077
473ad712
EG		 2078 /* CSR registers */
2079 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2080
2081 /* PRPH registers */
67c65f2c
EG		 2082 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2083 /* The range includes both boundaries */
2084 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2085 iwl_prph_dump_addr[i].start + 4;
2086
2087 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2088 num_bytes_in_chunk;
2089 }
2090
06d51e0d
LK		 2091 /* FH registers */
2092 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2093
473ad712 2094 /* FW monitor */
99684ae3 2095 if (trans_pcie->fw_mon_page) {
c544e9c4 2096 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2097 trans_pcie->fw_mon_size;
2098 monitor_len = trans_pcie->fw_mon_size;
2099 } else if (trans->dbg_dest_tlv) {
2100 u32 base, end;
2101
2102 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2103 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2104
2105 base = iwl_read_prph(trans, base) <<
2106 trans->dbg_dest_tlv->base_shift;
2107 end = iwl_read_prph(trans, end) <<
2108 trans->dbg_dest_tlv->end_shift;
2109
2110 /* Make "end" point to the actual end */
2111 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2112 end += (1 << trans->dbg_dest_tlv->end_shift);
2113 monitor_len = end - base;
2114 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2115 monitor_len;
2116 } else {
2117 monitor_len = 0;
2118 }
c2d20201 2119
48eb7b34
EG		 2120 dump_data = vzalloc(len);
2121 if (!dump_data)
2122 return NULL;
4d075007
JB		 2123
2124 len = 0;
48eb7b34 2125 data = (void *)dump_data->data;
4d075007
JB		 2126 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2127 txcmd = (void *)data->data;
2128 spin_lock_bh(&cmdq->lock);
2129 ptr = cmdq->q.write_ptr;
2130 for (i = 0; i < cmdq->q.n_window; i++) {
2131 u8 idx = get_cmd_index(&cmdq->q, ptr);
2132 u32 caplen, cmdlen;
2133
2134 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2135 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2136
2137 if (cmdlen) {
2138 len += sizeof(*txcmd) + caplen;
2139 txcmd->cmdlen = cpu_to_le32(cmdlen);
2140 txcmd->caplen = cpu_to_le32(caplen);
2141 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2142 txcmd = (void *)((u8 *)txcmd->data + caplen);
2143 }
2144
2145 ptr = iwl_queue_dec_wrap(ptr);
2146 }
2147 spin_unlock_bh(&cmdq->lock);
2148
2149 data->len = cpu_to_le32(len);
c2d20201 2150 len += sizeof(*data);
67c65f2c
EG		 2151 data = iwl_fw_error_next_data(data);
2152
2153 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2154 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2155 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
67c65f2c 2156 /* data is already pointing to the next section */
c2d20201 2157
99684ae3
LK		 2158 if ((trans_pcie->fw_mon_page &&
2159 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2160 trans->dbg_dest_tlv) {
c544e9c4 2161 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
99684ae3
LK		 2162 u32 base, write_ptr, wrap_cnt;
2163
2164 /* If there was a dest TLV - use the values from there */
2165 if (trans->dbg_dest_tlv) {
2166 write_ptr =
2167 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2168 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2169 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2170 } else {
2171 base = MON_BUFF_BASE_ADDR;
2172 write_ptr = MON_BUFF_WRPTR;
2173 wrap_cnt = MON_BUFF_CYCLE_CNT;
2174 }
c2d20201 2175
c2d20201 2176 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
c2d20201
EG		 2177 fw_mon_data = (void *)data->data;
2178 fw_mon_data->fw_mon_wr_ptr =
99684ae3 2179 cpu_to_le32(iwl_read_prph(trans, write_ptr));
c2d20201 2180 fw_mon_data->fw_mon_cycle_cnt =
99684ae3 2181 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
c2d20201 2182 fw_mon_data->fw_mon_base_ptr =
99684ae3
LK		 2183 cpu_to_le32(iwl_read_prph(trans, base));
2184
2185 len += sizeof(*data) + sizeof(*fw_mon_data);
2186 if (trans_pcie->fw_mon_page) {
2187 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2188 sizeof(*fw_mon_data));
2189
2190 /*
2191 * The firmware is now asserted, it won't write anything
2192 * to the buffer. CPU can take ownership to fetch the
2193 * data. The buffer will be handed back to the device
2194 * before the firmware will be restarted.
2195 */
2196 dma_sync_single_for_cpu(trans->dev,
2197 trans_pcie->fw_mon_phys,
2198 trans_pcie->fw_mon_size,
2199 DMA_FROM_DEVICE);
2200 memcpy(fw_mon_data->data,
2201 page_address(trans_pcie->fw_mon_page),
2202 trans_pcie->fw_mon_size);
2203
2204 len += trans_pcie->fw_mon_size;
2205 } else {
2206 /* If we are here then the buffer is internal */
2207
2208 /*
2209 * Update pointers to reflect actual values after
2210 * shifting
2211 */
2212 base = iwl_read_prph(trans, base) <<
2213 trans->dbg_dest_tlv->base_shift;
2214 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2215 monitor_len / sizeof(u32));
2216 data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2217 monitor_len);
2218 len += monitor_len;
2219 }
c2d20201
EG		 2220 }
2221
48eb7b34
EG		 2222 dump_data->len = len;
2223
2224 return dump_data;
4d075007 2225}
87e5666c 2226
d1ff5253 2227static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2228 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2229 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2230 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2231 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2232 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2233
ddaf5a5b
JB		 2234 .d3_suspend = iwl_trans_pcie_d3_suspend,
2235 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2236
f02831be 2237 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2238
e6bb4c9c 2239 .tx = iwl_trans_pcie_tx,
a0eaad71 2240 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2241
d0624be6 2242 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2243 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2244
87e5666c 2245 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2246
990aa6d7 2247 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
5f178cd2 2248
03905495
EG		 2249 .write8 = iwl_trans_pcie_write8,
2250 .write32 = iwl_trans_pcie_write32,
2251 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2252 .read_prph = iwl_trans_pcie_read_prph,
2253 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2254 .read_mem = iwl_trans_pcie_read_mem,
2255 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2256 .configure = iwl_trans_pcie_configure,
47107e84 2257 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2258 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2259 .release_nic_access = iwl_trans_pcie_release_nic_access,
2260 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2261
4d075007 2262 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2263};
a42a1844 2264
87ce05a2 2265struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2266 const struct pci_device_id *ent,
2267 const struct iwl_cfg *cfg)
a42a1844 2268{
a42a1844
EG		 2269 struct iwl_trans_pcie *trans_pcie;
2270 struct iwl_trans *trans;
2271 u16 pci_cmd;
2272 int err;
2273
2274 trans = kzalloc(sizeof(struct iwl_trans) +
20d3b647 2275 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
6965a354
LC		 2276 if (!trans) {
2277 err = -ENOMEM;
2278 goto out;
2279 }
a42a1844
EG		 2280
2281 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2282
2283 trans->ops = &trans_ops_pcie;
035f7ff2 2284 trans->cfg = cfg;
2bfb5092 2285 trans_lockdep_init(trans);
a42a1844 2286 trans_pcie->trans = trans;
7b11488f 2287 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2288 spin_lock_init(&trans_pcie->reg_lock);
13df1aab 2289 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2290
d819c6cf
JB		 2291 err = pci_enable_device(pdev);
2292 if (err)
2293 goto out_no_pci;
2294
f2532b04
EG		 2295 if (!cfg->base_params->pcie_l1_allowed) {
2296 /*
2297 * W/A - seems to solve weird behavior. We need to remove this
2298 * if we don't want to stay in L1 all the time. This wastes a
2299 * lot of power.
2300 */
2301 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2302 PCIE_LINK_STATE_L1 |
2303 PCIE_LINK_STATE_CLKPM);
2304 }
a42a1844 2305
a42a1844
EG		 2306 pci_set_master(pdev);
2307
2308 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2309 if (!err)
2310 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2311 if (err) {
2312 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2313 if (!err)
2314 err = pci_set_consistent_dma_mask(pdev,
20d3b647 2315 DMA_BIT_MASK(32));
a42a1844
EG		 2316 /* both attempts failed: */
2317 if (err) {
6a4b09f8 2318 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2319 goto out_pci_disable_device;
2320 }
2321 }
2322
2323 err = pci_request_regions(pdev, DRV_NAME);
2324 if (err) {
6a4b09f8 2325 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2326 goto out_pci_disable_device;
2327 }
2328
05f5b97e 2329 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2330 if (!trans_pcie->hw_base) {
6a4b09f8 2331 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
a42a1844
EG		 2332 err = -ENODEV;
2333 goto out_pci_release_regions;
2334 }
2335
a42a1844
EG		 2336 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2337 * PCI Tx retries from interfering with C3 CPU state */
2338 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2339
83f7a85f
EG		 2340 trans->dev = &pdev->dev;
2341 trans_pcie->pci_dev = pdev;
2342 iwl_disable_interrupts(trans);
2343
a42a1844 2344 err = pci_enable_msi(pdev);
9f904b38 2345 if (err) {
6a4b09f8 2346 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
9f904b38
EG		 2347 /* enable rfkill interrupt: hw bug w/a */
2348 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2349 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2350 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2351 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2352 }
2353 }
a42a1844 2354
08079a49 2355 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2356 /*
2357 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2358 * changed, and now the revision step also includes bit 0-1 (no more
2359 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2360 * in the old format.
2361 */
2362 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2363 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2364 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2365
99673ee5 2366 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2367 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2368 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2369
69a10b29 2370 /* Initialize the wait queue for commands */
f946b529 2371 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2372
3ec45882
JB		 2373 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2374 "iwl_cmd_pool:%s", dev_name(trans->dev));
59c647b6
EG		 2375
2376 trans->dev_cmd_headroom = 0;
2377 trans->dev_cmd_pool =
3ec45882 2378 kmem_cache_create(trans->dev_cmd_pool_name,
59c647b6
EG		 2379 sizeof(struct iwl_device_cmd)
2380 + trans->dev_cmd_headroom,
2381 sizeof(void *),
2382 SLAB_HWCACHE_ALIGN,
2383 NULL);
2384
6965a354
LC		 2385 if (!trans->dev_cmd_pool) {
2386 err = -ENOMEM;
59c647b6 2387 goto out_pci_disable_msi;
6965a354 2388 }
59c647b6 2389
a8b691e6
JB		 2390 if (iwl_pcie_alloc_ict(trans))
2391 goto out_free_cmd_pool;
2392
85bf9da1 2393 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2394 iwl_pcie_irq_handler,
2395 IRQF_SHARED, DRV_NAME, trans);
2396 if (err) {
a8b691e6
JB		 2397 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2398 goto out_free_ict;
2399 }
2400
83f7a85f
EG		 2401 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2402
a42a1844
EG		 2403 return trans;
2404
a8b691e6
JB		 2405out_free_ict:
2406 iwl_pcie_free_ict(trans);
2407out_free_cmd_pool:
2408 kmem_cache_destroy(trans->dev_cmd_pool);
59c647b6
EG		 2409out_pci_disable_msi:
2410 pci_disable_msi(pdev);
a42a1844
EG		 2411out_pci_release_regions:
2412 pci_release_regions(pdev);
2413out_pci_disable_device:
2414 pci_disable_device(pdev);
2415out_no_pci:
2416 kfree(trans);
6965a354
LC		 2417out:
2418 return ERR_PTR(err);
a42a1844 2419}
Linux kernel - Deliverables
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