projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: pcie: don't panic if pcie transport alloc fails
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
553452e5
LK		 34 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
cb6bb128 78#include "iwl-scd.h"
7a10e3e4 79#include "iwl-agn-hw.h"
4d075007 80#include "iwl-fw-error-dump.h"
6468a01a 81#include "internal.h"
06d51e0d 82#include "iwl-fh.h"
0439bb62 83
fe45773b
AN		 84/* extended range in FW SRAM */
85#define IWL_FW_MEM_EXTENDED_START 0x40000
86#define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
c2d20201
EG		 88static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89{
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102}
103
96c285da 104static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 105{
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 107 struct page *page = NULL;
c2d20201 108 dma_addr_t phys;
96c285da 109 u32 size = 0;
c2d20201
EG		 110 u8 power;
111
96c285da
EG		 112 if (!max_power) {
113 /* default max_power is maximum */
114 max_power = 26;
115 } else {
116 max_power += 11;
117 }
118
119 if (WARN(max_power > 26,
120 "External buffer size for monitor is too big %d, check the FW TLV\n",
121 max_power))
122 return;
123
c2d20201
EG		 124 if (trans_pcie->fw_mon_page) {
125 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
126 trans_pcie->fw_mon_size,
127 DMA_FROM_DEVICE);
128 return;
129 }
130
131 phys = 0;
96c285da 132 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 133 int order;
134
135 size = BIT(power);
136 order = get_order(size);
137 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
138 order);
139 if (!page)
140 continue;
141
142 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
143 DMA_FROM_DEVICE);
144 if (dma_mapping_error(trans->dev, phys)) {
145 __free_pages(page, order);
553452e5 146 page = NULL;
c2d20201
EG		 147 continue;
148 }
149 IWL_INFO(trans,
150 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
151 size, order);
152 break;
153 }
154
40a76905 155 if (WARN_ON_ONCE(!page))
c2d20201
EG		 156 return;
157
96c285da
EG		 158 if (power != max_power)
159 IWL_ERR(trans,
160 "Sorry - debug buffer is only %luK while you requested %luK\n",
161 (unsigned long)BIT(power - 10),
162 (unsigned long)BIT(max_power - 10));
163
c2d20201
EG		 164 trans_pcie->fw_mon_page = page;
165 trans_pcie->fw_mon_phys = phys;
166 trans_pcie->fw_mon_size = size;
167}
168
a812cba9
AB		 169static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
170{
171 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
172 ((reg & 0x0000ffff) | (2 << 28)));
173 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
174}
175
176static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
177{
178 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
179 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
180 ((reg & 0x0000ffff) | (3 << 28)));
181}
182
ddaf5a5b 183static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 184{
66337b7c 185 if (trans->cfg->apmg_not_supported)
95411d04
AA		 186 return;
187
ddaf5a5b
JB		 188 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
189 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
190 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
191 ~APMG_PS_CTRL_MSK_PWR_SRC);
192 else
193 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
194 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
195 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 196}
197
af634bee
EG		 198/* PCI registers */
199#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 200
7afe3705 201static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 202{
20d3b647 203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 204 u16 lctl;
9180ac50 205 u16 cap;
af634bee 206
af634bee
EG		 207 /*
208 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
209 * Check if BIOS (or OS) enabled L1-ASPM on this device.
210 * If so (likely), disable L0S, so device moves directly L0->L1;
211 * costs negligible amount of power savings.
212 * If not (unlikely), enable L0S, so there is at least some
213 * power savings, even without L1.
214 */
7afe3705 215 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 216 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 217 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 218 else
af634bee 219 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 220 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 221
222 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
223 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
224 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
225 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
226 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 227}
228
a6c684ee
EG		 229/*
230 * Start up NIC's basic functionality after it has been reset
7afe3705 231 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 232 * NOTE: This does not load uCode nor start the embedded processor
233 */
7afe3705 234static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 235{
236 int ret = 0;
237 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
238
239 /*
240 * Use "set_bit" below rather than "write", to preserve any hardware
241 * bits already set by default after reset.
242 */
243
244 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 245 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
246 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
247 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 248
249 /*
250 * Disable L0s without affecting L1;
251 * don't wait for ICH L0s (ICH bug W/A)
252 */
253 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 254 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 255
256 /* Set FH wait threshold to maximum (HW error during stress W/A) */
257 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
258
259 /*
260 * Enable HAP INTA (interrupt from management bus) to
261 * wake device's PCI Express link L1a -> L0s
262 */
263 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 264 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 265
7afe3705 266 iwl_pcie_apm_config(trans);
a6c684ee
EG		 267
268 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 269 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 270 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 271 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 272
273 /*
274 * Set "initialization complete" bit to move adapter from
275 * D0U* --> D0A* (powered-up active) state.
276 */
277 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
278
279 /*
280 * Wait for clock stabilization; once stabilized, access to
281 * device-internal resources is supported, e.g. iwl_write_prph()
282 * and accesses to uCode SRAM.
283 */
284 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 285 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
286 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 287 if (ret < 0) {
288 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
289 goto out;
290 }
291
2d93aee1
EG		 292 if (trans->cfg->host_interrupt_operation_mode) {
293 /*
294 * This is a bit of an abuse - This is needed for 7260 / 3160
295 * only check host_interrupt_operation_mode even if this is
296 * not related to host_interrupt_operation_mode.
297 *
298 * Enable the oscillator to count wake up time for L1 exit. This
299 * consumes slightly more power (100uA) - but allows to be sure
300 * that we wake up from L1 on time.
301 *
302 * This looks weird: read twice the same register, discard the
303 * value, set a bit, and yet again, read that same register
304 * just to discard the value. But that's the way the hardware
305 * seems to like it.
306 */
307 iwl_read_prph(trans, OSC_CLK);
308 iwl_read_prph(trans, OSC_CLK);
309 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 }
313
a6c684ee
EG		 314 /*
315 * Enable DMA clock and wait for it to stabilize.
316 *
3073d8c0
EH		 317 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
318 * bits do not disable clocks. This preserves any hardware
319 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 320 */
95411d04 321 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 322 iwl_write_prph(trans, APMG_CLK_EN_REG,
323 APMG_CLK_VAL_DMA_CLK_RQT);
324 udelay(20);
325
326 /* Disable L1-Active */
327 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
328 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
329
330 /* Clear the interrupt in APMG if the NIC is in RFKILL */
331 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
332 APMG_RTC_INT_STT_RFKILL);
333 }
889b1696 334
eb7ff77e 335 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 336
337out:
338 return ret;
339}
340
a812cba9
AB		 341/*
342 * Enable LP XTAL to avoid HW bug where device may consume much power if
343 * FW is not loaded after device reset. LP XTAL is disabled by default
344 * after device HW reset. Do it only if XTAL is fed by internal source.
345 * Configure device's "persistence" mode to avoid resetting XTAL again when
346 * SHRD_HW_RST occurs in S3.
347 */
348static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
349{
350 int ret;
351 u32 apmg_gp1_reg;
352 u32 apmg_xtal_cfg_reg;
353 u32 dl_cfg_reg;
354
355 /* Force XTAL ON */
356 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
357 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
358
359 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
360 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
361
362 udelay(10);
363
364 /*
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
367 */
368 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
369
370 /*
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is possible.
373 */
374 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 25000);
378 if (WARN_ON(ret < 0)) {
379 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
380 /* Release XTAL ON request */
381 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383 return;
384 }
385
386 /*
387 * Clear "disable persistence" to avoid LP XTAL resetting when
388 * SHRD_HW_RST is applied in S3.
389 */
390 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
391 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
392
393 /*
394 * Force APMG XTAL to be active to prevent its disabling by HW
395 * caused by APMG idle state.
396 */
397 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
398 SHR_APMG_XTAL_CFG_REG);
399 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
400 apmg_xtal_cfg_reg |
401 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
402
403 /*
404 * Reset entire device again - do controller reset (results in
405 * SHRD_HW_RST). Turn MAC off before proceeding.
406 */
407 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
408
409 udelay(10);
410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
7afe3705 451static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
b7aaeae4 469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
b7aaeae4
EG		 473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
482 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
483 CSR_HW_IF_CONFIG_REG_PREPARE |
484 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
485 mdelay(5);
486 }
487
eb7ff77e 488 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 489
490 /* Stop device's DMA activity */
7afe3705 491 iwl_pcie_apm_stop_master(trans);
cc56feb2 492
a812cba9
AB		 493 if (trans->cfg->lp_xtal_workaround) {
494 iwl_pcie_apm_lp_xtal_enable(trans);
495 return;
496 }
497
cc56feb2
EG		 498 /* Reset the entire device */
499 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
500
501 udelay(10);
502
503 /*
504 * Clear "initialization complete" bit to move adapter from
505 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
506 */
507 iwl_clear_bit(trans, CSR_GP_CNTRL,
508 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
509}
510
7afe3705 511static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 512{
7b11488f 513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 514
515 /* nic_init */
7b70bd63 516 spin_lock(&trans_pcie->irq_lock);
7afe3705 517 iwl_pcie_apm_init(trans);
392f8b78 518
7b70bd63 519 spin_unlock(&trans_pcie->irq_lock);
392f8b78 520
95411d04 521 iwl_pcie_set_pwr(trans, false);
392f8b78 522
ecdb975c 523 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 524
525 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 526 iwl_pcie_rx_init(trans);
392f8b78
EG		 527
528 /* Allocate or reset and init all Tx and Command queues */
f02831be 529 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 530 return -ENOMEM;
531
035f7ff2 532 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 533 /* enable shadow regs in HW */
20d3b647 534 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 535 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 536 }
537
392f8b78
EG		 538 return 0;
539}
540
541#define HW_READY_TIMEOUT (50)
542
543/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 544static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 545{
546 int ret;
547
1042db2a 548 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 549 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 550
551 /* See if we got it */
1042db2a 552 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 553 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
555 HW_READY_TIMEOUT);
392f8b78 556
6a08f514
EG		 557 if (ret >= 0)
558 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
559
6d8f6eeb 560 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 561 return ret;
562}
563
564/* Note: returns standard 0/-ERROR code */
7afe3705 565static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 566{
567 int ret;
289e5501 568 int t = 0;
501fd989 569 int iter;
392f8b78 570
6d8f6eeb 571 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 572
7afe3705 573 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 574 /* If the card is ready, exit 0 */
392f8b78
EG		 575 if (ret >= 0)
576 return 0;
577
501fd989
EG		 578 for (iter = 0; iter < 10; iter++) {
579 /* If HW is not ready, prepare the conditions to check again */
580 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
581 CSR_HW_IF_CONFIG_REG_PREPARE);
582
583 do {
584 ret = iwl_pcie_set_hw_ready(trans);
585 if (ret >= 0)
586 return 0;
392f8b78 587
501fd989
EG		 588 usleep_range(200, 1000);
589 t += 200;
590 } while (t < 150000);
591 msleep(25);
592 }
392f8b78 593
7f2ac8fb 594 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 595
392f8b78
EG		 596 return ret;
597}
598
cf614297
EG		 599/*
600 * ucode
601 */
7afe3705 602static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 603 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 604{
13df1aab 605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 606 int ret;
607
13df1aab 608 trans_pcie->ucode_write_complete = false;
cf614297
EG		 609
610 iwl_write_direct32(trans,
20d3b647
JB		 611 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
612 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 613
614 iwl_write_direct32(trans,
20d3b647
JB		 615 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
616 dst_addr);
cf614297
EG		 617
618 iwl_write_direct32(trans,
83f84d7b
JB		 619 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
620 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 621
622 iwl_write_direct32(trans,
20d3b647
JB		 623 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
624 (iwl_get_dma_hi_addr(phy_addr)
625 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 626
627 iwl_write_direct32(trans,
20d3b647
JB		 628 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
630 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 632
633 iwl_write_direct32(trans,
20d3b647
JB		 634 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
637 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 638
13df1aab
JB		 639 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
640 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 641 if (!ret) {
83f84d7b 642 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 643 return -ETIMEDOUT;
644 }
645
646 return 0;
647}
648
7afe3705 649static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 650 const struct fw_desc *section)
cf614297 651{
83f84d7b
JB		 652 u8 *v_addr;
653 dma_addr_t p_addr;
baa21e83 654 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 655 int ret = 0;
656
83f84d7b
JB		 657 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
658 section_num);
659
c571573a
EG		 660 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
661 GFP_KERNEL | __GFP_NOWARN);
662 if (!v_addr) {
663 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
664 chunk_sz = PAGE_SIZE;
665 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
666 &p_addr, GFP_KERNEL);
667 if (!v_addr)
668 return -ENOMEM;
669 }
83f84d7b 670
c571573a 671 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 672 u32 copy_size, dst_addr;
673 bool extended_addr = false;
83f84d7b 674
c571573a 675 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 676 dst_addr = section->offset + offset;
677
678 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
679 dst_addr <= IWL_FW_MEM_EXTENDED_END)
680 extended_addr = true;
681
682 if (extended_addr)
683 iwl_set_bits_prph(trans, LMPM_CHICK,
684 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 685
83f84d7b 686 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 687 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
688 copy_size);
689
690 if (extended_addr)
691 iwl_clear_bits_prph(trans, LMPM_CHICK,
692 LMPM_CHICK_EXTENDED_ADDR_SPACE);
693
83f84d7b
JB		 694 if (ret) {
695 IWL_ERR(trans,
696 "Could not load the [%d] uCode section\n",
697 section_num);
698 break;
6dfa8d01 699 }
83f84d7b
JB		 700 }
701
c571573a 702 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 703 return ret;
704}
705
16bc119b
EH		 706/*
707 * Driver Takes the ownership on secure machine before FW load
708 * and prevent race with the BT load.
709 * W/A for ROM bug. (should be remove in the next Si step)
710 */
711static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
712{
713 u32 val, loop = 1000;
714
1e167071
EH		 715 /*
716 * Check the RSA semaphore is accessible.
717 * If the HW isn't locked and the rsa semaphore isn't accessible,
718 * we are in trouble.
719 */
16bc119b
EH		 720 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
721 if (val & (BIT(1) | BIT(17))) {
1e167071
EH		 722 IWL_INFO(trans,
723 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 724 return 0;
725 }
726
727 /* take ownership on the AUX IF */
728 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
729 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
730
731 do {
732 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
733 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
734 if (val == 0x1) {
735 iwl_write_prph(trans, RSA_ENABLE, 0);
736 return 0;
737 }
738
739 udelay(10);
740 loop--;
741 } while (loop > 0);
742
743 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
744 return -EIO;
745}
746
5dd9c68a
EG		 747static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
748 const struct fw_img *image,
749 int cpu,
750 int *first_ucode_section)
e2d6f4e7
EH		 751{
752 int shift_param;
dcab8ecd
EH		 753 int i, ret = 0, sec_num = 0x1;
754 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 755
756 if (cpu == 1) {
757 shift_param = 0;
034846cf 758 *first_ucode_section = 0;
e2d6f4e7
EH		 759 } else {
760 shift_param = 16;
034846cf 761 (*first_ucode_section)++;
e2d6f4e7
EH		 762 }
763
034846cf
EH		 764 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
765 last_read_idx = i;
766
767 if (!image->sec[i].data ||
768 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
769 IWL_DEBUG_FW(trans,
770 "Break since Data not valid or Empty section, sec = %d\n",
771 i);
189fa2fa 772 break;
034846cf
EH		 773 }
774
189fa2fa
EH		 775 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
776 if (ret)
777 return ret;
dcab8ecd
EH		 778
779 /* Notify the ucode of the loaded section number and status */
780 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
781 val = val | (sec_num << shift_param);
782 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
783 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 784 }
785
034846cf
EH		 786 *first_ucode_section = last_read_idx;
787
afb88917
EH		 788 if (cpu == 1)
789 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
790 else
791 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
792
189fa2fa
EH		 793 return 0;
794}
e2d6f4e7 795
189fa2fa
EH		 796static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
797 const struct fw_img *image,
034846cf
EH		 798 int cpu,
799 int *first_ucode_section)
189fa2fa
EH		 800{
801 int shift_param;
189fa2fa 802 int i, ret = 0;
034846cf 803 u32 last_read_idx = 0;
189fa2fa
EH		 804
805 if (cpu == 1) {
806 shift_param = 0;
034846cf 807 *first_ucode_section = 0;
189fa2fa
EH		 808 } else {
809 shift_param = 16;
034846cf 810 (*first_ucode_section)++;
189fa2fa
EH		 811 }
812
034846cf
EH		 813 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
814 last_read_idx = i;
815
816 if (!image->sec[i].data ||
817 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
818 IWL_DEBUG_FW(trans,
819 "Break since Data not valid or Empty section, sec = %d\n",
820 i);
189fa2fa 821 break;
034846cf
EH		 822 }
823
189fa2fa
EH		 824 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
825 if (ret)
826 return ret;
e2d6f4e7
EH		 827 }
828
189fa2fa
EH		 829 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
830 iwl_set_bits_prph(trans,
831 CSR_UCODE_LOAD_STATUS_ADDR,
832 (LMPM_CPU_UCODE_LOADING_COMPLETED |
833 LMPM_CPU_HDRS_LOADING_COMPLETED |
834 LMPM_CPU_UCODE_LOADING_STARTED) <<
835 shift_param);
836
034846cf
EH		 837 *first_ucode_section = last_read_idx;
838
e2d6f4e7
EH		 839 return 0;
840}
841
09e350f7
LK		 842static void iwl_pcie_apply_destination(struct iwl_trans *trans)
843{
844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
845 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
846 int i;
847
848 if (dest->version)
849 IWL_ERR(trans,
850 "DBG DEST version is %d - expect issues\n",
851 dest->version);
852
853 IWL_INFO(trans, "Applying debug destination %s\n",
854 get_fw_dbg_mode_string(dest->monitor_mode));
855
856 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 857 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 858 else
859 IWL_WARN(trans, "PCI should have external buffer debug\n");
860
861 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
862 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
863 u32 val = le32_to_cpu(dest->reg_ops[i].val);
864
865 switch (dest->reg_ops[i].op) {
866 case CSR_ASSIGN:
867 iwl_write32(trans, addr, val);
868 break;
869 case CSR_SETBIT:
870 iwl_set_bit(trans, addr, BIT(val));
871 break;
872 case CSR_CLEARBIT:
873 iwl_clear_bit(trans, addr, BIT(val));
874 break;
875 case PRPH_ASSIGN:
876 iwl_write_prph(trans, addr, val);
877 break;
878 case PRPH_SETBIT:
879 iwl_set_bits_prph(trans, addr, BIT(val));
880 break;
881 case PRPH_CLEARBIT:
882 iwl_clear_bits_prph(trans, addr, BIT(val));
883 break;
884 default:
885 IWL_ERR(trans, "FW debug - unknown OP %d\n",
886 dest->reg_ops[i].op);
887 break;
888 }
889 }
890
891 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
892 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
893 trans_pcie->fw_mon_phys >> dest->base_shift);
894 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
895 (trans_pcie->fw_mon_phys +
896 trans_pcie->fw_mon_size) >> dest->end_shift);
897 }
898}
899
7afe3705 900static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 901 const struct fw_img *image)
cf614297 902{
c2d20201 903 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 904 int ret = 0;
034846cf 905 int first_ucode_section;
cf614297 906
dcab8ecd 907 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 908 image->is_dual_cpus ? "Dual" : "Single");
909
dcab8ecd
EH		 910 /* load to FW the binary non secured sections of CPU1 */
911 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
912 if (ret)
913 return ret;
e2d6f4e7
EH		 914
915 if (image->is_dual_cpus) {
189fa2fa
EH		 916 /* set CPU2 header address */
917 iwl_write_prph(trans,
918 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
919 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 920
189fa2fa 921 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 922 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
923 &first_ucode_section);
189fa2fa
EH		 924 if (ret)
925 return ret;
e2d6f4e7 926 }
cf614297 927
c2d20201
EG		 928 /* supported for 7000 only for the moment */
929 if (iwlwifi_mod_params.fw_monitor &&
930 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 931 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 932
933 if (trans_pcie->fw_mon_size) {
934 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
935 trans_pcie->fw_mon_phys >> 4);
936 iwl_write_prph(trans, MON_BUFF_END_ADDR,
937 (trans_pcie->fw_mon_phys +
938 trans_pcie->fw_mon_size) >> 4);
939 }
09e350f7
LK		 940 } else if (trans->dbg_dest_tlv) {
941 iwl_pcie_apply_destination(trans);
c2d20201
EG		 942 }
943
e12ba844 944 /* release CPU reset */
5dd9c68a 945 iwl_write32(trans, CSR_RESET, 0);
e12ba844 946
dcab8ecd
EH		 947 return 0;
948}
189fa2fa 949
5dd9c68a
EG		 950static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
951 const struct fw_img *image)
dcab8ecd
EH		 952{
953 int ret = 0;
954 int first_ucode_section;
dcab8ecd
EH		 955
956 IWL_DEBUG_FW(trans, "working with %s CPU\n",
957 image->is_dual_cpus ? "Dual" : "Single");
958
a2227ce2
EG		 959 if (trans->dbg_dest_tlv)
960 iwl_pcie_apply_destination(trans);
961
16bc119b
EH		 962 /* TODO: remove in the next Si step */
963 ret = iwl_pcie_rsa_race_bug_wa(trans);
964 if (ret)
965 return ret;
966
dcab8ecd
EH		 967 /* configure the ucode to be ready to get the secured image */
968 /* release CPU reset */
969 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
970
971 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 972 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
973 &first_ucode_section);
dcab8ecd
EH		 974 if (ret)
975 return ret;
976
977 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 978 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
979 &first_ucode_section);
cf614297
EG		 980}
981
0692fe41 982static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 983 const struct fw_img *fw, bool run_in_rfkill)
392f8b78
EG		 984{
985 int ret;
c9eec95c 986 bool hw_rfkill;
392f8b78 987
496bab39 988 /* This may fail if AMT took ownership of the device */
7afe3705 989 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 990 IWL_WARN(trans, "Exit HW not ready\n");
392f8b78
EG		 991 return -EIO;
992 }
993
8c46bb70
EG		 994 iwl_enable_rfkill_int(trans);
995
392f8b78 996 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 997 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 998 if (hw_rfkill)
eb7ff77e 999 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1000 else
eb7ff77e 1001 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1002 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
6ae02f3e 1003 if (hw_rfkill && !run_in_rfkill)
392f8b78 1004 return -ERFKILL;
392f8b78 1005
1042db2a 1006 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 1007
7afe3705 1008 ret = iwl_pcie_nic_init(trans);
392f8b78 1009 if (ret) {
6d8f6eeb 1010 IWL_ERR(trans, "Unable to init nic\n");
392f8b78
EG		 1011 return ret;
1012 }
1013
1014 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 1015 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1016 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 1017 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1018
1019 /* clear (again), then enable host interrupts */
1042db2a 1020 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 1021 iwl_enable_interrupts(trans);
392f8b78
EG		 1022
1023 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 1024 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1025 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 1026
cf614297 1027 /* Load the given image to the HW */
5dd9c68a
EG		 1028 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1029 return iwl_pcie_load_given_ucode_8000(trans, fw);
dcab8ecd
EH		 1030 else
1031 return iwl_pcie_load_given_ucode(trans, fw);
b3c2ce13
EG		 1032}
1033
adca1235 1034static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 1035{
990aa6d7 1036 iwl_pcie_reset_ict(trans);
f02831be 1037 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 1038}
1039
8d193ca2 1040static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1041{
43e58856 1042 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1043 bool hw_rfkill, was_hw_rfkill;
1044
1045 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1046
43e58856 1047 /* tell the device to stop sending interrupts */
7b70bd63 1048 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1049 iwl_disable_interrupts(trans);
7b70bd63 1050 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1051
ab6cf8e8 1052 /* device going down, Stop using ICT table */
990aa6d7 1053 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1054
1055 /*
1056 * If a HW restart happens during firmware loading,
1057 * then the firmware loading might call this function
1058 * and later it might be called again due to the
1059 * restart. So don't process again if the device is
1060 * already dead.
1061 */
31b8b343
EG		 1062 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1063 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1064 iwl_pcie_tx_stop(trans);
9805c446 1065 iwl_pcie_rx_stop(trans);
6379103e 1066
ab6cf8e8 1067 /* Power-down device's busmaster DMA clocks */
95411d04 1068 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1069 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1070 APMG_CLK_VAL_DMA_CLK_RQT);
1071 udelay(5);
1072 }
ab6cf8e8
EG		 1073 }
1074
1075 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1076 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1077 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1078
1079 /* Stop the device, and put it in low power state */
b7aaeae4 1080 iwl_pcie_apm_stop(trans, false);
43e58856 1081
03d6c3b0
EG		 1082 /* stop and reset the on-board processor */
1083 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1084 udelay(20);
1085
1086 /*
1087 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1088 * This is a bug in certain verions of the hardware.
1089 * Certain devices also keep sending HW RF kill interrupt all
1090 * the time, unless the interrupt is ACKed even if the interrupt
1091 * should be masked. Re-ACK all the interrupts here.
43e58856 1092 */
7b70bd63 1093 spin_lock(&trans_pcie->irq_lock);
43e58856 1094 iwl_disable_interrupts(trans);
7b70bd63 1095 spin_unlock(&trans_pcie->irq_lock);
43e58856 1096
74fda971
DF		 1097
1098 /* clear all status bits */
eb7ff77e
AN		 1099 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1100 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1101 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1102 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1103
1104 /*
1105 * Even if we stop the HW, we still want the RF kill
1106 * interrupt
1107 */
1108 iwl_enable_rfkill_int(trans);
1109
1110 /*
1111 * Check again since the RF kill state may have changed while
1112 * all the interrupts were disabled, in this case we couldn't
1113 * receive the RF kill interrupt and update the state in the
1114 * op_mode.
3dc3374f
EG		 1115 * Don't call the op_mode if the rkfill state hasn't changed.
1116 * This allows the op_mode to call stop_device from the rfkill
1117 * notification without endless recursion. Under very rare
1118 * circumstances, we might have a small recursion if the rfkill
1119 * state changed exactly now while we were called from stop_device.
1120 * This is very unlikely but can happen and is supported.
a4082843
AN		 1121 */
1122 hw_rfkill = iwl_is_rfkill_set(trans);
1123 if (hw_rfkill)
eb7ff77e 1124 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1125 else
eb7ff77e 1126 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1127 if (hw_rfkill != was_hw_rfkill)
14cfca71 1128 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1129
1130 /* re-take ownership to prevent other users from stealing the deivce */
1131 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1132}
1133
1134void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1135{
1136 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
8d193ca2 1137 iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1138}
1139
debff618 1140static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1141{
2dd4f9f7 1142 iwl_disable_interrupts(trans);
debff618
JB		 1143
1144 /*
1145 * in testing mode, the host stays awake and the
1146 * hardware won't be reset (not even partially)
1147 */
1148 if (test)
1149 return;
1150
ddaf5a5b
JB		 1151 iwl_pcie_disable_ict(trans);
1152
2dd4f9f7
JB		 1153 iwl_clear_bit(trans, CSR_GP_CNTRL,
1154 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1155 iwl_clear_bit(trans, CSR_GP_CNTRL,
1156 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1157
1158 /*
1159 * reset TX queues -- some of their registers reset during S3
1160 * so if we don't reset everything here the D3 image would try
1161 * to execute some invalid memory upon resume
1162 */
1163 iwl_trans_pcie_tx_reset(trans);
1164
1165 iwl_pcie_set_pwr(trans, true);
1166}
1167
1168static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1169 enum iwl_d3_status *status,
1170 bool test)
ddaf5a5b
JB		 1171{
1172 u32 val;
1173 int ret;
1174
debff618
JB		 1175 if (test) {
1176 iwl_enable_interrupts(trans);
1177 *status = IWL_D3_STATUS_ALIVE;
1178 return 0;
1179 }
1180
ddaf5a5b
JB		 1181 /*
1182 * Also enables interrupts - none will happen as the device doesn't
1183 * know we're waking it up, only when the opmode actually tells it
1184 * after this call.
1185 */
1186 iwl_pcie_reset_ict(trans);
1187
1188 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1189 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1190
01e58a28
EG		 1191 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1192 udelay(2);
1193
ddaf5a5b
JB		 1194 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1195 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1196 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1197 25000);
7f2ac8fb 1198 if (ret < 0) {
ddaf5a5b
JB		 1199 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1200 return ret;
1201 }
1202
a3ead656
EG		 1203 iwl_pcie_set_pwr(trans, false);
1204
ddaf5a5b
JB		 1205 iwl_trans_pcie_tx_reset(trans);
1206
1207 ret = iwl_pcie_rx_init(trans);
1208 if (ret) {
1209 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1210 return ret;
1211 }
1212
a3ead656
EG		 1213 val = iwl_read32(trans, CSR_RESET);
1214 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1215 *status = IWL_D3_STATUS_RESET;
1216 else
1217 *status = IWL_D3_STATUS_ALIVE;
1218
ddaf5a5b 1219 return 0;
2dd4f9f7
JB		 1220}
1221
8d193ca2 1222static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1223{
c9eec95c 1224 bool hw_rfkill;
a8b691e6 1225 int err;
e6bb4c9c 1226
7afe3705 1227 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1228 if (err) {
d6f1c316 1229 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1230 return err;
ebb7678d 1231 }
a6c684ee 1232
2997494f 1233 /* Reset the entire device */
ce836c76 1234 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1235
1236 usleep_range(10, 15);
1237
7afe3705 1238 iwl_pcie_apm_init(trans);
a6c684ee 1239
226c02ca
EG		 1240 /* From now on, the op_mode will be kept updated about RF kill state */
1241 iwl_enable_rfkill_int(trans);
1242
8d425517 1243 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1244 if (hw_rfkill)
eb7ff77e 1245 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1246 else
eb7ff77e 1247 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1248 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1249
a8b691e6 1250 return 0;
e6bb4c9c
EG		 1251}
1252
a4082843 1253static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1254{
20d3b647 1255 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1256
a4082843 1257 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1258 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1259 iwl_disable_interrupts(trans);
7b70bd63 1260 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1261
b7aaeae4 1262 iwl_pcie_apm_stop(trans, true);
cc56feb2 1263
7b70bd63 1264 spin_lock(&trans_pcie->irq_lock);
218733cf 1265 iwl_disable_interrupts(trans);
7b70bd63 1266 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1267
8d96bb61 1268 iwl_pcie_disable_ict(trans);
cc56feb2
EG		 1269}
1270
03905495
EG		 1271static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1272{
05f5b97e 1273 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1274}
1275
1276static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1277{
05f5b97e 1278 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1279}
1280
1281static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1282{
05f5b97e 1283 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1284}
1285
6a06b6c1
EG		 1286static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1287{
f9477c17
AP		 1288 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1289 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1290 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1291}
1292
1293static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1294 u32 val)
1295{
1296 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1297 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1298 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1299}
1300
f14d6b39
JB		 1301static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1302{
1303 WARN_ON(1);
1304 return 0;
1305}
1306
c6f600fc 1307static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1308 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1309{
1310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1311
1312 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1313 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1314 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1315 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1316 trans_pcie->n_no_reclaim_cmds = 0;
1317 else
1318 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1319 if (trans_pcie->n_no_reclaim_cmds)
1320 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1321 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1322
b2cf410c
JB		 1323 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1324 if (trans_pcie->rx_buf_size_8k)
1325 trans_pcie->rx_page_order = get_order(8 * 1024);
1326 else
1327 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8 1328
d9fb6465 1329 trans_pcie->command_names = trans_cfg->command_names;
046db346 1330 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1331 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39 1332
483f3ab1
EP		 1333 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1334 trans_pcie->ref_count = 1;
1335
f14d6b39
JB		 1336 /* Initialize NAPI here - it should be before registering to mac80211
1337 * in the opmode but after the HW struct is allocated.
1338 * As this function may be called again in some corner cases don't
1339 * do anything if NAPI was already initialized.
1340 */
1341 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1342 init_dummy_netdev(&trans_pcie->napi_dev);
1343 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1344 &trans_pcie->napi_dev,
1345 iwl_pcie_dummy_napi_poll, 64);
1346 }
c6f600fc
MV		 1347}
1348
d1ff5253 1349void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1350{
20d3b647 1351 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1352
0aa86df6 1353 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1354
f02831be 1355 iwl_pcie_tx_free(trans);
9805c446 1356 iwl_pcie_rx_free(trans);
6379103e 1357
a8b691e6
JB		 1358 free_irq(trans_pcie->pci_dev->irq, trans);
1359 iwl_pcie_free_ict(trans);
a42a1844
EG		 1360
1361 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1362 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1363 pci_release_regions(trans_pcie->pci_dev);
1364 pci_disable_device(trans_pcie->pci_dev);
1365
f14d6b39
JB		 1366 if (trans_pcie->napi.poll)
1367 netif_napi_del(&trans_pcie->napi);
1368
c2d20201
EG		 1369 iwl_pcie_free_fw_monitor(trans);
1370
7b501d10 1371 iwl_trans_free(trans);
34c1b7ba
EG		 1372}
1373
47107e84
DF		 1374static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1375{
47107e84 1376 if (state)
eb7ff77e 1377 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1378 else
eb7ff77e 1379 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1380}
1381
e56b04ef
LE		 1382static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1383 unsigned long *flags)
7a65d170
EG		 1384{
1385 int ret;
cfb4e624
JB		 1386 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1387
1388 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1389
fc8a350d 1390 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1391 goto out;
1392
7a65d170 1393 /* this bit wakes up the NIC */
e139dc4a
LE		 1394 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1395 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1396 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1397 udelay(2);
7a65d170
EG		 1398
1399 /*
1400 * These bits say the device is running, and should keep running for
1401 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1402 * but they do not indicate that embedded SRAM is restored yet;
1403 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1404 * to/from host DRAM when sleeping/waking for power-saving.
1405 * Each direction takes approximately 1/4 millisecond; with this
1406 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1407 * series of register accesses are expected (e.g. reading Event Log),
1408 * to keep device from sleeping.
1409 *
1410 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1411 * SRAM is okay/restored. We don't check that here because this call
1412 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1413 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1414 *
1415 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1416 * and do not save/restore SRAM when power cycling.
1417 */
1418 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1419 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1420 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1421 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1422 if (unlikely(ret < 0)) {
1423 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1424 if (!silent) {
1425 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1426 WARN_ONCE(1,
1427 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1428 val);
cfb4e624 1429 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1430 return false;
1431 }
1432 }
1433
b9439491 1434out:
e56b04ef
LE		 1435 /*
1436 * Fool sparse by faking we release the lock - sparse will
1437 * track nic_access anyway.
1438 */
cfb4e624 1439 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1440 return true;
1441}
1442
e56b04ef
LE		 1443static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1444 unsigned long *flags)
7a65d170 1445{
cfb4e624 1446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1447
cfb4e624 1448 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1449
1450 /*
1451 * Fool sparse by faking we acquiring the lock - sparse will
1452 * track nic_access anyway.
1453 */
cfb4e624 1454 __acquire(&trans_pcie->reg_lock);
e56b04ef 1455
fc8a350d 1456 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1457 goto out;
1458
e139dc4a
LE		 1459 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1460 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1461 /*
1462 * Above we read the CSR_GP_CNTRL register, which will flush
1463 * any previous writes, but we need the write that clears the
1464 * MAC_ACCESS_REQ bit to be performed before any other writes
1465 * scheduled on different CPUs (after we drop reg_lock).
1466 */
1467 mmiowb();
b9439491 1468out:
cfb4e624 1469 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1470}
1471
4fd442db
EG		 1472static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1473 void *buf, int dwords)
1474{
1475 unsigned long flags;
1476 int offs, ret = 0;
1477 u32 *vals = buf;
1478
e56b04ef 1479 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1480 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1481 for (offs = 0; offs < dwords; offs++)
1482 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1483 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1484 } else {
1485 ret = -EBUSY;
1486 }
4fd442db
EG		 1487 return ret;
1488}
1489
1490static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1491 const void *buf, int dwords)
4fd442db
EG		 1492{
1493 unsigned long flags;
1494 int offs, ret = 0;
bf0fd5da 1495 const u32 *vals = buf;
4fd442db 1496
e56b04ef 1497 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1498 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1499 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1500 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1501 vals ? vals[offs] : 0);
e56b04ef 1502 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1503 } else {
1504 ret = -EBUSY;
1505 }
4fd442db
EG		 1506 return ret;
1507}
7a65d170 1508
e0b8d405
EG		 1509static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1510 unsigned long txqs,
1511 bool freeze)
1512{
1513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1514 int queue;
1515
1516 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1517 struct iwl_txq *txq = &trans_pcie->txq[queue];
1518 unsigned long now;
1519
1520 spin_lock_bh(&txq->lock);
1521
1522 now = jiffies;
1523
1524 if (txq->frozen == freeze)
1525 goto next_queue;
1526
1527 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1528 freeze ? "Freezing" : "Waking", queue);
1529
1530 txq->frozen = freeze;
1531
1532 if (txq->q.read_ptr == txq->q.write_ptr)
1533 goto next_queue;
1534
1535 if (freeze) {
1536 if (unlikely(time_after(now,
1537 txq->stuck_timer.expires))) {
1538 /*
1539 * The timer should have fired, maybe it is
1540 * spinning right now on the lock.
1541 */
1542 goto next_queue;
1543 }
1544 /* remember how long until the timer fires */
1545 txq->frozen_expiry_remainder =
1546 txq->stuck_timer.expires - now;
1547 del_timer(&txq->stuck_timer);
1548 goto next_queue;
1549 }
1550
1551 /*
1552 * Wake a non-empty queue -> arm timer with the
1553 * remainder before it froze
1554 */
1555 mod_timer(&txq->stuck_timer,
1556 now + txq->frozen_expiry_remainder);
1557
1558next_queue:
1559 spin_unlock_bh(&txq->lock);
1560 }
1561}
1562
5f178cd2
EG		 1563#define IWL_FLUSH_WAIT_MS 2000
1564
3cafdbe6 1565static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1566{
8ad71bef 1567 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1568 struct iwl_txq *txq;
5f178cd2
EG		 1569 struct iwl_queue *q;
1570 int cnt;
1571 unsigned long now = jiffies;
1c3fea82
EG		 1572 u32 scd_sram_addr;
1573 u8 buf[16];
5f178cd2
EG		 1574 int ret = 0;
1575
1576 /* waiting for all the tx frames complete might take a while */
035f7ff2 1577 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1578 u8 wr_ptr;
1579
9ba1947a 1580 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1581 continue;
3cafdbe6
EG		 1582 if (!test_bit(cnt, trans_pcie->queue_used))
1583 continue;
1584 if (!(BIT(cnt) & txq_bm))
1585 continue;
748fa67c
EG		 1586
1587 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1588 txq = &trans_pcie->txq[cnt];
5f178cd2 1589 q = &txq->q;
fa1a91fd
EG		 1590 wr_ptr = ACCESS_ONCE(q->write_ptr);
1591
1592 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1593 !time_after(jiffies,
1594 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1595 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1596
1597 if (WARN_ONCE(wr_ptr != write_ptr,
1598 "WR pointer moved while flushing %d -> %d\n",
1599 wr_ptr, write_ptr))
1600 return -ETIMEDOUT;
5f178cd2 1601 msleep(1);
fa1a91fd 1602 }
5f178cd2
EG		 1603
1604 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1605 IWL_ERR(trans,
1606 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1607 ret = -ETIMEDOUT;
1608 break;
1609 }
748fa67c 1610 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1611 }
1c3fea82
EG		 1612
1613 if (!ret)
1614 return 0;
1615
1616 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1617 txq->q.read_ptr, txq->q.write_ptr);
1618
1619 scd_sram_addr = trans_pcie->scd_base_addr +
1620 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1621 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1622
1623 iwl_print_hex_error(trans, buf, sizeof(buf));
1624
1625 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1626 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1627 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1628
1629 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1630 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1631 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1632 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1633 u32 tbl_dw =
1634 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1635 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1636
1637 if (cnt & 0x1)
1638 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1639 else
1640 tbl_dw = tbl_dw & 0x0000FFFF;
1641
1642 IWL_ERR(trans,
1643 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1644 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1645 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1646 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1647 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1648 }
1649
5f178cd2
EG		 1650 return ret;
1651}
1652
e139dc4a
LE		 1653static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1654 u32 mask, u32 value)
1655{
e56b04ef 1656 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1657 unsigned long flags;
1658
e56b04ef 1659 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1660 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1661 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1662}
1663
7616f334
EP		 1664void iwl_trans_pcie_ref(struct iwl_trans *trans)
1665{
1666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1667 unsigned long flags;
1668
1669 if (iwlwifi_mod_params.d0i3_disable)
1670 return;
1671
1672 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1673 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1674 trans_pcie->ref_count++;
1675 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1676}
1677
1678void iwl_trans_pcie_unref(struct iwl_trans *trans)
1679{
1680 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1681 unsigned long flags;
1682
1683 if (iwlwifi_mod_params.d0i3_disable)
1684 return;
1685
1686 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1687 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1688 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1689 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1690 return;
1691 }
1692 trans_pcie->ref_count--;
1693 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1694}
1695
ff620849
EG		 1696static const char *get_csr_string(int cmd)
1697{
d9fb6465 1698#define IWL_CMD(x) case x: return #x
ff620849
EG		 1699 switch (cmd) {
1700 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1701 IWL_CMD(CSR_INT_COALESCING);
1702 IWL_CMD(CSR_INT);
1703 IWL_CMD(CSR_INT_MASK);
1704 IWL_CMD(CSR_FH_INT_STATUS);
1705 IWL_CMD(CSR_GPIO_IN);
1706 IWL_CMD(CSR_RESET);
1707 IWL_CMD(CSR_GP_CNTRL);
1708 IWL_CMD(CSR_HW_REV);
1709 IWL_CMD(CSR_EEPROM_REG);
1710 IWL_CMD(CSR_EEPROM_GP);
1711 IWL_CMD(CSR_OTP_GP_REG);
1712 IWL_CMD(CSR_GIO_REG);
1713 IWL_CMD(CSR_GP_UCODE_REG);
1714 IWL_CMD(CSR_GP_DRIVER_REG);
1715 IWL_CMD(CSR_UCODE_DRV_GP1);
1716 IWL_CMD(CSR_UCODE_DRV_GP2);
1717 IWL_CMD(CSR_LED_REG);
1718 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1719 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1720 IWL_CMD(CSR_ANA_PLL_CFG);
1721 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1722 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1723 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1724 default:
1725 return "UNKNOWN";
1726 }
d9fb6465 1727#undef IWL_CMD
ff620849
EG		 1728}
1729
990aa6d7 1730void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1731{
1732 int i;
1733 static const u32 csr_tbl[] = {
1734 CSR_HW_IF_CONFIG_REG,
1735 CSR_INT_COALESCING,
1736 CSR_INT,
1737 CSR_INT_MASK,
1738 CSR_FH_INT_STATUS,
1739 CSR_GPIO_IN,
1740 CSR_RESET,
1741 CSR_GP_CNTRL,
1742 CSR_HW_REV,
1743 CSR_EEPROM_REG,
1744 CSR_EEPROM_GP,
1745 CSR_OTP_GP_REG,
1746 CSR_GIO_REG,
1747 CSR_GP_UCODE_REG,
1748 CSR_GP_DRIVER_REG,
1749 CSR_UCODE_DRV_GP1,
1750 CSR_UCODE_DRV_GP2,
1751 CSR_LED_REG,
1752 CSR_DRAM_INT_TBL_REG,
1753 CSR_GIO_CHICKEN_BITS,
1754 CSR_ANA_PLL_CFG,
a812cba9 1755 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1756 CSR_HW_REV_WA_REG,
1757 CSR_DBG_HPET_MEM_REG
1758 };
1759 IWL_ERR(trans, "CSR values:\n");
1760 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1761 "CSR_INT_PERIODIC_REG)\n");
1762 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1763 IWL_ERR(trans, " %25s: 0X%08x\n",
1764 get_csr_string(csr_tbl[i]),
1042db2a 1765 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1766 }
1767}
1768
87e5666c
EG		 1769#ifdef CONFIG_IWLWIFI_DEBUGFS
1770/* create and remove of files */
1771#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1772 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1773 &iwl_dbgfs_##name##_ops)) \
9da987ac 1774 goto err; \
87e5666c
EG		 1775} while (0)
1776
1777/* file operation */
87e5666c 1778#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1779static const struct file_operations iwl_dbgfs_##name##_ops = { \
1780 .read = iwl_dbgfs_##name##_read, \
234e3405 1781 .open = simple_open, \
87e5666c
EG		 1782 .llseek = generic_file_llseek, \
1783};
1784
16db88ba 1785#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1786static const struct file_operations iwl_dbgfs_##name##_ops = { \
1787 .write = iwl_dbgfs_##name##_write, \
234e3405 1788 .open = simple_open, \
16db88ba
EG		 1789 .llseek = generic_file_llseek, \
1790};
1791
87e5666c 1792#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1793static const struct file_operations iwl_dbgfs_##name##_ops = { \
1794 .write = iwl_dbgfs_##name##_write, \
1795 .read = iwl_dbgfs_##name##_read, \
234e3405 1796 .open = simple_open, \
87e5666c
EG		 1797 .llseek = generic_file_llseek, \
1798};
1799
87e5666c 1800static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1801 char __user *user_buf,
1802 size_t count, loff_t *ppos)
8ad71bef 1803{
5a878bf6 1804 struct iwl_trans *trans = file->private_data;
8ad71bef 1805 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1806 struct iwl_txq *txq;
87e5666c
EG		 1807 struct iwl_queue *q;
1808 char *buf;
1809 int pos = 0;
1810 int cnt;
1811 int ret;
1745e440
WYG		 1812 size_t bufsz;
1813
e0b8d405 1814 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 1815
f9e75447 1816 if (!trans_pcie->txq)
87e5666c 1817 return -EAGAIN;
f9e75447 1818
87e5666c
EG		 1819 buf = kzalloc(bufsz, GFP_KERNEL);
1820 if (!buf)
1821 return -ENOMEM;
1822
035f7ff2 1823 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1824 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1825 q = &txq->q;
1826 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 1827 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 1828 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1829 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 1830 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 1831 txq->need_update, txq->frozen,
f40faf62 1832 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1833 }
1834 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1835 kfree(buf);
1836 return ret;
1837}
1838
1839static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1840 char __user *user_buf,
1841 size_t count, loff_t *ppos)
1842{
5a878bf6 1843 struct iwl_trans *trans = file->private_data;
20d3b647 1844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1845 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1846 char buf[256];
1847 int pos = 0;
1848 const size_t bufsz = sizeof(buf);
1849
1850 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1851 rxq->read);
1852 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1853 rxq->write);
f40faf62
AL		 1854 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1855 rxq->write_actual);
1856 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1857 rxq->need_update);
87e5666c
EG		 1858 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1859 rxq->free_count);
1860 if (rxq->rb_stts) {
1861 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1862 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1863 } else {
1864 pos += scnprintf(buf + pos, bufsz - pos,
1865 "closed_rb_num: Not Allocated\n");
1866 }
1867 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1868}
1869
1f7b6172
EG		 1870static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1871 char __user *user_buf,
20d3b647
JB		 1872 size_t count, loff_t *ppos)
1873{
1f7b6172 1874 struct iwl_trans *trans = file->private_data;
20d3b647 1875 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1876 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1877
1878 int pos = 0;
1879 char *buf;
1880 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1881 ssize_t ret;
1882
1883 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1884 if (!buf)
1f7b6172 1885 return -ENOMEM;
1f7b6172
EG		 1886
1887 pos += scnprintf(buf + pos, bufsz - pos,
1888 "Interrupt Statistics Report:\n");
1889
1890 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1891 isr_stats->hw);
1892 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1893 isr_stats->sw);
1894 if (isr_stats->sw || isr_stats->hw) {
1895 pos += scnprintf(buf + pos, bufsz - pos,
1896 "\tLast Restarting Code: 0x%X\n",
1897 isr_stats->err_code);
1898 }
1899#ifdef CONFIG_IWLWIFI_DEBUG
1900 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1901 isr_stats->sch);
1902 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1903 isr_stats->alive);
1904#endif
1905 pos += scnprintf(buf + pos, bufsz - pos,
1906 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1907
1908 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1909 isr_stats->ctkill);
1910
1911 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1912 isr_stats->wakeup);
1913
1914 pos += scnprintf(buf + pos, bufsz - pos,
1915 "Rx command responses:\t\t %u\n", isr_stats->rx);
1916
1917 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1918 isr_stats->tx);
1919
1920 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1921 isr_stats->unhandled);
1922
1923 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1924 kfree(buf);
1925 return ret;
1926}
1927
1928static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1929 const char __user *user_buf,
1930 size_t count, loff_t *ppos)
1931{
1932 struct iwl_trans *trans = file->private_data;
20d3b647 1933 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1934 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1935
1936 char buf[8];
1937 int buf_size;
1938 u32 reset_flag;
1939
1940 memset(buf, 0, sizeof(buf));
1941 buf_size = min(count, sizeof(buf) - 1);
1942 if (copy_from_user(buf, user_buf, buf_size))
1943 return -EFAULT;
1944 if (sscanf(buf, "%x", &reset_flag) != 1)
1945 return -EFAULT;
1946 if (reset_flag == 0)
1947 memset(isr_stats, 0, sizeof(*isr_stats));
1948
1949 return count;
1950}
1951
16db88ba 1952static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 1953 const char __user *user_buf,
1954 size_t count, loff_t *ppos)
16db88ba
EG		 1955{
1956 struct iwl_trans *trans = file->private_data;
1957 char buf[8];
1958 int buf_size;
1959 int csr;
1960
1961 memset(buf, 0, sizeof(buf));
1962 buf_size = min(count, sizeof(buf) - 1);
1963 if (copy_from_user(buf, user_buf, buf_size))
1964 return -EFAULT;
1965 if (sscanf(buf, "%d", &csr) != 1)
1966 return -EFAULT;
1967
990aa6d7 1968 iwl_pcie_dump_csr(trans);
16db88ba
EG		 1969
1970 return count;
1971}
1972
16db88ba 1973static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 1974 char __user *user_buf,
1975 size_t count, loff_t *ppos)
16db88ba
EG		 1976{
1977 struct iwl_trans *trans = file->private_data;
94543a8d 1978 char *buf = NULL;
56c2477f 1979 ssize_t ret;
16db88ba 1980
56c2477f
JB		 1981 ret = iwl_dump_fh(trans, &buf);
1982 if (ret < 0)
1983 return ret;
1984 if (!buf)
1985 return -EINVAL;
1986 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1987 kfree(buf);
16db88ba
EG		 1988 return ret;
1989}
1990
1f7b6172 1991DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 1992DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 1993DEBUGFS_READ_FILE_OPS(rx_queue);
1994DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 1995DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 1996
1997/*
1998 * Create the debugfs files and directories
1999 *
2000 */
2001static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 2002 struct dentry *dir)
87e5666c 2003{
87e5666c
EG		 2004 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2005 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2006 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2007 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2008 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2009 return 0;
9da987ac
MV		 2010
2011err:
2012 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2013 return -ENOMEM;
87e5666c 2014}
aadede6e
JB		 2015#else
2016static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2017 struct dentry *dir)
2018{
2019 return 0;
2020}
2021#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2022
2023static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2024{
2025 u32 cmdlen = 0;
2026 int i;
2027
2028 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2029 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2030
2031 return cmdlen;
2032}
2033
67c65f2c
EG		 2034static const struct {
2035 u32 start, end;
2036} iwl_prph_dump_addr[] = {
2037 { .start = 0x00a00000, .end = 0x00a00000 },
2038 { .start = 0x00a0000c, .end = 0x00a00024 },
2039 { .start = 0x00a0002c, .end = 0x00a0003c },
2040 { .start = 0x00a00410, .end = 0x00a00418 },
2041 { .start = 0x00a00420, .end = 0x00a00420 },
2042 { .start = 0x00a00428, .end = 0x00a00428 },
2043 { .start = 0x00a00430, .end = 0x00a0043c },
2044 { .start = 0x00a00444, .end = 0x00a00444 },
2045 { .start = 0x00a004c0, .end = 0x00a004cc },
2046 { .start = 0x00a004d8, .end = 0x00a004d8 },
2047 { .start = 0x00a004e0, .end = 0x00a004f0 },
2048 { .start = 0x00a00840, .end = 0x00a00840 },
2049 { .start = 0x00a00850, .end = 0x00a00858 },
2050 { .start = 0x00a01004, .end = 0x00a01008 },
2051 { .start = 0x00a01010, .end = 0x00a01010 },
2052 { .start = 0x00a01018, .end = 0x00a01018 },
2053 { .start = 0x00a01024, .end = 0x00a01024 },
2054 { .start = 0x00a0102c, .end = 0x00a01034 },
2055 { .start = 0x00a0103c, .end = 0x00a01040 },
2056 { .start = 0x00a01048, .end = 0x00a01094 },
2057 { .start = 0x00a01c00, .end = 0x00a01c20 },
2058 { .start = 0x00a01c58, .end = 0x00a01c58 },
2059 { .start = 0x00a01c7c, .end = 0x00a01c7c },
2060 { .start = 0x00a01c28, .end = 0x00a01c54 },
2061 { .start = 0x00a01c5c, .end = 0x00a01c5c },
6a65bd53 2062 { .start = 0x00a01c60, .end = 0x00a01cdc },
67c65f2c
EG		 2063 { .start = 0x00a01ce0, .end = 0x00a01d0c },
2064 { .start = 0x00a01d18, .end = 0x00a01d20 },
2065 { .start = 0x00a01d2c, .end = 0x00a01d30 },
2066 { .start = 0x00a01d40, .end = 0x00a01d5c },
2067 { .start = 0x00a01d80, .end = 0x00a01d80 },
6a65bd53
EG		 2068 { .start = 0x00a01d98, .end = 0x00a01d9c },
2069 { .start = 0x00a01da8, .end = 0x00a01da8 },
2070 { .start = 0x00a01db8, .end = 0x00a01df4 },
67c65f2c
EG		 2071 { .start = 0x00a01dc0, .end = 0x00a01dfc },
2072 { .start = 0x00a01e00, .end = 0x00a01e2c },
2073 { .start = 0x00a01e40, .end = 0x00a01e60 },
6a65bd53
EG		 2074 { .start = 0x00a01e68, .end = 0x00a01e6c },
2075 { .start = 0x00a01e74, .end = 0x00a01e74 },
67c65f2c
EG		 2076 { .start = 0x00a01e84, .end = 0x00a01e90 },
2077 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
6a65bd53
EG		 2078 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2079 { .start = 0x00a01f00, .end = 0x00a01f1c },
2080 { .start = 0x00a01f44, .end = 0x00a01ffc },
67c65f2c
EG		 2081 { .start = 0x00a02000, .end = 0x00a02048 },
2082 { .start = 0x00a02068, .end = 0x00a020f0 },
2083 { .start = 0x00a02100, .end = 0x00a02118 },
2084 { .start = 0x00a02140, .end = 0x00a0214c },
2085 { .start = 0x00a02168, .end = 0x00a0218c },
2086 { .start = 0x00a021c0, .end = 0x00a021c0 },
2087 { .start = 0x00a02400, .end = 0x00a02410 },
2088 { .start = 0x00a02418, .end = 0x00a02420 },
2089 { .start = 0x00a02428, .end = 0x00a0242c },
2090 { .start = 0x00a02434, .end = 0x00a02434 },
2091 { .start = 0x00a02440, .end = 0x00a02460 },
2092 { .start = 0x00a02468, .end = 0x00a024b0 },
2093 { .start = 0x00a024c8, .end = 0x00a024cc },
2094 { .start = 0x00a02500, .end = 0x00a02504 },
2095 { .start = 0x00a0250c, .end = 0x00a02510 },
2096 { .start = 0x00a02540, .end = 0x00a02554 },
2097 { .start = 0x00a02580, .end = 0x00a025f4 },
2098 { .start = 0x00a02600, .end = 0x00a0260c },
2099 { .start = 0x00a02648, .end = 0x00a02650 },
2100 { .start = 0x00a02680, .end = 0x00a02680 },
2101 { .start = 0x00a026c0, .end = 0x00a026d0 },
2102 { .start = 0x00a02700, .end = 0x00a0270c },
2103 { .start = 0x00a02804, .end = 0x00a02804 },
2104 { .start = 0x00a02818, .end = 0x00a0281c },
2105 { .start = 0x00a02c00, .end = 0x00a02db4 },
2106 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2107 { .start = 0x00a03000, .end = 0x00a03014 },
2108 { .start = 0x00a0301c, .end = 0x00a0302c },
2109 { .start = 0x00a03034, .end = 0x00a03038 },
2110 { .start = 0x00a03040, .end = 0x00a03048 },
2111 { .start = 0x00a03060, .end = 0x00a03068 },
2112 { .start = 0x00a03070, .end = 0x00a03074 },
2113 { .start = 0x00a0307c, .end = 0x00a0307c },
2114 { .start = 0x00a03080, .end = 0x00a03084 },
2115 { .start = 0x00a0308c, .end = 0x00a03090 },
2116 { .start = 0x00a03098, .end = 0x00a03098 },
2117 { .start = 0x00a030a0, .end = 0x00a030a0 },
2118 { .start = 0x00a030a8, .end = 0x00a030b4 },
2119 { .start = 0x00a030bc, .end = 0x00a030bc },
2120 { .start = 0x00a030c0, .end = 0x00a0312c },
2121 { .start = 0x00a03c00, .end = 0x00a03c5c },
2122 { .start = 0x00a04400, .end = 0x00a04454 },
2123 { .start = 0x00a04460, .end = 0x00a04474 },
2124 { .start = 0x00a044c0, .end = 0x00a044ec },
2125 { .start = 0x00a04500, .end = 0x00a04504 },
2126 { .start = 0x00a04510, .end = 0x00a04538 },
2127 { .start = 0x00a04540, .end = 0x00a04548 },
2128 { .start = 0x00a04560, .end = 0x00a0457c },
2129 { .start = 0x00a04590, .end = 0x00a04598 },
2130 { .start = 0x00a045c0, .end = 0x00a045f4 },
2131};
2132
2133static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2134 struct iwl_fw_error_dump_data **data)
2135{
2136 struct iwl_fw_error_dump_prph *prph;
2137 unsigned long flags;
2138 u32 prph_len = 0, i;
2139
2140 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2141 return 0;
2142
2143 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2144 /* The range includes both boundaries */
2145 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2146 iwl_prph_dump_addr[i].start + 4;
2147 int reg;
2148 __le32 *val;
2149
87dd634a 2150 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 2151
2152 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2153 (*data)->len = cpu_to_le32(sizeof(*prph) +
2154 num_bytes_in_chunk);
2155 prph = (void *)(*data)->data;
2156 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2157 val = (void *)prph->data;
2158
2159 for (reg = iwl_prph_dump_addr[i].start;
2160 reg <= iwl_prph_dump_addr[i].end;
2161 reg += 4)
2162 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2163 reg));
2164 *data = iwl_fw_error_next_data(*data);
2165 }
2166
2167 iwl_trans_release_nic_access(trans, &flags);
2168
2169 return prph_len;
2170}
2171
473ad712
EG		 2172#define IWL_CSR_TO_DUMP (0x250)
2173
2174static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2175 struct iwl_fw_error_dump_data **data)
2176{
2177 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2178 __le32 *val;
2179 int i;
2180
2181 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2182 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2183 val = (void *)(*data)->data;
2184
2185 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2186 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2187
2188 *data = iwl_fw_error_next_data(*data);
2189
2190 return csr_len;
2191}
2192
06d51e0d
LK		 2193static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2194 struct iwl_fw_error_dump_data **data)
2195{
2196 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2197 unsigned long flags;
2198 __le32 *val;
2199 int i;
2200
2201 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2202 return 0;
2203
2204 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2205 (*data)->len = cpu_to_le32(fh_regs_len);
2206 val = (void *)(*data)->data;
2207
2208 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2209 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2210
2211 iwl_trans_release_nic_access(trans, &flags);
2212
2213 *data = iwl_fw_error_next_data(*data);
2214
2215 return sizeof(**data) + fh_regs_len;
2216}
2217
cc79ef66
LK		 2218static u32
2219iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2220 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2221 u32 monitor_len)
2222{
2223 u32 buf_size_in_dwords = (monitor_len >> 2);
2224 u32 *buffer = (u32 *)fw_mon_data->data;
2225 unsigned long flags;
2226 u32 i;
2227
2228 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2229 return 0;
2230
2231 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2232 for (i = 0; i < buf_size_in_dwords; i++)
2233 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2234 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2235
2236 iwl_trans_release_nic_access(trans, &flags);
2237
2238 return monitor_len;
2239}
2240
48eb7b34
EG		 2241static
2242struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
4d075007
JB		 2243{
2244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2245 struct iwl_fw_error_dump_data *data;
2246 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2247 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2248 struct iwl_trans_dump_data *dump_data;
4d075007 2249 u32 len;
99684ae3 2250 u32 monitor_len;
4d075007
JB		 2251 int i, ptr;
2252
473ad712
EG		 2253 /* transport dump header */
2254 len = sizeof(*dump_data);
2255
2256 /* host commands */
2257 len += sizeof(*data) +
c2d20201
EG		 2258 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2259
473ad712
EG		 2260 /* CSR registers */
2261 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2262
2263 /* PRPH registers */
67c65f2c
EG		 2264 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2265 /* The range includes both boundaries */
2266 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2267 iwl_prph_dump_addr[i].start + 4;
2268
2269 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2270 num_bytes_in_chunk;
2271 }
2272
06d51e0d
LK		 2273 /* FH registers */
2274 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2275
473ad712 2276 /* FW monitor */
99684ae3 2277 if (trans_pcie->fw_mon_page) {
c544e9c4 2278 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2279 trans_pcie->fw_mon_size;
2280 monitor_len = trans_pcie->fw_mon_size;
2281 } else if (trans->dbg_dest_tlv) {
2282 u32 base, end;
2283
2284 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2285 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2286
2287 base = iwl_read_prph(trans, base) <<
2288 trans->dbg_dest_tlv->base_shift;
2289 end = iwl_read_prph(trans, end) <<
2290 trans->dbg_dest_tlv->end_shift;
2291
2292 /* Make "end" point to the actual end */
cc79ef66
LK		 2293 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2294 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2295 end += (1 << trans->dbg_dest_tlv->end_shift);
2296 monitor_len = end - base;
2297 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2298 monitor_len;
2299 } else {
2300 monitor_len = 0;
2301 }
c2d20201 2302
48eb7b34
EG		 2303 dump_data = vzalloc(len);
2304 if (!dump_data)
2305 return NULL;
4d075007
JB		 2306
2307 len = 0;
48eb7b34 2308 data = (void *)dump_data->data;
4d075007
JB		 2309 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2310 txcmd = (void *)data->data;
2311 spin_lock_bh(&cmdq->lock);
2312 ptr = cmdq->q.write_ptr;
2313 for (i = 0; i < cmdq->q.n_window; i++) {
2314 u8 idx = get_cmd_index(&cmdq->q, ptr);
2315 u32 caplen, cmdlen;
2316
2317 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2318 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2319
2320 if (cmdlen) {
2321 len += sizeof(*txcmd) + caplen;
2322 txcmd->cmdlen = cpu_to_le32(cmdlen);
2323 txcmd->caplen = cpu_to_le32(caplen);
2324 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2325 txcmd = (void *)((u8 *)txcmd->data + caplen);
2326 }
2327
2328 ptr = iwl_queue_dec_wrap(ptr);
2329 }
2330 spin_unlock_bh(&cmdq->lock);
2331
2332 data->len = cpu_to_le32(len);
c2d20201 2333 len += sizeof(*data);
67c65f2c
EG		 2334 data = iwl_fw_error_next_data(data);
2335
2336 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2337 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2338 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
67c65f2c 2339 /* data is already pointing to the next section */
c2d20201 2340
99684ae3
LK		 2341 if ((trans_pcie->fw_mon_page &&
2342 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2343 trans->dbg_dest_tlv) {
c544e9c4 2344 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
99684ae3
LK		 2345 u32 base, write_ptr, wrap_cnt;
2346
2347 /* If there was a dest TLV - use the values from there */
2348 if (trans->dbg_dest_tlv) {
2349 write_ptr =
2350 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2351 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2352 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2353 } else {
2354 base = MON_BUFF_BASE_ADDR;
2355 write_ptr = MON_BUFF_WRPTR;
2356 wrap_cnt = MON_BUFF_CYCLE_CNT;
2357 }
c2d20201 2358
c2d20201 2359 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
c2d20201
EG		 2360 fw_mon_data = (void *)data->data;
2361 fw_mon_data->fw_mon_wr_ptr =
99684ae3 2362 cpu_to_le32(iwl_read_prph(trans, write_ptr));
c2d20201 2363 fw_mon_data->fw_mon_cycle_cnt =
99684ae3 2364 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
c2d20201 2365 fw_mon_data->fw_mon_base_ptr =
99684ae3
LK		 2366 cpu_to_le32(iwl_read_prph(trans, base));
2367
2368 len += sizeof(*data) + sizeof(*fw_mon_data);
2369 if (trans_pcie->fw_mon_page) {
99684ae3
LK		 2370 /*
2371 * The firmware is now asserted, it won't write anything
2372 * to the buffer. CPU can take ownership to fetch the
2373 * data. The buffer will be handed back to the device
2374 * before the firmware will be restarted.
2375 */
2376 dma_sync_single_for_cpu(trans->dev,
2377 trans_pcie->fw_mon_phys,
2378 trans_pcie->fw_mon_size,
2379 DMA_FROM_DEVICE);
2380 memcpy(fw_mon_data->data,
2381 page_address(trans_pcie->fw_mon_page),
2382 trans_pcie->fw_mon_size);
2383
cc79ef66
LK		 2384 monitor_len = trans_pcie->fw_mon_size;
2385 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
99684ae3
LK		 2386 /*
2387 * Update pointers to reflect actual values after
2388 * shifting
2389 */
2390 base = iwl_read_prph(trans, base) <<
2391 trans->dbg_dest_tlv->base_shift;
2392 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2393 monitor_len / sizeof(u32));
cc79ef66
LK		 2394 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2395 monitor_len =
2396 iwl_trans_pci_dump_marbh_monitor(trans,
2397 fw_mon_data,
2398 monitor_len);
2399 } else {
2400 /* Didn't match anything - output no monitor data */
2401 monitor_len = 0;
99684ae3 2402 }
cc79ef66
LK		 2403
2404 len += monitor_len;
2405 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
c2d20201
EG		 2406 }
2407
48eb7b34
EG		 2408 dump_data->len = len;
2409
2410 return dump_data;
4d075007 2411}
87e5666c 2412
d1ff5253 2413static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2414 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2415 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2416 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2417 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2418 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2419
ddaf5a5b
JB		 2420 .d3_suspend = iwl_trans_pcie_d3_suspend,
2421 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2422
f02831be 2423 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2424
e6bb4c9c 2425 .tx = iwl_trans_pcie_tx,
a0eaad71 2426 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2427
d0624be6 2428 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2429 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2430
87e5666c 2431 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2432
990aa6d7 2433 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2434 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
5f178cd2 2435
03905495
EG		 2436 .write8 = iwl_trans_pcie_write8,
2437 .write32 = iwl_trans_pcie_write32,
2438 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2439 .read_prph = iwl_trans_pcie_read_prph,
2440 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2441 .read_mem = iwl_trans_pcie_read_mem,
2442 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2443 .configure = iwl_trans_pcie_configure,
47107e84 2444 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2445 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2446 .release_nic_access = iwl_trans_pcie_release_nic_access,
2447 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2448
7616f334
EP		 2449 .ref = iwl_trans_pcie_ref,
2450 .unref = iwl_trans_pcie_unref,
2451
4d075007 2452 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2453};
a42a1844 2454
87ce05a2 2455struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2456 const struct pci_device_id *ent,
2457 const struct iwl_cfg *cfg)
a42a1844 2458{
a42a1844
EG		 2459 struct iwl_trans_pcie *trans_pcie;
2460 struct iwl_trans *trans;
2461 u16 pci_cmd;
af3f2f74 2462 int ret;
a42a1844 2463
7b501d10
JB		 2464 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2465 &pdev->dev, cfg, &trans_ops_pcie, 0);
2466 if (!trans)
2467 return ERR_PTR(-ENOMEM);
a42a1844
EG		 2468
2469 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2470
a42a1844 2471 trans_pcie->trans = trans;
7b11488f 2472 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2473 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2474 spin_lock_init(&trans_pcie->ref_lock);
13df1aab 2475 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2476
af3f2f74
EG		 2477 ret = pci_enable_device(pdev);
2478 if (ret)
d819c6cf
JB		 2479 goto out_no_pci;
2480
f2532b04
EG		 2481 if (!cfg->base_params->pcie_l1_allowed) {
2482 /*
2483 * W/A - seems to solve weird behavior. We need to remove this
2484 * if we don't want to stay in L1 all the time. This wastes a
2485 * lot of power.
2486 */
2487 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2488 PCIE_LINK_STATE_L1 |
2489 PCIE_LINK_STATE_CLKPM);
2490 }
a42a1844 2491
a42a1844
EG		 2492 pci_set_master(pdev);
2493
af3f2f74
EG		 2494 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2495 if (!ret)
2496 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2497 if (ret) {
2498 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2499 if (!ret)
2500 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2501 DMA_BIT_MASK(32));
a42a1844 2502 /* both attempts failed: */
af3f2f74 2503 if (ret) {
6a4b09f8 2504 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2505 goto out_pci_disable_device;
2506 }
2507 }
2508
af3f2f74
EG		 2509 ret = pci_request_regions(pdev, DRV_NAME);
2510 if (ret) {
6a4b09f8 2511 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2512 goto out_pci_disable_device;
2513 }
2514
05f5b97e 2515 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2516 if (!trans_pcie->hw_base) {
6a4b09f8 2517 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
af3f2f74 2518 ret = -ENODEV;
a42a1844
EG		 2519 goto out_pci_release_regions;
2520 }
2521
a42a1844
EG		 2522 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2523 * PCI Tx retries from interfering with C3 CPU state */
2524 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2525
83f7a85f
EG		 2526 trans->dev = &pdev->dev;
2527 trans_pcie->pci_dev = pdev;
2528 iwl_disable_interrupts(trans);
2529
af3f2f74
EG		 2530 ret = pci_enable_msi(pdev);
2531 if (ret) {
2532 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
9f904b38
EG		 2533 /* enable rfkill interrupt: hw bug w/a */
2534 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2535 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2536 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2537 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2538 }
2539 }
a42a1844 2540
08079a49 2541 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2542 /*
2543 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2544 * changed, and now the revision step also includes bit 0-1 (no more
2545 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2546 * in the old format.
2547 */
7a42baa6
EH		 2548 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2549 unsigned long flags;
7a42baa6 2550
b513ee7f 2551 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2552 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2553
7a42baa6
EH		 2554 /*
2555 * in-order to recognize C step driver should read chip version
2556 * id located at the AUX bus MISC address space.
2557 */
2558 iwl_set_bit(trans, CSR_GP_CNTRL,
2559 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2560 udelay(2);
2561
2562 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2563 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2564 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2565 25000);
2566 if (ret < 0) {
2567 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2568 goto out_pci_disable_msi;
2569 }
2570
2571 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2572 u32 hw_step;
2573
2574 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2575 hw_step |= ENABLE_WFPM;
2576 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2577 hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2578 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2579 if (hw_step == 0x3)
2580 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2581 (SILICON_C_STEP << 2);
2582 iwl_trans_release_nic_access(trans, &flags);
2583 }
2584 }
2585
99673ee5 2586 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2587 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2588 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2589
69a10b29 2590 /* Initialize the wait queue for commands */
f946b529 2591 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2592
af3f2f74
EG		 2593 ret = iwl_pcie_alloc_ict(trans);
2594 if (ret)
7b501d10 2595 goto out_pci_disable_msi;
a8b691e6 2596
af3f2f74 2597 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2598 iwl_pcie_irq_handler,
2599 IRQF_SHARED, DRV_NAME, trans);
af3f2f74 2600 if (ret) {
a8b691e6
JB		 2601 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2602 goto out_free_ict;
2603 }
2604
83f7a85f 2605 trans_pcie->inta_mask = CSR_INI_SET_MASK;
6735943f 2606 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
83f7a85f 2607
a42a1844
EG		 2608 return trans;
2609
a8b691e6
JB		 2610out_free_ict:
2611 iwl_pcie_free_ict(trans);
59c647b6
EG		 2612out_pci_disable_msi:
2613 pci_disable_msi(pdev);
a42a1844
EG		 2614out_pci_release_regions:
2615 pci_release_regions(pdev);
2616out_pci_disable_device:
2617 pci_disable_device(pdev);
2618out_no_pci:
7b501d10 2619 iwl_trans_free(trans);
af3f2f74 2620 return ERR_PTR(ret);
a42a1844 2621}
Linux kernel - Deliverables
This page took 0.615901 seconds and 5 git commands to generate.