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Merge remote-tracking branch 'md/for-next'
[deliverable/linux.git] / drivers / net / wireless / marvell / mwifiex / pcie.c
CommitLineData
d930faee
AK		 1/*
2 * Marvell Wireless LAN device driver: PCIE specific handling
3 *
65da33f5 4 * Copyright (C) 2011-2014, Marvell International Ltd.
d930faee
AK		 5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#include <linux/firmware.h>
21
22#include "decl.h"
23#include "ioctl.h"
24#include "util.h"
25#include "fw.h"
26#include "main.h"
27#include "wmm.h"
28#include "11n.h"
29#include "pcie.h"
30
31#define PCIE_VERSION "1.0"
32#define DRV_NAME "Marvell mwifiex PCIe"
33
34static u8 user_rmmod;
35
36static struct mwifiex_if_ops pcie_ops;
37
38static struct semaphore add_remove_card_sem;
d930faee 39
fc331460
AP		 40static int
41mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
dbccc92b 42 size_t size, int flags)
d930faee 43{
fc331460 44 struct pcie_service_card *card = adapter->card;
dbccc92b 45 struct mwifiex_dma_mapping mapping;
d930faee 46
dbccc92b
AD		 47 mapping.addr = pci_map_single(card->dev, skb->data, size, flags);
48 if (pci_dma_mapping_error(card->dev, mapping.addr)) {
acebe8c1 49 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n");
fc331460
AP		 50 return -1;
51 }
dbccc92b 52 mapping.len = size;
bca463e8 53 mwifiex_store_mapping(skb, &mapping);
fc331460 54 return 0;
d930faee
AK		 55}
56
dbccc92b
AD		 57static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter,
58 struct sk_buff *skb, int flags)
59{
60 struct pcie_service_card *card = adapter->card;
61 struct mwifiex_dma_mapping mapping;
62
bca463e8 63 mwifiex_get_mapping(skb, &mapping);
dbccc92b
AD		 64 pci_unmap_single(card->dev, mapping.addr, mapping.len, flags);
65}
66
d930faee
AK		 67/*
68 * This function reads sleep cookie and checks if FW is ready
69 */
70static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
71{
72 u32 *cookie_addr;
73 struct pcie_service_card *card = adapter->card;
52301a81
AP		 74 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
75
76 if (!reg->sleep_cookie)
77 return true;
d930faee 78
fc331460
AP		 79 if (card->sleep_cookie_vbase) {
80 cookie_addr = (u32 *)card->sleep_cookie_vbase;
acebe8c1
ZL		 81 mwifiex_dbg(adapter, INFO,
82 "info: ACCESS_HW: sleep cookie=0x%x\n",
83 *cookie_addr);
d930faee
AK		 84 if (*cookie_addr == FW_AWAKE_COOKIE)
85 return true;
86 }
87
88 return false;
89}
90
3266d732 91#ifdef CONFIG_PM_SLEEP
fcca8d5a
BZ		 92/*
93 * Kernel needs to suspend all functions separately. Therefore all
94 * registered functions must have drivers with suspend and resume
95 * methods. Failing that the kernel simply removes the whole card.
96 *
97 * If already not suspended, this function allocates and sends a host
98 * sleep activate request to the firmware and turns off the traffic.
99 */
3266d732 100static int mwifiex_pcie_suspend(struct device *dev)
fcca8d5a
BZ		 101{
102 struct mwifiex_adapter *adapter;
103 struct pcie_service_card *card;
104 int hs_actived;
3266d732 105 struct pci_dev *pdev = to_pci_dev(dev);
fcca8d5a
BZ		 106
107 if (pdev) {
b2a31204 108 card = pci_get_drvdata(pdev);
fcca8d5a
BZ		 109 if (!card || !card->adapter) {
110 pr_err("Card or adapter structure is not valid\n");
111 return 0;
112 }
113 } else {
114 pr_err("PCIE device is not specified\n");
115 return 0;
116 }
117
118 adapter = card->adapter;
119
120 hs_actived = mwifiex_enable_hs(adapter);
121
122 /* Indicate device suspended */
123 adapter->is_suspended = true;
c0dbba66 124 adapter->hs_enabling = false;
fcca8d5a
BZ		 125
126 return 0;
127}
128
129/*
130 * Kernel needs to suspend all functions separately. Therefore all
131 * registered functions must have drivers with suspend and resume
132 * methods. Failing that the kernel simply removes the whole card.
133 *
134 * If already not resumed, this function turns on the traffic and
135 * sends a host sleep cancel request to the firmware.
136 */
3266d732 137static int mwifiex_pcie_resume(struct device *dev)
fcca8d5a
BZ		 138{
139 struct mwifiex_adapter *adapter;
140 struct pcie_service_card *card;
3266d732 141 struct pci_dev *pdev = to_pci_dev(dev);
fcca8d5a
BZ		 142
143 if (pdev) {
b2a31204 144 card = pci_get_drvdata(pdev);
fcca8d5a
BZ		 145 if (!card || !card->adapter) {
146 pr_err("Card or adapter structure is not valid\n");
147 return 0;
148 }
149 } else {
150 pr_err("PCIE device is not specified\n");
151 return 0;
152 }
153
154 adapter = card->adapter;
155
156 if (!adapter->is_suspended) {
acebe8c1
ZL		 157 mwifiex_dbg(adapter, WARN,
158 "Device already resumed\n");
fcca8d5a
BZ		 159 return 0;
160 }
161
162 adapter->is_suspended = false;
163
164 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
165 MWIFIEX_ASYNC_CMD);
166
167 return 0;
168}
8509e820 169#endif
fcca8d5a 170
d930faee
AK		 171/*
172 * This function probes an mwifiex device and registers it. It allocates
173 * the card structure, enables PCIE function number and initiates the
174 * device registration and initialization procedure by adding a logical
175 * interface.
176 */
177static int mwifiex_pcie_probe(struct pci_dev *pdev,
178 const struct pci_device_id *ent)
179{
180 struct pcie_service_card *card;
181
182 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
f57c1edc 183 pdev->vendor, pdev->device, pdev->revision);
d930faee
AK		 184
185 card = kzalloc(sizeof(struct pcie_service_card), GFP_KERNEL);
e404decb 186 if (!card)
d930faee 187 return -ENOMEM;
d930faee
AK		 188
189 card->dev = pdev;
190
dd04e6ac
AP		 191 if (ent->driver_data) {
192 struct mwifiex_pcie_device *data = (void *)ent->driver_data;
dd04e6ac
AP		 193 card->pcie.reg = data->reg;
194 card->pcie.blksz_fw_dl = data->blksz_fw_dl;
828cf222 195 card->pcie.tx_buf_size = data->tx_buf_size;
b4e8aebb 196 card->pcie.can_dump_fw = data->can_dump_fw;
50632092
XH		 197 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl;
198 card->pcie.num_mem_types = data->num_mem_types;
1fe192d8 199 card->pcie.can_ext_scan = data->can_ext_scan;
dd04e6ac
AP		 200 }
201
d930faee
AK		 202 if (mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops,
203 MWIFIEX_PCIE)) {
204 pr_err("%s failed\n", __func__);
d930faee
AK		 205 return -1;
206 }
207
208 return 0;
209}
210
211/*
212 * This function removes the interface and frees up the card structure.
213 */
214static void mwifiex_pcie_remove(struct pci_dev *pdev)
215{
216 struct pcie_service_card *card;
217 struct mwifiex_adapter *adapter;
f57c1edc 218 struct mwifiex_private *priv;
d930faee
AK		 219
220 card = pci_get_drvdata(pdev);
221 if (!card)
222 return;
223
224 adapter = card->adapter;
225 if (!adapter || !adapter->priv_num)
226 return;
227
cf5383b0 228 if (user_rmmod && !adapter->mfg_mode) {
3266d732 229#ifdef CONFIG_PM_SLEEP
d930faee 230 if (adapter->is_suspended)
3266d732 231 mwifiex_pcie_resume(&pdev->dev);
d930faee
AK		 232#endif
233
848819f4 234 mwifiex_deauthenticate_all(adapter);
d930faee 235
f57c1edc 236 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
d930faee 237
f57c1edc
YAP		 238 mwifiex_disable_auto_ds(priv);
239
240 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
d930faee
AK		 241 }
242
243 mwifiex_remove_card(card->adapter, &add_remove_card_sem);
d930faee
AK		 244}
245
43ba6b9f
AK		 246static void mwifiex_pcie_shutdown(struct pci_dev *pdev)
247{
248 user_rmmod = 1;
249 mwifiex_pcie_remove(pdev);
250
251 return;
252}
253
9baa3c34 254static const struct pci_device_id mwifiex_ids[] = {
d930faee
AK		 255 {
256 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6d85ef00 258 .driver_data = (unsigned long)&mwifiex_pcie8766,
d930faee 259 },
ca8f2112
AP		 260 {
261 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6d85ef00
ZL		 263 .driver_data = (unsigned long)&mwifiex_pcie8897,
264 },
265 {
266 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 .driver_data = (unsigned long)&mwifiex_pcie8997,
ca8f2112 269 },
a362e16b
SL		 270 {
271 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 .driver_data = (unsigned long)&mwifiex_pcie8997,
274 },
d930faee
AK		 275 {},
276};
277
278MODULE_DEVICE_TABLE(pci, mwifiex_ids);
279
4c5dae59
AK		 280static void mwifiex_pcie_reset_notify(struct pci_dev *pdev, bool prepare)
281{
282 struct mwifiex_adapter *adapter;
283 struct pcie_service_card *card;
284
285 if (!pdev) {
286 pr_err("%s: PCIe device is not specified\n", __func__);
287 return;
288 }
289
290 card = (struct pcie_service_card *)pci_get_drvdata(pdev);
291 if (!card || !card->adapter) {
292 pr_err("%s: Card or adapter structure is not valid (%ld)\n",
293 __func__, (long)card);
294 return;
295 }
296
297 adapter = card->adapter;
298 mwifiex_dbg(adapter, INFO,
299 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d %s\n",
300 __func__, pdev->vendor, pdev->device,
301 pdev->revision,
302 prepare ? "Pre-FLR" : "Post-FLR");
303
304 if (prepare) {
305 /* Kernel would be performing FLR after this notification.
306 * Cleanup all software without cleaning anything related to
307 * PCIe and HW.
308 */
309 mwifiex_do_flr(adapter, prepare);
310 adapter->surprise_removed = true;
311 } else {
312 /* Kernel stores and restores PCIe function context before and
313 * after performing FLR respectively. Reconfigure the software
314 * and firmware including firmware redownload
315 */
316 adapter->surprise_removed = false;
317 mwifiex_do_flr(adapter, prepare);
318 }
319 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
320}
321
322static const struct pci_error_handlers mwifiex_pcie_err_handler[] = {
323 { .reset_notify = mwifiex_pcie_reset_notify, },
324};
325
3266d732
SK		 326#ifdef CONFIG_PM_SLEEP
327/* Power Management Hooks */
328static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend,
329 mwifiex_pcie_resume);
330#endif
331
d930faee
AK		 332/* PCI Device Driver */
333static struct pci_driver __refdata mwifiex_pcie = {
334 .name = "mwifiex_pcie",
335 .id_table = mwifiex_ids,
336 .probe = mwifiex_pcie_probe,
337 .remove = mwifiex_pcie_remove,
3266d732
SK		 338#ifdef CONFIG_PM_SLEEP
339 .driver = {
340 .pm = &mwifiex_pcie_pm_ops,
341 },
d930faee 342#endif
43ba6b9f 343 .shutdown = mwifiex_pcie_shutdown,
4c5dae59 344 .err_handler = mwifiex_pcie_err_handler,
d930faee
AK		 345};
346
347/*
348 * This function writes data into PCIE card register.
349 */
350static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data)
351{
352 struct pcie_service_card *card = adapter->card;
353
354 iowrite32(data, card->pci_mmap1 + reg);
355
356 return 0;
357}
358
359/*
360 * This function reads data from PCIE card register.
361 */
362static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data)
363{
364 struct pcie_service_card *card = adapter->card;
365
366 *data = ioread32(card->pci_mmap1 + reg);
af051483
XH		 367 if (*data == 0xffffffff)
368 return 0xffffffff;
d930faee
AK		 369
370 return 0;
371}
372
92c2538f
AK		 373/* This function reads u8 data from PCIE card register. */
374static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter,
375 int reg, u8 *data)
376{
377 struct pcie_service_card *card = adapter->card;
378
379 *data = ioread8(card->pci_mmap1 + reg);
380
381 return 0;
382}
383
d930faee 384/*
c0880a29 385 * This function adds delay loop to ensure FW is awake before proceeding.
d930faee 386 */
c0880a29 387static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter)
d930faee
AK		 388{
389 int i = 0;
390
c0880a29 391 while (mwifiex_pcie_ok_to_access_hw(adapter)) {
d930faee 392 i++;
e7891ba2 393 usleep_range(10, 20);
d930faee 394 /* 50ms max wait */
3e7a4ff7 395 if (i == 5000)
d930faee
AK		 396 break;
397 }
398
c0880a29
AP		 399 return;
400}
401
c4bc980f
AP		 402static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter,
403 u32 max_delay_loop_cnt)
404{
405 struct pcie_service_card *card = adapter->card;
406 u8 *buffer;
407 u32 sleep_cookie, count;
408
409 for (count = 0; count < max_delay_loop_cnt; count++) {
410 buffer = card->cmdrsp_buf->data - INTF_HEADER_LEN;
411 sleep_cookie = *(u32 *)buffer;
412
413 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) {
acebe8c1
ZL		 414 mwifiex_dbg(adapter, INFO,
415 "sleep cookie found at count %d\n", count);
c4bc980f
AP		 416 break;
417 }
418 usleep_range(20, 30);
419 }
420
421 if (count >= max_delay_loop_cnt)
acebe8c1
ZL		 422 mwifiex_dbg(adapter, INFO,
423 "max count reached while accessing sleep cookie\n");
c4bc980f
AP		 424}
425
c0880a29
AP		 426/* This function wakes up the card by reading fw_status register. */
427static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
428{
429 u32 fw_status;
430 struct pcie_service_card *card = adapter->card;
431 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
432
acebe8c1
ZL		 433 mwifiex_dbg(adapter, EVENT,
434 "event: Wakeup device...\n");
d930faee 435
c0880a29
AP		 436 if (reg->sleep_cookie)
437 mwifiex_pcie_dev_wakeup_delay(adapter);
438
439 /* Reading fw_status register will wakeup device */
440 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) {
acebe8c1
ZL		 441 mwifiex_dbg(adapter, ERROR,
442 "Reading fw_status register failed\n");
d930faee
AK		 443 return -1;
444 }
445
c0880a29
AP		 446 if (reg->sleep_cookie) {
447 mwifiex_pcie_dev_wakeup_delay(adapter);
acebe8c1
ZL		 448 mwifiex_dbg(adapter, INFO,
449 "PCIE wakeup: Setting PS_STATE_AWAKE\n");
c0880a29
AP		 450 adapter->ps_state = PS_STATE_AWAKE;
451 }
d930faee
AK		 452
453 return 0;
454}
455
456/*
457 * This function is called after the card has woken up.
458 *
459 * The card configuration register is reset.
460 */
461static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
462{
acebe8c1
ZL		 463 mwifiex_dbg(adapter, CMD,
464 "cmd: Wakeup device completed\n");
d930faee
AK		 465
466 return 0;
467}
468
469/*
470 * This function disables the host interrupt.
471 *
472 * The host interrupt mask is read, the disable bit is reset and
473 * written back to the card host interrupt mask register.
474 */
475static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter)
476{
477 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
478 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
479 0x00000000)) {
acebe8c1
ZL		 480 mwifiex_dbg(adapter, ERROR,
481 "Disable host interrupt failed\n");
d930faee
AK		 482 return -1;
483 }
484 }
485
486 return 0;
487}
488
d41376ca
BN		 489static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter)
490{
491 WARN_ON(mwifiex_pcie_disable_host_int(adapter));
492}
493
d930faee
AK		 494/*
495 * This function enables the host interrupt.
496 *
497 * The host interrupt enable mask is written to the card
498 * host interrupt mask register.
499 */
500static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter)
501{
502 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
503 /* Simply write the mask to the register */
504 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
505 HOST_INTR_MASK)) {
acebe8c1
ZL		 506 mwifiex_dbg(adapter, ERROR,
507 "Enable host interrupt failed\n");
d930faee
AK		 508 return -1;
509 }
510 }
511
512 return 0;
513}
514
515/*
0732484b
AP		 516 * This function initializes TX buffer ring descriptors
517 */
518static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter)
519{
520 struct pcie_service_card *card = adapter->card;
ca8f2112 521 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b 522 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 523 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 524 int i;
525
526 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
527 card->tx_buf_list[i] = NULL;
ca8f2112
AP		 528 if (reg->pfu_enabled) {
529 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
530 (sizeof(*desc2) * i);
531 desc2 = card->txbd_ring[i];
532 memset(desc2, 0, sizeof(*desc2));
533 } else {
534 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
535 (sizeof(*desc) * i);
536 desc = card->txbd_ring[i];
537 memset(desc, 0, sizeof(*desc));
538 }
0732484b
AP		 539 }
540
541 return 0;
542}
543
544/* This function initializes RX buffer ring descriptors. Each SKB is allocated
545 * here and after mapping PCI memory, its physical address is assigned to
546 * PCIE Rx buffer descriptor's physical address.
547 */
548static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter)
549{
550 struct pcie_service_card *card = adapter->card;
ca8f2112 551 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b
AP		 552 struct sk_buff *skb;
553 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 554 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 555 dma_addr_t buf_pa;
556 int i;
557
558 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
559 /* Allocate skb here so that firmware can DMA data from it */
62159944 560 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
5c87a55a 561 GFP_KERNEL);
0732484b 562 if (!skb) {
acebe8c1
ZL		 563 mwifiex_dbg(adapter, ERROR,
564 "Unable to allocate skb for RX ring.\n");
0732484b
AP		 565 kfree(card->rxbd_ring_vbase);
566 return -ENOMEM;
567 }
568
569 if (mwifiex_map_pci_memory(adapter, skb,
570 MWIFIEX_RX_DATA_BUF_SIZE,
571 PCI_DMA_FROMDEVICE))
572 return -1;
573
dbccc92b 574 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
0732484b 575
acebe8c1
ZL		 576 mwifiex_dbg(adapter, INFO,
577 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
578 skb, skb->len, skb->data, (u32)buf_pa,
579 (u32)((u64)buf_pa >> 32));
0732484b
AP		 580
581 card->rx_buf_list[i] = skb;
ca8f2112
AP		 582 if (reg->pfu_enabled) {
583 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase +
584 (sizeof(*desc2) * i);
585 desc2 = card->rxbd_ring[i];
586 desc2->paddr = buf_pa;
587 desc2->len = (u16)skb->len;
588 desc2->frag_len = (u16)skb->len;
589 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop;
590 desc2->offset = 0;
591 } else {
592 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase +
593 (sizeof(*desc) * i));
594 desc = card->rxbd_ring[i];
595 desc->paddr = buf_pa;
596 desc->len = (u16)skb->len;
597 desc->flags = 0;
598 }
0732484b
AP		 599 }
600
601 return 0;
602}
603
604/* This function initializes event buffer ring descriptors. Each SKB is
605 * allocated here and after mapping PCI memory, its physical address is assigned
606 * to PCIE Rx buffer descriptor's physical address
607 */
608static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
609{
610 struct pcie_service_card *card = adapter->card;
e05dc3e9 611 struct mwifiex_evt_buf_desc *desc;
0732484b
AP		 612 struct sk_buff *skb;
613 dma_addr_t buf_pa;
614 int i;
615
616 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
617 /* Allocate skb here so that firmware can DMA data from it */
618 skb = dev_alloc_skb(MAX_EVENT_SIZE);
619 if (!skb) {
acebe8c1
ZL		 620 mwifiex_dbg(adapter, ERROR,
621 "Unable to allocate skb for EVENT buf.\n");
0732484b
AP		 622 kfree(card->evtbd_ring_vbase);
623 return -ENOMEM;
624 }
625 skb_put(skb, MAX_EVENT_SIZE);
626
627 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
628 PCI_DMA_FROMDEVICE))
629 return -1;
630
dbccc92b 631 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
0732484b 632
acebe8c1
ZL		 633 mwifiex_dbg(adapter, EVENT,
634 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
635 skb, skb->len, skb->data, (u32)buf_pa,
636 (u32)((u64)buf_pa >> 32));
0732484b
AP		 637
638 card->evt_buf_list[i] = skb;
639 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase +
640 (sizeof(*desc) * i));
0732484b
AP		 641 desc = card->evtbd_ring[i];
642 desc->paddr = buf_pa;
643 desc->len = (u16)skb->len;
644 desc->flags = 0;
645 }
646
647 return 0;
648}
649
650/* This function cleans up TX buffer rings. If any of the buffer list has valid
651 * SKB address, associated SKB is freed.
652 */
653static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter)
654{
655 struct pcie_service_card *card = adapter->card;
ca8f2112 656 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b
AP		 657 struct sk_buff *skb;
658 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 659 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 660 int i;
661
662 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
ca8f2112
AP		 663 if (reg->pfu_enabled) {
664 desc2 = card->txbd_ring[i];
665 if (card->tx_buf_list[i]) {
666 skb = card->tx_buf_list[i];
dbccc92b
AD		 667 mwifiex_unmap_pci_memory(adapter, skb,
668 PCI_DMA_TODEVICE);
ca8f2112
AP		 669 dev_kfree_skb_any(skb);
670 }
671 memset(desc2, 0, sizeof(*desc2));
672 } else {
673 desc = card->txbd_ring[i];
674 if (card->tx_buf_list[i]) {
675 skb = card->tx_buf_list[i];
dbccc92b
AD		 676 mwifiex_unmap_pci_memory(adapter, skb,
677 PCI_DMA_TODEVICE);
ca8f2112
AP		 678 dev_kfree_skb_any(skb);
679 }
680 memset(desc, 0, sizeof(*desc));
0732484b
AP		 681 }
682 card->tx_buf_list[i] = NULL;
0732484b
AP		 683 }
684
685 return;
686}
687
688/* This function cleans up RX buffer rings. If any of the buffer list has valid
689 * SKB address, associated SKB is freed.
690 */
691static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter)
692{
693 struct pcie_service_card *card = adapter->card;
ca8f2112 694 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b 695 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 696 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 697 struct sk_buff *skb;
698 int i;
699
700 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
ca8f2112
AP		 701 if (reg->pfu_enabled) {
702 desc2 = card->rxbd_ring[i];
703 if (card->rx_buf_list[i]) {
704 skb = card->rx_buf_list[i];
dbccc92b
AD		 705 mwifiex_unmap_pci_memory(adapter, skb,
706 PCI_DMA_FROMDEVICE);
ca8f2112
AP		 707 dev_kfree_skb_any(skb);
708 }
709 memset(desc2, 0, sizeof(*desc2));
710 } else {
711 desc = card->rxbd_ring[i];
712 if (card->rx_buf_list[i]) {
713 skb = card->rx_buf_list[i];
dbccc92b
AD		 714 mwifiex_unmap_pci_memory(adapter, skb,
715 PCI_DMA_FROMDEVICE);
ca8f2112
AP		 716 dev_kfree_skb_any(skb);
717 }
718 memset(desc, 0, sizeof(*desc));
0732484b 719 }
ca8f2112 720 card->rx_buf_list[i] = NULL;
0732484b
AP		 721 }
722
723 return;
724}
725
726/* This function cleans up event buffer rings. If any of the buffer list has
727 * valid SKB address, associated SKB is freed.
728 */
729static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter)
730{
731 struct pcie_service_card *card = adapter->card;
e05dc3e9 732 struct mwifiex_evt_buf_desc *desc;
0732484b
AP		 733 struct sk_buff *skb;
734 int i;
735
736 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
737 desc = card->evtbd_ring[i];
738 if (card->evt_buf_list[i]) {
739 skb = card->evt_buf_list[i];
dbccc92b
AD		 740 mwifiex_unmap_pci_memory(adapter, skb,
741 PCI_DMA_FROMDEVICE);
0732484b
AP		 742 dev_kfree_skb_any(skb);
743 }
744 card->evt_buf_list[i] = NULL;
745 memset(desc, 0, sizeof(*desc));
746 }
747
748 return;
749}
750
751/* This function creates buffer descriptor ring for TX
d930faee
AK		 752 */
753static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter)
754{
755 struct pcie_service_card *card = adapter->card;
dd04e6ac 756 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 757
758 /*
759 * driver maintaines the write pointer and firmware maintaines the read
760 * pointer. The write pointer starts at 0 (zero) while the read pointer
761 * starts at zero with rollover bit set
762 */
763 card->txbd_wrptr = 0;
ca8f2112
AP		 764
765 if (reg->pfu_enabled)
766 card->txbd_rdptr = 0;
767 else
768 card->txbd_rdptr |= reg->tx_rollover_ind;
d930faee
AK		 769
770 /* allocate shared memory for the BD ring and divide the same in to
771 several descriptors */
ca8f2112
AP		 772 if (reg->pfu_enabled)
773 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
774 MWIFIEX_MAX_TXRX_BD;
775 else
776 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
777 MWIFIEX_MAX_TXRX_BD;
778
acebe8c1
ZL		 779 mwifiex_dbg(adapter, INFO,
780 "info: txbd_ring: Allocating %d bytes\n",
781 card->txbd_ring_size);
fc331460
AP		 782 card->txbd_ring_vbase = pci_alloc_consistent(card->dev,
783 card->txbd_ring_size,
784 &card->txbd_ring_pbase);
d930faee 785 if (!card->txbd_ring_vbase) {
acebe8c1
ZL		 786 mwifiex_dbg(adapter, ERROR,
787 "allocate consistent memory (%d bytes) failed!\n",
788 card->txbd_ring_size);
8c53e42d 789 return -ENOMEM;
d930faee 790 }
acebe8c1
ZL		 791 mwifiex_dbg(adapter, DATA,
792 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %x\n",
793 card->txbd_ring_vbase, (unsigned int)card->txbd_ring_pbase,
794 (u32)((u64)card->txbd_ring_pbase >> 32),
795 card->txbd_ring_size);
d930faee 796
0732484b 797 return mwifiex_init_txq_ring(adapter);
d930faee
AK		 798}
799
800static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter)
801{
802 struct pcie_service_card *card = adapter->card;
dd04e6ac 803 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 804
0732484b 805 mwifiex_cleanup_txq_ring(adapter);
d930faee 806
fc331460
AP		 807 if (card->txbd_ring_vbase)
808 pci_free_consistent(card->dev, card->txbd_ring_size,
809 card->txbd_ring_vbase,
810 card->txbd_ring_pbase);
d930faee
AK		 811 card->txbd_ring_size = 0;
812 card->txbd_wrptr = 0;
dd04e6ac 813 card->txbd_rdptr = 0 | reg->tx_rollover_ind;
d930faee 814 card->txbd_ring_vbase = NULL;
fc331460 815 card->txbd_ring_pbase = 0;
d930faee
AK		 816
817 return 0;
818}
819
820/*
821 * This function creates buffer descriptor ring for RX
822 */
823static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter)
824{
825 struct pcie_service_card *card = adapter->card;
dd04e6ac 826 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 827
828 /*
829 * driver maintaines the read pointer and firmware maintaines the write
830 * pointer. The write pointer starts at 0 (zero) while the read pointer
831 * starts at zero with rollover bit set
832 */
833 card->rxbd_wrptr = 0;
dd04e6ac 834 card->rxbd_rdptr = reg->rx_rollover_ind;
d930faee 835
ca8f2112
AP		 836 if (reg->pfu_enabled)
837 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
838 MWIFIEX_MAX_TXRX_BD;
839 else
840 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
841 MWIFIEX_MAX_TXRX_BD;
842
acebe8c1
ZL		 843 mwifiex_dbg(adapter, INFO,
844 "info: rxbd_ring: Allocating %d bytes\n",
845 card->rxbd_ring_size);
fc331460
AP		 846 card->rxbd_ring_vbase = pci_alloc_consistent(card->dev,
847 card->rxbd_ring_size,
848 &card->rxbd_ring_pbase);
d930faee 849 if (!card->rxbd_ring_vbase) {
acebe8c1
ZL		 850 mwifiex_dbg(adapter, ERROR,
851 "allocate consistent memory (%d bytes) failed!\n",
852 card->rxbd_ring_size);
8c53e42d 853 return -ENOMEM;
d930faee 854 }
d930faee 855
acebe8c1
ZL		 856 mwifiex_dbg(adapter, DATA,
857 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
858 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase,
859 (u32)((u64)card->rxbd_ring_pbase >> 32),
860 card->rxbd_ring_size);
d930faee 861
0732484b 862 return mwifiex_init_rxq_ring(adapter);
d930faee
AK		 863}
864
865/*
866 * This function deletes Buffer descriptor ring for RX
867 */
868static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter)
869{
870 struct pcie_service_card *card = adapter->card;
dd04e6ac 871 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 872
0732484b 873 mwifiex_cleanup_rxq_ring(adapter);
d930faee 874
fc331460
AP		 875 if (card->rxbd_ring_vbase)
876 pci_free_consistent(card->dev, card->rxbd_ring_size,
877 card->rxbd_ring_vbase,
878 card->rxbd_ring_pbase);
d930faee
AK		 879 card->rxbd_ring_size = 0;
880 card->rxbd_wrptr = 0;
dd04e6ac 881 card->rxbd_rdptr = 0 | reg->rx_rollover_ind;
d930faee 882 card->rxbd_ring_vbase = NULL;
fc331460 883 card->rxbd_ring_pbase = 0;
d930faee
AK		 884
885 return 0;
886}
887
888/*
889 * This function creates buffer descriptor ring for Events
890 */
891static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter)
892{
893 struct pcie_service_card *card = adapter->card;
dd04e6ac 894 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 895
896 /*
897 * driver maintaines the read pointer and firmware maintaines the write
898 * pointer. The write pointer starts at 0 (zero) while the read pointer
899 * starts at zero with rollover bit set
900 */
901 card->evtbd_wrptr = 0;
dd04e6ac 902 card->evtbd_rdptr = reg->evt_rollover_ind;
d930faee 903
e05dc3e9 904 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) *
ca8f2112
AP		 905 MWIFIEX_MAX_EVT_BD;
906
acebe8c1
ZL		 907 mwifiex_dbg(adapter, INFO,
908 "info: evtbd_ring: Allocating %d bytes\n",
f57c1edc 909 card->evtbd_ring_size);
fc331460
AP		 910 card->evtbd_ring_vbase = pci_alloc_consistent(card->dev,
911 card->evtbd_ring_size,
912 &card->evtbd_ring_pbase);
d930faee 913 if (!card->evtbd_ring_vbase) {
acebe8c1
ZL		 914 mwifiex_dbg(adapter, ERROR,
915 "allocate consistent memory (%d bytes) failed!\n",
916 card->evtbd_ring_size);
8c53e42d 917 return -ENOMEM;
d930faee 918 }
d930faee 919
acebe8c1
ZL		 920 mwifiex_dbg(adapter, EVENT,
921 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n",
922 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase,
923 (u32)((u64)card->evtbd_ring_pbase >> 32),
924 card->evtbd_ring_size);
d930faee 925
0732484b 926 return mwifiex_pcie_init_evt_ring(adapter);
d930faee
AK		 927}
928
929/*
930 * This function deletes Buffer descriptor ring for Events
931 */
932static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter)
933{
934 struct pcie_service_card *card = adapter->card;
dd04e6ac 935 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 936
0732484b 937 mwifiex_cleanup_evt_ring(adapter);
d930faee 938
fc331460
AP		 939 if (card->evtbd_ring_vbase)
940 pci_free_consistent(card->dev, card->evtbd_ring_size,
941 card->evtbd_ring_vbase,
942 card->evtbd_ring_pbase);
d930faee 943 card->evtbd_wrptr = 0;
dd04e6ac 944 card->evtbd_rdptr = 0 | reg->evt_rollover_ind;
d930faee
AK		 945 card->evtbd_ring_size = 0;
946 card->evtbd_ring_vbase = NULL;
fc331460 947 card->evtbd_ring_pbase = 0;
d930faee
AK		 948
949 return 0;
950}
951
952/*
953 * This function allocates a buffer for CMDRSP
954 */
955static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter)
956{
957 struct pcie_service_card *card = adapter->card;
958 struct sk_buff *skb;
959
960 /* Allocate memory for receiving command response data */
961 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
962 if (!skb) {
acebe8c1
ZL		 963 mwifiex_dbg(adapter, ERROR,
964 "Unable to allocate skb for command response data.\n");
d930faee
AK		 965 return -ENOMEM;
966 }
d930faee 967 skb_put(skb, MWIFIEX_UPLD_SIZE);
fc331460
AP		 968 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
969 PCI_DMA_FROMDEVICE))
970 return -1;
d930faee 971
fc331460 972 card->cmdrsp_buf = skb;
d930faee
AK		 973
974 return 0;
975}
976
977/*
978 * This function deletes a buffer for CMDRSP
979 */
980static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter)
981{
982 struct pcie_service_card *card;
983
984 if (!adapter)
985 return 0;
986
987 card = adapter->card;
988
fc331460 989 if (card && card->cmdrsp_buf) {
dbccc92b
AD		 990 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf,
991 PCI_DMA_FROMDEVICE);
d930faee 992 dev_kfree_skb_any(card->cmdrsp_buf);
fc331460 993 }
d930faee 994
fc331460 995 if (card && card->cmd_buf) {
dbccc92b
AD		 996 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
997 PCI_DMA_TODEVICE);
fc331460 998 }
d930faee
AK		 999 return 0;
1000}
1001
1002/*
1003 * This function allocates a buffer for sleep cookie
1004 */
1005static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter)
1006{
d930faee
AK		 1007 struct pcie_service_card *card = adapter->card;
1008
fc331460
AP		 1009 card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32),
1010 &card->sleep_cookie_pbase);
1011 if (!card->sleep_cookie_vbase) {
acebe8c1
ZL		 1012 mwifiex_dbg(adapter, ERROR,
1013 "pci_alloc_consistent failed!\n");
d930faee
AK		 1014 return -ENOMEM;
1015 }
d930faee 1016 /* Init val of Sleep Cookie */
fc331460 1017 *(u32 *)card->sleep_cookie_vbase = FW_AWAKE_COOKIE;
d930faee 1018
acebe8c1
ZL		 1019 mwifiex_dbg(adapter, INFO,
1020 "alloc_scook: sleep cookie=0x%x\n",
1021 *((u32 *)card->sleep_cookie_vbase));
d930faee
AK		 1022
1023 return 0;
1024}
1025
1026/*
1027 * This function deletes buffer for sleep cookie
1028 */
1029static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter)
1030{
1031 struct pcie_service_card *card;
1032
1033 if (!adapter)
1034 return 0;
1035
1036 card = adapter->card;
1037
fc331460
AP		 1038 if (card && card->sleep_cookie_vbase) {
1039 pci_free_consistent(card->dev, sizeof(u32),
1040 card->sleep_cookie_vbase,
1041 card->sleep_cookie_pbase);
1042 card->sleep_cookie_vbase = NULL;
d930faee
AK		 1043 }
1044
1045 return 0;
1046}
1047
fbd7e7ac
AP		 1048/* This function flushes the TX buffer descriptor ring
1049 * This function defined as handler is also called while cleaning TXRX
1050 * during disconnect/ bss stop.
1051 */
1052static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter)
1053{
1054 struct pcie_service_card *card = adapter->card;
fbd7e7ac 1055
48f4d916 1056 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) {
fbd7e7ac
AP		 1057 card->txbd_flush = 1;
1058 /* write pointer already set at last send
1059 * send dnld-rdy intr again, wait for completion.
1060 */
1061 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1062 CPU_INTR_DNLD_RDY)) {
acebe8c1
ZL		 1063 mwifiex_dbg(adapter, ERROR,
1064 "failed to assert dnld-rdy interrupt.\n");
fbd7e7ac
AP		 1065 return -1;
1066 }
1067 }
1068 return 0;
1069}
1070
d930faee 1071/*
e7f767a7 1072 * This function unmaps and frees downloaded data buffer
d930faee 1073 */
e7f767a7 1074static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter)
d930faee 1075{
e7f767a7 1076 struct sk_buff *skb;
ca8f2112 1077 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0;
e05dc3e9 1078 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 1079 struct mwifiex_pfu_buf_desc *desc2;
d930faee 1080 struct pcie_service_card *card = adapter->card;
dd04e6ac 1081 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1082
1083 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1084 mwifiex_pm_wakeup_card(adapter);
1085
1086 /* Read the TX ring read pointer set by firmware */
dd04e6ac 1087 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) {
acebe8c1
ZL		 1088 mwifiex_dbg(adapter, ERROR,
1089 "SEND COMP: failed to read reg->tx_rdptr\n");
d930faee
AK		 1090 return -1;
1091 }
1092
acebe8c1
ZL		 1093 mwifiex_dbg(adapter, DATA,
1094 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n",
1095 card->txbd_rdptr, rdptr);
d930faee 1096
ca8f2112 1097 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
e7f767a7 1098 /* free from previous txbd_rdptr to current txbd_rdptr */
dd04e6ac
AP		 1099 while (((card->txbd_rdptr & reg->tx_mask) !=
1100 (rdptr & reg->tx_mask)) ||
1101 ((card->txbd_rdptr & reg->tx_rollover_ind) !=
1102 (rdptr & reg->tx_rollover_ind))) {
ca8f2112
AP		 1103 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >>
1104 reg->tx_start_ptr;
e7f767a7
AP		 1105
1106 skb = card->tx_buf_list[wrdoneidx];
dbccc92b 1107
e7f767a7 1108 if (skb) {
acebe8c1
ZL		 1109 mwifiex_dbg(adapter, DATA,
1110 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n",
1111 skb, wrdoneidx);
dbccc92b
AD		 1112 mwifiex_unmap_pci_memory(adapter, skb,
1113 PCI_DMA_TODEVICE);
e7f767a7
AP		 1114
1115 unmap_count++;
1116
1117 if (card->txbd_flush)
1118 mwifiex_write_data_complete(adapter, skb, 0,
1119 -1);
1120 else
1121 mwifiex_write_data_complete(adapter, skb, 0, 0);
1122 }
1123
1124 card->tx_buf_list[wrdoneidx] = NULL;
ca8f2112
AP		 1125
1126 if (reg->pfu_enabled) {
45d18c56 1127 desc2 = card->txbd_ring[wrdoneidx];
ca8f2112
AP		 1128 memset(desc2, 0, sizeof(*desc2));
1129 } else {
1130 desc = card->txbd_ring[wrdoneidx];
1131 memset(desc, 0, sizeof(*desc));
1132 }
1133 switch (card->dev->device) {
1134 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1135 card->txbd_rdptr++;
1136 break;
1137 case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00 1138 case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112
AP		 1139 card->txbd_rdptr += reg->ring_tx_start_ptr;
1140 break;
1141 }
1142
e7f767a7 1143
dd04e6ac 1144 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs)
e7f767a7 1145 card->txbd_rdptr = ((card->txbd_rdptr &
dd04e6ac
AP		 1146 reg->tx_rollover_ind) ^
1147 reg->tx_rollover_ind);
e7f767a7
AP		 1148 }
1149
1150 if (unmap_count)
1151 adapter->data_sent = false;
1152
1153 if (card->txbd_flush) {
3d482038 1154 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr))
e7f767a7
AP		 1155 card->txbd_flush = 0;
1156 else
1157 mwifiex_clean_pcie_ring_buf(adapter);
1158 }
1159
1160 return 0;
1161}
1162
1163/* This function sends data buffer to device. First 4 bytes of payload
1164 * are filled with payload length and payload type. Then this payload
1165 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly.
1166 * Download ready interrupt to FW is deffered if Tx ring is not full and
1167 * additional payload can be accomodated.
8d767dcb 1168 * Caller must ensure tx_param parameter to this function is not NULL.
e7f767a7
AP		 1169 */
1170static int
1171mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb,
1172 struct mwifiex_tx_param *tx_param)
1173{
1174 struct pcie_service_card *card = adapter->card;
dd04e6ac 1175 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1176 u32 wrindx, num_tx_buffs, rx_val;
e7f767a7
AP		 1177 int ret;
1178 dma_addr_t buf_pa;
9931078e
BZ		 1179 struct mwifiex_pcie_buf_desc *desc = NULL;
1180 struct mwifiex_pfu_buf_desc *desc2 = NULL;
e7f767a7
AP		 1181 __le16 *tmp;
1182
1183 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1184 mwifiex_dbg(adapter, ERROR,
1185 "%s(): invalid parameter <%p, %#x>\n",
1186 __func__, skb->data, skb->len);
e7f767a7
AP		 1187 return -1;
1188 }
1189
1190 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1191 mwifiex_pm_wakeup_card(adapter);
1192
ca8f2112 1193 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
acebe8c1
ZL		 1194 mwifiex_dbg(adapter, DATA,
1195 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n",
e7f767a7
AP		 1196 card->txbd_rdptr, card->txbd_wrptr);
1197 if (mwifiex_pcie_txbd_not_full(card)) {
d930faee
AK		 1198 u8 *payload;
1199
1200 adapter->data_sent = true;
e7f767a7 1201 payload = skb->data;
d930faee
AK		 1202 tmp = (__le16 *)&payload[0];
1203 *tmp = cpu_to_le16((u16)skb->len);
1204 tmp = (__le16 *)&payload[2];
1205 *tmp = cpu_to_le16(MWIFIEX_TYPE_DATA);
e7f767a7 1206
dbccc92b 1207 if (mwifiex_map_pci_memory(adapter, skb, skb->len,
e7f767a7
AP		 1208 PCI_DMA_TODEVICE))
1209 return -1;
1210
ca8f2112 1211 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr;
dbccc92b 1212 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
e7f767a7 1213 card->tx_buf_list[wrindx] = skb;
d930faee 1214
ca8f2112 1215 if (reg->pfu_enabled) {
45d18c56 1216 desc2 = card->txbd_ring[wrindx];
ca8f2112
AP		 1217 desc2->paddr = buf_pa;
1218 desc2->len = (u16)skb->len;
1219 desc2->frag_len = (u16)skb->len;
1220 desc2->offset = 0;
1221 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1222 MWIFIEX_BD_FLAG_LAST_DESC;
1223 } else {
1224 desc = card->txbd_ring[wrindx];
1225 desc->paddr = buf_pa;
1226 desc->len = (u16)skb->len;
1227 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1228 MWIFIEX_BD_FLAG_LAST_DESC;
1229 }
1230
1231 switch (card->dev->device) {
1232 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1233 card->txbd_wrptr++;
1234 break;
1235 case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00 1236 case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112
AP		 1237 card->txbd_wrptr += reg->ring_tx_start_ptr;
1238 break;
1239 }
1240
1241 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs)
d930faee 1242 card->txbd_wrptr = ((card->txbd_wrptr &
dd04e6ac
AP		 1243 reg->tx_rollover_ind) ^
1244 reg->tx_rollover_ind);
d930faee 1245
ca8f2112 1246 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask;
dd04e6ac
AP		 1247 /* Write the TX ring write pointer in to reg->tx_wrptr */
1248 if (mwifiex_write_reg(adapter, reg->tx_wrptr,
ca8f2112 1249 card->txbd_wrptr | rx_val)) {
acebe8c1
ZL		 1250 mwifiex_dbg(adapter, ERROR,
1251 "SEND DATA: failed to write reg->tx_wrptr\n");
e7f767a7
AP		 1252 ret = -1;
1253 goto done_unmap;
d930faee 1254 }
e7f767a7
AP		 1255 if ((mwifiex_pcie_txbd_not_full(card)) &&
1256 tx_param->next_pkt_len) {
1257 /* have more packets and TxBD still can hold more */
acebe8c1
ZL		 1258 mwifiex_dbg(adapter, DATA,
1259 "SEND DATA: delay dnld-rdy interrupt.\n");
e7f767a7
AP		 1260 adapter->data_sent = false;
1261 } else {
1262 /* Send the TX ready interrupt */
1263 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1264 CPU_INTR_DNLD_RDY)) {
acebe8c1
ZL		 1265 mwifiex_dbg(adapter, ERROR,
1266 "SEND DATA: failed to assert dnld-rdy interrupt.\n");
e7f767a7
AP		 1267 ret = -1;
1268 goto done_unmap;
1269 }
d930faee 1270 }
acebe8c1
ZL		 1271 mwifiex_dbg(adapter, DATA,
1272 "info: SEND DATA: Updated <Rd: %#x, Wr:\t"
1273 "%#x> and sent packet to firmware successfully\n",
1274 card->txbd_rdptr, card->txbd_wrptr);
d930faee 1275 } else {
acebe8c1
ZL		 1276 mwifiex_dbg(adapter, DATA,
1277 "info: TX Ring full, can't send packets to fw\n");
d930faee
AK		 1278 adapter->data_sent = true;
1279 /* Send the TX ready interrupt */
1280 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1281 CPU_INTR_DNLD_RDY))
acebe8c1
ZL		 1282 mwifiex_dbg(adapter, ERROR,
1283 "SEND DATA: failed to assert door-bell intr\n");
d930faee
AK		 1284 return -EBUSY;
1285 }
1286
e7f767a7
AP		 1287 return -EINPROGRESS;
1288done_unmap:
dbccc92b 1289 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
e7f767a7 1290 card->tx_buf_list[wrindx] = NULL;
ca8f2112
AP		 1291 if (reg->pfu_enabled)
1292 memset(desc2, 0, sizeof(*desc2));
1293 else
1294 memset(desc, 0, sizeof(*desc));
1295
e7f767a7 1296 return ret;
d930faee
AK		 1297}
1298
1299/*
1300 * This function handles received buffer ring and
1301 * dispatches packets to upper
1302 */
1303static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter)
1304{
1305 struct pcie_service_card *card = adapter->card;
dd04e6ac 1306 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1307 u32 wrptr, rd_index, tx_val;
e7f767a7 1308 dma_addr_t buf_pa;
d930faee
AK		 1309 int ret = 0;
1310 struct sk_buff *skb_tmp = NULL;
e05dc3e9 1311 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 1312 struct mwifiex_pfu_buf_desc *desc2;
d930faee 1313
e7f767a7
AP		 1314 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1315 mwifiex_pm_wakeup_card(adapter);
1316
d930faee 1317 /* Read the RX ring Write pointer set by firmware */
dd04e6ac 1318 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
acebe8c1
ZL		 1319 mwifiex_dbg(adapter, ERROR,
1320 "RECV DATA: failed to read reg->rx_wrptr\n");
d930faee
AK		 1321 ret = -1;
1322 goto done;
1323 }
e7f767a7 1324 card->rxbd_wrptr = wrptr;
d930faee 1325
dd04e6ac
AP		 1326 while (((wrptr & reg->rx_mask) !=
1327 (card->rxbd_rdptr & reg->rx_mask)) ||
1328 ((wrptr & reg->rx_rollover_ind) ==
1329 (card->rxbd_rdptr & reg->rx_rollover_ind))) {
d930faee
AK		 1330 struct sk_buff *skb_data;
1331 u16 rx_len;
e7f767a7 1332 __le16 pkt_len;
d930faee 1333
dd04e6ac 1334 rd_index = card->rxbd_rdptr & reg->rx_mask;
d930faee
AK		 1335 skb_data = card->rx_buf_list[rd_index];
1336
bb8e6a1e
AK		 1337 /* If skb allocation was failed earlier for Rx packet,
1338 * rx_buf_list[rd_index] would have been left with a NULL.
1339 */
1340 if (!skb_data)
1341 return -ENOMEM;
1342
dbccc92b 1343 mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE);
e7f767a7
AP		 1344 card->rx_buf_list[rd_index] = NULL;
1345
d930faee 1346 /* Get data length from interface header -
e7f767a7
AP		 1347 * first 2 bytes for len, next 2 bytes is for type
1348 */
1349 pkt_len = *((__le16 *)skb_data->data);
1350 rx_len = le16_to_cpu(pkt_len);
42a028aa
AP		 1351 if (WARN_ON(rx_len <= INTF_HEADER_LEN ||
1352 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) {
acebe8c1
ZL		 1353 mwifiex_dbg(adapter, ERROR,
1354 "Invalid RX len %d, Rd=%#x, Wr=%#x\n",
1355 rx_len, card->rxbd_rdptr, wrptr);
42a028aa
AP		 1356 dev_kfree_skb_any(skb_data);
1357 } else {
1358 skb_put(skb_data, rx_len);
acebe8c1
ZL		 1359 mwifiex_dbg(adapter, DATA,
1360 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n",
1361 card->rxbd_rdptr, wrptr, rx_len);
42a028aa 1362 skb_pull(skb_data, INTF_HEADER_LEN);
6e251174 1363 if (adapter->rx_work_enabled) {
6e251174 1364 skb_queue_tail(&adapter->rx_data_q, skb_data);
6e251174
AP		 1365 adapter->data_received = true;
1366 atomic_inc(&adapter->rx_pending);
1367 } else {
1368 mwifiex_handle_rx_packet(adapter, skb_data);
1369 }
42a028aa 1370 }
e7f767a7 1371
62159944 1372 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
5c87a55a 1373 GFP_KERNEL);
d930faee 1374 if (!skb_tmp) {
acebe8c1
ZL		 1375 mwifiex_dbg(adapter, ERROR,
1376 "Unable to allocate skb.\n");
e7f767a7 1377 return -ENOMEM;
d930faee
AK		 1378 }
1379
e7f767a7
AP		 1380 if (mwifiex_map_pci_memory(adapter, skb_tmp,
1381 MWIFIEX_RX_DATA_BUF_SIZE,
1382 PCI_DMA_FROMDEVICE))
1383 return -1;
1384
dbccc92b 1385 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp);
e7f767a7 1386
acebe8c1
ZL		 1387 mwifiex_dbg(adapter, INFO,
1388 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n",
1389 skb_tmp, rd_index);
e7f767a7 1390 card->rx_buf_list[rd_index] = skb_tmp;
ca8f2112
AP		 1391
1392 if (reg->pfu_enabled) {
45d18c56 1393 desc2 = card->rxbd_ring[rd_index];
ca8f2112
AP		 1394 desc2->paddr = buf_pa;
1395 desc2->len = skb_tmp->len;
1396 desc2->frag_len = skb_tmp->len;
1397 desc2->offset = 0;
1398 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop;
1399 } else {
1400 desc = card->rxbd_ring[rd_index];
1401 desc->paddr = buf_pa;
1402 desc->len = skb_tmp->len;
1403 desc->flags = 0;
1404 }
d930faee 1405
dd04e6ac 1406 if ((++card->rxbd_rdptr & reg->rx_mask) ==
d930faee
AK		 1407 MWIFIEX_MAX_TXRX_BD) {
1408 card->rxbd_rdptr = ((card->rxbd_rdptr &
dd04e6ac
AP		 1409 reg->rx_rollover_ind) ^
1410 reg->rx_rollover_ind);
d930faee 1411 }
acebe8c1
ZL		 1412 mwifiex_dbg(adapter, DATA,
1413 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n",
1414 card->rxbd_rdptr, wrptr);
d930faee 1415
ca8f2112 1416 tx_val = card->txbd_wrptr & reg->tx_wrap_mask;
dd04e6ac
AP		 1417 /* Write the RX ring read pointer in to reg->rx_rdptr */
1418 if (mwifiex_write_reg(adapter, reg->rx_rdptr,
ca8f2112 1419 card->rxbd_rdptr | tx_val)) {
acebe8c1
ZL		 1420 mwifiex_dbg(adapter, DATA,
1421 "RECV DATA: failed to write reg->rx_rdptr\n");
d930faee
AK		 1422 ret = -1;
1423 goto done;
1424 }
1425
1426 /* Read the RX ring Write pointer set by firmware */
dd04e6ac 1427 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
acebe8c1
ZL		 1428 mwifiex_dbg(adapter, ERROR,
1429 "RECV DATA: failed to read reg->rx_wrptr\n");
d930faee
AK		 1430 ret = -1;
1431 goto done;
1432 }
acebe8c1
ZL		 1433 mwifiex_dbg(adapter, DATA,
1434 "info: RECV DATA: Rcvd packet from fw successfully\n");
e7f767a7 1435 card->rxbd_wrptr = wrptr;
d930faee
AK		 1436 }
1437
1438done:
d930faee
AK		 1439 return ret;
1440}
1441
1442/*
1443 * This function downloads the boot command to device
1444 */
1445static int
1446mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1447{
fc331460
AP		 1448 dma_addr_t buf_pa;
1449 struct pcie_service_card *card = adapter->card;
dd04e6ac 1450 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 1451
fc331460 1452 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1453 mwifiex_dbg(adapter, ERROR,
1454 "Invalid parameter in %s <%p. len %d>\n",
1455 __func__, skb->data, skb->len);
d930faee
AK		 1456 return -1;
1457 }
1458
3a968d76 1459 if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
fc331460
AP		 1460 return -1;
1461
dbccc92b 1462 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
fc331460 1463
dd04e6ac
AP		 1464 /* Write the lower 32bits of the physical address to low command
1465 * address scratch register
1466 */
1467 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) {
acebe8c1
ZL		 1468 mwifiex_dbg(adapter, ERROR,
1469 "%s: failed to write download command to boot code.\n",
1470 __func__);
dbccc92b 1471 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1472 return -1;
1473 }
1474
dd04e6ac
AP		 1475 /* Write the upper 32bits of the physical address to high command
1476 * address scratch register
1477 */
1478 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
fc331460 1479 (u32)((u64)buf_pa >> 32))) {
acebe8c1
ZL		 1480 mwifiex_dbg(adapter, ERROR,
1481 "%s: failed to write download command to boot code.\n",
1482 __func__);
dbccc92b 1483 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1484 return -1;
1485 }
1486
dd04e6ac
AP		 1487 /* Write the command length to cmd_size scratch register */
1488 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) {
acebe8c1
ZL		 1489 mwifiex_dbg(adapter, ERROR,
1490 "%s: failed to write command len to cmd_size scratch reg\n",
1491 __func__);
dbccc92b 1492 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1493 return -1;
1494 }
1495
1496 /* Ring the door bell */
1497 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1498 CPU_INTR_DOOR_BELL)) {
acebe8c1
ZL		 1499 mwifiex_dbg(adapter, ERROR,
1500 "%s: failed to assert door-bell intr\n", __func__);
dbccc92b 1501 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1502 return -1;
1503 }
1504
1505 return 0;
1506}
1507
c6d1d87a
AP		 1508/* This function init rx port in firmware which in turn enables to receive data
1509 * from device before transmitting any packet.
1510 */
1511static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter)
1512{
1513 struct pcie_service_card *card = adapter->card;
dd04e6ac 1514 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1515 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask;
c6d1d87a 1516
dd04e6ac 1517 /* Write the RX ring read pointer in to reg->rx_rdptr */
ca8f2112
AP		 1518 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr |
1519 tx_wrap)) {
acebe8c1
ZL		 1520 mwifiex_dbg(adapter, ERROR,
1521 "RECV DATA: failed to write reg->rx_rdptr\n");
c6d1d87a
AP		 1522 return -1;
1523 }
1524 return 0;
1525}
1526
1527/* This function downloads commands to the device
d930faee
AK		 1528 */
1529static int
1530mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1531{
1532 struct pcie_service_card *card = adapter->card;
dd04e6ac 1533 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 1534 int ret = 0;
fc331460
AP		 1535 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa;
1536 u8 *payload = (u8 *)skb->data;
d930faee
AK		 1537
1538 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1539 mwifiex_dbg(adapter, ERROR,
1540 "Invalid parameter in %s <%p, %#x>\n",
1541 __func__, skb->data, skb->len);
d930faee
AK		 1542 return -1;
1543 }
1544
1545 /* Make sure a command response buffer is available */
1546 if (!card->cmdrsp_buf) {
acebe8c1
ZL		 1547 mwifiex_dbg(adapter, ERROR,
1548 "No response buffer available, send command failed\n");
d930faee
AK		 1549 return -EBUSY;
1550 }
1551
fc331460
AP		 1552 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1553 mwifiex_pm_wakeup_card(adapter);
d930faee
AK		 1554
1555 adapter->cmd_sent = true;
fc331460
AP		 1556
1557 *(__le16 *)&payload[0] = cpu_to_le16((u16)skb->len);
1558 *(__le16 *)&payload[2] = cpu_to_le16(MWIFIEX_TYPE_CMD);
1559
1560 if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
1561 return -1;
1562
1563 card->cmd_buf = skb;
d930faee
AK		 1564
1565 /* To send a command, the driver will:
1566 1. Write the 64bit physical address of the data buffer to
dd04e6ac 1567 cmd response address low + cmd response address high
d930faee
AK		 1568 2. Ring the door bell (i.e. set the door bell interrupt)
1569
1570 In response to door bell interrupt, the firmware will perform
1571 the DMA of the command packet (first header to obtain the total
1572 length and then rest of the command).
1573 */
1574
1575 if (card->cmdrsp_buf) {
dbccc92b 1576 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf);
d930faee
AK		 1577 /* Write the lower 32bits of the cmdrsp buffer physical
1578 address */
dd04e6ac 1579 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo,
fc331460 1580 (u32)cmdrsp_buf_pa)) {
acebe8c1
ZL		 1581 mwifiex_dbg(adapter, ERROR,
1582 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1583 ret = -1;
1584 goto done;
1585 }
1586 /* Write the upper 32bits of the cmdrsp buffer physical
1587 address */
dd04e6ac 1588 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi,
fc331460 1589 (u32)((u64)cmdrsp_buf_pa >> 32))) {
acebe8c1
ZL		 1590 mwifiex_dbg(adapter, ERROR,
1591 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1592 ret = -1;
1593 goto done;
1594 }
1595 }
1596
dbccc92b 1597 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf);
dd04e6ac
AP		 1598 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */
1599 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo,
1600 (u32)cmd_buf_pa)) {
acebe8c1
ZL		 1601 mwifiex_dbg(adapter, ERROR,
1602 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1603 ret = -1;
1604 goto done;
1605 }
dd04e6ac
AP		 1606 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */
1607 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
fc331460 1608 (u32)((u64)cmd_buf_pa >> 32))) {
acebe8c1
ZL		 1609 mwifiex_dbg(adapter, ERROR,
1610 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1611 ret = -1;
1612 goto done;
1613 }
1614
dd04e6ac
AP		 1615 /* Write the command length to reg->cmd_size */
1616 if (mwifiex_write_reg(adapter, reg->cmd_size,
1617 card->cmd_buf->len)) {
acebe8c1
ZL		 1618 mwifiex_dbg(adapter, ERROR,
1619 "Failed to write cmd len to reg->cmd_size\n");
d930faee
AK		 1620 ret = -1;
1621 goto done;
1622 }
1623
1624 /* Ring the door bell */
1625 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1626 CPU_INTR_DOOR_BELL)) {
acebe8c1
ZL		 1627 mwifiex_dbg(adapter, ERROR,
1628 "Failed to assert door-bell intr\n");
d930faee
AK		 1629 ret = -1;
1630 goto done;
1631 }
1632
1633done:
1634 if (ret)
1635 adapter->cmd_sent = false;
1636
1637 return 0;
1638}
1639
1640/*
1641 * This function handles command complete interrupt
1642 */
1643static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
1644{
1645 struct pcie_service_card *card = adapter->card;
dd04e6ac 1646 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
f57c1edc 1647 struct sk_buff *skb = card->cmdrsp_buf;
d930faee 1648 int count = 0;
fc331460
AP		 1649 u16 rx_len;
1650 __le16 pkt_len;
d930faee 1651
acebe8c1
ZL		 1652 mwifiex_dbg(adapter, CMD,
1653 "info: Rx CMD Response\n");
d930faee 1654
dbccc92b 1655 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE);
fc331460 1656
189b3299
AD		 1657 /* Unmap the command as a response has been received. */
1658 if (card->cmd_buf) {
1659 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1660 PCI_DMA_TODEVICE);
1661 card->cmd_buf = NULL;
1662 }
1663
fc331460
AP		 1664 pkt_len = *((__le16 *)skb->data);
1665 rx_len = le16_to_cpu(pkt_len);
2fd40d2d 1666 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
fc331460
AP		 1667 skb_trim(skb, rx_len);
1668 skb_pull(skb, INTF_HEADER_LEN);
1669
d930faee 1670 if (!adapter->curr_cmd) {
d930faee 1671 if (adapter->ps_state == PS_STATE_SLEEP_CFM) {
f57c1edc
YAP		 1672 mwifiex_process_sleep_confirm_resp(adapter, skb->data,
1673 skb->len);
1c97560f
AK		 1674 mwifiex_pcie_enable_host_int(adapter);
1675 if (mwifiex_write_reg(adapter,
1676 PCIE_CPU_INT_EVENT,
1677 CPU_INTR_SLEEP_CFM_DONE)) {
acebe8c1
ZL		 1678 mwifiex_dbg(adapter, ERROR,
1679 "Write register failed\n");
1c97560f
AK		 1680 return -1;
1681 }
c4bc980f
AP		 1682 mwifiex_delay_for_sleep_cookie(adapter,
1683 MWIFIEX_MAX_DELAY_COUNT);
52301a81
AP		 1684 while (reg->sleep_cookie && (count++ < 10) &&
1685 mwifiex_pcie_ok_to_access_hw(adapter))
e7891ba2 1686 usleep_range(50, 60);
d930faee 1687 } else {
acebe8c1
ZL		 1688 mwifiex_dbg(adapter, ERROR,
1689 "There is no command but got cmdrsp\n");
d930faee 1690 }
f57c1edc
YAP		 1691 memcpy(adapter->upld_buf, skb->data,
1692 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
0f49d64c 1693 skb_push(skb, INTF_HEADER_LEN);
fc331460
AP		 1694 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1695 PCI_DMA_FROMDEVICE))
1696 return -1;
d930faee 1697 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) {
f57c1edc 1698 adapter->curr_cmd->resp_skb = skb;
d930faee
AK		 1699 adapter->cmd_resp_received = true;
1700 /* Take the pointer and set it to CMD node and will
1701 return in the response complete callback */
1702 card->cmdrsp_buf = NULL;
1703
1704 /* Clear the cmd-rsp buffer address in scratch registers. This
1705 will prevent firmware from writing to the same response
1706 buffer again. */
dd04e6ac 1707 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) {
acebe8c1
ZL		 1708 mwifiex_dbg(adapter, ERROR,
1709 "cmd_done: failed to clear cmd_rsp_addr_lo\n");
d930faee
AK		 1710 return -1;
1711 }
1712 /* Write the upper 32bits of the cmdrsp buffer physical
1713 address */
dd04e6ac 1714 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) {
acebe8c1
ZL		 1715 mwifiex_dbg(adapter, ERROR,
1716 "cmd_done: failed to clear cmd_rsp_addr_hi\n");
d930faee
AK		 1717 return -1;
1718 }
1719 }
1720
1721 return 0;
1722}
1723
1724/*
1725 * Command Response processing complete handler
1726 */
1727static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter,
1728 struct sk_buff *skb)
1729{
1730 struct pcie_service_card *card = adapter->card;
1731
1732 if (skb) {
1733 card->cmdrsp_buf = skb;
1734 skb_push(card->cmdrsp_buf, INTF_HEADER_LEN);
fc331460
AP		 1735 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1736 PCI_DMA_FROMDEVICE))
1737 return -1;
1738 }
1739
d930faee
AK		 1740 return 0;
1741}
1742
1743/*
1744 * This function handles firmware event ready interrupt
1745 */
1746static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
1747{
1748 struct pcie_service_card *card = adapter->card;
dd04e6ac 1749 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1750 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
1751 u32 wrptr, event;
e05dc3e9 1752 struct mwifiex_evt_buf_desc *desc;
fc331460
AP		 1753
1754 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1755 mwifiex_pm_wakeup_card(adapter);
d930faee
AK		 1756
1757 if (adapter->event_received) {
acebe8c1
ZL		 1758 mwifiex_dbg(adapter, EVENT,
1759 "info: Event being processed,\t"
1760 "do not process this interrupt just yet\n");
d930faee
AK		 1761 return 0;
1762 }
1763
1764 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
acebe8c1
ZL		 1765 mwifiex_dbg(adapter, ERROR,
1766 "info: Invalid read pointer...\n");
d930faee
AK		 1767 return -1;
1768 }
1769
1770 /* Read the event ring write pointer set by firmware */
dd04e6ac 1771 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
acebe8c1
ZL		 1772 mwifiex_dbg(adapter, ERROR,
1773 "EventReady: failed to read reg->evt_wrptr\n");
d930faee
AK		 1774 return -1;
1775 }
1776
acebe8c1
ZL		 1777 mwifiex_dbg(adapter, EVENT,
1778 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>",
1779 card->evtbd_rdptr, wrptr);
f57c1edc
YAP		 1780 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr
1781 & MWIFIEX_EVTBD_MASK)) ||
dd04e6ac
AP		 1782 ((wrptr & reg->evt_rollover_ind) ==
1783 (card->evtbd_rdptr & reg->evt_rollover_ind))) {
d930faee
AK		 1784 struct sk_buff *skb_cmd;
1785 __le16 data_len = 0;
1786 u16 evt_len;
1787
acebe8c1
ZL		 1788 mwifiex_dbg(adapter, INFO,
1789 "info: Read Index: %d\n", rdptr);
d930faee 1790 skb_cmd = card->evt_buf_list[rdptr];
dbccc92b 1791 mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE);
fc331460 1792
d930faee
AK		 1793 /* Take the pointer and set it to event pointer in adapter
1794 and will return back after event handling callback */
1795 card->evt_buf_list[rdptr] = NULL;
e05dc3e9
AP		 1796 desc = card->evtbd_ring[rdptr];
1797 memset(desc, 0, sizeof(*desc));
d930faee
AK		 1798
1799 event = *(u32 *) &skb_cmd->data[INTF_HEADER_LEN];
1800 adapter->event_cause = event;
1801 /* The first 4bytes will be the event transfer header
1802 len is 2 bytes followed by type which is 2 bytes */
1803 memcpy(&data_len, skb_cmd->data, sizeof(__le16));
1804 evt_len = le16_to_cpu(data_len);
868093a9 1805 skb_trim(skb_cmd, evt_len);
d930faee 1806 skb_pull(skb_cmd, INTF_HEADER_LEN);
acebe8c1
ZL		 1807 mwifiex_dbg(adapter, EVENT,
1808 "info: Event length: %d\n", evt_len);
d930faee
AK		 1809
1810 if ((evt_len > 0) && (evt_len < MAX_EVENT_SIZE))
1811 memcpy(adapter->event_body, skb_cmd->data +
1812 MWIFIEX_EVENT_HEADER_LEN, evt_len -
1813 MWIFIEX_EVENT_HEADER_LEN);
1814
1815 adapter->event_received = true;
1816 adapter->event_skb = skb_cmd;
1817
1818 /* Do not update the event read pointer here, wait till the
1819 buffer is released. This is just to make things simpler,
1820 we need to find a better method of managing these buffers.
1821 */
2703a668
AP		 1822 } else {
1823 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1824 CPU_INTR_EVENT_DONE)) {
acebe8c1
ZL		 1825 mwifiex_dbg(adapter, ERROR,
1826 "Write register failed\n");
2703a668
AP		 1827 return -1;
1828 }
d930faee
AK		 1829 }
1830
1831 return 0;
1832}
1833
1834/*
1835 * Event processing complete handler
1836 */
1837static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter,
1838 struct sk_buff *skb)
1839{
1840 struct pcie_service_card *card = adapter->card;
dd04e6ac 1841 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1842 int ret = 0;
1843 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
1844 u32 wrptr;
e05dc3e9 1845 struct mwifiex_evt_buf_desc *desc;
d930faee
AK		 1846
1847 if (!skb)
1848 return 0;
1849
1eb54c8a 1850 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
acebe8c1
ZL		 1851 mwifiex_dbg(adapter, ERROR,
1852 "event_complete: Invalid rdptr 0x%x\n",
1853 rdptr);
8c53e42d 1854 return -EINVAL;
1eb54c8a 1855 }
d930faee
AK		 1856
1857 /* Read the event ring write pointer set by firmware */
dd04e6ac 1858 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
acebe8c1
ZL		 1859 mwifiex_dbg(adapter, ERROR,
1860 "event_complete: failed to read reg->evt_wrptr\n");
8c53e42d 1861 return -1;
d930faee
AK		 1862 }
1863
1864 if (!card->evt_buf_list[rdptr]) {
1865 skb_push(skb, INTF_HEADER_LEN);
2728cecd 1866 skb_put(skb, MAX_EVENT_SIZE - skb->len);
fc331460
AP		 1867 if (mwifiex_map_pci_memory(adapter, skb,
1868 MAX_EVENT_SIZE,
1869 PCI_DMA_FROMDEVICE))
1870 return -1;
d930faee 1871 card->evt_buf_list[rdptr] = skb;
e05dc3e9 1872 desc = card->evtbd_ring[rdptr];
dbccc92b 1873 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb);
e05dc3e9
AP		 1874 desc->len = (u16)skb->len;
1875 desc->flags = 0;
d930faee
AK		 1876 skb = NULL;
1877 } else {
acebe8c1
ZL		 1878 mwifiex_dbg(adapter, ERROR,
1879 "info: ERROR: buf still valid at index %d, <%p, %p>\n",
1880 rdptr, card->evt_buf_list[rdptr], skb);
d930faee
AK		 1881 }
1882
1883 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) {
1884 card->evtbd_rdptr = ((card->evtbd_rdptr &
dd04e6ac
AP		 1885 reg->evt_rollover_ind) ^
1886 reg->evt_rollover_ind);
d930faee
AK		 1887 }
1888
acebe8c1
ZL		 1889 mwifiex_dbg(adapter, EVENT,
1890 "info: Updated <Rd: 0x%x, Wr: 0x%x>",
1891 card->evtbd_rdptr, wrptr);
d930faee 1892
dd04e6ac
AP		 1893 /* Write the event ring read pointer in to reg->evt_rdptr */
1894 if (mwifiex_write_reg(adapter, reg->evt_rdptr,
1895 card->evtbd_rdptr)) {
acebe8c1
ZL		 1896 mwifiex_dbg(adapter, ERROR,
1897 "event_complete: failed to read reg->evt_rdptr\n");
8c53e42d 1898 return -1;
d930faee
AK		 1899 }
1900
acebe8c1
ZL		 1901 mwifiex_dbg(adapter, EVENT,
1902 "info: Check Events Again\n");
d930faee
AK		 1903 ret = mwifiex_pcie_process_event_ready(adapter);
1904
1905 return ret;
1906}
1907
1908/*
1909 * This function downloads the firmware to the card.
1910 *
1911 * Firmware is downloaded to the card in blocks. Every block download
1912 * is tested for CRC errors, and retried a number of times before
1913 * returning failure.
1914 */
1915static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter,
1916 struct mwifiex_fw_image *fw)
1917{
1918 int ret;
1919 u8 *firmware = fw->fw_buf;
1920 u32 firmware_len = fw->fw_len;
1921 u32 offset = 0;
1922 struct sk_buff *skb;
1923 u32 txlen, tx_blocks = 0, tries, len;
1924 u32 block_retry_cnt = 0;
fc331460 1925 struct pcie_service_card *card = adapter->card;
dd04e6ac 1926 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1927
1928 if (!firmware || !firmware_len) {
acebe8c1
ZL		 1929 mwifiex_dbg(adapter, ERROR,
1930 "No firmware image found! Terminating download\n");
d930faee
AK		 1931 return -1;
1932 }
1933
acebe8c1
ZL		 1934 mwifiex_dbg(adapter, INFO,
1935 "info: Downloading FW image (%d bytes)\n",
1936 firmware_len);
d930faee
AK		 1937
1938 if (mwifiex_pcie_disable_host_int(adapter)) {
acebe8c1
ZL		 1939 mwifiex_dbg(adapter, ERROR,
1940 "%s: Disabling interrupts failed.\n", __func__);
d930faee
AK		 1941 return -1;
1942 }
1943
1944 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
1945 if (!skb) {
1946 ret = -ENOMEM;
1947 goto done;
1948 }
d930faee
AK		 1949
1950 /* Perform firmware data transfer */
1951 do {
1952 u32 ireg_intr = 0;
1953
1954 /* More data? */
1955 if (offset >= firmware_len)
1956 break;
1957
1958 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
dd04e6ac 1959 ret = mwifiex_read_reg(adapter, reg->cmd_size,
d930faee
AK		 1960 &len);
1961 if (ret) {
acebe8c1
ZL		 1962 mwifiex_dbg(adapter, FATAL,
1963 "Failed reading len from boot code\n");
d930faee
AK		 1964 goto done;
1965 }
1966 if (len)
1967 break;
e7891ba2 1968 usleep_range(10, 20);
d930faee
AK		 1969 }
1970
1971 if (!len) {
1972 break;
1973 } else if (len > MWIFIEX_UPLD_SIZE) {
acebe8c1
ZL		 1974 mwifiex_dbg(adapter, ERROR,
1975 "FW download failure @ %d, invalid length %d\n",
1976 offset, len);
d930faee
AK		 1977 ret = -1;
1978 goto done;
1979 }
1980
1981 txlen = len;
1982
1983 if (len & BIT(0)) {
1984 block_retry_cnt++;
1985 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) {
acebe8c1
ZL		 1986 mwifiex_dbg(adapter, ERROR,
1987 "FW download failure @ %d, over max\t"
1988 "retry count\n", offset);
d930faee
AK		 1989 ret = -1;
1990 goto done;
1991 }
acebe8c1
ZL		 1992 mwifiex_dbg(adapter, ERROR,
1993 "FW CRC error indicated by the\t"
1994 "helper: len = 0x%04X, txlen = %d\n",
1995 len, txlen);
d930faee
AK		 1996 len &= ~BIT(0);
1997 /* Setting this to 0 to resend from same offset */
1998 txlen = 0;
1999 } else {
2000 block_retry_cnt = 0;
2001 /* Set blocksize to transfer - checking for
2002 last block */
2003 if (firmware_len - offset < txlen)
2004 txlen = firmware_len - offset;
2005
dd04e6ac
AP		 2006 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) /
2007 card->pcie.blksz_fw_dl;
d930faee
AK		 2008
2009 /* Copy payload to buffer */
2010 memmove(skb->data, &firmware[offset], txlen);
2011 }
2012
2013 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
dd04e6ac 2014 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl);
d930faee
AK		 2015
2016 /* Send the boot command to device */
2017 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) {
acebe8c1
ZL		 2018 mwifiex_dbg(adapter, ERROR,
2019 "Failed to send firmware download command\n");
d930faee
AK		 2020 ret = -1;
2021 goto done;
2022 }
fc331460 2023
d930faee
AK		 2024 /* Wait for the command done interrupt */
2025 do {
2026 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS,
2027 &ireg_intr)) {
acebe8c1
ZL		 2028 mwifiex_dbg(adapter, ERROR,
2029 "%s: Failed to read\t"
2030 "interrupt status during fw dnld.\n",
2031 __func__);
dbccc92b
AD		 2032 mwifiex_unmap_pci_memory(adapter, skb,
2033 PCI_DMA_TODEVICE);
d930faee
AK		 2034 ret = -1;
2035 goto done;
2036 }
2037 } while ((ireg_intr & CPU_INTR_DOOR_BELL) ==
2038 CPU_INTR_DOOR_BELL);
fc331460 2039
dbccc92b 2040 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
fc331460 2041
d930faee
AK		 2042 offset += txlen;
2043 } while (true);
2044
acebe8c1
ZL		 2045 mwifiex_dbg(adapter, MSG,
2046 "info: FW download over, size %d bytes\n", offset);
d930faee
AK		 2047
2048 ret = 0;
2049
2050done:
2051 dev_kfree_skb_any(skb);
2052 return ret;
2053}
2054
2055/*
2056 * This function checks the firmware status in card.
d930faee
AK		 2057 */
2058static int
2059mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num)
2060{
2061 int ret = 0;
2fd5c6ed 2062 u32 firmware_stat;
dd04e6ac
AP		 2063 struct pcie_service_card *card = adapter->card;
2064 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 2065 u32 tries;
2066
2067 /* Mask spurios interrupts */
2068 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK,
f57c1edc 2069 HOST_INTR_MASK)) {
acebe8c1
ZL		 2070 mwifiex_dbg(adapter, ERROR,
2071 "Write register failed\n");
d930faee
AK		 2072 return -1;
2073 }
2074
acebe8c1
ZL		 2075 mwifiex_dbg(adapter, INFO,
2076 "Setting driver ready signature\n");
dd04e6ac
AP		 2077 if (mwifiex_write_reg(adapter, reg->drv_rdy,
2078 FIRMWARE_READY_PCIE)) {
acebe8c1
ZL		 2079 mwifiex_dbg(adapter, ERROR,
2080 "Failed to write driver ready signature\n");
d930faee
AK		 2081 return -1;
2082 }
2083
2084 /* Wait for firmware initialization event */
2085 for (tries = 0; tries < poll_num; tries++) {
dd04e6ac 2086 if (mwifiex_read_reg(adapter, reg->fw_status,
d930faee
AK		 2087 &firmware_stat))
2088 ret = -1;
2089 else
2090 ret = 0;
09dd9ec5
SG		 2091
2092 mwifiex_dbg(adapter, INFO, "Try %d if FW is ready <%d,%#x>",
2093 tries, ret, firmware_stat);
2094
d930faee
AK		 2095 if (ret)
2096 continue;
2097 if (firmware_stat == FIRMWARE_READY_PCIE) {
2098 ret = 0;
2099 break;
2100 } else {
a76b20e5 2101 msleep(100);
d930faee
AK		 2102 ret = -1;
2103 }
2104 }
2105
2fd5c6ed 2106 return ret;
2107}
2108
2109/* This function checks if WLAN is the winner.
2110 */
2111static int
2112mwifiex_check_winner_status(struct mwifiex_adapter *adapter)
2113{
2114 u32 winner = 0;
2115 int ret = 0;
2116 struct pcie_service_card *card = adapter->card;
2117 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2118
2119 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) {
2120 ret = -1;
2121 } else if (!winner) {
2122 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n");
2123 adapter->winner = 1;
2124 } else {
2125 mwifiex_dbg(adapter, ERROR,
fd3fbb65 2126 "PCI-E is not the winner <%#x>", winner);
d930faee
AK		 2127 }
2128
2129 return ret;
2130}
2131
2132/*
2133 * This function reads the interrupt status from card.
2134 */
99074fc1
XH		 2135static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter,
2136 int msg_id)
d930faee
AK		 2137{
2138 u32 pcie_ireg;
2139 unsigned long flags;
99074fc1 2140 struct pcie_service_card *card = adapter->card;
d930faee 2141
5781fc29
SL		 2142 if (card->msi_enable) {
2143 spin_lock_irqsave(&adapter->int_lock, flags);
2144 adapter->int_status = 1;
2145 spin_unlock_irqrestore(&adapter->int_lock, flags);
2146 return;
2147 }
2148
d930faee
AK		 2149 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2150 return;
2151
99074fc1
XH		 2152 if (card->msix_enable && msg_id >= 0) {
2153 pcie_ireg = BIT(msg_id);
2154 } else {
2155 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2156 &pcie_ireg)) {
2157 mwifiex_dbg(adapter, ERROR, "Read register failed\n");
2158 return;
2159 }
2160
2161 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg)
2162 return;
d930faee 2163
d930faee
AK		 2164
2165 mwifiex_pcie_disable_host_int(adapter);
2166
2167 /* Clear the pending interrupts */
2168 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS,
2169 ~pcie_ireg)) {
acebe8c1
ZL		 2170 mwifiex_dbg(adapter, ERROR,
2171 "Write register failed\n");
d930faee
AK		 2172 return;
2173 }
99074fc1
XH		 2174 }
2175
99074fc1
XH		 2176 if (!adapter->pps_uapsd_mode &&
2177 adapter->ps_state == PS_STATE_SLEEP &&
2178 mwifiex_pcie_ok_to_access_hw(adapter)) {
2179 /* Potentially for PCIe we could get other
2180 * interrupts like shared. Don't change power
2181 * state until cookie is set
2182 */
2183 adapter->ps_state = PS_STATE_AWAKE;
2184 adapter->pm_wakeup_fw_try = false;
2185 del_timer(&adapter->wakeup_timer);
d930faee 2186 }
dc896b15
SL		 2187
2188 spin_lock_irqsave(&adapter->int_lock, flags);
2189 adapter->int_status |= pcie_ireg;
2190 spin_unlock_irqrestore(&adapter->int_lock, flags);
2191 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg);
d930faee
AK		 2192}
2193
2194/*
2195 * Interrupt handler for PCIe root port
2196 *
2197 * This function reads the interrupt status from firmware and assigns
2198 * the main process in workqueue which will handle the interrupt.
2199 */
2200static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context)
2201{
99074fc1
XH		 2202 struct mwifiex_msix_context *ctx = context;
2203 struct pci_dev *pdev = ctx->dev;
d930faee
AK		 2204 struct pcie_service_card *card;
2205 struct mwifiex_adapter *adapter;
2206
2207 if (!pdev) {
91442431 2208 pr_err("info: %s: pdev is NULL\n", __func__);
d930faee
AK		 2209 goto exit;
2210 }
2211
b2a31204 2212 card = pci_get_drvdata(pdev);
d930faee 2213 if (!card || !card->adapter) {
91442431
XH		 2214 pr_err("info: %s: card=%p adapter=%p\n", __func__, card,
2215 card ? card->adapter : NULL);
d930faee
AK		 2216 goto exit;
2217 }
2218 adapter = card->adapter;
2219
2220 if (adapter->surprise_removed)
2221 goto exit;
2222
99074fc1
XH		 2223 if (card->msix_enable)
2224 mwifiex_interrupt_status(adapter, ctx->msg_id);
2225 else
2226 mwifiex_interrupt_status(adapter, -1);
2227
b2713f67 2228 mwifiex_queue_main_work(adapter);
d930faee
AK		 2229
2230exit:
2231 return IRQ_HANDLED;
2232}
2233
2234/*
2235 * This function checks the current interrupt status.
2236 *
2237 * The following interrupts are checked and handled by this function -
2238 * - Data sent
2239 * - Command sent
2240 * - Command received
2241 * - Packets received
2242 * - Events received
2243 *
2244 * In case of Rx packets received, the packets are uploaded from card to
2245 * host and processed accordingly.
2246 */
99074fc1 2247static int mwifiex_process_pcie_int(struct mwifiex_adapter *adapter)
d930faee
AK		 2248{
2249 int ret;
5781fc29 2250 u32 pcie_ireg = 0;
d930faee 2251 unsigned long flags;
5781fc29 2252 struct pcie_service_card *card = adapter->card;
d930faee
AK		 2253
2254 spin_lock_irqsave(&adapter->int_lock, flags);
5781fc29
SL		 2255 if (!card->msi_enable) {
2256 /* Clear out unused interrupts */
2257 pcie_ireg = adapter->int_status;
2258 }
659c4788 2259 adapter->int_status = 0;
d930faee
AK		 2260 spin_unlock_irqrestore(&adapter->int_lock, flags);
2261
5781fc29
SL		 2262 if (card->msi_enable) {
2263 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
2264 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2265 &pcie_ireg)) {
2266 mwifiex_dbg(adapter, ERROR,
2267 "Read register failed\n");
2268 return -1;
2269 }
2270
2271 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
2272 if (mwifiex_write_reg(adapter,
2273 PCIE_HOST_INT_STATUS,
2274 ~pcie_ireg)) {
2275 mwifiex_dbg(adapter, ERROR,
2276 "Write register failed\n");
2277 return -1;
2278 }
2279 if (!adapter->pps_uapsd_mode &&
2280 adapter->ps_state == PS_STATE_SLEEP) {
2281 adapter->ps_state = PS_STATE_AWAKE;
2282 adapter->pm_wakeup_fw_try = false;
2283 del_timer(&adapter->wakeup_timer);
2284 }
2285 }
2286 }
2287 }
659c4788
AP		 2288 while (pcie_ireg & HOST_INTR_MASK) {
2289 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2290 pcie_ireg &= ~HOST_INTR_DNLD_DONE;
acebe8c1
ZL		 2291 mwifiex_dbg(adapter, INTR,
2292 "info: TX DNLD Done\n");
e7f767a7
AP		 2293 ret = mwifiex_pcie_send_data_complete(adapter);
2294 if (ret)
2295 return ret;
d930faee 2296 }
659c4788
AP		 2297 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2298 pcie_ireg &= ~HOST_INTR_UPLD_RDY;
acebe8c1
ZL		 2299 mwifiex_dbg(adapter, INTR,
2300 "info: Rx DATA\n");
d930faee
AK		 2301 ret = mwifiex_pcie_process_recv_data(adapter);
2302 if (ret)
2303 return ret;
2304 }
659c4788
AP		 2305 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2306 pcie_ireg &= ~HOST_INTR_EVENT_RDY;
acebe8c1
ZL		 2307 mwifiex_dbg(adapter, INTR,
2308 "info: Rx EVENT\n");
d930faee
AK		 2309 ret = mwifiex_pcie_process_event_ready(adapter);
2310 if (ret)
2311 return ret;
2312 }
2313
659c4788
AP		 2314 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2315 pcie_ireg &= ~HOST_INTR_CMD_DONE;
d930faee 2316 if (adapter->cmd_sent) {
acebe8c1
ZL		 2317 mwifiex_dbg(adapter, INTR,
2318 "info: CMD sent Interrupt\n");
d930faee
AK		 2319 adapter->cmd_sent = false;
2320 }
2321 /* Handle command response */
2322 ret = mwifiex_pcie_process_cmd_complete(adapter);
2323 if (ret)
2324 return ret;
2325 }
2326
5781fc29
SL		 2327 if (card->msi_enable) {
2328 spin_lock_irqsave(&adapter->int_lock, flags);
2329 adapter->int_status = 0;
2330 spin_unlock_irqrestore(&adapter->int_lock, flags);
2331 }
2332
d930faee
AK		 2333 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
2334 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2335 &pcie_ireg)) {
acebe8c1
ZL		 2336 mwifiex_dbg(adapter, ERROR,
2337 "Read register failed\n");
d930faee
AK		 2338 return -1;
2339 }
2340
2341 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
2342 if (mwifiex_write_reg(adapter,
f57c1edc
YAP		 2343 PCIE_HOST_INT_STATUS,
2344 ~pcie_ireg)) {
acebe8c1
ZL		 2345 mwifiex_dbg(adapter, ERROR,
2346 "Write register failed\n");
d930faee
AK		 2347 return -1;
2348 }
d930faee
AK		 2349 }
2350
2351 }
51495288
AK		 2352 if (!card->msi_enable) {
2353 spin_lock_irqsave(&adapter->int_lock, flags);
2354 pcie_ireg |= adapter->int_status;
2355 adapter->int_status = 0;
2356 spin_unlock_irqrestore(&adapter->int_lock, flags);
2357 }
d930faee 2358 }
acebe8c1
ZL		 2359 mwifiex_dbg(adapter, INTR,
2360 "info: cmd_sent=%d data_sent=%d\n",
2361 adapter->cmd_sent, adapter->data_sent);
5781fc29 2362 if (!card->msi_enable && adapter->ps_state != PS_STATE_SLEEP)
b2fda1f6 2363 mwifiex_pcie_enable_host_int(adapter);
d930faee
AK		 2364
2365 return 0;
2366}
2367
99074fc1
XH		 2368static int mwifiex_process_msix_int(struct mwifiex_adapter *adapter)
2369{
2370 int ret;
2371 u32 pcie_ireg;
2372 unsigned long flags;
2373
2374 spin_lock_irqsave(&adapter->int_lock, flags);
2375 /* Clear out unused interrupts */
2376 pcie_ireg = adapter->int_status;
2377 adapter->int_status = 0;
2378 spin_unlock_irqrestore(&adapter->int_lock, flags);
2379
2380 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2381 mwifiex_dbg(adapter, INTR,
2382 "info: TX DNLD Done\n");
2383 ret = mwifiex_pcie_send_data_complete(adapter);
2384 if (ret)
2385 return ret;
2386 }
2387 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2388 mwifiex_dbg(adapter, INTR,
2389 "info: Rx DATA\n");
2390 ret = mwifiex_pcie_process_recv_data(adapter);
2391 if (ret)
2392 return ret;
2393 }
2394 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2395 mwifiex_dbg(adapter, INTR,
2396 "info: Rx EVENT\n");
2397 ret = mwifiex_pcie_process_event_ready(adapter);
2398 if (ret)
2399 return ret;
2400 }
2401
2402 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2403 if (adapter->cmd_sent) {
2404 mwifiex_dbg(adapter, INTR,
2405 "info: CMD sent Interrupt\n");
2406 adapter->cmd_sent = false;
2407 }
2408 /* Handle command response */
2409 ret = mwifiex_pcie_process_cmd_complete(adapter);
2410 if (ret)
2411 return ret;
2412 }
2413
2414 mwifiex_dbg(adapter, INTR,
2415 "info: cmd_sent=%d data_sent=%d\n",
2416 adapter->cmd_sent, adapter->data_sent);
2417
2418 return 0;
2419}
2420
2421static int mwifiex_process_int_status(struct mwifiex_adapter *adapter)
2422{
2423 struct pcie_service_card *card = adapter->card;
2424
2425 if (card->msix_enable)
2426 return mwifiex_process_msix_int(adapter);
2427 else
2428 return mwifiex_process_pcie_int(adapter);
2429}
2430
d930faee
AK		 2431/*
2432 * This function downloads data from driver to card.
2433 *
2434 * Both commands and data packets are transferred to the card by this
2435 * function.
2436 *
2437 * This function adds the PCIE specific header to the front of the buffer
2438 * before transferring. The header contains the length of the packet and
2439 * the type. The firmware handles the packets based upon this set type.
2440 */
2441static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type,
2442 struct sk_buff *skb,
2443 struct mwifiex_tx_param *tx_param)
2444{
fa161cb7 2445 if (!skb) {
acebe8c1
ZL		 2446 mwifiex_dbg(adapter, ERROR,
2447 "Passed NULL skb to %s\n", __func__);
d930faee
AK		 2448 return -1;
2449 }
2450
2451 if (type == MWIFIEX_TYPE_DATA)
e7f767a7 2452 return mwifiex_pcie_send_data(adapter, skb, tx_param);
d930faee
AK		 2453 else if (type == MWIFIEX_TYPE_CMD)
2454 return mwifiex_pcie_send_cmd(adapter, skb);
2455
2456 return 0;
2457}
2458
4646968b
XH		 2459/* Function to dump PCIE scratch registers in case of FW crash
2460 */
2461static int
2462mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf)
2463{
2464 char *p = drv_buf;
2465 char buf[256], *ptr;
2466 int i;
2467 u32 value;
2468 struct pcie_service_card *card = adapter->card;
2469 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2470 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG,
2471 PCIE_SCRATCH_13_REG,
2472 PCIE_SCRATCH_14_REG};
2473
2474 if (!p)
2475 return 0;
2476
2477 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n");
2478
2479 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) {
2480 mwifiex_dbg(adapter, ERROR, "failed to read firmware status");
2481 return 0;
2482 }
2483
2484 ptr = buf;
2485 mwifiex_dbg(adapter, MSG, "pcie scratch register:");
2486 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) {
2487 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value);
2488 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n",
2489 pcie_scratch_reg[i], value);
2490 }
2491
2492 mwifiex_dbg(adapter, MSG, "%s\n", buf);
2493 p += sprintf(p, "%s\n", buf);
2494
2495 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n");
2496
2497 return p - drv_buf;
2498}
2499
92c2538f
AK		 2500/* This function read/write firmware */
2501static enum rdwr_status
2502mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag)
2503{
2504 int ret, tries;
2505 u8 ctrl_data;
0172404d 2506 u32 fw_status;
92c2538f
AK		 2507 struct pcie_service_card *card = adapter->card;
2508 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2509
0172404d
XH		 2510 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status))
2511 return RDWR_STATUS_FAILURE;
2512
50632092
XH		 2513 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2514 reg->fw_dump_host_ready);
92c2538f 2515 if (ret) {
acebe8c1
ZL		 2516 mwifiex_dbg(adapter, ERROR,
2517 "PCIE write err\n");
92c2538f
AK		 2518 return RDWR_STATUS_FAILURE;
2519 }
2520
2521 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2522 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data);
2523 if (ctrl_data == FW_DUMP_DONE)
2524 return RDWR_STATUS_SUCCESS;
2525 if (doneflag && ctrl_data == doneflag)
2526 return RDWR_STATUS_DONE;
50632092 2527 if (ctrl_data != reg->fw_dump_host_ready) {
acebe8c1
ZL		 2528 mwifiex_dbg(adapter, WARN,
2529 "The ctrl reg was changed, re-try again!\n");
24716876 2530 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
50632092 2531 reg->fw_dump_host_ready);
92c2538f 2532 if (ret) {
acebe8c1
ZL		 2533 mwifiex_dbg(adapter, ERROR,
2534 "PCIE write err\n");
92c2538f
AK		 2535 return RDWR_STATUS_FAILURE;
2536 }
2537 }
2538 usleep_range(100, 200);
2539 }
2540
acebe8c1 2541 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n");
92c2538f
AK		 2542 return RDWR_STATUS_FAILURE;
2543}
2544
2545/* This function dump firmware memory to file */
fc697159 2546static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter)
92c2538f
AK		 2547{
2548 struct pcie_service_card *card = adapter->card;
2549 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg;
2550 unsigned int reg, reg_start, reg_end;
11e70824 2551 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num;
56486026 2552 u8 idx, i, read_reg, doneflag = 0;
92c2538f
AK		 2553 enum rdwr_status stat;
2554 u32 memory_size;
24716876 2555 int ret;
92c2538f 2556
b4e8aebb 2557 if (!card->pcie.can_dump_fw)
92c2538f
AK		 2558 return;
2559
50632092
XH		 2560 for (idx = 0; idx < adapter->num_mem_types; idx++) {
2561 struct memory_type_mapping *entry =
2562 &adapter->mem_type_mapping_tbl[idx];
92c2538f
AK		 2563
2564 if (entry->mem_ptr) {
2565 vfree(entry->mem_ptr);
2566 entry->mem_ptr = NULL;
2567 }
2568 entry->mem_size = 0;
2569 }
2570
03f0f7cd 2571 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n");
92c2538f
AK		 2572
2573 /* Read the number of the memories which will dump */
2574 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2575 if (stat == RDWR_STATUS_FAILURE)
57670ee8 2576 return;
92c2538f
AK		 2577
2578 reg = creg->fw_dump_start;
11e70824
XH		 2579 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num);
2580
2581 /* W8997 chipset firmware dump will be restore in single region*/
2582 if (fw_dump_num == 0)
2583 dump_num = 1;
2584 else
2585 dump_num = fw_dump_num;
92c2538f
AK		 2586
2587 /* Read the length of every memory which will dump */
2588 for (idx = 0; idx < dump_num; idx++) {
50632092
XH		 2589 struct memory_type_mapping *entry =
2590 &adapter->mem_type_mapping_tbl[idx];
92c2538f 2591 memory_size = 0;
11e70824
XH		 2592 if (fw_dump_num != 0) {
2593 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2594 if (stat == RDWR_STATUS_FAILURE)
2595 return;
2596
2597 reg = creg->fw_dump_start;
2598 for (i = 0; i < 4; i++) {
2599 mwifiex_read_reg_byte(adapter, reg, &read_reg);
2600 memory_size |= (read_reg << (i * 8));
ccf5fa4f 2601 reg++;
11e70824
XH		 2602 }
2603 } else {
2604 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE;
92c2538f
AK		 2605 }
2606
2607 if (memory_size == 0) {
acebe8c1 2608 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n");
7e174833 2609 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl,
50632092 2610 creg->fw_dump_read_done);
7e174833 2611 if (ret) {
acebe8c1 2612 mwifiex_dbg(adapter, ERROR, "PCIE write err\n");
57670ee8 2613 return;
7e174833 2614 }
92c2538f
AK		 2615 break;
2616 }
2617
acebe8c1
ZL		 2618 mwifiex_dbg(adapter, DUMP,
2619 "%s_SIZE=0x%x\n", entry->mem_name, memory_size);
92c2538f
AK		 2620 entry->mem_ptr = vmalloc(memory_size + 1);
2621 entry->mem_size = memory_size;
2622 if (!entry->mem_ptr) {
acebe8c1
ZL		 2623 mwifiex_dbg(adapter, ERROR,
2624 "Vmalloc %s failed\n", entry->mem_name);
57670ee8 2625 return;
92c2538f
AK		 2626 }
2627 dbg_ptr = entry->mem_ptr;
2628 end_ptr = dbg_ptr + memory_size;
2629
2630 doneflag = entry->done_flag;
acebe8c1
ZL		 2631 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n",
2632 entry->mem_name);
92c2538f
AK		 2633
2634 do {
2635 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2636 if (RDWR_STATUS_FAILURE == stat)
57670ee8 2637 return;
92c2538f
AK		 2638
2639 reg_start = creg->fw_dump_start;
2640 reg_end = creg->fw_dump_end;
2641 for (reg = reg_start; reg <= reg_end; reg++) {
2642 mwifiex_read_reg_byte(adapter, reg, dbg_ptr);
24716876 2643 if (dbg_ptr < end_ptr) {
92c2538f 2644 dbg_ptr++;
56486026 2645 continue;
24716876 2646 }
56486026
XH		 2647 mwifiex_dbg(adapter, ERROR,
2648 "pre-allocated buf not enough\n");
2649 tmp_ptr =
2650 vzalloc(memory_size + MWIFIEX_SIZE_4K);
2651 if (!tmp_ptr)
2652 return;
2653 memcpy(tmp_ptr, entry->mem_ptr, memory_size);
2654 vfree(entry->mem_ptr);
2655 entry->mem_ptr = tmp_ptr;
2656 tmp_ptr = NULL;
2657 dbg_ptr = entry->mem_ptr + memory_size;
2658 memory_size += MWIFIEX_SIZE_4K;
2659 end_ptr = entry->mem_ptr + memory_size;
92c2538f
AK		 2660 }
2661
2662 if (stat != RDWR_STATUS_DONE)
2663 continue;
2664
acebe8c1
ZL		 2665 mwifiex_dbg(adapter, DUMP,
2666 "%s done: size=0x%tx\n",
2667 entry->mem_name, dbg_ptr - entry->mem_ptr);
92c2538f
AK		 2668 break;
2669 } while (true);
2670 }
03f0f7cd 2671 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n");
92c2538f
AK		 2672}
2673
fc697159
AK		 2674static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter)
2675{
2676 mwifiex_drv_info_dump(adapter);
2677 mwifiex_pcie_fw_dump(adapter);
57670ee8 2678 mwifiex_upload_device_dump(adapter);
fc697159
AK		 2679}
2680
2f5872b6
MH		 2681static unsigned long iface_work_flags;
2682static struct mwifiex_adapter *save_adapter;
92c2538f
AK		 2683static void mwifiex_pcie_work(struct work_struct *work)
2684{
fc697159 2685 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
2f5872b6 2686 &iface_work_flags))
fc697159 2687 mwifiex_pcie_device_dump_work(save_adapter);
92c2538f
AK		 2688}
2689
2f5872b6 2690static DECLARE_WORK(pcie_work, mwifiex_pcie_work);
92c2538f 2691/* This function dumps FW information */
fc697159 2692static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter)
92c2538f 2693{
2f5872b6 2694 save_adapter = adapter;
fc697159 2695 if (test_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &iface_work_flags))
92c2538f
AK		 2696 return;
2697
fc697159 2698 set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &iface_work_flags);
92c2538f 2699
2f5872b6 2700 schedule_work(&pcie_work);
92c2538f
AK		 2701}
2702
d930faee
AK		 2703/*
2704 * This function initializes the PCI-E host memory space, WCB rings, etc.
2705 *
2706 * The following initializations steps are followed -
2707 * - Allocate TXBD ring buffers
2708 * - Allocate RXBD ring buffers
2709 * - Allocate event BD ring buffers
2710 * - Allocate command response ring buffer
2711 * - Allocate sleep cookie buffer
2712 */
2713static int mwifiex_pcie_init(struct mwifiex_adapter *adapter)
2714{
2715 struct pcie_service_card *card = adapter->card;
2716 int ret;
2717 struct pci_dev *pdev = card->dev;
52301a81 2718 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 2719
2720 pci_set_drvdata(pdev, card);
2721
2722 ret = pci_enable_device(pdev);
2723 if (ret)
2724 goto err_enable_dev;
2725
2726 pci_set_master(pdev);
2727
fdb1e28e 2728 pr_notice("try set_consistent_dma_mask(32)\n");
d930faee
AK		 2729 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2730 if (ret) {
fdb1e28e 2731 pr_err("set_dma_mask(32) failed\n");
d930faee
AK		 2732 goto err_set_dma_mask;
2733 }
2734
2735 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2736 if (ret) {
fdb1e28e 2737 pr_err("set_consistent_dma_mask(64) failed\n");
d930faee
AK		 2738 goto err_set_dma_mask;
2739 }
2740
2741 ret = pci_request_region(pdev, 0, DRV_NAME);
2742 if (ret) {
fdb1e28e 2743 pr_err("req_reg(0) error\n");
d930faee
AK		 2744 goto err_req_region0;
2745 }
2746 card->pci_mmap = pci_iomap(pdev, 0, 0);
2747 if (!card->pci_mmap) {
fdb1e28e 2748 pr_err("iomap(0) error\n");
3220712d 2749 ret = -EIO;
d930faee
AK		 2750 goto err_iomap0;
2751 }
2752 ret = pci_request_region(pdev, 2, DRV_NAME);
2753 if (ret) {
fdb1e28e 2754 pr_err("req_reg(2) error\n");
d930faee
AK		 2755 goto err_req_region2;
2756 }
2757 card->pci_mmap1 = pci_iomap(pdev, 2, 0);
2758 if (!card->pci_mmap1) {
fdb1e28e 2759 pr_err("iomap(2) error\n");
3220712d 2760 ret = -EIO;
d930faee
AK		 2761 goto err_iomap2;
2762 }
2763
fdb1e28e
XH		 2764 pr_notice("PCI memory map Virt0: %p PCI memory map Virt2: %p\n",
2765 card->pci_mmap, card->pci_mmap1);
d930faee
AK		 2766
2767 card->cmdrsp_buf = NULL;
2768 ret = mwifiex_pcie_create_txbd_ring(adapter);
2769 if (ret)
2770 goto err_cre_txbd;
2771 ret = mwifiex_pcie_create_rxbd_ring(adapter);
2772 if (ret)
2773 goto err_cre_rxbd;
2774 ret = mwifiex_pcie_create_evtbd_ring(adapter);
2775 if (ret)
2776 goto err_cre_evtbd;
2777 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter);
2778 if (ret)
2779 goto err_alloc_cmdbuf;
52301a81
AP		 2780 if (reg->sleep_cookie) {
2781 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter);
2782 if (ret)
2783 goto err_alloc_cookie;
2784 } else {
2785 card->sleep_cookie_vbase = NULL;
2786 }
d930faee
AK		 2787 return ret;
2788
2789err_alloc_cookie:
2790 mwifiex_pcie_delete_cmdrsp_buf(adapter);
2791err_alloc_cmdbuf:
2792 mwifiex_pcie_delete_evtbd_ring(adapter);
2793err_cre_evtbd:
2794 mwifiex_pcie_delete_rxbd_ring(adapter);
2795err_cre_rxbd:
2796 mwifiex_pcie_delete_txbd_ring(adapter);
2797err_cre_txbd:
2798 pci_iounmap(pdev, card->pci_mmap1);
2799err_iomap2:
2800 pci_release_region(pdev, 2);
2801err_req_region2:
2802 pci_iounmap(pdev, card->pci_mmap);
2803err_iomap0:
2804 pci_release_region(pdev, 0);
2805err_req_region0:
2806err_set_dma_mask:
2807 pci_disable_device(pdev);
2808err_enable_dev:
2809 pci_set_drvdata(pdev, NULL);
2810 return ret;
2811}
2812
2813/*
2814 * This function cleans up the allocated card buffers.
2815 *
2816 * The following are freed by this function -
2817 * - TXBD ring buffers
2818 * - RXBD ring buffers
2819 * - Event BD ring buffers
2820 * - Command response ring buffer
2821 * - Sleep cookie buffer
2822 */
2823static void mwifiex_pcie_cleanup(struct mwifiex_adapter *adapter)
2824{
2825 struct pcie_service_card *card = adapter->card;
2826 struct pci_dev *pdev = card->dev;
dd04e6ac 2827 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 2828
d930faee 2829 if (user_rmmod) {
acebe8c1
ZL		 2830 mwifiex_dbg(adapter, INFO,
2831 "Clearing driver ready signature\n");
dd04e6ac 2832 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
acebe8c1
ZL		 2833 mwifiex_dbg(adapter, ERROR,
2834 "Failed to write driver not-ready signature\n");
d930faee
AK		 2835 }
2836
2837 if (pdev) {
2838 pci_iounmap(pdev, card->pci_mmap);
2839 pci_iounmap(pdev, card->pci_mmap1);
5b0d9b21 2840 pci_disable_device(pdev);
c380aafb
YAP		 2841 pci_release_region(pdev, 2);
2842 pci_release_region(pdev, 0);
d930faee
AK		 2843 pci_set_drvdata(pdev, NULL);
2844 }
3c59e328 2845 kfree(card);
d930faee
AK		 2846}
2847
7be0f5b5
AP		 2848static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter)
2849{
99074fc1 2850 int ret, i, j;
7be0f5b5
AP		 2851 struct pcie_service_card *card = adapter->card;
2852 struct pci_dev *pdev = card->dev;
2853
99074fc1
XH		 2854 if (card->pcie.reg->msix_support) {
2855 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
2856 card->msix_entries[i].entry = i;
2857 ret = pci_enable_msix_exact(pdev, card->msix_entries,
2858 MWIFIEX_NUM_MSIX_VECTORS);
2859 if (!ret) {
2860 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) {
2861 card->msix_ctx[i].dev = pdev;
2862 card->msix_ctx[i].msg_id = i;
2863
2864 ret = request_irq(card->msix_entries[i].vector,
2865 mwifiex_pcie_interrupt, 0,
2866 "MWIFIEX_PCIE_MSIX",
2867 &card->msix_ctx[i]);
2868 if (ret)
2869 break;
2870 }
2871
2872 if (ret) {
2873 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n",
2874 ret);
2875 for (j = 0; j < i; j++)
2876 free_irq(card->msix_entries[j].vector,
2877 &card->msix_ctx[i]);
2878 pci_disable_msix(pdev);
2879 } else {
2880 mwifiex_dbg(adapter, MSG, "MSIx enabled!");
2881 card->msix_enable = 1;
2882 return 0;
2883 }
2884 }
2885 }
2886
7be0f5b5
AP		 2887 if (pci_enable_msi(pdev) != 0)
2888 pci_disable_msi(pdev);
2889 else
2890 card->msi_enable = 1;
2891
2892 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable);
2893
99074fc1
XH		 2894 card->share_irq_ctx.dev = pdev;
2895 card->share_irq_ctx.msg_id = -1;
7be0f5b5 2896 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED,
99074fc1 2897 "MRVL_PCIE", &card->share_irq_ctx);
7be0f5b5
AP		 2898 if (ret) {
2899 pr_err("request_irq failed: ret=%d\n", ret);
7be0f5b5
AP		 2900 return -1;
2901 }
2902
2903 return 0;
2904}
2905
a362e16b 2906/*
47ce90f9 2907 * This function gets the firmware name for downloading by revision id
a362e16b
SL		 2908 *
2909 * Read revision id register to get revision id
2910 */
2911static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter)
2912{
2913 int revision_id = 0;
e87650bc 2914 int version;
a362e16b
SL		 2915 struct pcie_service_card *card = adapter->card;
2916
2917 switch (card->dev->device) {
2918 case PCIE_DEVICE_ID_MARVELL_88W8766P:
2919 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME);
2920 break;
2921 case PCIE_DEVICE_ID_MARVELL_88W8897:
2922 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000);
2923 mwifiex_read_reg(adapter, 0x0c58, &revision_id);
2924 revision_id &= 0xff00;
2925 switch (revision_id) {
2926 case PCIE8897_A0:
2927 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME);
2928 break;
2929 case PCIE8897_B0:
2930 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME);
2931 break;
2932 default:
b9db3978
SL		 2933 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME);
2934
a362e16b
SL		 2935 break;
2936 }
c865a700 2937 break;
a362e16b
SL		 2938 case PCIE_DEVICE_ID_MARVELL_88W8997:
2939 mwifiex_read_reg(adapter, 0x0c48, &revision_id);
e87650bc
SL		 2940 mwifiex_read_reg(adapter, 0x0cd0, &version);
2941 version &= 0x7;
a362e16b
SL		 2942 switch (revision_id) {
2943 case PCIE8997_V2:
473dfbfa 2944 if (version == CHIP_VER_PCIEUART)
e87650bc 2945 strcpy(adapter->fw_name,
473dfbfa 2946 PCIEUART8997_FW_NAME_V2);
e87650bc
SL		 2947 else
2948 strcpy(adapter->fw_name,
473dfbfa 2949 PCIEUSB8997_FW_NAME_V2);
a362e16b
SL		 2950 break;
2951 case PCIE8997_Z:
473dfbfa 2952 if (version == CHIP_VER_PCIEUART)
e87650bc 2953 strcpy(adapter->fw_name,
473dfbfa 2954 PCIEUART8997_FW_NAME_Z);
e87650bc
SL		 2955 else
2956 strcpy(adapter->fw_name,
473dfbfa 2957 PCIEUSB8997_FW_NAME_Z);
a362e16b
SL		 2958 break;
2959 default:
b9db3978 2960 strcpy(adapter->fw_name, PCIE8997_DEFAULT_FW_NAME);
a362e16b
SL		 2961 break;
2962 }
2963 default:
2964 break;
2965 }
2966}
2967
d930faee
AK		 2968/*
2969 * This function registers the PCIE device.
2970 *
2971 * PCIE IRQ is claimed, block size is set and driver data is initialized.
2972 */
2973static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
2974{
d930faee
AK		 2975 struct pcie_service_card *card = adapter->card;
2976 struct pci_dev *pdev = card->dev;
2977
2978 /* save adapter pointer in card */
2979 card->adapter = adapter;
fdb1e28e 2980 adapter->dev = &pdev->dev;
d930faee 2981
7be0f5b5 2982 if (mwifiex_pcie_request_irq(adapter))
d930faee 2983 return -1;
d930faee 2984
828cf222 2985 adapter->tx_buf_size = card->pcie.tx_buf_size;
50632092
XH		 2986 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl;
2987 adapter->num_mem_types = card->pcie.num_mem_types;
1fe192d8 2988 adapter->ext_scan = card->pcie.can_ext_scan;
a362e16b 2989 mwifiex_pcie_get_fw_name(adapter);
d930faee
AK		 2990
2991 return 0;
2992}
2993
2994/*
2995 * This function unregisters the PCIE device.
2996 *
2997 * The PCIE IRQ is released, the function is disabled and driver
2998 * data is set to null.
2999 */
3000static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter)
3001{
3002 struct pcie_service_card *card = adapter->card;
141bcf09 3003 struct pci_dev *pdev;
99074fc1 3004 int i;
d930faee
AK		 3005
3006 if (card) {
141bcf09 3007 pdev = card->dev;
99074fc1
XH		 3008 if (card->msix_enable) {
3009 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3010 synchronize_irq(card->msix_entries[i].vector);
3011
3012 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3013 free_irq(card->msix_entries[i].vector,
3014 &card->msix_ctx[i]);
3015
3016 card->msix_enable = 0;
3017 pci_disable_msix(pdev);
3018 } else {
3019 mwifiex_dbg(adapter, INFO,
3020 "%s(): calling free_irq()\n", __func__);
3021 free_irq(card->dev->irq, &card->share_irq_ctx);
3022
3023 if (card->msi_enable)
3024 pci_disable_msi(pdev);
3025 }
4c5dae59
AK		 3026 }
3027}
fc331460 3028
4c5dae59
AK		 3029/* This function initializes the PCI-E host memory space, WCB rings, etc.
3030 *
3031 * The following initializations steps are followed -
3032 * - Allocate TXBD ring buffers
3033 * - Allocate RXBD ring buffers
3034 * - Allocate event BD ring buffers
3035 * - Allocate command response ring buffer
3036 * - Allocate sleep cookie buffer
3037 * Part of mwifiex_pcie_init(), not reset the PCIE registers
3038 */
3039static void mwifiex_pcie_up_dev(struct mwifiex_adapter *adapter)
3040{
3041 struct pcie_service_card *card = adapter->card;
3042 int ret;
3043 struct pci_dev *pdev = card->dev;
3044 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3045
3046 card->cmdrsp_buf = NULL;
3047 ret = mwifiex_pcie_create_txbd_ring(adapter);
3048 if (ret) {
3049 mwifiex_dbg(adapter, ERROR, "Failed to create txbd ring\n");
3050 goto err_cre_txbd;
3051 }
3052
3053 ret = mwifiex_pcie_create_rxbd_ring(adapter);
3054 if (ret) {
3055 mwifiex_dbg(adapter, ERROR, "Failed to create rxbd ring\n");
3056 goto err_cre_rxbd;
3057 }
3058
3059 ret = mwifiex_pcie_create_evtbd_ring(adapter);
3060 if (ret) {
3061 mwifiex_dbg(adapter, ERROR, "Failed to create evtbd ring\n");
3062 goto err_cre_evtbd;
3063 }
3064
3065 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter);
3066 if (ret) {
3067 mwifiex_dbg(adapter, ERROR, "Failed to allocate cmdbuf buffer\n");
3068 goto err_alloc_cmdbuf;
3069 }
3070
3071 if (reg->sleep_cookie) {
3072 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter);
3073 if (ret) {
3074 mwifiex_dbg(adapter, ERROR, "Failed to allocate sleep_cookie buffer\n");
3075 goto err_alloc_cookie;
3076 }
3077 } else {
3078 card->sleep_cookie_vbase = NULL;
3079 }
3080 return;
3081
3082err_alloc_cookie:
3083 mwifiex_pcie_delete_cmdrsp_buf(adapter);
3084err_alloc_cmdbuf:
3085 mwifiex_pcie_delete_evtbd_ring(adapter);
3086err_cre_evtbd:
3087 mwifiex_pcie_delete_rxbd_ring(adapter);
3088err_cre_rxbd:
3089 mwifiex_pcie_delete_txbd_ring(adapter);
3090err_cre_txbd:
3091 pci_iounmap(pdev, card->pci_mmap1);
3092}
3093
3094/* This function cleans up the PCI-E host memory space.
3095 * Some code is extracted from mwifiex_unregister_dev()
3096 *
3097 */
3098static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter)
3099{
3100 struct pcie_service_card *card = adapter->card;
3101 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3102
3103 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
3104 mwifiex_dbg(adapter, ERROR, "Failed to write driver not-ready signature\n");
3105
3106 adapter->seq_num = 0;
3107 adapter->tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K;
3108
3109 if (card) {
52301a81
AP		 3110 if (reg->sleep_cookie)
3111 mwifiex_pcie_delete_sleep_cookie_buf(adapter);
3112
fc331460
AP		 3113 mwifiex_pcie_delete_cmdrsp_buf(adapter);
3114 mwifiex_pcie_delete_evtbd_ring(adapter);
3115 mwifiex_pcie_delete_rxbd_ring(adapter);
3116 mwifiex_pcie_delete_txbd_ring(adapter);
3117 card->cmdrsp_buf = NULL;
d930faee 3118 }
4c5dae59
AK		 3119
3120 return;
d930faee
AK		 3121}
3122
3123static struct mwifiex_if_ops pcie_ops = {
3124 .init_if = mwifiex_pcie_init,
3125 .cleanup_if = mwifiex_pcie_cleanup,
3126 .check_fw_status = mwifiex_check_fw_status,
2fd5c6ed 3127 .check_winner_status = mwifiex_check_winner_status,
d930faee
AK		 3128 .prog_fw = mwifiex_prog_fw_w_helper,
3129 .register_dev = mwifiex_register_dev,
3130 .unregister_dev = mwifiex_unregister_dev,
3131 .enable_int = mwifiex_pcie_enable_host_int,
d41376ca 3132 .disable_int = mwifiex_pcie_disable_host_int_noerr,
d930faee
AK		 3133 .process_int_status = mwifiex_process_int_status,
3134 .host_to_card = mwifiex_pcie_host_to_card,
3135 .wakeup = mwifiex_pm_wakeup_card,
3136 .wakeup_complete = mwifiex_pm_wakeup_card_complete,
3137
3138 /* PCIE specific */
3139 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete,
3140 .event_complete = mwifiex_pcie_event_complete,
3141 .update_mp_end_port = NULL,
3142 .cleanup_mpa_buf = NULL,
c6d1d87a 3143 .init_fw_port = mwifiex_pcie_init_fw_port,
fbd7e7ac 3144 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf,
4646968b 3145 .reg_dump = mwifiex_pcie_reg_dump,
fc697159 3146 .device_dump = mwifiex_pcie_device_dump,
4c5dae59
AK		 3147 .down_dev = mwifiex_pcie_down_dev,
3148 .up_dev = mwifiex_pcie_up_dev,
d930faee
AK		 3149};
3150
3151/*
3152 * This function initializes the PCIE driver module.
3153 *
3154 * This initiates the semaphore and registers the device with
3155 * PCIE bus.
3156 */
3157static int mwifiex_pcie_init_module(void)
3158{
3159 int ret;
3160
ca8f2112 3161 pr_debug("Marvell PCIe Driver\n");
d930faee
AK		 3162
3163 sema_init(&add_remove_card_sem, 1);
3164
3165 /* Clear the flag in case user removes the card. */
3166 user_rmmod = 0;
3167
3168 ret = pci_register_driver(&mwifiex_pcie);
3169 if (ret)
3170 pr_err("Driver register failed!\n");
3171 else
3172 pr_debug("info: Driver registered successfully!\n");
3173
3174 return ret;
3175}
3176
3177/*
3178 * This function cleans up the PCIE driver.
3179 *
3180 * The following major steps are followed for cleanup -
3181 * - Resume the device if its suspended
3182 * - Disconnect the device if connected
3183 * - Shutdown the firmware
3184 * - Unregister the device from PCIE bus.
3185 */
3186static void mwifiex_pcie_cleanup_module(void)
3187{
3188 if (!down_interruptible(&add_remove_card_sem))
3189 up(&add_remove_card_sem);
3190
3191 /* Set the flag as user is removing this module. */
3192 user_rmmod = 1;
3193
2f5872b6 3194 cancel_work_sync(&pcie_work);
d930faee
AK		 3195 pci_unregister_driver(&mwifiex_pcie);
3196}
3197
3198module_init(mwifiex_pcie_init_module);
3199module_exit(mwifiex_pcie_cleanup_module);
3200
3201MODULE_AUTHOR("Marvell International Ltd.");
3202MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION);
3203MODULE_VERSION(PCIE_VERSION);
3204MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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