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c869f77d JK |
1 | /* |
2 | * (c) Copyright 2002-2010, Ralink Technology, Inc. | |
3 | * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> | |
4 | * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 | |
8 | * as published by the Free Software Foundation | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include "mt7601u.h" | |
17 | #include "eeprom.h" | |
18 | #include "trace.h" | |
19 | #include "mcu.h" | |
20 | ||
21 | #include "initvals.h" | |
22 | ||
23 | static void | |
24 | mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable) | |
25 | { | |
26 | int i; | |
27 | ||
28 | /* Note: we don't turn off WLAN_CLK because that makes the device | |
29 | * not respond properly on the probe path. | |
30 | * In case anyone (PSM?) wants to use this function we can | |
31 | * bring the clock stuff back and fixup the probe path. | |
32 | */ | |
33 | ||
34 | if (enable) | |
35 | val |= (MT_WLAN_FUN_CTRL_WLAN_EN | | |
36 | MT_WLAN_FUN_CTRL_WLAN_CLK_EN); | |
37 | else | |
38 | val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); | |
39 | ||
40 | mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); | |
41 | udelay(20); | |
42 | ||
43 | if (enable) { | |
44 | set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state); | |
45 | } else { | |
46 | clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state); | |
47 | return; | |
48 | } | |
49 | ||
50 | for (i = 200; i; i--) { | |
51 | val = mt7601u_rr(dev, MT_CMB_CTRL); | |
52 | ||
53 | if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD) | |
54 | break; | |
55 | ||
56 | udelay(20); | |
57 | } | |
58 | ||
59 | /* Note: vendor driver tries to disable/enable wlan here and retry | |
60 | * but the code which does it is so buggy it must have never | |
61 | * triggered, so don't bother. | |
62 | */ | |
63 | if (!i) | |
64 | dev_err(dev->dev, "Error: PLL and XTAL check failed!\n"); | |
65 | } | |
66 | ||
67 | static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset) | |
68 | { | |
69 | u32 val; | |
70 | ||
71 | mutex_lock(&dev->hw_atomic_mutex); | |
72 | ||
73 | val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL); | |
74 | ||
75 | if (reset) { | |
76 | val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; | |
77 | val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; | |
78 | ||
79 | if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { | |
80 | val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | | |
81 | MT_WLAN_FUN_CTRL_WLAN_RESET_RF); | |
82 | mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); | |
83 | udelay(20); | |
84 | ||
85 | val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | | |
86 | MT_WLAN_FUN_CTRL_WLAN_RESET_RF); | |
87 | } | |
88 | } | |
89 | ||
90 | mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); | |
91 | udelay(20); | |
92 | ||
93 | mt7601u_set_wlan_state(dev, val, enable); | |
94 | ||
95 | mutex_unlock(&dev->hw_atomic_mutex); | |
96 | } | |
97 | ||
98 | static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev) | |
99 | { | |
100 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR | | |
101 | MT_MAC_SYS_CTRL_RESET_BBP)); | |
102 | mt7601u_wr(dev, MT_USB_DMA_CFG, 0); | |
103 | msleep(1); | |
104 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); | |
105 | } | |
106 | ||
107 | static void mt7601u_init_usb_dma(struct mt7601u_dev *dev) | |
108 | { | |
109 | u32 val; | |
110 | ||
d43af505 JK |
111 | val = FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) | |
112 | FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_LMT, | |
113 | MT_USB_AGGR_SIZE_LIMIT) | | |
c869f77d JK |
114 | MT_USB_DMA_CFG_RX_BULK_EN | |
115 | MT_USB_DMA_CFG_TX_BULK_EN; | |
116 | if (dev->in_max_packet == 512) | |
117 | val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN; | |
118 | mt7601u_wr(dev, MT_USB_DMA_CFG, val); | |
119 | ||
120 | val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP; | |
121 | mt7601u_wr(dev, MT_USB_DMA_CFG, val); | |
122 | val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP; | |
123 | mt7601u_wr(dev, MT_USB_DMA_CFG, val); | |
124 | } | |
125 | ||
126 | static int mt7601u_init_bbp(struct mt7601u_dev *dev) | |
127 | { | |
128 | int ret; | |
129 | ||
130 | ret = mt7601u_wait_bbp_ready(dev); | |
131 | if (ret) | |
132 | return ret; | |
133 | ||
134 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals, | |
135 | ARRAY_SIZE(bbp_common_vals)); | |
136 | if (ret) | |
137 | return ret; | |
138 | ||
139 | return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals, | |
140 | ARRAY_SIZE(bbp_chip_vals)); | |
141 | } | |
142 | ||
143 | static void | |
144 | mt76_init_beacon_offsets(struct mt7601u_dev *dev) | |
145 | { | |
146 | u16 base = MT_BEACON_BASE; | |
147 | u32 regs[4] = {}; | |
148 | int i; | |
149 | ||
150 | for (i = 0; i < 16; i++) { | |
151 | u16 addr = dev->beacon_offsets[i]; | |
152 | ||
153 | regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4)); | |
154 | } | |
155 | ||
156 | for (i = 0; i < 4; i++) | |
157 | mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]); | |
158 | } | |
159 | ||
160 | static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev) | |
161 | { | |
162 | int ret; | |
163 | ||
164 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals, | |
165 | ARRAY_SIZE(mac_common_vals)); | |
166 | if (ret) | |
167 | return ret; | |
168 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, | |
169 | mac_chip_vals, ARRAY_SIZE(mac_chip_vals)); | |
170 | if (ret) | |
171 | return ret; | |
172 | ||
173 | mt76_init_beacon_offsets(dev); | |
174 | ||
175 | mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev) | |
181 | { | |
182 | u32 *vals; | |
183 | int i, ret; | |
184 | ||
185 | vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL); | |
186 | if (!vals) | |
187 | return -ENOMEM; | |
188 | ||
189 | for (i = 0; i < N_WCIDS; i++) { | |
190 | vals[i * 2] = 0xffffffff; | |
191 | vals[i * 2 + 1] = 0x00ffffff; | |
192 | } | |
193 | ||
194 | ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE, | |
195 | vals, N_WCIDS * 2); | |
196 | kfree(vals); | |
197 | ||
198 | return ret; | |
199 | } | |
200 | ||
201 | static int mt7601u_init_key_mem(struct mt7601u_dev *dev) | |
202 | { | |
203 | u32 vals[4] = {}; | |
204 | ||
205 | return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0, | |
206 | vals, ARRAY_SIZE(vals)); | |
207 | } | |
208 | ||
209 | static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev) | |
210 | { | |
211 | u32 *vals; | |
212 | int i, ret; | |
213 | ||
214 | vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL); | |
215 | if (!vals) | |
216 | return -ENOMEM; | |
217 | ||
218 | for (i = 0; i < N_WCIDS * 2; i++) | |
219 | vals[i] = 1; | |
220 | ||
221 | ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE, | |
222 | vals, N_WCIDS * 2); | |
223 | kfree(vals); | |
224 | ||
225 | return ret; | |
226 | } | |
227 | ||
228 | static void mt7601u_reset_counters(struct mt7601u_dev *dev) | |
229 | { | |
230 | mt7601u_rr(dev, MT_RX_STA_CNT0); | |
231 | mt7601u_rr(dev, MT_RX_STA_CNT1); | |
232 | mt7601u_rr(dev, MT_RX_STA_CNT2); | |
233 | mt7601u_rr(dev, MT_TX_STA_CNT0); | |
234 | mt7601u_rr(dev, MT_TX_STA_CNT1); | |
235 | mt7601u_rr(dev, MT_TX_STA_CNT2); | |
236 | } | |
237 | ||
238 | int mt7601u_mac_start(struct mt7601u_dev *dev) | |
239 | { | |
240 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); | |
241 | ||
242 | if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY | | |
243 | MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000)) | |
244 | return -ETIMEDOUT; | |
245 | ||
246 | dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR | | |
247 | MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC | | |
248 | MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP | | |
249 | MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND | | |
250 | MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS | | |
251 | MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL | | |
252 | MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV; | |
253 | mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter); | |
254 | ||
255 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, | |
256 | MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); | |
257 | ||
258 | if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY | | |
259 | MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50)) | |
260 | return -ETIMEDOUT; | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev) | |
266 | { | |
267 | int i, ok; | |
268 | ||
269 | if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) | |
270 | return; | |
271 | ||
272 | mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN | | |
273 | MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN | | |
274 | MT_BEACON_TIME_CFG_BEACON_TX); | |
275 | ||
276 | if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000)) | |
277 | dev_warn(dev->dev, "Warning: TX DMA did not stop!\n"); | |
278 | ||
279 | /* Page count on TxQ */ | |
280 | i = 200; | |
281 | while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || | |
282 | (mt76_rr(dev, 0x0a30) & 0x000000ff) || | |
283 | (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) | |
284 | msleep(10); | |
285 | ||
286 | if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) | |
287 | dev_warn(dev->dev, "Warning: MAC TX did not stop!\n"); | |
288 | ||
289 | mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | | |
290 | MT_MAC_SYS_CTRL_ENABLE_TX); | |
291 | ||
292 | /* Page count on RxQ */ | |
293 | ok = 0; | |
294 | i = 200; | |
295 | while (i--) { | |
296 | if ((mt76_rr(dev, 0x0430) & 0x00ff0000) || | |
297 | (mt76_rr(dev, 0x0a30) & 0xffffffff) || | |
298 | (mt76_rr(dev, 0x0a34) & 0xffffffff)) | |
299 | ok++; | |
300 | if (ok > 6) | |
301 | break; | |
302 | ||
303 | msleep(1); | |
304 | } | |
305 | ||
306 | if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) | |
307 | dev_warn(dev->dev, "Warning: MAC RX did not stop!\n"); | |
308 | ||
309 | if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000)) | |
310 | dev_warn(dev->dev, "Warning: RX DMA did not stop!\n"); | |
311 | } | |
312 | ||
313 | void mt7601u_mac_stop(struct mt7601u_dev *dev) | |
314 | { | |
315 | mt7601u_mac_stop_hw(dev); | |
316 | flush_delayed_work(&dev->stat_work); | |
317 | cancel_delayed_work_sync(&dev->stat_work); | |
318 | } | |
319 | ||
320 | static void mt7601u_stop_hardware(struct mt7601u_dev *dev) | |
321 | { | |
322 | mt7601u_chip_onoff(dev, false, false); | |
323 | } | |
324 | ||
325 | int mt7601u_init_hardware(struct mt7601u_dev *dev) | |
326 | { | |
327 | static const u16 beacon_offsets[16] = { | |
328 | /* 512 byte per beacon */ | |
329 | 0xc000, 0xc200, 0xc400, 0xc600, | |
330 | 0xc800, 0xca00, 0xcc00, 0xce00, | |
331 | 0xd000, 0xd200, 0xd400, 0xd600, | |
332 | 0xd800, 0xda00, 0xdc00, 0xde00 | |
333 | }; | |
334 | int ret; | |
335 | ||
336 | dev->beacon_offsets = beacon_offsets; | |
337 | ||
338 | mt7601u_chip_onoff(dev, true, false); | |
339 | ||
340 | ret = mt7601u_wait_asic_ready(dev); | |
341 | if (ret) | |
342 | goto err; | |
343 | ret = mt7601u_mcu_init(dev); | |
344 | if (ret) | |
345 | goto err; | |
346 | ||
347 | if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG, | |
348 | MT_WPDMA_GLO_CFG_TX_DMA_BUSY | | |
349 | MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) { | |
350 | ret = -EIO; | |
351 | goto err; | |
352 | } | |
353 | ||
354 | /* Wait for ASIC ready after FW load. */ | |
355 | ret = mt7601u_wait_asic_ready(dev); | |
356 | if (ret) | |
357 | goto err; | |
358 | ||
359 | mt7601u_reset_csr_bbp(dev); | |
360 | mt7601u_init_usb_dma(dev); | |
361 | ||
362 | ret = mt7601u_mcu_cmd_init(dev); | |
363 | if (ret) | |
364 | goto err; | |
365 | ret = mt7601u_dma_init(dev); | |
366 | if (ret) | |
367 | goto err_mcu; | |
368 | ret = mt7601u_write_mac_initvals(dev); | |
369 | if (ret) | |
370 | goto err_rx; | |
371 | ||
372 | if (!mt76_poll_msec(dev, MT_MAC_STATUS, | |
373 | MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 100)) { | |
374 | ret = -EIO; | |
375 | goto err_rx; | |
376 | } | |
377 | ||
378 | ret = mt7601u_init_bbp(dev); | |
379 | if (ret) | |
380 | goto err_rx; | |
381 | ret = mt7601u_init_wcid_mem(dev); | |
382 | if (ret) | |
383 | goto err_rx; | |
384 | ret = mt7601u_init_key_mem(dev); | |
385 | if (ret) | |
386 | goto err_rx; | |
387 | ret = mt7601u_init_wcid_attr_mem(dev); | |
388 | if (ret) | |
389 | goto err_rx; | |
390 | ||
391 | mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN | | |
392 | MT_BEACON_TIME_CFG_SYNC_MODE | | |
393 | MT_BEACON_TIME_CFG_TBTT_EN | | |
394 | MT_BEACON_TIME_CFG_BEACON_TX)); | |
395 | ||
396 | mt7601u_reset_counters(dev); | |
397 | ||
398 | mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e); | |
399 | ||
d43af505 JK |
400 | mt7601u_wr(dev, MT_TXOP_CTRL_CFG, |
401 | FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) | | |
402 | FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58)); | |
c869f77d JK |
403 | |
404 | ret = mt7601u_eeprom_init(dev); | |
405 | if (ret) | |
406 | goto err_rx; | |
407 | ||
408 | ret = mt7601u_phy_init(dev); | |
409 | if (ret) | |
410 | goto err_rx; | |
411 | ||
412 | mt7601u_set_rx_path(dev, 0); | |
413 | mt7601u_set_tx_dac(dev, 0); | |
414 | ||
415 | mt7601u_mac_set_ctrlch(dev, false); | |
416 | mt7601u_bbp_set_ctrlch(dev, false); | |
417 | mt7601u_bbp_set_bw(dev, MT_BW_20); | |
418 | ||
419 | return 0; | |
420 | ||
421 | err_rx: | |
422 | mt7601u_dma_cleanup(dev); | |
423 | err_mcu: | |
424 | mt7601u_mcu_cmd_deinit(dev); | |
425 | err: | |
426 | mt7601u_chip_onoff(dev, false, false); | |
427 | return ret; | |
428 | } | |
429 | ||
430 | void mt7601u_cleanup(struct mt7601u_dev *dev) | |
431 | { | |
9a15b57e JK |
432 | if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state)) |
433 | return; | |
434 | ||
c869f77d JK |
435 | mt7601u_stop_hardware(dev); |
436 | mt7601u_dma_cleanup(dev); | |
437 | mt7601u_mcu_cmd_deinit(dev); | |
438 | } | |
439 | ||
440 | struct mt7601u_dev *mt7601u_alloc_device(struct device *pdev) | |
441 | { | |
442 | struct ieee80211_hw *hw; | |
443 | struct mt7601u_dev *dev; | |
444 | ||
445 | hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops); | |
446 | if (!hw) | |
447 | return NULL; | |
448 | ||
449 | dev = hw->priv; | |
450 | dev->dev = pdev; | |
451 | dev->hw = hw; | |
452 | mutex_init(&dev->vendor_req_mutex); | |
453 | mutex_init(&dev->reg_atomic_mutex); | |
454 | mutex_init(&dev->hw_atomic_mutex); | |
455 | mutex_init(&dev->mutex); | |
456 | spin_lock_init(&dev->tx_lock); | |
457 | spin_lock_init(&dev->rx_lock); | |
458 | spin_lock_init(&dev->lock); | |
78623bfb | 459 | spin_lock_init(&dev->mac_lock); |
c869f77d JK |
460 | spin_lock_init(&dev->con_mon_lock); |
461 | atomic_set(&dev->avg_ampdu_len, 1); | |
4513493d | 462 | skb_queue_head_init(&dev->tx_skb_done); |
c869f77d JK |
463 | |
464 | dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0); | |
465 | if (!dev->stat_wq) { | |
466 | ieee80211_free_hw(hw); | |
467 | return NULL; | |
468 | } | |
469 | ||
470 | return dev; | |
471 | } | |
472 | ||
473 | #define CHAN2G(_idx, _freq) { \ | |
57fbcce3 | 474 | .band = NL80211_BAND_2GHZ, \ |
c869f77d JK |
475 | .center_freq = (_freq), \ |
476 | .hw_value = (_idx), \ | |
477 | .max_power = 30, \ | |
478 | } | |
479 | ||
480 | static const struct ieee80211_channel mt76_channels_2ghz[] = { | |
481 | CHAN2G(1, 2412), | |
482 | CHAN2G(2, 2417), | |
483 | CHAN2G(3, 2422), | |
484 | CHAN2G(4, 2427), | |
485 | CHAN2G(5, 2432), | |
486 | CHAN2G(6, 2437), | |
487 | CHAN2G(7, 2442), | |
488 | CHAN2G(8, 2447), | |
489 | CHAN2G(9, 2452), | |
490 | CHAN2G(10, 2457), | |
491 | CHAN2G(11, 2462), | |
492 | CHAN2G(12, 2467), | |
493 | CHAN2G(13, 2472), | |
494 | CHAN2G(14, 2484), | |
495 | }; | |
496 | ||
497 | #define CCK_RATE(_idx, _rate) { \ | |
498 | .bitrate = _rate, \ | |
499 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ | |
500 | .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \ | |
501 | .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \ | |
502 | } | |
503 | ||
504 | #define OFDM_RATE(_idx, _rate) { \ | |
505 | .bitrate = _rate, \ | |
506 | .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \ | |
507 | .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \ | |
508 | } | |
509 | ||
510 | static struct ieee80211_rate mt76_rates[] = { | |
511 | CCK_RATE(0, 10), | |
512 | CCK_RATE(1, 20), | |
513 | CCK_RATE(2, 55), | |
514 | CCK_RATE(3, 110), | |
515 | OFDM_RATE(0, 60), | |
516 | OFDM_RATE(1, 90), | |
517 | OFDM_RATE(2, 120), | |
518 | OFDM_RATE(3, 180), | |
519 | OFDM_RATE(4, 240), | |
520 | OFDM_RATE(5, 360), | |
521 | OFDM_RATE(6, 480), | |
522 | OFDM_RATE(7, 540), | |
523 | }; | |
524 | ||
525 | static int | |
526 | mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband, | |
527 | const struct ieee80211_channel *chan, int n_chan, | |
528 | struct ieee80211_rate *rates, int n_rates) | |
529 | { | |
530 | struct ieee80211_sta_ht_cap *ht_cap; | |
531 | void *chanlist; | |
532 | int size; | |
533 | ||
534 | size = n_chan * sizeof(*chan); | |
535 | chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL); | |
536 | if (!chanlist) | |
537 | return -ENOMEM; | |
538 | ||
539 | sband->channels = chanlist; | |
540 | sband->n_channels = n_chan; | |
541 | sband->bitrates = rates; | |
542 | sband->n_bitrates = n_rates; | |
543 | ||
544 | ht_cap = &sband->ht_cap; | |
545 | ht_cap->ht_supported = true; | |
546 | ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
547 | IEEE80211_HT_CAP_GRN_FLD | | |
548 | IEEE80211_HT_CAP_SGI_20 | | |
549 | IEEE80211_HT_CAP_SGI_40 | | |
550 | (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
551 | ||
552 | ht_cap->mcs.rx_mask[0] = 0xff; | |
553 | ht_cap->mcs.rx_mask[4] = 0x1; | |
554 | ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
555 | ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; | |
556 | ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2; | |
557 | ||
558 | dev->chandef.chan = &sband->channels[0]; | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
563 | static int | |
564 | mt76_init_sband_2g(struct mt7601u_dev *dev) | |
565 | { | |
566 | dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g), | |
567 | GFP_KERNEL); | |
57fbcce3 | 568 | dev->hw->wiphy->bands[NL80211_BAND_2GHZ] = dev->sband_2g; |
c869f77d JK |
569 | |
570 | WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num > | |
571 | ARRAY_SIZE(mt76_channels_2ghz)); | |
572 | ||
573 | return mt76_init_sband(dev, dev->sband_2g, | |
574 | &mt76_channels_2ghz[dev->ee->reg.start - 1], | |
575 | dev->ee->reg.num, | |
576 | mt76_rates, ARRAY_SIZE(mt76_rates)); | |
577 | } | |
578 | ||
579 | int mt7601u_register_device(struct mt7601u_dev *dev) | |
580 | { | |
581 | struct ieee80211_hw *hw = dev->hw; | |
582 | struct wiphy *wiphy = hw->wiphy; | |
583 | int ret; | |
584 | ||
585 | /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to | |
586 | * entry no. 1 like it does in the vendor driver. | |
587 | */ | |
588 | dev->wcid_mask[0] |= 1; | |
589 | ||
590 | /* init fake wcid for monitor interfaces */ | |
591 | dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid), | |
592 | GFP_KERNEL); | |
593 | if (!dev->mon_wcid) | |
594 | return -ENOMEM; | |
595 | dev->mon_wcid->idx = 0xff; | |
596 | dev->mon_wcid->hw_key_idx = -1; | |
597 | ||
598 | SET_IEEE80211_DEV(hw, dev->dev); | |
599 | ||
600 | hw->queues = 4; | |
30686bf7 JB |
601 | ieee80211_hw_set(hw, SIGNAL_DBM); |
602 | ieee80211_hw_set(hw, PS_NULLFUNC_STACK); | |
603 | ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES); | |
604 | ieee80211_hw_set(hw, AMPDU_AGGREGATION); | |
605 | ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); | |
c869f77d JK |
606 | hw->max_rates = 1; |
607 | hw->max_report_rates = 7; | |
608 | hw->max_rate_tries = 1; | |
609 | ||
610 | hw->sta_data_size = sizeof(struct mt76_sta); | |
611 | hw->vif_data_size = sizeof(struct mt76_vif); | |
612 | ||
613 | SET_IEEE80211_PERM_ADDR(hw, dev->macaddr); | |
614 | ||
615 | wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; | |
616 | wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
617 | ||
618 | ret = mt76_init_sband_2g(dev); | |
619 | if (ret) | |
620 | return ret; | |
621 | ||
622 | INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work); | |
623 | INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat); | |
624 | ||
625 | ret = ieee80211_register_hw(hw); | |
626 | if (ret) | |
627 | return ret; | |
628 | ||
629 | mt7601u_init_debugfs(dev); | |
630 | ||
631 | return 0; | |
632 | } |